1 //===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "MCTargetDesc/ARMBaseInfo.h"
22 #include "Utils/ARMBaseInfo.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/RegisterScavenging.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetOpcodes.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCDwarf.h"
47 #include "llvm/MC/MCInstrDesc.h"
48 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Compiler.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
66 #define DEBUG_TYPE "arm-frame-lowering"
71 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
72 cl::desc("Align ARM NEON spills in prolog and epilog"));
74 static MachineBasicBlock::iterator
75 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
76 unsigned NumAlignedDPRCS2Regs);
78 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
79 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
82 bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const {
83 // iOS always has a FP for backtracking, force other targets to keep their FP
84 // when doing FastISel. The emitted code is currently superior, and in cases
85 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.
86 return TargetFrameLowering::noFramePointerElim(MF) ||
87 MF.getSubtarget<ARMSubtarget>().useFastISel();
90 /// hasFP - Return true if the specified function should have a dedicated frame
91 /// pointer register. This is true if the function has variable sized allocas
92 /// or if frame pointer elimination is disabled.
93 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
94 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
95 const MachineFrameInfo &MFI = MF.getFrameInfo();
97 // ABI-required frame pointer.
98 if (MF.getTarget().Options.DisableFramePointerElim(MF))
101 // Frame pointer required for use within this function.
102 return (RegInfo->needsStackRealignment(MF) ||
103 MFI.hasVarSizedObjects() ||
104 MFI.isFrameAddressTaken());
107 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
108 /// not required, we reserve argument space for call sites in the function
109 /// immediately on entry to the current function. This eliminates the need for
110 /// add/sub sp brackets around call sites. Returns true if the call frame is
111 /// included as part of the stack frame.
112 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
113 const MachineFrameInfo &MFI = MF.getFrameInfo();
114 unsigned CFSize = MFI.getMaxCallFrameSize();
115 // It's not always a good idea to include the call frame as part of the
116 // stack frame. ARM (especially Thumb) has small immediate offset to
117 // address the stack frame. So a large call frame can cause poor codegen
118 // and may even makes it impossible to scavenge a register.
119 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
122 return !MFI.hasVarSizedObjects();
125 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
126 /// call frame pseudos can be simplified. Unlike most targets, having a FP
127 /// is not sufficient here since we still may reference some objects via SP
128 /// even when FP is available in Thumb2 mode.
130 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
131 return hasReservedCallFrame(MF) || MF.getFrameInfo().hasVarSizedObjects();
134 static bool isCSRestore(MachineInstr &MI, const ARMBaseInstrInfo &TII,
135 const MCPhysReg *CSRegs) {
136 // Integer spill area is handled with "pop".
137 if (isPopOpcode(MI.getOpcode())) {
138 // The first two operands are predicates. The last two are
139 // imp-def and imp-use of SP. Check everything in between.
140 for (int i = 5, e = MI.getNumOperands(); i != e; ++i)
141 if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
145 if ((MI.getOpcode() == ARM::LDR_POST_IMM ||
146 MI.getOpcode() == ARM::LDR_POST_REG ||
147 MI.getOpcode() == ARM::t2LDR_POST) &&
148 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs) &&
149 MI.getOperand(1).getReg() == ARM::SP)
155 static void emitRegPlusImmediate(
156 bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
157 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
158 unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,
159 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
161 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
162 Pred, PredReg, TII, MIFlags);
164 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
165 Pred, PredReg, TII, MIFlags);
168 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
169 MachineBasicBlock::iterator &MBBI, const DebugLoc &dl,
170 const ARMBaseInstrInfo &TII, int NumBytes,
171 unsigned MIFlags = MachineInstr::NoFlags,
172 ARMCC::CondCodes Pred = ARMCC::AL,
173 unsigned PredReg = 0) {
174 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
175 MIFlags, Pred, PredReg);
178 static int sizeOfSPAdjustment(const MachineInstr &MI) {
180 switch (MI.getOpcode()) {
181 case ARM::VSTMDDB_UPD:
185 case ARM::t2STMDB_UPD:
189 case ARM::STR_PRE_IMM:
192 llvm_unreachable("Unknown push or pop like instruction");
196 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
197 // pred) so the list starts at 4.
198 for (int i = MI.getNumOperands() - 1; i >= 4; --i)
203 static bool WindowsRequiresStackProbe(const MachineFunction &MF,
204 size_t StackSizeInBytes) {
205 const MachineFrameInfo &MFI = MF.getFrameInfo();
206 const Function &F = MF.getFunction();
207 unsigned StackProbeSize = (MFI.getStackProtectorIndex() > 0) ? 4080 : 4096;
208 if (F.hasFnAttribute("stack-probe-size"))
209 F.getFnAttribute("stack-probe-size")
211 .getAsInteger(0, StackProbeSize);
212 return StackSizeInBytes >= StackProbeSize;
217 struct StackAdjustingInsts {
219 MachineBasicBlock::iterator I;
224 SmallVector<InstInfo, 4> Insts;
226 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
227 bool BeforeFPSet = false) {
228 InstInfo Info = {I, SPAdjust, BeforeFPSet};
229 Insts.push_back(Info);
232 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
234 llvm::find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
235 assert(Info != Insts.end() && "invalid sp adjusting instruction");
236 Info->SPAdjust += ExtraBytes;
239 void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl,
240 const ARMBaseInstrInfo &TII, bool HasFP) {
241 MachineFunction &MF = *MBB.getParent();
242 unsigned CFAOffset = 0;
243 for (auto &Info : Insts) {
244 if (HasFP && !Info.BeforeFPSet)
247 CFAOffset -= Info.SPAdjust;
248 unsigned CFIIndex = MF.addFrameInst(
249 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
250 BuildMI(MBB, std::next(Info.I), dl,
251 TII.get(TargetOpcode::CFI_INSTRUCTION))
252 .addCFIIndex(CFIIndex)
253 .setMIFlags(MachineInstr::FrameSetup);
258 } // end anonymous namespace
260 /// Emit an instruction sequence that will align the address in
261 /// register Reg by zero-ing out the lower bits. For versions of the
262 /// architecture that support Neon, this must be done in a single
263 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a
264 /// single instruction. That function only gets called when optimizing
265 /// spilling of D registers on a core with the Neon instruction set
267 static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
268 const TargetInstrInfo &TII,
269 MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator MBBI,
271 const DebugLoc &DL, const unsigned Reg,
272 const unsigned Alignment,
273 const bool MustBeSingleInstruction) {
274 const ARMSubtarget &AST =
275 static_cast<const ARMSubtarget &>(MF.getSubtarget());
276 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
277 const unsigned AlignMask = Alignment - 1;
278 const unsigned NrBitsToZero = countTrailingZeros(Alignment);
279 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
280 if (!AFI->isThumbFunction()) {
281 // if the BFC instruction is available, use that to zero the lower
283 // bfc Reg, #0, log2(Alignment)
284 // otherwise use BIC, if the mask to zero the required number of bits
285 // can be encoded in the bic immediate field
286 // bic Reg, Reg, Alignment-1
288 // lsr Reg, Reg, log2(Alignment)
289 // lsl Reg, Reg, log2(Alignment)
291 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
292 .addReg(Reg, RegState::Kill)
294 .add(predOps(ARMCC::AL));
295 } else if (AlignMask <= 255) {
296 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
297 .addReg(Reg, RegState::Kill)
299 .add(predOps(ARMCC::AL))
302 assert(!MustBeSingleInstruction &&
303 "Shouldn't call emitAligningInstructions demanding a single "
304 "instruction to be emitted for large stack alignment for a target "
306 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
307 .addReg(Reg, RegState::Kill)
308 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))
309 .add(predOps(ARMCC::AL))
311 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
312 .addReg(Reg, RegState::Kill)
313 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))
314 .add(predOps(ARMCC::AL))
318 // Since this is only reached for Thumb-2 targets, the BFC instruction
319 // should always be available.
321 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
322 .addReg(Reg, RegState::Kill)
324 .add(predOps(ARMCC::AL));
328 /// We need the offset of the frame pointer relative to other MachineFrameInfo
329 /// offsets which are encoded relative to SP at function begin.
330 /// See also emitPrologue() for how the FP is set up.
331 /// Unfortunately we cannot determine this value in determineCalleeSaves() yet
332 /// as assignCalleeSavedSpillSlots() hasn't run at this point. Instead we use
333 /// this to produce a conservative estimate that we check in an assert() later.
334 static int getMaxFPOffset(const Function &F, const ARMFunctionInfo &AFI) {
335 // This is a conservative estimation: Assume the frame pointer being r7 and
336 // pc("r15") up to r8 getting spilled before (= 8 registers).
337 return -AFI.getArgRegsSaveSize() - (8 * 4);
340 void ARMFrameLowering::emitPrologue(MachineFunction &MF,
341 MachineBasicBlock &MBB) const {
342 MachineBasicBlock::iterator MBBI = MBB.begin();
343 MachineFrameInfo &MFI = MF.getFrameInfo();
344 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
345 MachineModuleInfo &MMI = MF.getMMI();
346 MCContext &Context = MMI.getContext();
347 const TargetMachine &TM = MF.getTarget();
348 const MCRegisterInfo *MRI = Context.getRegisterInfo();
349 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
350 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
351 assert(!AFI->isThumb1OnlyFunction() &&
352 "This emitPrologue does not support Thumb1!");
353 bool isARM = !AFI->isThumbFunction();
354 unsigned Align = STI.getFrameLowering()->getStackAlignment();
355 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
356 unsigned NumBytes = MFI.getStackSize();
357 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
359 // Debug location must be unknown since the first debug location is used
360 // to determine the end of the prologue.
363 unsigned FramePtr = RegInfo->getFrameRegister(MF);
365 // Determine the sizes of each callee-save spill areas and record which frame
366 // belongs to which callee-save spill areas.
367 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
368 int FramePtrSpillFI = 0;
371 // All calls are tail calls in GHC calling conv, and functions have no
372 // prologue/epilogue.
373 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
376 StackAdjustingInsts DefCFAOffsetCandidates;
377 bool HasFP = hasFP(MF);
379 // Allocate the vararg register save area.
380 if (ArgRegsSaveSize) {
381 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
382 MachineInstr::FrameSetup);
383 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
386 if (!AFI->hasStackFrame() &&
387 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
388 if (NumBytes - ArgRegsSaveSize != 0) {
389 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
390 MachineInstr::FrameSetup);
391 DefCFAOffsetCandidates.addInst(std::prev(MBBI),
392 NumBytes - ArgRegsSaveSize, true);
394 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
398 // Determine spill area sizes.
399 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
400 unsigned Reg = CSI[i].getReg();
401 int FI = CSI[i].getFrameIdx();
408 if (STI.splitFramePushPop(MF)) {
423 FramePtrSpillFI = FI;
427 // This is a DPR. Exclude the aligned DPRCS2 spills.
430 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
436 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
437 if (GPRCS1Size > 0) {
438 GPRCS1Push = LastPush = MBBI++;
439 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
442 // Determine starting offsets of spill areas.
443 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
444 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
445 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
446 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
447 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
448 int FramePtrOffsetInPush = 0;
450 int FPOffset = MFI.getObjectOffset(FramePtrSpillFI);
451 assert(getMaxFPOffset(MF.getFunction(), *AFI) <= FPOffset &&
452 "Max FP estimation is wrong");
453 FramePtrOffsetInPush = FPOffset + ArgRegsSaveSize;
454 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
457 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
458 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
459 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
462 if (GPRCS2Size > 0) {
463 GPRCS2Push = LastPush = MBBI++;
464 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
467 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
468 // .cfi_offset operations will reflect that.
470 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
471 if (LastPush != MBB.end() &&
472 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize))
473 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
475 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
476 MachineInstr::FrameSetup);
477 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
483 // Since vpush register list cannot have gaps, there may be multiple vpush
484 // instructions in the prologue.
485 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
486 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
491 // Move past the aligned DPRCS2 area.
492 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
493 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
494 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
495 // leaves the stack pointer pointing to the DPRCS2 area.
497 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
498 NumBytes += MFI.getObjectOffset(D8SpillFI);
500 NumBytes = DPRCSOffset;
502 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
503 uint32_t NumWords = NumBytes >> 2;
505 if (NumWords < 65536)
506 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
508 .setMIFlags(MachineInstr::FrameSetup)
509 .add(predOps(ARMCC::AL));
511 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
513 .setMIFlags(MachineInstr::FrameSetup);
515 switch (TM.getCodeModel()) {
516 case CodeModel::Small:
517 case CodeModel::Medium:
518 case CodeModel::Kernel:
519 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
520 .add(predOps(ARMCC::AL))
521 .addExternalSymbol("__chkstk")
522 .addReg(ARM::R4, RegState::Implicit)
523 .setMIFlags(MachineInstr::FrameSetup);
525 case CodeModel::Large:
526 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
527 .addExternalSymbol("__chkstk")
528 .setMIFlags(MachineInstr::FrameSetup);
530 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
531 .add(predOps(ARMCC::AL))
532 .addReg(ARM::R12, RegState::Kill)
533 .addReg(ARM::R4, RegState::Implicit)
534 .setMIFlags(MachineInstr::FrameSetup);
538 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
539 .addReg(ARM::SP, RegState::Kill)
540 .addReg(ARM::R4, RegState::Kill)
541 .setMIFlags(MachineInstr::FrameSetup)
542 .add(predOps(ARMCC::AL))
548 // Adjust SP after all the callee-save spills.
549 if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
550 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
551 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
553 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
554 MachineInstr::FrameSetup);
555 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
559 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
560 // Note it's not safe to do this in Thumb2 mode because it would have
561 // taken two instructions:
564 // If an interrupt is taken between the two instructions, then sp is in
565 // an inconsistent state (pointing to the middle of callee-saved area).
566 // The interrupt handler can end up clobbering the registers.
567 AFI->setShouldRestoreSPFromFP(true);
570 // Set FP to point to the stack slot that contains the previous FP.
571 // For iOS, FP is R7, which has now been stored in spill area 1.
572 // Otherwise, if this is not iOS, all the callee-saved registers go
573 // into spill area 1, including the FP in R11. In either case, it
574 // is in area one and the adjustment needs to take place just after
577 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
578 unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
579 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
580 dl, TII, FramePtr, ARM::SP,
581 PushSize + FramePtrOffsetInPush,
582 MachineInstr::FrameSetup);
583 if (FramePtrOffsetInPush + PushSize != 0) {
584 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
585 nullptr, MRI->getDwarfRegNum(FramePtr, true),
586 -(ArgRegsSaveSize - FramePtrOffsetInPush)));
587 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
588 .addCFIIndex(CFIIndex)
589 .setMIFlags(MachineInstr::FrameSetup);
592 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
593 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
594 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
595 .addCFIIndex(CFIIndex)
596 .setMIFlags(MachineInstr::FrameSetup);
600 // Now that the prologue's actual instructions are finalised, we can insert
601 // the necessary DWARF cf instructions to describe the situation. Start by
602 // recording where each register ended up:
603 if (GPRCS1Size > 0) {
604 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
606 for (const auto &Entry : CSI) {
607 unsigned Reg = Entry.getReg();
608 int FI = Entry.getFrameIdx();
615 if (STI.splitFramePushPop(MF))
627 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
628 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
629 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
630 .addCFIIndex(CFIIndex)
631 .setMIFlags(MachineInstr::FrameSetup);
637 if (GPRCS2Size > 0) {
638 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
639 for (const auto &Entry : CSI) {
640 unsigned Reg = Entry.getReg();
641 int FI = Entry.getFrameIdx();
648 if (STI.splitFramePushPop(MF)) {
649 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
650 unsigned Offset = MFI.getObjectOffset(FI);
651 unsigned CFIIndex = MF.addFrameInst(
652 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
653 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
654 .addCFIIndex(CFIIndex)
655 .setMIFlags(MachineInstr::FrameSetup);
663 // Since vpush register list cannot have gaps, there may be multiple vpush
664 // instructions in the prologue.
665 MachineBasicBlock::iterator Pos = std::next(LastPush);
666 for (const auto &Entry : CSI) {
667 unsigned Reg = Entry.getReg();
668 int FI = Entry.getFrameIdx();
669 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
670 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
671 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
672 unsigned Offset = MFI.getObjectOffset(FI);
673 unsigned CFIIndex = MF.addFrameInst(
674 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
675 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
676 .addCFIIndex(CFIIndex)
677 .setMIFlags(MachineInstr::FrameSetup);
682 // Now we can emit descriptions of where the canonical frame address was
683 // throughout the process. If we have a frame pointer, it takes over the job
684 // half-way through, so only the first few .cfi_def_cfa_offset instructions
685 // actually get emitted.
686 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
688 if (STI.isTargetELF() && hasFP(MF))
689 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
690 AFI->getFramePtrSpillOffset());
692 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
693 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
694 AFI->setDPRCalleeSavedGapSize(DPRGapSize);
695 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
697 // If we need dynamic stack realignment, do it here. Be paranoid and make
698 // sure if we also have VLAs, we have a base pointer for frame access.
699 // If aligned NEON registers were spilled, the stack has already been
701 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
702 unsigned MaxAlign = MFI.getMaxAlignment();
703 assert(!AFI->isThumb1OnlyFunction());
704 if (!AFI->isThumbFunction()) {
705 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
708 // We cannot use sp as source/dest register here, thus we're using r4 to
709 // perform the calculations. We're emitting the following sequence:
711 // -- use emitAligningInstructions to produce best sequence to zero
712 // -- out lower bits in r4
714 // FIXME: It will be better just to find spare register here.
715 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
716 .addReg(ARM::SP, RegState::Kill)
717 .add(predOps(ARMCC::AL));
718 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
720 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
721 .addReg(ARM::R4, RegState::Kill)
722 .add(predOps(ARMCC::AL));
725 AFI->setShouldRestoreSPFromFP(true);
728 // If we need a base pointer, set it up here. It's whatever the value
729 // of the stack pointer is at this point. Any variable size objects
730 // will be allocated after this, so we can still use the base pointer
731 // to reference locals.
732 // FIXME: Clarify FrameSetup flags here.
733 if (RegInfo->hasBasePointer(MF)) {
735 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())
737 .add(predOps(ARMCC::AL))
740 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())
742 .add(predOps(ARMCC::AL));
745 // If the frame has variable sized objects then the epilogue must restore
746 // the sp from fp. We can assume there's an FP here since hasFP already
747 // checks for hasVarSizedObjects.
748 if (MFI.hasVarSizedObjects())
749 AFI->setShouldRestoreSPFromFP(true);
752 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
753 MachineBasicBlock &MBB) const {
754 MachineFrameInfo &MFI = MF.getFrameInfo();
755 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
756 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
757 const ARMBaseInstrInfo &TII =
758 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
759 assert(!AFI->isThumb1OnlyFunction() &&
760 "This emitEpilogue does not support Thumb1!");
761 bool isARM = !AFI->isThumbFunction();
763 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
764 int NumBytes = (int)MFI.getStackSize();
765 unsigned FramePtr = RegInfo->getFrameRegister(MF);
767 // All calls are tail calls in GHC calling conv, and functions have no
768 // prologue/epilogue.
769 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
772 // First put ourselves on the first (from top) terminator instructions.
773 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
774 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
776 if (!AFI->hasStackFrame()) {
777 if (NumBytes - ArgRegsSaveSize != 0)
778 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
780 // Unwind MBBI to point to first LDR / VLDRD.
781 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
782 if (MBBI != MBB.begin()) {
785 } while (MBBI != MBB.begin() && isCSRestore(*MBBI, TII, CSRegs));
786 if (!isCSRestore(*MBBI, TII, CSRegs))
790 // Move SP to start of FP callee save spill area.
791 NumBytes -= (ArgRegsSaveSize +
792 AFI->getGPRCalleeSavedArea1Size() +
793 AFI->getGPRCalleeSavedArea2Size() +
794 AFI->getDPRCalleeSavedGapSize() +
795 AFI->getDPRCalleeSavedAreaSize());
797 // Reset SP based on frame pointer only if the stack frame extends beyond
798 // frame pointer stack slot or target is ELF and the function has FP.
799 if (AFI->shouldRestoreSPFromFP()) {
800 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
803 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
806 // It's not possible to restore SP from FP in a single instruction.
807 // For iOS, this looks like:
810 // This is bad, if an interrupt is taken after the mov, sp is in an
811 // inconsistent state.
812 // Use the first callee-saved register as a scratch register.
813 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
814 "No scratch register to restore SP from FP!");
815 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
817 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
819 .add(predOps(ARMCC::AL));
824 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
826 .add(predOps(ARMCC::AL))
829 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
831 .add(predOps(ARMCC::AL));
833 } else if (NumBytes &&
834 !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
835 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
837 // Increment past our save areas.
838 if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) {
840 // Since vpop register list cannot have gaps, there may be multiple vpop
841 // instructions in the epilogue.
842 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD)
845 if (AFI->getDPRCalleeSavedGapSize()) {
846 assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
847 "unexpected DPR alignment gap");
848 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
851 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
852 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
856 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
859 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
860 /// debug info. It's the same as what we use for resolving the code-gen
861 /// references for now. FIXME: This can go wrong when references are
862 /// SP-relative and simple call frames aren't used.
864 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
865 unsigned &FrameReg) const {
866 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
870 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
871 int FI, unsigned &FrameReg,
873 const MachineFrameInfo &MFI = MF.getFrameInfo();
874 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
875 MF.getSubtarget().getRegisterInfo());
876 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
877 int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
878 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
879 bool isFixed = MFI.isFixedObjectIndex(FI);
884 // SP can move around if there are allocas. We may also lose track of SP
885 // when emergency spilling inside a non-reserved call frame setup.
886 bool hasMovingSP = !hasReservedCallFrame(MF);
888 // When dynamically realigning the stack, use the frame pointer for
889 // parameters, and the stack/base pointer for locals.
890 if (RegInfo->needsStackRealignment(MF)) {
891 assert(hasFP(MF) && "dynamic stack realignment without a FP!");
893 FrameReg = RegInfo->getFrameRegister(MF);
895 } else if (hasMovingSP) {
896 assert(RegInfo->hasBasePointer(MF) &&
897 "VLAs and dynamic stack alignment, but missing base pointer!");
898 FrameReg = RegInfo->getBaseRegister();
903 // If there is a frame pointer, use it when we can.
904 if (hasFP(MF) && AFI->hasStackFrame()) {
905 // Use frame pointer to reference fixed objects. Use it for locals if
906 // there are VLAs (and thus the SP isn't reliable as a base).
907 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
908 FrameReg = RegInfo->getFrameRegister(MF);
910 } else if (hasMovingSP) {
911 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
912 if (AFI->isThumb2Function()) {
913 // Try to use the frame pointer if we can, else use the base pointer
914 // since it's available. This is handy for the emergency spill slot, in
916 if (FPOffset >= -255 && FPOffset < 0) {
917 FrameReg = RegInfo->getFrameRegister(MF);
921 } else if (AFI->isThumb2Function()) {
922 // Use add <rd>, sp, #<imm8>
923 // ldr <rd>, [sp, #<imm8>]
924 // if at all possible to save space.
925 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
927 // In Thumb2 mode, the negative offset is very limited. Try to avoid
928 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
929 if (FPOffset >= -255 && FPOffset < 0) {
930 FrameReg = RegInfo->getFrameRegister(MF);
933 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
934 // Otherwise, use SP or FP, whichever is closer to the stack slot.
935 FrameReg = RegInfo->getFrameRegister(MF);
939 // Use the base pointer if we have one.
940 if (RegInfo->hasBasePointer(MF))
941 FrameReg = RegInfo->getBaseRegister();
945 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
946 MachineBasicBlock::iterator MI,
947 const std::vector<CalleeSavedInfo> &CSI,
948 unsigned StmOpc, unsigned StrOpc,
950 bool(*Func)(unsigned, bool),
951 unsigned NumAlignedDPRCS2Regs,
952 unsigned MIFlags) const {
953 MachineFunction &MF = *MBB.getParent();
954 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
955 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
959 using RegAndKill = std::pair<unsigned, bool>;
961 SmallVector<RegAndKill, 4> Regs;
962 unsigned i = CSI.size();
964 unsigned LastReg = 0;
965 for (; i != 0; --i) {
966 unsigned Reg = CSI[i-1].getReg();
967 if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
969 // D-registers in the aligned area DPRCS2 are NOT spilled here.
970 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
973 const MachineRegisterInfo &MRI = MF.getRegInfo();
974 bool isLiveIn = MRI.isLiveIn(Reg);
975 if (!isLiveIn && !MRI.isReserved(Reg))
977 // If NoGap is true, push consecutive registers and then leave the rest
978 // for other instructions. e.g.
979 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
980 if (NoGap && LastReg && LastReg != Reg-1)
983 // Do not set a kill flag on values that are also marked as live-in. This
984 // happens with the @llvm-returnaddress intrinsic and with arguments
985 // passed in callee saved registers.
986 // Omitting the kill flags is conservatively correct even if the live-in
987 // is not used after all.
988 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
994 std::sort(Regs.begin(), Regs.end(), [&](const RegAndKill &LHS,
995 const RegAndKill &RHS) {
996 return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
999 if (Regs.size() > 1 || StrOpc== 0) {
1000 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1002 .setMIFlags(MIFlags)
1003 .add(predOps(ARMCC::AL));
1004 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1005 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1006 } else if (Regs.size() == 1) {
1007 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)
1008 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
1010 .setMIFlags(MIFlags)
1012 .add(predOps(ARMCC::AL));
1016 // Put any subsequent vpush instructions before this one: they will refer to
1017 // higher register numbers so need to be pushed first in order to preserve
1019 if (MI != MBB.begin())
1024 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
1025 MachineBasicBlock::iterator MI,
1026 std::vector<CalleeSavedInfo> &CSI,
1027 unsigned LdmOpc, unsigned LdrOpc,
1028 bool isVarArg, bool NoGap,
1029 bool(*Func)(unsigned, bool),
1030 unsigned NumAlignedDPRCS2Regs) const {
1031 MachineFunction &MF = *MBB.getParent();
1032 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1033 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
1034 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1036 bool isTailCall = false;
1037 bool isInterrupt = false;
1038 bool isTrap = false;
1039 if (MBB.end() != MI) {
1040 DL = MI->getDebugLoc();
1041 unsigned RetOpcode = MI->getOpcode();
1042 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri);
1044 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
1046 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
1047 RetOpcode == ARM::tTRAP;
1050 SmallVector<unsigned, 4> Regs;
1051 unsigned i = CSI.size();
1053 unsigned LastReg = 0;
1054 bool DeleteRet = false;
1055 for (; i != 0; --i) {
1056 CalleeSavedInfo &Info = CSI[i-1];
1057 unsigned Reg = Info.getReg();
1058 if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
1060 // The aligned reloads from area DPRCS2 are not inserted here.
1061 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1064 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
1065 !isTrap && STI.hasV5TOps()) {
1066 if (MBB.succ_empty()) {
1069 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
1070 // We 'restore' LR into PC so it is not live out of the return block:
1071 // Clear Restored bit.
1072 Info.setRestored(false);
1074 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1075 // Fold the return instruction into the LDM.
1078 // If NoGap is true, pop consecutive registers and then leave the rest
1079 // for other instructions. e.g.
1080 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
1081 if (NoGap && LastReg && LastReg != Reg-1)
1085 Regs.push_back(Reg);
1091 std::sort(Regs.begin(), Regs.end(), [&](unsigned LHS, unsigned RHS) {
1092 return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
1095 if (Regs.size() > 1 || LdrOpc == 0) {
1096 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1098 .add(predOps(ARMCC::AL));
1099 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1100 MIB.addReg(Regs[i], getDefRegState(true));
1102 if (MI != MBB.end()) {
1103 MIB.copyImplicitOps(*MI);
1104 MI->eraseFromParent();
1108 } else if (Regs.size() == 1) {
1109 // If we adjusted the reg to PC from LR above, switch it back here. We
1110 // only do that for LDM.
1111 if (Regs[0] == ARM::PC)
1113 MachineInstrBuilder MIB =
1114 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1115 .addReg(ARM::SP, RegState::Define)
1117 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1118 // that refactoring is complete (eventually).
1119 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1121 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1124 MIB.add(predOps(ARMCC::AL));
1128 // Put any subsequent vpop instructions after this one: they will refer to
1129 // higher register numbers so need to be popped afterwards.
1130 if (MI != MBB.end())
1135 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1136 /// starting from d8. Also insert stack realignment code and leave the stack
1137 /// pointer pointing to the d8 spill slot.
1138 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1139 MachineBasicBlock::iterator MI,
1140 unsigned NumAlignedDPRCS2Regs,
1141 const std::vector<CalleeSavedInfo> &CSI,
1142 const TargetRegisterInfo *TRI) {
1143 MachineFunction &MF = *MBB.getParent();
1144 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1145 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1146 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1147 MachineFrameInfo &MFI = MF.getFrameInfo();
1149 // Mark the D-register spill slots as properly aligned. Since MFI computes
1150 // stack slot layout backwards, this can actually mean that the d-reg stack
1151 // slot offsets can be wrong. The offset for d8 will always be correct.
1152 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1153 unsigned DNum = CSI[i].getReg() - ARM::D8;
1154 if (DNum > NumAlignedDPRCS2Regs - 1)
1156 int FI = CSI[i].getFrameIdx();
1157 // The even-numbered registers will be 16-byte aligned, the odd-numbered
1158 // registers will be 8-byte aligned.
1159 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
1161 // The stack slot for D8 needs to be maximally aligned because this is
1162 // actually the point where we align the stack pointer. MachineFrameInfo
1163 // computes all offsets relative to the incoming stack pointer which is a
1164 // bit weird when realigning the stack. Any extra padding for this
1165 // over-alignment is not realized because the code inserted below adjusts
1166 // the stack pointer by numregs * 8 before aligning the stack pointer.
1168 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1171 // Move the stack pointer to the d8 spill slot, and align it at the same
1172 // time. Leave the stack slot address in the scratch register r4.
1174 // sub r4, sp, #numregs * 8
1175 // bic r4, r4, #align - 1
1178 bool isThumb = AFI->isThumbFunction();
1179 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1180 AFI->setShouldRestoreSPFromFP(true);
1182 // sub r4, sp, #numregs * 8
1183 // The immediate is <= 64, so it doesn't need any special encoding.
1184 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1185 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1187 .addImm(8 * NumAlignedDPRCS2Regs)
1188 .add(predOps(ARMCC::AL))
1191 unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
1192 // We must set parameter MustBeSingleInstruction to true, since
1193 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
1194 // stack alignment. Luckily, this can always be done since all ARM
1195 // architecture versions that support Neon also support the BFC
1197 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1200 // The stack pointer must be adjusted before spilling anything, otherwise
1201 // the stack slots could be clobbered by an interrupt handler.
1202 // Leave r4 live, it is used below.
1203 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1204 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1206 .add(predOps(ARMCC::AL));
1208 MIB.add(condCodeOp());
1210 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1211 // r4 holds the stack slot address.
1212 unsigned NextReg = ARM::D8;
1214 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1215 // The writeback is only needed when emitting two vst1.64 instructions.
1216 if (NumAlignedDPRCS2Regs >= 6) {
1217 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1218 &ARM::QQPRRegClass);
1219 MBB.addLiveIn(SupReg);
1220 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
1221 .addReg(ARM::R4, RegState::Kill)
1224 .addReg(SupReg, RegState::ImplicitKill)
1225 .add(predOps(ARMCC::AL));
1227 NumAlignedDPRCS2Regs -= 4;
1230 // We won't modify r4 beyond this point. It currently points to the next
1231 // register to be spilled.
1232 unsigned R4BaseReg = NextReg;
1234 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1235 if (NumAlignedDPRCS2Regs >= 4) {
1236 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1237 &ARM::QQPRRegClass);
1238 MBB.addLiveIn(SupReg);
1239 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1243 .addReg(SupReg, RegState::ImplicitKill)
1244 .add(predOps(ARMCC::AL));
1246 NumAlignedDPRCS2Regs -= 4;
1249 // 16-byte aligned vst1.64 with 2 d-regs.
1250 if (NumAlignedDPRCS2Regs >= 2) {
1251 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1253 MBB.addLiveIn(SupReg);
1254 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1258 .add(predOps(ARMCC::AL));
1260 NumAlignedDPRCS2Regs -= 2;
1263 // Finally, use a vanilla vstr.64 for the odd last register.
1264 if (NumAlignedDPRCS2Regs) {
1265 MBB.addLiveIn(NextReg);
1266 // vstr.64 uses addrmode5 which has an offset scale of 4.
1267 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1270 .addImm((NextReg - R4BaseReg) * 2)
1271 .add(predOps(ARMCC::AL));
1274 // The last spill instruction inserted should kill the scratch register r4.
1275 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1278 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1279 /// iterator to the following instruction.
1280 static MachineBasicBlock::iterator
1281 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1282 unsigned NumAlignedDPRCS2Regs) {
1283 // sub r4, sp, #numregs * 8
1284 // bic r4, r4, #align - 1
1287 assert(MI->mayStore() && "Expecting spill instruction");
1289 // These switches all fall through.
1290 switch(NumAlignedDPRCS2Regs) {
1293 assert(MI->mayStore() && "Expecting spill instruction");
1297 assert(MI->mayStore() && "Expecting spill instruction");
1302 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1308 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1309 /// starting from d8. These instructions are assumed to execute while the
1310 /// stack is still aligned, unlike the code inserted by emitPopInst.
1311 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1312 MachineBasicBlock::iterator MI,
1313 unsigned NumAlignedDPRCS2Regs,
1314 const std::vector<CalleeSavedInfo> &CSI,
1315 const TargetRegisterInfo *TRI) {
1316 MachineFunction &MF = *MBB.getParent();
1317 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1318 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1319 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1321 // Find the frame index assigned to d8.
1323 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1324 if (CSI[i].getReg() == ARM::D8) {
1325 D8SpillFI = CSI[i].getFrameIdx();
1329 // Materialize the address of the d8 spill slot into the scratch register r4.
1330 // This can be fairly complicated if the stack frame is large, so just use
1331 // the normal frame index elimination mechanism to do it. This code runs as
1332 // the initial part of the epilog where the stack and base pointers haven't
1333 // been changed yet.
1334 bool isThumb = AFI->isThumbFunction();
1335 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1337 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1338 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1339 .addFrameIndex(D8SpillFI)
1341 .add(predOps(ARMCC::AL))
1344 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1345 unsigned NextReg = ARM::D8;
1347 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1348 if (NumAlignedDPRCS2Regs >= 6) {
1349 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1350 &ARM::QQPRRegClass);
1351 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1352 .addReg(ARM::R4, RegState::Define)
1353 .addReg(ARM::R4, RegState::Kill)
1355 .addReg(SupReg, RegState::ImplicitDefine)
1356 .add(predOps(ARMCC::AL));
1358 NumAlignedDPRCS2Regs -= 4;
1361 // We won't modify r4 beyond this point. It currently points to the next
1362 // register to be spilled.
1363 unsigned R4BaseReg = NextReg;
1365 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1366 if (NumAlignedDPRCS2Regs >= 4) {
1367 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1368 &ARM::QQPRRegClass);
1369 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1372 .addReg(SupReg, RegState::ImplicitDefine)
1373 .add(predOps(ARMCC::AL));
1375 NumAlignedDPRCS2Regs -= 4;
1378 // 16-byte aligned vld1.64 with 2 d-regs.
1379 if (NumAlignedDPRCS2Regs >= 2) {
1380 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1382 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1385 .add(predOps(ARMCC::AL));
1387 NumAlignedDPRCS2Regs -= 2;
1390 // Finally, use a vanilla vldr.64 for the remaining odd register.
1391 if (NumAlignedDPRCS2Regs)
1392 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1394 .addImm(2 * (NextReg - R4BaseReg))
1395 .add(predOps(ARMCC::AL));
1397 // Last store kills r4.
1398 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1401 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1402 MachineBasicBlock::iterator MI,
1403 const std::vector<CalleeSavedInfo> &CSI,
1404 const TargetRegisterInfo *TRI) const {
1408 MachineFunction &MF = *MBB.getParent();
1409 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1411 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1412 unsigned PushOneOpc = AFI->isThumbFunction() ?
1413 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1414 unsigned FltOpc = ARM::VSTMDDB_UPD;
1415 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1416 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1417 MachineInstr::FrameSetup);
1418 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1419 MachineInstr::FrameSetup);
1420 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1421 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1423 // The code above does not insert spill code for the aligned DPRCS2 registers.
1424 // The stack realignment code will be inserted between the push instructions
1425 // and these spills.
1426 if (NumAlignedDPRCS2Regs)
1427 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1432 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1433 MachineBasicBlock::iterator MI,
1434 std::vector<CalleeSavedInfo> &CSI,
1435 const TargetRegisterInfo *TRI) const {
1439 MachineFunction &MF = *MBB.getParent();
1440 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1441 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1442 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1444 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1445 // registers. Do that here instead.
1446 if (NumAlignedDPRCS2Regs)
1447 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1449 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1450 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1451 unsigned FltOpc = ARM::VLDMDIA_UPD;
1452 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1453 NumAlignedDPRCS2Regs);
1454 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1455 &isARMArea2Register, 0);
1456 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1457 &isARMArea1Register, 0);
1462 // FIXME: Make generic?
1463 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1464 const ARMBaseInstrInfo &TII) {
1465 unsigned FnSize = 0;
1466 for (auto &MBB : MF) {
1467 for (auto &MI : MBB)
1468 FnSize += TII.getInstSizeInBytes(MI);
1473 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1474 /// frames and return the stack size limit beyond which some of these
1475 /// instructions will require a scratch register during their expansion later.
1476 // FIXME: Move to TII?
1477 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1478 const TargetFrameLowering *TFI) {
1479 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1480 unsigned Limit = (1 << 12) - 1;
1481 for (auto &MBB : MF) {
1482 for (auto &MI : MBB) {
1483 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1484 if (!MI.getOperand(i).isFI())
1487 // When using ADDri to get the address of a stack object, 255 is the
1488 // largest offset guaranteed to fit in the immediate offset.
1489 if (MI.getOpcode() == ARM::ADDri) {
1490 Limit = std::min(Limit, (1U << 8) - 1);
1494 // Otherwise check the addressing mode.
1495 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1496 case ARMII::AddrMode3:
1497 case ARMII::AddrModeT2_i8:
1498 Limit = std::min(Limit, (1U << 8) - 1);
1500 case ARMII::AddrMode5:
1501 case ARMII::AddrModeT2_i8s4:
1502 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1504 case ARMII::AddrModeT2_i12:
1505 // i12 supports only positive offset so these will be converted to
1506 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1507 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1508 Limit = std::min(Limit, (1U << 8) - 1);
1510 case ARMII::AddrMode4:
1511 case ARMII::AddrMode6:
1512 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1513 // immediate offset for stack references.
1518 break; // At most one FI per instruction
1526 // In functions that realign the stack, it can be an advantage to spill the
1527 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1528 // instructions take alignment hints that can improve performance.
1530 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
1531 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1532 if (!SpillAlignedNEONRegs)
1535 // Naked functions don't spill callee-saved registers.
1536 if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1539 // We are planning to use NEON instructions vst1 / vld1.
1540 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1543 // Don't bother if the default stack alignment is sufficiently high.
1544 if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
1547 // Aligned spills require stack realignment.
1548 if (!static_cast<const ARMBaseRegisterInfo *>(
1549 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
1552 // We always spill contiguous d-registers starting from d8. Count how many
1553 // needs spilling. The register allocator will almost always use the
1554 // callee-saved registers in order, but it can happen that there are holes in
1555 // the range. Registers above the hole will be spilled to the standard DPRCS
1557 unsigned NumSpills = 0;
1558 for (; NumSpills < 8; ++NumSpills)
1559 if (!SavedRegs.test(ARM::D8 + NumSpills))
1562 // Don't do this for just one d-register. It's not worth it.
1566 // Spill the first NumSpills D-registers after realigning the stack.
1567 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1569 // A scratch register is required for the vst1 / vld1 instructions.
1570 SavedRegs.set(ARM::R4);
1573 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
1574 BitVector &SavedRegs,
1575 RegScavenger *RS) const {
1576 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1577 // This tells PEI to spill the FP as if it is any other callee-save register
1578 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1579 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1580 // to combine multiple loads / stores.
1581 bool CanEliminateFrame = true;
1582 bool CS1Spilled = false;
1583 bool LRSpilled = false;
1584 unsigned NumGPRSpills = 0;
1585 unsigned NumFPRSpills = 0;
1586 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1587 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1588 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1589 MF.getSubtarget().getRegisterInfo());
1590 const ARMBaseInstrInfo &TII =
1591 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1592 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1593 MachineFrameInfo &MFI = MF.getFrameInfo();
1594 MachineRegisterInfo &MRI = MF.getRegInfo();
1595 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1596 (void)TRI; // Silence unused warning in non-assert builds.
1597 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1599 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1600 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1601 // since it's not always possible to restore sp from fp in a single
1603 // FIXME: It will be better just to find spare register here.
1604 if (AFI->isThumb2Function() &&
1605 (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1606 SavedRegs.set(ARM::R4);
1608 if (AFI->isThumb1OnlyFunction()) {
1609 // Spill LR if Thumb1 function uses variable length argument lists.
1610 if (AFI->getArgRegsSaveSize() > 0)
1611 SavedRegs.set(ARM::LR);
1613 // Spill R4 if Thumb1 epilogue has to restore SP from FP or the function
1614 // requires stack alignment. We don't know for sure what the stack size
1615 // will be, but for this, an estimate is good enough. If there anything
1616 // changes it, it'll be a spill, which implies we've used all the registers
1617 // and so R4 is already used, so not marking it here will be OK.
1618 // FIXME: It will be better just to find spare register here.
1619 if (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) ||
1620 MFI.estimateStackSize(MF) > 508)
1621 SavedRegs.set(ARM::R4);
1624 // See if we can spill vector registers to aligned stack.
1625 checkNumAlignedDPRCS2Regs(MF, SavedRegs);
1627 // Spill the BasePtr if it's used.
1628 if (RegInfo->hasBasePointer(MF))
1629 SavedRegs.set(RegInfo->getBaseRegister());
1631 // Don't spill FP if the frame can be eliminated. This is determined
1632 // by scanning the callee-save registers to see if any is modified.
1633 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1634 for (unsigned i = 0; CSRegs[i]; ++i) {
1635 unsigned Reg = CSRegs[i];
1636 bool Spilled = false;
1637 if (SavedRegs.test(Reg)) {
1639 CanEliminateFrame = false;
1642 if (!ARM::GPRRegClass.contains(Reg)) {
1644 if (ARM::SPRRegClass.contains(Reg))
1646 else if (ARM::DPRRegClass.contains(Reg))
1648 else if (ARM::QPRRegClass.contains(Reg))
1657 if (!STI.splitFramePushPop(MF)) {
1664 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1669 case ARM::R0: case ARM::R1:
1670 case ARM::R2: case ARM::R3:
1671 case ARM::R4: case ARM::R5:
1672 case ARM::R6: case ARM::R7:
1679 if (!STI.splitFramePushPop(MF)) {
1680 UnspilledCS1GPRs.push_back(Reg);
1685 case ARM::R0: case ARM::R1:
1686 case ARM::R2: case ARM::R3:
1687 case ARM::R4: case ARM::R5:
1688 case ARM::R6: case ARM::R7:
1690 UnspilledCS1GPRs.push_back(Reg);
1693 UnspilledCS2GPRs.push_back(Reg);
1699 bool ForceLRSpill = false;
1700 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1701 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1702 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1703 // use of BL to implement far jump. If it turns out that it's not needed
1704 // then the branch fix up path will undo it.
1705 if (FnSize >= (1 << 11)) {
1706 CanEliminateFrame = false;
1707 ForceLRSpill = true;
1711 // If any of the stack slot references may be out of range of an immediate
1712 // offset, make sure a register (or a spill slot) is available for the
1713 // register scavenger. Note that if we're indexing off the frame pointer, the
1714 // effective stack size is 4 bytes larger since the FP points to the stack
1715 // slot of the previous FP. Also, if we have variable sized objects in the
1716 // function, stack slot references will often be negative, and some of
1717 // our instructions are positive-offset only, so conservatively consider
1718 // that case to want a spill slot (or register) as well. Similarly, if
1719 // the function adjusts the stack pointer during execution and the
1720 // adjustments aren't already part of our stack size estimate, our offset
1721 // calculations may be off, so be conservative.
1722 // FIXME: We could add logic to be more precise about negative offsets
1723 // and which instructions will need a scratch register for them. Is it
1724 // worth the effort and added fragility?
1725 unsigned EstimatedStackSize =
1726 MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);
1728 // Determine biggest (positive) SP offset in MachineFrameInfo.
1729 int MaxFixedOffset = 0;
1730 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
1731 int MaxObjectOffset = MFI.getObjectOffset(I) + MFI.getObjectSize(I);
1732 MaxFixedOffset = std::max(MaxFixedOffset, MaxObjectOffset);
1735 bool HasFP = hasFP(MF);
1737 if (AFI->hasStackFrame())
1738 EstimatedStackSize += 4;
1740 // If FP is not used, SP will be used to access arguments, so count the
1741 // size of arguments into the estimation.
1742 EstimatedStackSize += MaxFixedOffset;
1744 EstimatedStackSize += 16; // For possible paddings.
1746 unsigned EstimatedRSStackSizeLimit = estimateRSStackSizeLimit(MF, this);
1747 int MaxFPOffset = getMaxFPOffset(MF.getFunction(), *AFI);
1748 bool BigFrameOffsets = EstimatedStackSize >= EstimatedRSStackSizeLimit ||
1749 MFI.hasVarSizedObjects() ||
1750 (MFI.adjustsStack() && !canSimplifyCallFramePseudos(MF)) ||
1751 // For large argument stacks fp relative addressed may overflow.
1752 (HasFP && (MaxFixedOffset - MaxFPOffset) >= (int)EstimatedRSStackSizeLimit);
1753 if (BigFrameOffsets ||
1754 !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1755 AFI->setHasStackFrame(true);
1758 SavedRegs.set(FramePtr);
1759 // If the frame pointer is required by the ABI, also spill LR so that we
1760 // emit a complete frame record.
1761 if (MF.getTarget().Options.DisableFramePointerElim(MF) && !LRSpilled) {
1762 SavedRegs.set(ARM::LR);
1765 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR);
1766 if (LRPos != UnspilledCS1GPRs.end())
1767 UnspilledCS1GPRs.erase(LRPos);
1769 auto FPPos = llvm::find(UnspilledCS1GPRs, FramePtr);
1770 if (FPPos != UnspilledCS1GPRs.end())
1771 UnspilledCS1GPRs.erase(FPPos);
1773 if (FramePtr == ARM::R7)
1777 // This is true when we inserted a spill for an unused register that can now
1778 // be used for register scavenging.
1779 bool ExtraCSSpill = false;
1781 if (AFI->isThumb1OnlyFunction()) {
1782 // For Thumb1-only targets, we need some low registers when we save and
1783 // restore the high registers (which aren't allocatable, but could be
1784 // used by inline assembly) because the push/pop instructions can not
1785 // access high registers. If necessary, we might need to push more low
1786 // registers to ensure that there is at least one free that can be used
1787 // for the saving & restoring, and preferably we should ensure that as
1788 // many as are needed are available so that fewer push/pop instructions
1791 // Low registers which are not currently pushed, but could be (r4-r7).
1792 SmallVector<unsigned, 4> AvailableRegs;
1794 // Unused argument registers (r0-r3) can be clobbered in the prologue for
1796 int EntryRegDeficit = 0;
1797 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
1798 if (!MF.getRegInfo().isLiveIn(Reg)) {
1800 DEBUG(dbgs() << printReg(Reg, TRI)
1801 << " is unused argument register, EntryRegDeficit = "
1802 << EntryRegDeficit << "\n");
1806 // Unused return registers can be clobbered in the epilogue for free.
1807 int ExitRegDeficit = AFI->getReturnRegsCount() - 4;
1808 DEBUG(dbgs() << AFI->getReturnRegsCount()
1809 << " return regs used, ExitRegDeficit = " << ExitRegDeficit
1812 int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);
1813 DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n");
1815 // r4-r6 can be used in the prologue if they are pushed by the first push
1817 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
1818 if (SavedRegs.test(Reg)) {
1820 DEBUG(dbgs() << printReg(Reg, TRI)
1821 << " is saved low register, RegDeficit = " << RegDeficit
1824 AvailableRegs.push_back(Reg);
1826 << printReg(Reg, TRI)
1827 << " is non-saved low register, adding to AvailableRegs\n");
1831 // r7 can be used if it is not being used as the frame pointer.
1833 if (SavedRegs.test(ARM::R7)) {
1835 DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
1836 << RegDeficit << "\n");
1838 AvailableRegs.push_back(ARM::R7);
1840 << "%r7 is non-saved low register, adding to AvailableRegs\n");
1844 // Each of r8-r11 needs to be copied to a low register, then pushed.
1845 for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
1846 if (SavedRegs.test(Reg)) {
1848 DEBUG(dbgs() << printReg(Reg, TRI)
1849 << " is saved high register, RegDeficit = " << RegDeficit
1854 // LR can only be used by PUSH, not POP, and can't be used at all if the
1855 // llvm.returnaddress intrinsic is used. This is only worth doing if we
1856 // are more limited at function entry than exit.
1857 if ((EntryRegDeficit > ExitRegDeficit) &&
1858 !(MF.getRegInfo().isLiveIn(ARM::LR) &&
1859 MF.getFrameInfo().isReturnAddressTaken())) {
1860 if (SavedRegs.test(ARM::LR)) {
1862 DEBUG(dbgs() << "%lr is saved register, RegDeficit = " << RegDeficit
1865 AvailableRegs.push_back(ARM::LR);
1866 DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n");
1870 // If there are more high registers that need pushing than low registers
1871 // available, push some more low registers so that we can use fewer push
1872 // instructions. This might not reduce RegDeficit all the way to zero,
1873 // because we can only guarantee that r4-r6 are available, but r8-r11 may
1875 DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");
1876 for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) {
1877 unsigned Reg = AvailableRegs.pop_back_val();
1878 DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
1879 << " to make up reg deficit\n");
1883 assert(!MRI.isReserved(Reg) && "Should not be reserved");
1884 if (!MRI.isPhysRegUsed(Reg))
1885 ExtraCSSpill = true;
1886 UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg));
1890 DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit << "\n");
1893 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1894 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1895 if (!LRSpilled && CS1Spilled) {
1896 SavedRegs.set(ARM::LR);
1898 SmallVectorImpl<unsigned>::iterator LRPos;
1899 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR);
1900 if (LRPos != UnspilledCS1GPRs.end())
1901 UnspilledCS1GPRs.erase(LRPos);
1903 ForceLRSpill = false;
1904 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR))
1905 ExtraCSSpill = true;
1908 // If stack and double are 8-byte aligned and we are spilling an odd number
1909 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1910 // the integer and double callee save areas.
1911 DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n");
1912 unsigned TargetAlign = getStackAlignment();
1913 if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
1914 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1915 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1916 unsigned Reg = UnspilledCS1GPRs[i];
1917 // Don't spill high register if the function is thumb. In the case of
1918 // Windows on ARM, accept R11 (frame pointer)
1919 if (!AFI->isThumbFunction() ||
1920 (STI.isTargetWindows() && Reg == ARM::R11) ||
1921 isARMLowRegister(Reg) || Reg == ARM::LR) {
1923 DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
1924 << " to make up alignment\n");
1925 if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
1926 ExtraCSSpill = true;
1930 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1931 unsigned Reg = UnspilledCS2GPRs.front();
1933 DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
1934 << " to make up alignment\n");
1935 if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
1936 ExtraCSSpill = true;
1940 // Estimate if we might need to scavenge a register at some point in order
1941 // to materialize a stack offset. If so, either spill one additional
1942 // callee-saved register or reserve a special spill slot to facilitate
1943 // register scavenging. Thumb1 needs a spill slot for stack pointer
1944 // adjustments also, even when the frame itself is small.
1945 if (BigFrameOffsets && !ExtraCSSpill) {
1946 // If any non-reserved CS register isn't spilled, just spill one or two
1947 // extra. That should take care of it!
1948 unsigned NumExtras = TargetAlign / 4;
1949 SmallVector<unsigned, 2> Extras;
1950 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1951 unsigned Reg = UnspilledCS1GPRs.back();
1952 UnspilledCS1GPRs.pop_back();
1953 if (!MRI.isReserved(Reg) &&
1954 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1956 Extras.push_back(Reg);
1960 // For non-Thumb1 functions, also check for hi-reg CS registers
1961 if (!AFI->isThumb1OnlyFunction()) {
1962 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1963 unsigned Reg = UnspilledCS2GPRs.back();
1964 UnspilledCS2GPRs.pop_back();
1965 if (!MRI.isReserved(Reg)) {
1966 Extras.push_back(Reg);
1971 if (NumExtras == 0) {
1972 for (unsigned Reg : Extras) {
1974 if (!MRI.isPhysRegUsed(Reg))
1975 ExtraCSSpill = true;
1978 if (!ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
1979 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1980 // closest to SP or frame pointer.
1981 assert(RS && "Register scavenging not provided");
1982 const TargetRegisterClass &RC = ARM::GPRRegClass;
1983 unsigned Size = TRI->getSpillSize(RC);
1984 unsigned Align = TRI->getSpillAlignment(RC);
1985 RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
1991 SavedRegs.set(ARM::LR);
1992 AFI->setLRIsSpilledForFarJump(true);
1996 MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(
1997 MachineFunction &MF, MachineBasicBlock &MBB,
1998 MachineBasicBlock::iterator I) const {
1999 const ARMBaseInstrInfo &TII =
2000 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2001 if (!hasReservedCallFrame(MF)) {
2002 // If we have alloca, convert as follows:
2003 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
2004 // ADJCALLSTACKUP -> add, sp, sp, amount
2005 MachineInstr &Old = *I;
2006 DebugLoc dl = Old.getDebugLoc();
2007 unsigned Amount = TII.getFrameSize(Old);
2009 // We need to keep the stack aligned properly. To do this, we round the
2010 // amount of space needed for the outgoing arguments up to the next
2011 // alignment boundary.
2012 Amount = alignSPAdjust(Amount);
2014 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2015 assert(!AFI->isThumb1OnlyFunction() &&
2016 "This eliminateCallFramePseudoInstr does not support Thumb1!");
2017 bool isARM = !AFI->isThumbFunction();
2019 // Replace the pseudo instruction with a new instruction...
2020 unsigned Opc = Old.getOpcode();
2021 int PIdx = Old.findFirstPredOperandIdx();
2022 ARMCC::CondCodes Pred =
2023 (PIdx == -1) ? ARMCC::AL
2024 : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm();
2025 unsigned PredReg = TII.getFramePred(Old);
2026 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
2027 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
2030 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
2031 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
2036 return MBB.erase(I);
2039 /// Get the minimum constant for ARM that is greater than or equal to the
2040 /// argument. In ARM, constants can have any value that can be produced by
2041 /// rotating an 8-bit value to the right by an even number of bits within a
2043 static uint32_t alignToARMConstant(uint32_t Value) {
2044 unsigned Shifted = 0;
2049 while (!(Value & 0xC0000000)) {
2054 bool Carry = (Value & 0x00FFFFFF);
2055 Value = ((Value & 0xFF000000) >> 24) + Carry;
2057 if (Value & 0x0000100)
2058 Value = Value & 0x000001FC;
2061 Value = Value >> (Shifted - 24);
2063 Value = Value << (24 - Shifted);
2068 // The stack limit in the TCB is set to this many bytes above the actual
2070 static const uint64_t kSplitStackAvailable = 256;
2072 // Adjust the function prologue to enable split stacks. This currently only
2073 // supports android and linux.
2075 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
2076 // must be well defined in order to allow for consistent implementations of the
2077 // __morestack helper function. The ABI is also not a normal ABI in that it
2078 // doesn't follow the normal calling conventions because this allows the
2079 // prologue of each function to be optimized further.
2081 // Currently, the ABI looks like (when calling __morestack)
2083 // * r4 holds the minimum stack size requested for this function call
2084 // * r5 holds the stack size of the arguments to the function
2085 // * the beginning of the function is 3 instructions after the call to
2088 // Implementations of __morestack should use r4 to allocate a new stack, r5 to
2089 // place the arguments on to the new stack, and the 3-instruction knowledge to
2090 // jump directly to the body of the function when working on the new stack.
2092 // An old (and possibly no longer compatible) implementation of __morestack for
2093 // ARM can be found at [1].
2095 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
2096 void ARMFrameLowering::adjustForSegmentedStacks(
2097 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2100 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
2101 bool Thumb = ST->isThumb();
2103 // Sadly, this currently doesn't support varargs, platforms other than
2104 // android/linux. Note that thumb1/thumb2 are support for android/linux.
2105 if (MF.getFunction().isVarArg())
2106 report_fatal_error("Segmented stacks do not support vararg functions.");
2107 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
2108 report_fatal_error("Segmented stacks not supported on this platform.");
2110 MachineFrameInfo &MFI = MF.getFrameInfo();
2111 MachineModuleInfo &MMI = MF.getMMI();
2112 MCContext &Context = MMI.getContext();
2113 const MCRegisterInfo *MRI = Context.getRegisterInfo();
2114 const ARMBaseInstrInfo &TII =
2115 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2116 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
2119 uint64_t StackSize = MFI.getStackSize();
2121 // Do not generate a prologue for functions with a stack of size zero
2125 // Use R4 and R5 as scratch registers.
2126 // We save R4 and R5 before use and restore them before leaving the function.
2127 unsigned ScratchReg0 = ARM::R4;
2128 unsigned ScratchReg1 = ARM::R5;
2129 uint64_t AlignedStackSize;
2131 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
2132 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
2133 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
2134 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
2135 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
2137 // Grab everything that reaches PrologueMBB to update there liveness as well.
2138 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
2139 SmallVector<MachineBasicBlock *, 2> WalkList;
2140 WalkList.push_back(&PrologueMBB);
2143 MachineBasicBlock *CurMBB = WalkList.pop_back_val();
2144 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {
2145 if (BeforePrologueRegion.insert(PredBB).second)
2146 WalkList.push_back(PredBB);
2148 } while (!WalkList.empty());
2150 // The order in that list is important.
2151 // The blocks will all be inserted before PrologueMBB using that order.
2152 // Therefore the block that should appear first in the CFG should appear
2153 // first in the list.
2154 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
2157 for (MachineBasicBlock *B : AddedBlocks)
2158 BeforePrologueRegion.insert(B);
2160 for (const auto &LI : PrologueMBB.liveins()) {
2161 for (MachineBasicBlock *PredBB : BeforePrologueRegion)
2162 PredBB->addLiveIn(LI);
2165 // Remove the newly added blocks from the list, since we know
2166 // we do not have to do the following updates for them.
2167 for (MachineBasicBlock *B : AddedBlocks) {
2168 BeforePrologueRegion.erase(B);
2169 MF.insert(PrologueMBB.getIterator(), B);
2172 for (MachineBasicBlock *MBB : BeforePrologueRegion) {
2173 // Make sure the LiveIns are still sorted and unique.
2174 MBB->sortUniqueLiveIns();
2175 // Replace the edges to PrologueMBB by edges to the sequences
2176 // we are about to add.
2177 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
2180 // The required stack size that is aligned to ARM constant criterion.
2181 AlignedStackSize = alignToARMConstant(StackSize);
2183 // When the frame size is less than 256 we just compare the stack
2184 // boundary directly to the value of the stack pointer, per gcc.
2185 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
2187 // We will use two of the callee save registers as scratch registers so we
2188 // need to save those registers onto the stack.
2189 // We will use SR0 to hold stack limit and SR1 to hold the stack size
2190 // requested and arguments for __morestack().
2191 // SR0: Scratch Register #0
2192 // SR1: Scratch Register #1
2195 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))
2196 .add(predOps(ARMCC::AL))
2197 .addReg(ScratchReg0)
2198 .addReg(ScratchReg1);
2200 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
2201 .addReg(ARM::SP, RegState::Define)
2203 .add(predOps(ARMCC::AL))
2204 .addReg(ScratchReg0)
2205 .addReg(ScratchReg1);
2208 // Emit the relevant DWARF information about the change in stack pointer as
2209 // well as where to find both r4 and r5 (the callee-save registers)
2211 MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
2212 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2213 .addCFIIndex(CFIIndex);
2214 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2215 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
2216 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2217 .addCFIIndex(CFIIndex);
2218 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2219 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
2220 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2221 .addCFIIndex(CFIIndex);
2225 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
2227 .add(predOps(ARMCC::AL));
2228 } else if (CompareStackPointer) {
2229 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
2231 .add(predOps(ARMCC::AL))
2235 // sub SR1, sp, #StackSize
2236 if (!CompareStackPointer && Thumb) {
2237 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
2239 .addReg(ScratchReg1)
2240 .addImm(AlignedStackSize)
2241 .add(predOps(ARMCC::AL));
2242 } else if (!CompareStackPointer) {
2243 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
2245 .addImm(AlignedStackSize)
2246 .add(predOps(ARMCC::AL))
2250 if (Thumb && ST->isThumb1Only()) {
2251 unsigned PCLabelId = ARMFI->createPICLabelUId();
2252 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
2253 MF.getFunction().getContext(), "__STACK_LIMIT", PCLabelId, 0);
2254 MachineConstantPool *MCP = MF.getConstantPool();
2255 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4);
2257 // ldr SR0, [pc, offset(STACK_LIMIT)]
2258 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
2259 .addConstantPoolIndex(CPI)
2260 .add(predOps(ARMCC::AL));
2263 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
2264 .addReg(ScratchReg0)
2266 .add(predOps(ARMCC::AL));
2268 // Get TLS base address from the coprocessor
2269 // mrc p15, #0, SR0, c13, c0, #3
2270 BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
2276 .add(predOps(ARMCC::AL));
2278 // Use the last tls slot on android and a private field of the TCP on linux.
2279 assert(ST->isTargetAndroid() || ST->isTargetLinux());
2280 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
2282 // Get the stack limit from the right offset
2283 // ldr SR0, [sr0, #4 * TlsOffset]
2284 BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
2285 .addReg(ScratchReg0)
2286 .addImm(4 * TlsOffset)
2287 .add(predOps(ARMCC::AL));
2290 // Compare stack limit with stack size requested.
2292 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
2293 BuildMI(GetMBB, DL, TII.get(Opcode))
2294 .addReg(ScratchReg0)
2295 .addReg(ScratchReg1)
2296 .add(predOps(ARMCC::AL));
2298 // This jump is taken if StackLimit < SP - stack required.
2299 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
2300 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2305 // Calling __morestack(StackSize, Size of stack arguments).
2306 // __morestack knows that the stack size requested is in SR0(r4)
2307 // and amount size of stack arguments is in SR1(r5).
2309 // Pass first argument for the __morestack by Scratch Register #0.
2310 // The amount size of stack required
2312 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
2314 .addImm(AlignedStackSize)
2315 .add(predOps(ARMCC::AL));
2317 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
2318 .addImm(AlignedStackSize)
2319 .add(predOps(ARMCC::AL))
2322 // Pass second argument for the __morestack by Scratch Register #1.
2323 // The amount size of stack consumed to save function arguments.
2325 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
2327 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2328 .add(predOps(ARMCC::AL));
2330 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
2331 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2332 .add(predOps(ARMCC::AL))
2336 // push {lr} - Save return address of this function.
2338 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))
2339 .add(predOps(ARMCC::AL))
2342 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2343 .addReg(ARM::SP, RegState::Define)
2345 .add(predOps(ARMCC::AL))
2349 // Emit the DWARF info about the change in stack as well as where to find the
2350 // previous link register
2352 MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2353 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2354 .addCFIIndex(CFIIndex);
2355 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2356 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2357 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2358 .addCFIIndex(CFIIndex);
2360 // Call __morestack().
2362 BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
2363 .add(predOps(ARMCC::AL))
2364 .addExternalSymbol("__morestack");
2366 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2367 .addExternalSymbol("__morestack");
2370 // pop {lr} - Restore return address of this original function.
2372 if (ST->isThumb1Only()) {
2373 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2374 .add(predOps(ARMCC::AL))
2375 .addReg(ScratchReg0);
2376 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2377 .addReg(ScratchReg0)
2378 .add(predOps(ARMCC::AL));
2380 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2381 .addReg(ARM::LR, RegState::Define)
2382 .addReg(ARM::SP, RegState::Define)
2385 .add(predOps(ARMCC::AL));
2388 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2389 .addReg(ARM::SP, RegState::Define)
2391 .add(predOps(ARMCC::AL))
2395 // Restore SR0 and SR1 in case of __morestack() was called.
2396 // __morestack() will skip PostStackMBB block so we need to restore
2397 // scratch registers from here.
2400 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2401 .add(predOps(ARMCC::AL))
2402 .addReg(ScratchReg0)
2403 .addReg(ScratchReg1);
2405 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2406 .addReg(ARM::SP, RegState::Define)
2408 .add(predOps(ARMCC::AL))
2409 .addReg(ScratchReg0)
2410 .addReg(ScratchReg1);
2413 // Update the CFA offset now that we've popped
2414 CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2415 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2416 .addCFIIndex(CFIIndex);
2418 // Return from this function.
2419 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
2421 // Restore SR0 and SR1 in case of __morestack() was not called.
2424 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
2425 .add(predOps(ARMCC::AL))
2426 .addReg(ScratchReg0)
2427 .addReg(ScratchReg1);
2429 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2430 .addReg(ARM::SP, RegState::Define)
2432 .add(predOps(ARMCC::AL))
2433 .addReg(ScratchReg0)
2434 .addReg(ScratchReg1);
2437 // Update the CFA offset now that we've popped
2438 CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2439 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2440 .addCFIIndex(CFIIndex);
2442 // Tell debuggers that r4 and r5 are now the same as they were in the
2443 // previous function, that they're the "Same Value".
2444 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2445 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2446 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2447 .addCFIIndex(CFIIndex);
2448 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2449 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2450 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2451 .addCFIIndex(CFIIndex);
2453 // Organizing MBB lists
2454 PostStackMBB->addSuccessor(&PrologueMBB);
2456 AllocMBB->addSuccessor(PostStackMBB);
2458 GetMBB->addSuccessor(PostStackMBB);
2459 GetMBB->addSuccessor(AllocMBB);
2461 McrMBB->addSuccessor(GetMBB);
2463 PrevStackMBB->addSuccessor(McrMBB);
2465 #ifdef EXPENSIVE_CHECKS