1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
33 #define DEBUG_TYPE "arm-frame-lowering"
38 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
39 cl::desc("Align ARM NEON spills in prolog and epilog"));
41 static MachineBasicBlock::iterator
42 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
43 unsigned NumAlignedDPRCS2Regs);
45 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
46 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
49 bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const {
50 // iOS always has a FP for backtracking, force other targets to keep their FP
51 // when doing FastISel. The emitted code is currently superior, and in cases
52 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.
53 return TargetFrameLowering::noFramePointerElim(MF) ||
54 MF.getSubtarget<ARMSubtarget>().useFastISel();
57 /// hasFP - Return true if the specified function should have a dedicated frame
58 /// pointer register. This is true if the function has variable sized allocas
59 /// or if frame pointer elimination is disabled.
60 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
61 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
62 const MachineFrameInfo &MFI = MF.getFrameInfo();
64 // ABI-required frame pointer.
65 if (MF.getTarget().Options.DisableFramePointerElim(MF))
68 // Frame pointer required for use within this function.
69 return (RegInfo->needsStackRealignment(MF) ||
70 MFI.hasVarSizedObjects() ||
71 MFI.isFrameAddressTaken());
74 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
75 /// not required, we reserve argument space for call sites in the function
76 /// immediately on entry to the current function. This eliminates the need for
77 /// add/sub sp brackets around call sites. Returns true if the call frame is
78 /// included as part of the stack frame.
79 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
80 const MachineFrameInfo &MFI = MF.getFrameInfo();
81 unsigned CFSize = MFI.getMaxCallFrameSize();
82 // It's not always a good idea to include the call frame as part of the
83 // stack frame. ARM (especially Thumb) has small immediate offset to
84 // address the stack frame. So a large call frame can cause poor codegen
85 // and may even makes it impossible to scavenge a register.
86 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
89 return !MFI.hasVarSizedObjects();
92 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
93 /// call frame pseudos can be simplified. Unlike most targets, having a FP
94 /// is not sufficient here since we still may reference some objects via SP
95 /// even when FP is available in Thumb2 mode.
97 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
98 return hasReservedCallFrame(MF) || MF.getFrameInfo().hasVarSizedObjects();
101 static bool isCSRestore(MachineInstr &MI, const ARMBaseInstrInfo &TII,
102 const MCPhysReg *CSRegs) {
103 // Integer spill area is handled with "pop".
104 if (isPopOpcode(MI.getOpcode())) {
105 // The first two operands are predicates. The last two are
106 // imp-def and imp-use of SP. Check everything in between.
107 for (int i = 5, e = MI.getNumOperands(); i != e; ++i)
108 if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
112 if ((MI.getOpcode() == ARM::LDR_POST_IMM ||
113 MI.getOpcode() == ARM::LDR_POST_REG ||
114 MI.getOpcode() == ARM::t2LDR_POST) &&
115 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs) &&
116 MI.getOperand(1).getReg() == ARM::SP)
122 static void emitRegPlusImmediate(
123 bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
124 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
125 unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,
126 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
128 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
129 Pred, PredReg, TII, MIFlags);
131 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
132 Pred, PredReg, TII, MIFlags);
135 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
136 MachineBasicBlock::iterator &MBBI, const DebugLoc &dl,
137 const ARMBaseInstrInfo &TII, int NumBytes,
138 unsigned MIFlags = MachineInstr::NoFlags,
139 ARMCC::CondCodes Pred = ARMCC::AL,
140 unsigned PredReg = 0) {
141 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
142 MIFlags, Pred, PredReg);
145 static int sizeOfSPAdjustment(const MachineInstr &MI) {
147 switch (MI.getOpcode()) {
148 case ARM::VSTMDDB_UPD:
152 case ARM::t2STMDB_UPD:
156 case ARM::STR_PRE_IMM:
159 llvm_unreachable("Unknown push or pop like instruction");
163 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
164 // pred) so the list starts at 4.
165 for (int i = MI.getNumOperands() - 1; i >= 4; --i)
170 static bool WindowsRequiresStackProbe(const MachineFunction &MF,
171 size_t StackSizeInBytes) {
172 const MachineFrameInfo &MFI = MF.getFrameInfo();
173 const Function *F = MF.getFunction();
174 unsigned StackProbeSize = (MFI.getStackProtectorIndex() > 0) ? 4080 : 4096;
175 if (F->hasFnAttribute("stack-probe-size"))
176 F->getFnAttribute("stack-probe-size")
178 .getAsInteger(0, StackProbeSize);
179 return StackSizeInBytes >= StackProbeSize;
183 struct StackAdjustingInsts {
185 MachineBasicBlock::iterator I;
190 SmallVector<InstInfo, 4> Insts;
192 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
193 bool BeforeFPSet = false) {
194 InstInfo Info = {I, SPAdjust, BeforeFPSet};
195 Insts.push_back(Info);
198 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
199 auto Info = find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
200 assert(Info != Insts.end() && "invalid sp adjusting instruction");
201 Info->SPAdjust += ExtraBytes;
204 void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl,
205 const ARMBaseInstrInfo &TII, bool HasFP) {
206 MachineFunction &MF = *MBB.getParent();
207 unsigned CFAOffset = 0;
208 for (auto &Info : Insts) {
209 if (HasFP && !Info.BeforeFPSet)
212 CFAOffset -= Info.SPAdjust;
213 unsigned CFIIndex = MF.addFrameInst(
214 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
215 BuildMI(MBB, std::next(Info.I), dl,
216 TII.get(TargetOpcode::CFI_INSTRUCTION))
217 .addCFIIndex(CFIIndex)
218 .setMIFlags(MachineInstr::FrameSetup);
224 /// Emit an instruction sequence that will align the address in
225 /// register Reg by zero-ing out the lower bits. For versions of the
226 /// architecture that support Neon, this must be done in a single
227 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a
228 /// single instruction. That function only gets called when optimizing
229 /// spilling of D registers on a core with the Neon instruction set
231 static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
232 const TargetInstrInfo &TII,
233 MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator MBBI,
235 const DebugLoc &DL, const unsigned Reg,
236 const unsigned Alignment,
237 const bool MustBeSingleInstruction) {
238 const ARMSubtarget &AST =
239 static_cast<const ARMSubtarget &>(MF.getSubtarget());
240 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
241 const unsigned AlignMask = Alignment - 1;
242 const unsigned NrBitsToZero = countTrailingZeros(Alignment);
243 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
244 if (!AFI->isThumbFunction()) {
245 // if the BFC instruction is available, use that to zero the lower
247 // bfc Reg, #0, log2(Alignment)
248 // otherwise use BIC, if the mask to zero the required number of bits
249 // can be encoded in the bic immediate field
250 // bic Reg, Reg, Alignment-1
252 // lsr Reg, Reg, log2(Alignment)
253 // lsl Reg, Reg, log2(Alignment)
255 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
256 .addReg(Reg, RegState::Kill)
257 .addImm(~AlignMask));
258 } else if (AlignMask <= 255) {
260 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
261 .addReg(Reg, RegState::Kill)
262 .addImm(AlignMask)));
264 assert(!MustBeSingleInstruction &&
265 "Shouldn't call emitAligningInstructions demanding a single "
266 "instruction to be emitted for large stack alignment for a target "
268 AddDefaultCC(AddDefaultPred(
269 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
270 .addReg(Reg, RegState::Kill)
271 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))));
272 AddDefaultCC(AddDefaultPred(
273 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
274 .addReg(Reg, RegState::Kill)
275 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))));
278 // Since this is only reached for Thumb-2 targets, the BFC instruction
279 // should always be available.
281 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
282 .addReg(Reg, RegState::Kill)
283 .addImm(~AlignMask));
287 void ARMFrameLowering::emitPrologue(MachineFunction &MF,
288 MachineBasicBlock &MBB) const {
289 MachineBasicBlock::iterator MBBI = MBB.begin();
290 MachineFrameInfo &MFI = MF.getFrameInfo();
291 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
292 MachineModuleInfo &MMI = MF.getMMI();
293 MCContext &Context = MMI.getContext();
294 const TargetMachine &TM = MF.getTarget();
295 const MCRegisterInfo *MRI = Context.getRegisterInfo();
296 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
297 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
298 assert(!AFI->isThumb1OnlyFunction() &&
299 "This emitPrologue does not support Thumb1!");
300 bool isARM = !AFI->isThumbFunction();
301 unsigned Align = STI.getFrameLowering()->getStackAlignment();
302 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
303 unsigned NumBytes = MFI.getStackSize();
304 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
306 // Debug location must be unknown since the first debug location is used
307 // to determine the end of the prologue.
310 unsigned FramePtr = RegInfo->getFrameRegister(MF);
312 // Determine the sizes of each callee-save spill areas and record which frame
313 // belongs to which callee-save spill areas.
314 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
315 int FramePtrSpillFI = 0;
318 // All calls are tail calls in GHC calling conv, and functions have no
319 // prologue/epilogue.
320 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
323 StackAdjustingInsts DefCFAOffsetCandidates;
324 bool HasFP = hasFP(MF);
326 // Allocate the vararg register save area.
327 if (ArgRegsSaveSize) {
328 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
329 MachineInstr::FrameSetup);
330 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
333 if (!AFI->hasStackFrame() &&
334 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
335 if (NumBytes - ArgRegsSaveSize != 0) {
336 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
337 MachineInstr::FrameSetup);
338 DefCFAOffsetCandidates.addInst(std::prev(MBBI),
339 NumBytes - ArgRegsSaveSize, true);
341 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
345 // Determine spill area sizes.
346 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
347 unsigned Reg = CSI[i].getReg();
348 int FI = CSI[i].getFrameIdx();
355 if (STI.splitFramePushPop(MF)) {
370 FramePtrSpillFI = FI;
374 // This is a DPR. Exclude the aligned DPRCS2 spills.
377 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
383 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
384 if (GPRCS1Size > 0) {
385 GPRCS1Push = LastPush = MBBI++;
386 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
389 // Determine starting offsets of spill areas.
390 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
391 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
392 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
393 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
394 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
395 int FramePtrOffsetInPush = 0;
397 FramePtrOffsetInPush =
398 MFI.getObjectOffset(FramePtrSpillFI) + ArgRegsSaveSize;
399 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
402 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
403 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
404 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
407 if (GPRCS2Size > 0) {
408 GPRCS2Push = LastPush = MBBI++;
409 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
412 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
413 // .cfi_offset operations will reflect that.
415 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
416 if (LastPush != MBB.end() &&
417 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize))
418 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
420 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
421 MachineInstr::FrameSetup);
422 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
428 // Since vpush register list cannot have gaps, there may be multiple vpush
429 // instructions in the prologue.
430 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
431 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
436 // Move past the aligned DPRCS2 area.
437 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
438 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
439 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
440 // leaves the stack pointer pointing to the DPRCS2 area.
442 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
443 NumBytes += MFI.getObjectOffset(D8SpillFI);
445 NumBytes = DPRCSOffset;
447 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
448 uint32_t NumWords = NumBytes >> 2;
450 if (NumWords < 65536)
451 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
453 .setMIFlags(MachineInstr::FrameSetup));
455 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
457 .setMIFlags(MachineInstr::FrameSetup);
459 switch (TM.getCodeModel()) {
460 case CodeModel::Small:
461 case CodeModel::Medium:
462 case CodeModel::Default:
463 case CodeModel::Kernel:
464 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
465 .addImm((unsigned)ARMCC::AL).addReg(0)
466 .addExternalSymbol("__chkstk")
467 .addReg(ARM::R4, RegState::Implicit)
468 .setMIFlags(MachineInstr::FrameSetup);
470 case CodeModel::Large:
471 case CodeModel::JITDefault:
472 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
473 .addExternalSymbol("__chkstk")
474 .setMIFlags(MachineInstr::FrameSetup);
476 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
477 .addImm((unsigned)ARMCC::AL).addReg(0)
478 .addReg(ARM::R12, RegState::Kill)
479 .addReg(ARM::R4, RegState::Implicit)
480 .setMIFlags(MachineInstr::FrameSetup);
484 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
486 .addReg(ARM::SP, RegState::Kill)
487 .addReg(ARM::R4, RegState::Kill)
488 .setMIFlags(MachineInstr::FrameSetup)));
493 // Adjust SP after all the callee-save spills.
494 if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
495 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
496 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
498 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
499 MachineInstr::FrameSetup);
500 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
504 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
505 // Note it's not safe to do this in Thumb2 mode because it would have
506 // taken two instructions:
509 // If an interrupt is taken between the two instructions, then sp is in
510 // an inconsistent state (pointing to the middle of callee-saved area).
511 // The interrupt handler can end up clobbering the registers.
512 AFI->setShouldRestoreSPFromFP(true);
515 // Set FP to point to the stack slot that contains the previous FP.
516 // For iOS, FP is R7, which has now been stored in spill area 1.
517 // Otherwise, if this is not iOS, all the callee-saved registers go
518 // into spill area 1, including the FP in R11. In either case, it
519 // is in area one and the adjustment needs to take place just after
522 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
523 unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
524 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
525 dl, TII, FramePtr, ARM::SP,
526 PushSize + FramePtrOffsetInPush,
527 MachineInstr::FrameSetup);
528 if (FramePtrOffsetInPush + PushSize != 0) {
529 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
530 nullptr, MRI->getDwarfRegNum(FramePtr, true),
531 -(ArgRegsSaveSize - FramePtrOffsetInPush)));
532 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
533 .addCFIIndex(CFIIndex)
534 .setMIFlags(MachineInstr::FrameSetup);
537 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
538 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
539 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
540 .addCFIIndex(CFIIndex)
541 .setMIFlags(MachineInstr::FrameSetup);
545 // Now that the prologue's actual instructions are finalised, we can insert
546 // the necessary DWARF cf instructions to describe the situation. Start by
547 // recording where each register ended up:
548 if (GPRCS1Size > 0) {
549 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
551 for (const auto &Entry : CSI) {
552 unsigned Reg = Entry.getReg();
553 int FI = Entry.getFrameIdx();
560 if (STI.splitFramePushPop(MF))
572 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
573 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
574 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
575 .addCFIIndex(CFIIndex)
576 .setMIFlags(MachineInstr::FrameSetup);
582 if (GPRCS2Size > 0) {
583 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
584 for (const auto &Entry : CSI) {
585 unsigned Reg = Entry.getReg();
586 int FI = Entry.getFrameIdx();
593 if (STI.splitFramePushPop(MF)) {
594 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
595 unsigned Offset = MFI.getObjectOffset(FI);
596 unsigned CFIIndex = MF.addFrameInst(
597 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
598 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
599 .addCFIIndex(CFIIndex)
600 .setMIFlags(MachineInstr::FrameSetup);
608 // Since vpush register list cannot have gaps, there may be multiple vpush
609 // instructions in the prologue.
610 MachineBasicBlock::iterator Pos = std::next(LastPush);
611 for (const auto &Entry : CSI) {
612 unsigned Reg = Entry.getReg();
613 int FI = Entry.getFrameIdx();
614 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
615 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
616 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
617 unsigned Offset = MFI.getObjectOffset(FI);
618 unsigned CFIIndex = MF.addFrameInst(
619 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
620 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
621 .addCFIIndex(CFIIndex)
622 .setMIFlags(MachineInstr::FrameSetup);
627 // Now we can emit descriptions of where the canonical frame address was
628 // throughout the process. If we have a frame pointer, it takes over the job
629 // half-way through, so only the first few .cfi_def_cfa_offset instructions
630 // actually get emitted.
631 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
633 if (STI.isTargetELF() && hasFP(MF))
634 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
635 AFI->getFramePtrSpillOffset());
637 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
638 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
639 AFI->setDPRCalleeSavedGapSize(DPRGapSize);
640 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
642 // If we need dynamic stack realignment, do it here. Be paranoid and make
643 // sure if we also have VLAs, we have a base pointer for frame access.
644 // If aligned NEON registers were spilled, the stack has already been
646 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
647 unsigned MaxAlign = MFI.getMaxAlignment();
648 assert(!AFI->isThumb1OnlyFunction());
649 if (!AFI->isThumbFunction()) {
650 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
653 // We cannot use sp as source/dest register here, thus we're using r4 to
654 // perform the calculations. We're emitting the following sequence:
656 // -- use emitAligningInstructions to produce best sequence to zero
657 // -- out lower bits in r4
659 // FIXME: It will be better just to find spare register here.
660 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
661 .addReg(ARM::SP, RegState::Kill));
662 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
664 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
665 .addReg(ARM::R4, RegState::Kill));
668 AFI->setShouldRestoreSPFromFP(true);
671 // If we need a base pointer, set it up here. It's whatever the value
672 // of the stack pointer is at this point. Any variable size objects
673 // will be allocated after this, so we can still use the base pointer
674 // to reference locals.
675 // FIXME: Clarify FrameSetup flags here.
676 if (RegInfo->hasBasePointer(MF)) {
678 BuildMI(MBB, MBBI, dl,
679 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
681 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
683 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
684 RegInfo->getBaseRegister())
688 // If the frame has variable sized objects then the epilogue must restore
689 // the sp from fp. We can assume there's an FP here since hasFP already
690 // checks for hasVarSizedObjects.
691 if (MFI.hasVarSizedObjects())
692 AFI->setShouldRestoreSPFromFP(true);
695 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
696 MachineBasicBlock &MBB) const {
697 MachineFrameInfo &MFI = MF.getFrameInfo();
698 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
699 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
700 const ARMBaseInstrInfo &TII =
701 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
702 assert(!AFI->isThumb1OnlyFunction() &&
703 "This emitEpilogue does not support Thumb1!");
704 bool isARM = !AFI->isThumbFunction();
706 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
707 int NumBytes = (int)MFI.getStackSize();
708 unsigned FramePtr = RegInfo->getFrameRegister(MF);
710 // All calls are tail calls in GHC calling conv, and functions have no
711 // prologue/epilogue.
712 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
715 // First put ourselves on the first (from top) terminator instructions.
716 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
717 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
719 if (!AFI->hasStackFrame()) {
720 if (NumBytes - ArgRegsSaveSize != 0)
721 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
723 // Unwind MBBI to point to first LDR / VLDRD.
724 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
725 if (MBBI != MBB.begin()) {
728 } while (MBBI != MBB.begin() && isCSRestore(*MBBI, TII, CSRegs));
729 if (!isCSRestore(*MBBI, TII, CSRegs))
733 // Move SP to start of FP callee save spill area.
734 NumBytes -= (ArgRegsSaveSize +
735 AFI->getGPRCalleeSavedArea1Size() +
736 AFI->getGPRCalleeSavedArea2Size() +
737 AFI->getDPRCalleeSavedGapSize() +
738 AFI->getDPRCalleeSavedAreaSize());
740 // Reset SP based on frame pointer only if the stack frame extends beyond
741 // frame pointer stack slot or target is ELF and the function has FP.
742 if (AFI->shouldRestoreSPFromFP()) {
743 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
746 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
749 // It's not possible to restore SP from FP in a single instruction.
750 // For iOS, this looks like:
753 // This is bad, if an interrupt is taken after the mov, sp is in an
754 // inconsistent state.
755 // Use the first callee-saved register as a scratch register.
756 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
757 "No scratch register to restore SP from FP!");
758 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
760 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
767 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
768 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
770 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
774 } else if (NumBytes &&
775 !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
776 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
778 // Increment past our save areas.
779 if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) {
781 // Since vpop register list cannot have gaps, there may be multiple vpop
782 // instructions in the epilogue.
783 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD)
786 if (AFI->getDPRCalleeSavedGapSize()) {
787 assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
788 "unexpected DPR alignment gap");
789 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
792 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
793 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
797 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
800 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
801 /// debug info. It's the same as what we use for resolving the code-gen
802 /// references for now. FIXME: This can go wrong when references are
803 /// SP-relative and simple call frames aren't used.
805 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
806 unsigned &FrameReg) const {
807 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
811 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
812 int FI, unsigned &FrameReg,
814 const MachineFrameInfo &MFI = MF.getFrameInfo();
815 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
816 MF.getSubtarget().getRegisterInfo());
817 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
818 int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
819 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
820 bool isFixed = MFI.isFixedObjectIndex(FI);
825 // SP can move around if there are allocas. We may also lose track of SP
826 // when emergency spilling inside a non-reserved call frame setup.
827 bool hasMovingSP = !hasReservedCallFrame(MF);
829 // When dynamically realigning the stack, use the frame pointer for
830 // parameters, and the stack/base pointer for locals.
831 if (RegInfo->needsStackRealignment(MF)) {
832 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
834 FrameReg = RegInfo->getFrameRegister(MF);
836 } else if (hasMovingSP) {
837 assert(RegInfo->hasBasePointer(MF) &&
838 "VLAs and dynamic stack alignment, but missing base pointer!");
839 FrameReg = RegInfo->getBaseRegister();
844 // If there is a frame pointer, use it when we can.
845 if (hasFP(MF) && AFI->hasStackFrame()) {
846 // Use frame pointer to reference fixed objects. Use it for locals if
847 // there are VLAs (and thus the SP isn't reliable as a base).
848 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
849 FrameReg = RegInfo->getFrameRegister(MF);
851 } else if (hasMovingSP) {
852 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
853 if (AFI->isThumb2Function()) {
854 // Try to use the frame pointer if we can, else use the base pointer
855 // since it's available. This is handy for the emergency spill slot, in
857 if (FPOffset >= -255 && FPOffset < 0) {
858 FrameReg = RegInfo->getFrameRegister(MF);
862 } else if (AFI->isThumb2Function()) {
863 // Use add <rd>, sp, #<imm8>
864 // ldr <rd>, [sp, #<imm8>]
865 // if at all possible to save space.
866 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
868 // In Thumb2 mode, the negative offset is very limited. Try to avoid
869 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
870 if (FPOffset >= -255 && FPOffset < 0) {
871 FrameReg = RegInfo->getFrameRegister(MF);
874 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
875 // Otherwise, use SP or FP, whichever is closer to the stack slot.
876 FrameReg = RegInfo->getFrameRegister(MF);
880 // Use the base pointer if we have one.
881 if (RegInfo->hasBasePointer(MF))
882 FrameReg = RegInfo->getBaseRegister();
886 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
887 MachineBasicBlock::iterator MI,
888 const std::vector<CalleeSavedInfo> &CSI,
889 unsigned StmOpc, unsigned StrOpc,
891 bool(*Func)(unsigned, bool),
892 unsigned NumAlignedDPRCS2Regs,
893 unsigned MIFlags) const {
894 MachineFunction &MF = *MBB.getParent();
895 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
896 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
900 typedef std::pair<unsigned, bool> RegAndKill;
901 SmallVector<RegAndKill, 4> Regs;
902 unsigned i = CSI.size();
904 unsigned LastReg = 0;
905 for (; i != 0; --i) {
906 unsigned Reg = CSI[i-1].getReg();
907 if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
909 // D-registers in the aligned area DPRCS2 are NOT spilled here.
910 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
913 bool isLiveIn = MF.getRegInfo().isLiveIn(Reg);
916 // If NoGap is true, push consecutive registers and then leave the rest
917 // for other instructions. e.g.
918 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
919 if (NoGap && LastReg && LastReg != Reg-1)
922 // Do not set a kill flag on values that are also marked as live-in. This
923 // happens with the @llvm-returnaddress intrinsic and with arguments
924 // passed in callee saved registers.
925 // Omitting the kill flags is conservatively correct even if the live-in
926 // is not used after all.
927 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
933 std::sort(Regs.begin(), Regs.end(), [&](const RegAndKill &LHS,
934 const RegAndKill &RHS) {
935 return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
938 if (Regs.size() > 1 || StrOpc== 0) {
939 MachineInstrBuilder MIB =
940 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
941 .addReg(ARM::SP).setMIFlags(MIFlags));
942 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
943 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
944 } else if (Regs.size() == 1) {
945 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
947 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
948 .addReg(ARM::SP).setMIFlags(MIFlags)
954 // Put any subsequent vpush instructions before this one: they will refer to
955 // higher register numbers so need to be pushed first in order to preserve
957 if (MI != MBB.begin())
962 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
963 MachineBasicBlock::iterator MI,
964 const std::vector<CalleeSavedInfo> &CSI,
965 unsigned LdmOpc, unsigned LdrOpc,
966 bool isVarArg, bool NoGap,
967 bool(*Func)(unsigned, bool),
968 unsigned NumAlignedDPRCS2Regs) const {
969 MachineFunction &MF = *MBB.getParent();
970 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
971 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
972 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
974 bool isTailCall = false;
975 bool isInterrupt = false;
977 if (MBB.end() != MI) {
978 DL = MI->getDebugLoc();
979 unsigned RetOpcode = MI->getOpcode();
980 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri);
982 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
984 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
985 RetOpcode == ARM::tTRAP;
988 SmallVector<unsigned, 4> Regs;
989 unsigned i = CSI.size();
991 unsigned LastReg = 0;
992 bool DeleteRet = false;
993 for (; i != 0; --i) {
994 unsigned Reg = CSI[i-1].getReg();
995 if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
997 // The aligned reloads from area DPRCS2 are not inserted here.
998 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1001 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
1002 !isTrap && STI.hasV5TOps()) {
1003 if (MBB.succ_empty()) {
1006 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
1008 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1009 // Fold the return instruction into the LDM.
1012 // If NoGap is true, pop consecutive registers and then leave the rest
1013 // for other instructions. e.g.
1014 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
1015 if (NoGap && LastReg && LastReg != Reg-1)
1019 Regs.push_back(Reg);
1025 std::sort(Regs.begin(), Regs.end(), [&](unsigned LHS, unsigned RHS) {
1026 return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
1029 if (Regs.size() > 1 || LdrOpc == 0) {
1030 MachineInstrBuilder MIB =
1031 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1033 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1034 MIB.addReg(Regs[i], getDefRegState(true));
1035 if (DeleteRet && MI != MBB.end()) {
1036 MIB.copyImplicitOps(*MI);
1037 MI->eraseFromParent();
1040 } else if (Regs.size() == 1) {
1041 // If we adjusted the reg to PC from LR above, switch it back here. We
1042 // only do that for LDM.
1043 if (Regs[0] == ARM::PC)
1045 MachineInstrBuilder MIB =
1046 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1047 .addReg(ARM::SP, RegState::Define)
1049 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1050 // that refactoring is complete (eventually).
1051 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1053 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1056 AddDefaultPred(MIB);
1060 // Put any subsequent vpop instructions after this one: they will refer to
1061 // higher register numbers so need to be popped afterwards.
1062 if (MI != MBB.end())
1067 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1068 /// starting from d8. Also insert stack realignment code and leave the stack
1069 /// pointer pointing to the d8 spill slot.
1070 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1071 MachineBasicBlock::iterator MI,
1072 unsigned NumAlignedDPRCS2Regs,
1073 const std::vector<CalleeSavedInfo> &CSI,
1074 const TargetRegisterInfo *TRI) {
1075 MachineFunction &MF = *MBB.getParent();
1076 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1077 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1078 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1079 MachineFrameInfo &MFI = MF.getFrameInfo();
1081 // Mark the D-register spill slots as properly aligned. Since MFI computes
1082 // stack slot layout backwards, this can actually mean that the d-reg stack
1083 // slot offsets can be wrong. The offset for d8 will always be correct.
1084 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1085 unsigned DNum = CSI[i].getReg() - ARM::D8;
1086 if (DNum > NumAlignedDPRCS2Regs - 1)
1088 int FI = CSI[i].getFrameIdx();
1089 // The even-numbered registers will be 16-byte aligned, the odd-numbered
1090 // registers will be 8-byte aligned.
1091 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
1093 // The stack slot for D8 needs to be maximally aligned because this is
1094 // actually the point where we align the stack pointer. MachineFrameInfo
1095 // computes all offsets relative to the incoming stack pointer which is a
1096 // bit weird when realigning the stack. Any extra padding for this
1097 // over-alignment is not realized because the code inserted below adjusts
1098 // the stack pointer by numregs * 8 before aligning the stack pointer.
1100 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1103 // Move the stack pointer to the d8 spill slot, and align it at the same
1104 // time. Leave the stack slot address in the scratch register r4.
1106 // sub r4, sp, #numregs * 8
1107 // bic r4, r4, #align - 1
1110 bool isThumb = AFI->isThumbFunction();
1111 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1112 AFI->setShouldRestoreSPFromFP(true);
1114 // sub r4, sp, #numregs * 8
1115 // The immediate is <= 64, so it doesn't need any special encoding.
1116 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1117 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1119 .addImm(8 * NumAlignedDPRCS2Regs)));
1121 unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
1122 // We must set parameter MustBeSingleInstruction to true, since
1123 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
1124 // stack alignment. Luckily, this can always be done since all ARM
1125 // architecture versions that support Neon also support the BFC
1127 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1130 // The stack pointer must be adjusted before spilling anything, otherwise
1131 // the stack slots could be clobbered by an interrupt handler.
1132 // Leave r4 live, it is used below.
1133 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1134 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1136 MIB = AddDefaultPred(MIB);
1140 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1141 // r4 holds the stack slot address.
1142 unsigned NextReg = ARM::D8;
1144 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1145 // The writeback is only needed when emitting two vst1.64 instructions.
1146 if (NumAlignedDPRCS2Regs >= 6) {
1147 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1148 &ARM::QQPRRegClass);
1149 MBB.addLiveIn(SupReg);
1150 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1152 .addReg(ARM::R4, RegState::Kill).addImm(16)
1154 .addReg(SupReg, RegState::ImplicitKill));
1156 NumAlignedDPRCS2Regs -= 4;
1159 // We won't modify r4 beyond this point. It currently points to the next
1160 // register to be spilled.
1161 unsigned R4BaseReg = NextReg;
1163 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1164 if (NumAlignedDPRCS2Regs >= 4) {
1165 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1166 &ARM::QQPRRegClass);
1167 MBB.addLiveIn(SupReg);
1168 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1169 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1170 .addReg(SupReg, RegState::ImplicitKill));
1172 NumAlignedDPRCS2Regs -= 4;
1175 // 16-byte aligned vst1.64 with 2 d-regs.
1176 if (NumAlignedDPRCS2Regs >= 2) {
1177 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1179 MBB.addLiveIn(SupReg);
1180 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1181 .addReg(ARM::R4).addImm(16).addReg(SupReg));
1183 NumAlignedDPRCS2Regs -= 2;
1186 // Finally, use a vanilla vstr.64 for the odd last register.
1187 if (NumAlignedDPRCS2Regs) {
1188 MBB.addLiveIn(NextReg);
1189 // vstr.64 uses addrmode5 which has an offset scale of 4.
1190 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1192 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1195 // The last spill instruction inserted should kill the scratch register r4.
1196 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1199 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1200 /// iterator to the following instruction.
1201 static MachineBasicBlock::iterator
1202 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1203 unsigned NumAlignedDPRCS2Regs) {
1204 // sub r4, sp, #numregs * 8
1205 // bic r4, r4, #align - 1
1208 assert(MI->mayStore() && "Expecting spill instruction");
1210 // These switches all fall through.
1211 switch(NumAlignedDPRCS2Regs) {
1214 assert(MI->mayStore() && "Expecting spill instruction");
1217 assert(MI->mayStore() && "Expecting spill instruction");
1221 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1227 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1228 /// starting from d8. These instructions are assumed to execute while the
1229 /// stack is still aligned, unlike the code inserted by emitPopInst.
1230 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1231 MachineBasicBlock::iterator MI,
1232 unsigned NumAlignedDPRCS2Regs,
1233 const std::vector<CalleeSavedInfo> &CSI,
1234 const TargetRegisterInfo *TRI) {
1235 MachineFunction &MF = *MBB.getParent();
1236 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1237 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1238 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1240 // Find the frame index assigned to d8.
1242 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1243 if (CSI[i].getReg() == ARM::D8) {
1244 D8SpillFI = CSI[i].getFrameIdx();
1248 // Materialize the address of the d8 spill slot into the scratch register r4.
1249 // This can be fairly complicated if the stack frame is large, so just use
1250 // the normal frame index elimination mechanism to do it. This code runs as
1251 // the initial part of the epilog where the stack and base pointers haven't
1252 // been changed yet.
1253 bool isThumb = AFI->isThumbFunction();
1254 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1256 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1257 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1258 .addFrameIndex(D8SpillFI).addImm(0)));
1260 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1261 unsigned NextReg = ARM::D8;
1263 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1264 if (NumAlignedDPRCS2Regs >= 6) {
1265 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1266 &ARM::QQPRRegClass);
1267 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1268 .addReg(ARM::R4, RegState::Define)
1269 .addReg(ARM::R4, RegState::Kill).addImm(16)
1270 .addReg(SupReg, RegState::ImplicitDefine));
1272 NumAlignedDPRCS2Regs -= 4;
1275 // We won't modify r4 beyond this point. It currently points to the next
1276 // register to be spilled.
1277 unsigned R4BaseReg = NextReg;
1279 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1280 if (NumAlignedDPRCS2Regs >= 4) {
1281 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1282 &ARM::QQPRRegClass);
1283 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1284 .addReg(ARM::R4).addImm(16)
1285 .addReg(SupReg, RegState::ImplicitDefine));
1287 NumAlignedDPRCS2Regs -= 4;
1290 // 16-byte aligned vld1.64 with 2 d-regs.
1291 if (NumAlignedDPRCS2Regs >= 2) {
1292 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1294 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1295 .addReg(ARM::R4).addImm(16));
1297 NumAlignedDPRCS2Regs -= 2;
1300 // Finally, use a vanilla vldr.64 for the remaining odd register.
1301 if (NumAlignedDPRCS2Regs)
1302 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1303 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
1305 // Last store kills r4.
1306 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1309 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1310 MachineBasicBlock::iterator MI,
1311 const std::vector<CalleeSavedInfo> &CSI,
1312 const TargetRegisterInfo *TRI) const {
1316 MachineFunction &MF = *MBB.getParent();
1317 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1319 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1320 unsigned PushOneOpc = AFI->isThumbFunction() ?
1321 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1322 unsigned FltOpc = ARM::VSTMDDB_UPD;
1323 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1324 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1325 MachineInstr::FrameSetup);
1326 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1327 MachineInstr::FrameSetup);
1328 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1329 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1331 // The code above does not insert spill code for the aligned DPRCS2 registers.
1332 // The stack realignment code will be inserted between the push instructions
1333 // and these spills.
1334 if (NumAlignedDPRCS2Regs)
1335 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1340 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1341 MachineBasicBlock::iterator MI,
1342 const std::vector<CalleeSavedInfo> &CSI,
1343 const TargetRegisterInfo *TRI) const {
1347 MachineFunction &MF = *MBB.getParent();
1348 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1349 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1350 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1352 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1353 // registers. Do that here instead.
1354 if (NumAlignedDPRCS2Regs)
1355 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1357 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1358 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1359 unsigned FltOpc = ARM::VLDMDIA_UPD;
1360 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1361 NumAlignedDPRCS2Regs);
1362 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1363 &isARMArea2Register, 0);
1364 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1365 &isARMArea1Register, 0);
1370 // FIXME: Make generic?
1371 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1372 const ARMBaseInstrInfo &TII) {
1373 unsigned FnSize = 0;
1374 for (auto &MBB : MF) {
1375 for (auto &MI : MBB)
1376 FnSize += TII.getInstSizeInBytes(MI);
1381 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1382 /// frames and return the stack size limit beyond which some of these
1383 /// instructions will require a scratch register during their expansion later.
1384 // FIXME: Move to TII?
1385 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1386 const TargetFrameLowering *TFI) {
1387 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1388 unsigned Limit = (1 << 12) - 1;
1389 for (auto &MBB : MF) {
1390 for (auto &MI : MBB) {
1391 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1392 if (!MI.getOperand(i).isFI())
1395 // When using ADDri to get the address of a stack object, 255 is the
1396 // largest offset guaranteed to fit in the immediate offset.
1397 if (MI.getOpcode() == ARM::ADDri) {
1398 Limit = std::min(Limit, (1U << 8) - 1);
1402 // Otherwise check the addressing mode.
1403 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1404 case ARMII::AddrMode3:
1405 case ARMII::AddrModeT2_i8:
1406 Limit = std::min(Limit, (1U << 8) - 1);
1408 case ARMII::AddrMode5:
1409 case ARMII::AddrModeT2_i8s4:
1410 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1412 case ARMII::AddrModeT2_i12:
1413 // i12 supports only positive offset so these will be converted to
1414 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1415 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1416 Limit = std::min(Limit, (1U << 8) - 1);
1418 case ARMII::AddrMode4:
1419 case ARMII::AddrMode6:
1420 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1421 // immediate offset for stack references.
1426 break; // At most one FI per instruction
1434 // In functions that realign the stack, it can be an advantage to spill the
1435 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1436 // instructions take alignment hints that can improve performance.
1439 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
1440 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1441 if (!SpillAlignedNEONRegs)
1444 // Naked functions don't spill callee-saved registers.
1445 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
1448 // We are planning to use NEON instructions vst1 / vld1.
1449 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1452 // Don't bother if the default stack alignment is sufficiently high.
1453 if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
1456 // Aligned spills require stack realignment.
1457 if (!static_cast<const ARMBaseRegisterInfo *>(
1458 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
1461 // We always spill contiguous d-registers starting from d8. Count how many
1462 // needs spilling. The register allocator will almost always use the
1463 // callee-saved registers in order, but it can happen that there are holes in
1464 // the range. Registers above the hole will be spilled to the standard DPRCS
1466 unsigned NumSpills = 0;
1467 for (; NumSpills < 8; ++NumSpills)
1468 if (!SavedRegs.test(ARM::D8 + NumSpills))
1471 // Don't do this for just one d-register. It's not worth it.
1475 // Spill the first NumSpills D-registers after realigning the stack.
1476 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1478 // A scratch register is required for the vst1 / vld1 instructions.
1479 SavedRegs.set(ARM::R4);
1482 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
1483 BitVector &SavedRegs,
1484 RegScavenger *RS) const {
1485 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1486 // This tells PEI to spill the FP as if it is any other callee-save register
1487 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1488 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1489 // to combine multiple loads / stores.
1490 bool CanEliminateFrame = true;
1491 bool CS1Spilled = false;
1492 bool LRSpilled = false;
1493 unsigned NumGPRSpills = 0;
1494 unsigned NumFPRSpills = 0;
1495 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1496 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1497 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1498 MF.getSubtarget().getRegisterInfo());
1499 const ARMBaseInstrInfo &TII =
1500 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1501 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1502 MachineFrameInfo &MFI = MF.getFrameInfo();
1503 MachineRegisterInfo &MRI = MF.getRegInfo();
1504 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1505 (void)TRI; // Silence unused warning in non-assert builds.
1506 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1508 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1509 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1510 // since it's not always possible to restore sp from fp in a single
1512 // FIXME: It will be better just to find spare register here.
1513 if (AFI->isThumb2Function() &&
1514 (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1515 SavedRegs.set(ARM::R4);
1517 if (AFI->isThumb1OnlyFunction()) {
1518 // Spill LR if Thumb1 function uses variable length argument lists.
1519 if (AFI->getArgRegsSaveSize() > 0)
1520 SavedRegs.set(ARM::LR);
1522 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1523 // for sure what the stack size will be, but for this, an estimate is good
1524 // enough. If there anything changes it, it'll be a spill, which implies
1525 // we've used all the registers and so R4 is already used, so not marking
1526 // it here will be OK.
1527 // FIXME: It will be better just to find spare register here.
1528 unsigned StackSize = MFI.estimateStackSize(MF);
1529 if (MFI.hasVarSizedObjects() || StackSize > 508)
1530 SavedRegs.set(ARM::R4);
1533 // See if we can spill vector registers to aligned stack.
1534 checkNumAlignedDPRCS2Regs(MF, SavedRegs);
1536 // Spill the BasePtr if it's used.
1537 if (RegInfo->hasBasePointer(MF))
1538 SavedRegs.set(RegInfo->getBaseRegister());
1540 // Don't spill FP if the frame can be eliminated. This is determined
1541 // by scanning the callee-save registers to see if any is modified.
1542 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1543 for (unsigned i = 0; CSRegs[i]; ++i) {
1544 unsigned Reg = CSRegs[i];
1545 bool Spilled = false;
1546 if (SavedRegs.test(Reg)) {
1548 CanEliminateFrame = false;
1551 if (!ARM::GPRRegClass.contains(Reg)) {
1553 if (ARM::SPRRegClass.contains(Reg))
1555 else if (ARM::DPRRegClass.contains(Reg))
1557 else if (ARM::QPRRegClass.contains(Reg))
1566 if (!STI.splitFramePushPop(MF)) {
1573 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1578 case ARM::R0: case ARM::R1:
1579 case ARM::R2: case ARM::R3:
1580 case ARM::R4: case ARM::R5:
1581 case ARM::R6: case ARM::R7:
1588 if (!STI.splitFramePushPop(MF)) {
1589 UnspilledCS1GPRs.push_back(Reg);
1594 case ARM::R0: case ARM::R1:
1595 case ARM::R2: case ARM::R3:
1596 case ARM::R4: case ARM::R5:
1597 case ARM::R6: case ARM::R7:
1599 UnspilledCS1GPRs.push_back(Reg);
1602 UnspilledCS2GPRs.push_back(Reg);
1608 bool ForceLRSpill = false;
1609 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1610 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1611 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1612 // use of BL to implement far jump. If it turns out that it's not needed
1613 // then the branch fix up path will undo it.
1614 if (FnSize >= (1 << 11)) {
1615 CanEliminateFrame = false;
1616 ForceLRSpill = true;
1620 // If any of the stack slot references may be out of range of an immediate
1621 // offset, make sure a register (or a spill slot) is available for the
1622 // register scavenger. Note that if we're indexing off the frame pointer, the
1623 // effective stack size is 4 bytes larger since the FP points to the stack
1624 // slot of the previous FP. Also, if we have variable sized objects in the
1625 // function, stack slot references will often be negative, and some of
1626 // our instructions are positive-offset only, so conservatively consider
1627 // that case to want a spill slot (or register) as well. Similarly, if
1628 // the function adjusts the stack pointer during execution and the
1629 // adjustments aren't already part of our stack size estimate, our offset
1630 // calculations may be off, so be conservative.
1631 // FIXME: We could add logic to be more precise about negative offsets
1632 // and which instructions will need a scratch register for them. Is it
1633 // worth the effort and added fragility?
1634 unsigned EstimatedStackSize =
1635 MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);
1637 if (AFI->hasStackFrame())
1638 EstimatedStackSize += 4;
1640 // If FP is not used, SP will be used to access arguments, so count the
1641 // size of arguments into the estimation.
1642 EstimatedStackSize += MF.getInfo<ARMFunctionInfo>()->getArgumentStackSize();
1644 EstimatedStackSize += 16; // For possible paddings.
1646 bool BigStack = EstimatedStackSize >= estimateRSStackSizeLimit(MF, this) ||
1647 MFI.hasVarSizedObjects() ||
1648 (MFI.adjustsStack() && !canSimplifyCallFramePseudos(MF));
1649 bool ExtraCSSpill = false;
1650 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1651 AFI->setHasStackFrame(true);
1654 SavedRegs.set(FramePtr);
1655 // If the frame pointer is required by the ABI, also spill LR so that we
1656 // emit a complete frame record.
1657 if (MF.getTarget().Options.DisableFramePointerElim(MF) && !LRSpilled) {
1658 SavedRegs.set(ARM::LR);
1661 auto LRPos = find(UnspilledCS1GPRs, ARM::LR);
1662 if (LRPos != UnspilledCS1GPRs.end())
1663 UnspilledCS1GPRs.erase(LRPos);
1665 auto FPPos = find(UnspilledCS1GPRs, FramePtr);
1666 if (FPPos != UnspilledCS1GPRs.end())
1667 UnspilledCS1GPRs.erase(FPPos);
1669 if (FramePtr == ARM::R7)
1673 if (AFI->isThumb1OnlyFunction()) {
1674 // For Thumb1-only targets, we need some low registers when we save and
1675 // restore the high registers (which aren't allocatable, but could be
1676 // used by inline assembly) because the push/pop instructions can not
1677 // access high registers. If necessary, we might need to push more low
1678 // registers to ensure that there is at least one free that can be used
1679 // for the saving & restoring, and preferably we should ensure that as
1680 // many as are needed are available so that fewer push/pop instructions
1683 // Low registers which are not currently pushed, but could be (r4-r7).
1684 SmallVector<unsigned, 4> AvailableRegs;
1686 // Unused argument registers (r0-r3) can be clobbered in the prologue for
1688 int EntryRegDeficit = 0;
1689 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
1690 if (!MF.getRegInfo().isLiveIn(Reg)) {
1692 DEBUG(dbgs() << PrintReg(Reg, TRI)
1693 << " is unused argument register, EntryRegDeficit = "
1694 << EntryRegDeficit << "\n");
1698 // Unused return registers can be clobbered in the epilogue for free.
1699 int ExitRegDeficit = AFI->getReturnRegsCount() - 4;
1700 DEBUG(dbgs() << AFI->getReturnRegsCount()
1701 << " return regs used, ExitRegDeficit = " << ExitRegDeficit
1704 int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);
1705 DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n");
1707 // r4-r6 can be used in the prologue if they are pushed by the first push
1709 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
1710 if (SavedRegs.test(Reg)) {
1712 DEBUG(dbgs() << PrintReg(Reg, TRI)
1713 << " is saved low register, RegDeficit = " << RegDeficit
1716 AvailableRegs.push_back(Reg);
1718 << PrintReg(Reg, TRI)
1719 << " is non-saved low register, adding to AvailableRegs\n");
1723 // r7 can be used if it is not being used as the frame pointer.
1725 if (SavedRegs.test(ARM::R7)) {
1727 DEBUG(dbgs() << "%R7 is saved low register, RegDeficit = "
1728 << RegDeficit << "\n");
1730 AvailableRegs.push_back(ARM::R7);
1732 << "%R7 is non-saved low register, adding to AvailableRegs\n");
1736 // Each of r8-r11 needs to be copied to a low register, then pushed.
1737 for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
1738 if (SavedRegs.test(Reg)) {
1740 DEBUG(dbgs() << PrintReg(Reg, TRI)
1741 << " is saved high register, RegDeficit = " << RegDeficit
1746 // LR can only be used by PUSH, not POP, and can't be used at all if the
1747 // llvm.returnaddress intrinsic is used. This is only worth doing if we
1748 // are more limited at function entry than exit.
1749 if ((EntryRegDeficit > ExitRegDeficit) &&
1750 !(MF.getRegInfo().isLiveIn(ARM::LR) &&
1751 MF.getFrameInfo().isReturnAddressTaken())) {
1752 if (SavedRegs.test(ARM::LR)) {
1754 DEBUG(dbgs() << "%LR is saved register, RegDeficit = " << RegDeficit
1757 AvailableRegs.push_back(ARM::LR);
1758 DEBUG(dbgs() << "%LR is not saved, adding to AvailableRegs\n");
1762 // If there are more high registers that need pushing than low registers
1763 // available, push some more low registers so that we can use fewer push
1764 // instructions. This might not reduce RegDeficit all the way to zero,
1765 // because we can only guarantee that r4-r6 are available, but r8-r11 may
1767 DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");
1768 for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) {
1769 unsigned Reg = AvailableRegs.pop_back_val();
1770 DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI)
1771 << " to make up reg deficit\n");
1775 ExtraCSSpill = true;
1776 UnspilledCS1GPRs.erase(find(UnspilledCS1GPRs, Reg));
1780 DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit << "\n");
1783 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1784 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1785 if (!LRSpilled && CS1Spilled) {
1786 SavedRegs.set(ARM::LR);
1788 SmallVectorImpl<unsigned>::iterator LRPos;
1789 LRPos = find(UnspilledCS1GPRs, (unsigned)ARM::LR);
1790 if (LRPos != UnspilledCS1GPRs.end())
1791 UnspilledCS1GPRs.erase(LRPos);
1793 ForceLRSpill = false;
1794 ExtraCSSpill = true;
1797 // If stack and double are 8-byte aligned and we are spilling an odd number
1798 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1799 // the integer and double callee save areas.
1800 DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n");
1801 unsigned TargetAlign = getStackAlignment();
1802 if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
1803 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1804 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1805 unsigned Reg = UnspilledCS1GPRs[i];
1806 // Don't spill high register if the function is thumb. In the case of
1807 // Windows on ARM, accept R11 (frame pointer)
1808 if (!AFI->isThumbFunction() ||
1809 (STI.isTargetWindows() && Reg == ARM::R11) ||
1810 isARMLowRegister(Reg) || Reg == ARM::LR) {
1812 DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI)
1813 << " to make up alignment\n");
1814 if (!MRI.isReserved(Reg))
1815 ExtraCSSpill = true;
1819 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1820 unsigned Reg = UnspilledCS2GPRs.front();
1822 DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI)
1823 << " to make up alignment\n");
1824 if (!MRI.isReserved(Reg))
1825 ExtraCSSpill = true;
1829 // Estimate if we might need to scavenge a register at some point in order
1830 // to materialize a stack offset. If so, either spill one additional
1831 // callee-saved register or reserve a special spill slot to facilitate
1832 // register scavenging. Thumb1 needs a spill slot for stack pointer
1833 // adjustments also, even when the frame itself is small.
1834 if (BigStack && !ExtraCSSpill) {
1835 // If any non-reserved CS register isn't spilled, just spill one or two
1836 // extra. That should take care of it!
1837 unsigned NumExtras = TargetAlign / 4;
1838 SmallVector<unsigned, 2> Extras;
1839 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1840 unsigned Reg = UnspilledCS1GPRs.back();
1841 UnspilledCS1GPRs.pop_back();
1842 if (!MRI.isReserved(Reg) &&
1843 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1845 Extras.push_back(Reg);
1849 // For non-Thumb1 functions, also check for hi-reg CS registers
1850 if (!AFI->isThumb1OnlyFunction()) {
1851 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1852 unsigned Reg = UnspilledCS2GPRs.back();
1853 UnspilledCS2GPRs.pop_back();
1854 if (!MRI.isReserved(Reg)) {
1855 Extras.push_back(Reg);
1860 if (Extras.size() && NumExtras == 0) {
1861 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1862 SavedRegs.set(Extras[i]);
1864 } else if (!AFI->isThumb1OnlyFunction()) {
1865 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1866 // closest to SP or frame pointer.
1867 assert(RS && "Register scavenging not provided");
1868 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1869 RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
1877 SavedRegs.set(ARM::LR);
1878 AFI->setLRIsSpilledForFarJump(true);
1882 MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(
1883 MachineFunction &MF, MachineBasicBlock &MBB,
1884 MachineBasicBlock::iterator I) const {
1885 const ARMBaseInstrInfo &TII =
1886 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1887 if (!hasReservedCallFrame(MF)) {
1888 // If we have alloca, convert as follows:
1889 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1890 // ADJCALLSTACKUP -> add, sp, sp, amount
1891 MachineInstr &Old = *I;
1892 DebugLoc dl = Old.getDebugLoc();
1893 unsigned Amount = Old.getOperand(0).getImm();
1895 // We need to keep the stack aligned properly. To do this, we round the
1896 // amount of space needed for the outgoing arguments up to the next
1897 // alignment boundary.
1898 Amount = alignSPAdjust(Amount);
1900 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1901 assert(!AFI->isThumb1OnlyFunction() &&
1902 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1903 bool isARM = !AFI->isThumbFunction();
1905 // Replace the pseudo instruction with a new instruction...
1906 unsigned Opc = Old.getOpcode();
1907 int PIdx = Old.findFirstPredOperandIdx();
1908 ARMCC::CondCodes Pred =
1909 (PIdx == -1) ? ARMCC::AL
1910 : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm();
1911 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1912 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1913 unsigned PredReg = Old.getOperand(2).getReg();
1914 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1917 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1918 unsigned PredReg = Old.getOperand(3).getReg();
1919 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1920 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1925 return MBB.erase(I);
1928 /// Get the minimum constant for ARM that is greater than or equal to the
1929 /// argument. In ARM, constants can have any value that can be produced by
1930 /// rotating an 8-bit value to the right by an even number of bits within a
1932 static uint32_t alignToARMConstant(uint32_t Value) {
1933 unsigned Shifted = 0;
1938 while (!(Value & 0xC0000000)) {
1943 bool Carry = (Value & 0x00FFFFFF);
1944 Value = ((Value & 0xFF000000) >> 24) + Carry;
1946 if (Value & 0x0000100)
1947 Value = Value & 0x000001FC;
1950 Value = Value >> (Shifted - 24);
1952 Value = Value << (24 - Shifted);
1957 // The stack limit in the TCB is set to this many bytes above the actual
1959 static const uint64_t kSplitStackAvailable = 256;
1961 // Adjust the function prologue to enable split stacks. This currently only
1962 // supports android and linux.
1964 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
1965 // must be well defined in order to allow for consistent implementations of the
1966 // __morestack helper function. The ABI is also not a normal ABI in that it
1967 // doesn't follow the normal calling conventions because this allows the
1968 // prologue of each function to be optimized further.
1970 // Currently, the ABI looks like (when calling __morestack)
1972 // * r4 holds the minimum stack size requested for this function call
1973 // * r5 holds the stack size of the arguments to the function
1974 // * the beginning of the function is 3 instructions after the call to
1977 // Implementations of __morestack should use r4 to allocate a new stack, r5 to
1978 // place the arguments on to the new stack, and the 3-instruction knowledge to
1979 // jump directly to the body of the function when working on the new stack.
1981 // An old (and possibly no longer compatible) implementation of __morestack for
1982 // ARM can be found at [1].
1984 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
1985 void ARMFrameLowering::adjustForSegmentedStacks(
1986 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1989 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
1990 bool Thumb = ST->isThumb();
1992 // Sadly, this currently doesn't support varargs, platforms other than
1993 // android/linux. Note that thumb1/thumb2 are support for android/linux.
1994 if (MF.getFunction()->isVarArg())
1995 report_fatal_error("Segmented stacks do not support vararg functions.");
1996 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
1997 report_fatal_error("Segmented stacks not supported on this platform.");
1999 MachineFrameInfo &MFI = MF.getFrameInfo();
2000 MachineModuleInfo &MMI = MF.getMMI();
2001 MCContext &Context = MMI.getContext();
2002 const MCRegisterInfo *MRI = Context.getRegisterInfo();
2003 const ARMBaseInstrInfo &TII =
2004 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2005 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
2008 uint64_t StackSize = MFI.getStackSize();
2010 // Do not generate a prologue for functions with a stack of size zero
2014 // Use R4 and R5 as scratch registers.
2015 // We save R4 and R5 before use and restore them before leaving the function.
2016 unsigned ScratchReg0 = ARM::R4;
2017 unsigned ScratchReg1 = ARM::R5;
2018 uint64_t AlignedStackSize;
2020 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
2021 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
2022 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
2023 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
2024 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
2026 // Grab everything that reaches PrologueMBB to update there liveness as well.
2027 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
2028 SmallVector<MachineBasicBlock *, 2> WalkList;
2029 WalkList.push_back(&PrologueMBB);
2032 MachineBasicBlock *CurMBB = WalkList.pop_back_val();
2033 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {
2034 if (BeforePrologueRegion.insert(PredBB).second)
2035 WalkList.push_back(PredBB);
2037 } while (!WalkList.empty());
2039 // The order in that list is important.
2040 // The blocks will all be inserted before PrologueMBB using that order.
2041 // Therefore the block that should appear first in the CFG should appear
2042 // first in the list.
2043 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
2046 for (MachineBasicBlock *B : AddedBlocks)
2047 BeforePrologueRegion.insert(B);
2049 for (const auto &LI : PrologueMBB.liveins()) {
2050 for (MachineBasicBlock *PredBB : BeforePrologueRegion)
2051 PredBB->addLiveIn(LI);
2054 // Remove the newly added blocks from the list, since we know
2055 // we do not have to do the following updates for them.
2056 for (MachineBasicBlock *B : AddedBlocks) {
2057 BeforePrologueRegion.erase(B);
2058 MF.insert(PrologueMBB.getIterator(), B);
2061 for (MachineBasicBlock *MBB : BeforePrologueRegion) {
2062 // Make sure the LiveIns are still sorted and unique.
2063 MBB->sortUniqueLiveIns();
2064 // Replace the edges to PrologueMBB by edges to the sequences
2065 // we are about to add.
2066 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
2069 // The required stack size that is aligned to ARM constant criterion.
2070 AlignedStackSize = alignToARMConstant(StackSize);
2072 // When the frame size is less than 256 we just compare the stack
2073 // boundary directly to the value of the stack pointer, per gcc.
2074 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
2076 // We will use two of the callee save registers as scratch registers so we
2077 // need to save those registers onto the stack.
2078 // We will use SR0 to hold stack limit and SR1 to hold the stack size
2079 // requested and arguments for __morestack().
2080 // SR0: Scratch Register #0
2081 // SR1: Scratch Register #1
2084 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)))
2085 .addReg(ScratchReg0).addReg(ScratchReg1);
2087 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
2088 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP))
2089 .addReg(ScratchReg0).addReg(ScratchReg1);
2092 // Emit the relevant DWARF information about the change in stack pointer as
2093 // well as where to find both r4 and r5 (the callee-save registers)
2095 MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
2096 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2097 .addCFIIndex(CFIIndex);
2098 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2099 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
2100 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2101 .addCFIIndex(CFIIndex);
2102 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2103 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
2104 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2105 .addCFIIndex(CFIIndex);
2109 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
2111 } else if (CompareStackPointer) {
2112 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
2113 .addReg(ARM::SP)).addReg(0);
2116 // sub SR1, sp, #StackSize
2117 if (!CompareStackPointer && Thumb) {
2119 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1))
2120 .addReg(ScratchReg1).addImm(AlignedStackSize));
2121 } else if (!CompareStackPointer) {
2122 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
2123 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);
2126 if (Thumb && ST->isThumb1Only()) {
2127 unsigned PCLabelId = ARMFI->createPICLabelUId();
2128 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
2129 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0);
2130 MachineConstantPool *MCP = MF.getConstantPool();
2131 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4);
2133 // ldr SR0, [pc, offset(STACK_LIMIT)]
2134 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
2135 .addConstantPoolIndex(CPI));
2138 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
2139 .addReg(ScratchReg0).addImm(0));
2141 // Get TLS base address from the coprocessor
2142 // mrc p15, #0, SR0, c13, c0, #3
2143 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
2150 // Use the last tls slot on android and a private field of the TCP on linux.
2151 assert(ST->isTargetAndroid() || ST->isTargetLinux());
2152 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
2154 // Get the stack limit from the right offset
2155 // ldr SR0, [sr0, #4 * TlsOffset]
2156 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
2157 .addReg(ScratchReg0).addImm(4 * TlsOffset));
2160 // Compare stack limit with stack size requested.
2162 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
2163 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode))
2164 .addReg(ScratchReg0)
2165 .addReg(ScratchReg1));
2167 // This jump is taken if StackLimit < SP - stack required.
2168 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
2169 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2174 // Calling __morestack(StackSize, Size of stack arguments).
2175 // __morestack knows that the stack size requested is in SR0(r4)
2176 // and amount size of stack arguments is in SR1(r5).
2178 // Pass first argument for the __morestack by Scratch Register #0.
2179 // The amount size of stack required
2181 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8),
2182 ScratchReg0)).addImm(AlignedStackSize));
2184 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
2185 .addImm(AlignedStackSize)).addReg(0);
2187 // Pass second argument for the __morestack by Scratch Register #1.
2188 // The amount size of stack consumed to save function arguments.
2191 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1))
2192 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())));
2194 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
2195 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))
2199 // push {lr} - Save return address of this function.
2201 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)))
2204 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2205 .addReg(ARM::SP, RegState::Define)
2210 // Emit the DWARF info about the change in stack as well as where to find the
2211 // previous link register
2213 MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2214 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2215 .addCFIIndex(CFIIndex);
2216 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2217 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2218 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2219 .addCFIIndex(CFIIndex);
2221 // Call __morestack().
2223 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL)))
2224 .addExternalSymbol("__morestack");
2226 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2227 .addExternalSymbol("__morestack");
2230 // pop {lr} - Restore return address of this original function.
2232 if (ST->isThumb1Only()) {
2233 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2234 .addReg(ScratchReg0);
2235 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2236 .addReg(ScratchReg0));
2238 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2239 .addReg(ARM::LR, RegState::Define)
2240 .addReg(ARM::SP, RegState::Define)
2245 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2246 .addReg(ARM::SP, RegState::Define)
2251 // Restore SR0 and SR1 in case of __morestack() was called.
2252 // __morestack() will skip PostStackMBB block so we need to restore
2253 // scratch registers from here.
2256 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2257 .addReg(ScratchReg0)
2258 .addReg(ScratchReg1);
2260 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2261 .addReg(ARM::SP, RegState::Define)
2263 .addReg(ScratchReg0)
2264 .addReg(ScratchReg1);
2267 // Update the CFA offset now that we've popped
2268 CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2269 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2270 .addCFIIndex(CFIIndex);
2272 // bx lr - Return from this function.
2273 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET;
2274 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode)));
2276 // Restore SR0 and SR1 in case of __morestack() was not called.
2279 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)))
2280 .addReg(ScratchReg0)
2281 .addReg(ScratchReg1);
2283 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2284 .addReg(ARM::SP, RegState::Define)
2286 .addReg(ScratchReg0)
2287 .addReg(ScratchReg1);
2290 // Update the CFA offset now that we've popped
2291 CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2292 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2293 .addCFIIndex(CFIIndex);
2295 // Tell debuggers that r4 and r5 are now the same as they were in the
2296 // previous function, that they're the "Same Value".
2297 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2298 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2299 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2300 .addCFIIndex(CFIIndex);
2301 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2302 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2303 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2304 .addCFIIndex(CFIIndex);
2306 // Organizing MBB lists
2307 PostStackMBB->addSuccessor(&PrologueMBB);
2309 AllocMBB->addSuccessor(PostStackMBB);
2311 GetMBB->addSuccessor(PostStackMBB);
2312 GetMBB->addSuccessor(AllocMBB);
2314 McrMBB->addSuccessor(GetMBB);
2316 PrevStackMBB->addSuccessor(McrMBB);
2318 #ifdef EXPENSIVE_CHECKS