1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMTargetMachine.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "Utils/ARMBaseInfo.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/CodeGen/TargetLowering.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "arm-isel"
43 DisableShifterOp("disable-shifter-op", cl::Hidden,
44 cl::desc("Disable isel of shifter-op"),
47 //===--------------------------------------------------------------------===//
48 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
49 /// instructions for SelectionDAG operations.
53 class ARMDAGToDAGISel : public SelectionDAGISel {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when generating code for different targets.
56 const ARMSubtarget *Subtarget;
59 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
60 : SelectionDAGISel(tm, OptLevel) {}
62 bool runOnMachineFunction(MachineFunction &MF) override {
63 // Reset the subtarget each time through.
64 Subtarget = &MF.getSubtarget<ARMSubtarget>();
65 SelectionDAGISel::runOnMachineFunction(MF);
69 StringRef getPassName() const override { return "ARM Instruction Selection"; }
71 void PreprocessISelDAG() override;
73 /// getI32Imm - Return a target constant of type i32 with the specified
75 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
76 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
79 void Select(SDNode *N) override;
81 bool hasNoVMLxHazardUse(SDNode *N) const;
82 bool isShifterOpProfitable(const SDValue &Shift,
83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
84 bool SelectRegShifterOperand(SDValue N, SDValue &A,
85 SDValue &B, SDValue &C,
86 bool CheckProfitability = true);
87 bool SelectImmShifterOperand(SDValue N, SDValue &A,
88 SDValue &B, bool CheckProfitability = true);
89 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
90 SDValue &B, SDValue &C) {
91 // Don't apply the profitability check
92 return SelectRegShifterOperand(N, A, B, C, false);
94 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
96 // Don't apply the profitability check
97 return SelectImmShifterOperand(N, A, B, false);
100 bool SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out);
102 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
103 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
105 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
106 const ConstantSDNode *CN = cast<ConstantSDNode>(N);
107 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32);
108 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
112 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
115 SDValue &Offset, SDValue &Opc);
116 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
117 SDValue &Offset, SDValue &Opc);
118 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
119 bool SelectAddrMode3(SDValue N, SDValue &Base,
120 SDValue &Offset, SDValue &Opc);
121 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
122 SDValue &Offset, SDValue &Opc);
123 bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
124 int Lwb, int Upb, bool FP16);
125 bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset);
126 bool SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset);
127 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
128 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
130 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
132 // Thumb Addressing Modes:
133 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
134 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
136 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
138 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
140 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
142 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
144 // Thumb 2 Addressing Modes:
145 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
146 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
148 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
150 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
151 SDValue &OffReg, SDValue &ShImm);
152 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
154 inline bool is_so_imm(unsigned Imm) const {
155 return ARM_AM::getSOImmVal(Imm) != -1;
158 inline bool is_so_imm_not(unsigned Imm) const {
159 return ARM_AM::getSOImmVal(~Imm) != -1;
162 inline bool is_t2_so_imm(unsigned Imm) const {
163 return ARM_AM::getT2SOImmVal(Imm) != -1;
166 inline bool is_t2_so_imm_not(unsigned Imm) const {
167 return ARM_AM::getT2SOImmVal(~Imm) != -1;
170 // Include the pieces autogenerated from the target description.
171 #include "ARMGenDAGISel.inc"
174 void transferMemOperands(SDNode *Src, SDNode *Dst);
176 /// Indexed (pre/post inc/dec) load matching code for ARM.
177 bool tryARMIndexedLoad(SDNode *N);
178 bool tryT1IndexedLoad(SDNode *N);
179 bool tryT2IndexedLoad(SDNode *N);
181 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
182 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
183 /// loads of D registers and even subregs and odd subregs of Q registers.
184 /// For NumVecs <= 2, QOpcodes1 is not used.
185 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
186 const uint16_t *DOpcodes, const uint16_t *QOpcodes0,
187 const uint16_t *QOpcodes1);
189 /// SelectVST - Select NEON store intrinsics. NumVecs should
190 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
191 /// stores of D registers and even subregs and odd subregs of Q registers.
192 /// For NumVecs <= 2, QOpcodes1 is not used.
193 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
194 const uint16_t *DOpcodes, const uint16_t *QOpcodes0,
195 const uint16_t *QOpcodes1);
197 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
198 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
199 /// load/store of D registers and Q registers.
200 void SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
201 unsigned NumVecs, const uint16_t *DOpcodes,
202 const uint16_t *QOpcodes);
204 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
205 /// should be 1, 2, 3 or 4. The opcode array specifies the instructions used
206 /// for loading D registers.
207 void SelectVLDDup(SDNode *N, bool IsIntrinsic, bool isUpdating,
208 unsigned NumVecs, const uint16_t *DOpcodes,
209 const uint16_t *QOpcodes0 = nullptr,
210 const uint16_t *QOpcodes1 = nullptr);
212 /// Try to select SBFX/UBFX instructions for ARM.
213 bool tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
215 // Select special operations if node forms integer ABS pattern
216 bool tryABSOp(SDNode *N);
218 bool tryReadRegister(SDNode *N);
219 bool tryWriteRegister(SDNode *N);
221 bool tryInlineAsm(SDNode *N);
223 void SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI);
225 void SelectCMP_SWAP(SDNode *N);
227 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
228 /// inline asm expressions.
229 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
230 std::vector<SDValue> &OutOps) override;
232 // Form pairs of consecutive R, S, D, or Q registers.
233 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
234 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
235 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
236 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
238 // Form sequences of 4 consecutive S, D, or Q registers.
239 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
240 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
241 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
243 // Get the alignment operand for a NEON VLD or VST instruction.
244 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
247 /// Returns the number of instructions required to materialize the given
248 /// constant in a register, or 3 if a literal pool load is needed.
249 unsigned ConstantMaterializationCost(unsigned Val) const;
251 /// Checks if N is a multiplication by a constant where we can extract out a
252 /// power of two from the constant so that it can be used in a shift, but only
253 /// if it simplifies the materialization of the constant. Returns true if it
254 /// is, and assigns to PowerOfTwo the power of two that should be extracted
255 /// out and to NewMulConst the new constant to be multiplied by.
256 bool canExtractShiftFromMul(const SDValue &N, unsigned MaxShift,
257 unsigned &PowerOfTwo, SDValue &NewMulConst) const;
259 /// Replace N with M in CurDAG, in a way that also ensures that M gets
260 /// selected when N would have been selected.
261 void replaceDAGValue(const SDValue &N, SDValue M);
265 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
266 /// operand. If so Imm will receive the 32-bit value.
267 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
268 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
269 Imm = cast<ConstantSDNode>(N)->getZExtValue();
275 // isInt32Immediate - This method tests to see if a constant operand.
276 // If so Imm will receive the 32 bit value.
277 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
278 return isInt32Immediate(N.getNode(), Imm);
281 // isOpcWithIntImmediate - This method tests to see if the node is a specific
282 // opcode and that it has a immediate integer right operand.
283 // If so Imm will receive the 32 bit value.
284 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
285 return N->getOpcode() == Opc &&
286 isInt32Immediate(N->getOperand(1).getNode(), Imm);
289 /// Check whether a particular node is a constant value representable as
290 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
292 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
293 static bool isScaledConstantInRange(SDValue Node, int Scale,
294 int RangeMin, int RangeMax,
295 int &ScaledConstant) {
296 assert(Scale > 0 && "Invalid scale!");
298 // Check that this is a constant.
299 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
303 ScaledConstant = (int) C->getZExtValue();
304 if ((ScaledConstant % Scale) != 0)
307 ScaledConstant /= Scale;
308 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
311 void ARMDAGToDAGISel::PreprocessISelDAG() {
312 if (!Subtarget->hasV6T2Ops())
315 bool isThumb2 = Subtarget->isThumb();
316 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
317 E = CurDAG->allnodes_end(); I != E; ) {
318 SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
320 if (N->getOpcode() != ISD::ADD)
323 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
324 // leading zeros, followed by consecutive set bits, followed by 1 or 2
325 // trailing zeros, e.g. 1020.
326 // Transform the expression to
327 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
328 // of trailing zeros of c2. The left shift would be folded as an shifter
329 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
332 SDValue N0 = N->getOperand(0);
333 SDValue N1 = N->getOperand(1);
334 unsigned And_imm = 0;
335 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
336 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
342 // Check if the AND mask is an immediate of the form: 000.....1111111100
343 unsigned TZ = countTrailingZeros(And_imm);
344 if (TZ != 1 && TZ != 2)
345 // Be conservative here. Shifter operands aren't always free. e.g. On
346 // Swift, left shifter operand of 1 / 2 for free but others are not.
348 // ubfx r3, r1, #16, #8
349 // ldr.w r3, [r0, r3, lsl #2]
352 // and.w r2, r9, r1, lsr #14
356 if (And_imm & (And_imm + 1))
359 // Look for (and (srl X, c1), c2).
360 SDValue Srl = N1.getOperand(0);
361 unsigned Srl_imm = 0;
362 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
366 // Make sure first operand is not a shifter operand which would prevent
367 // folding of the left shift.
372 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1))
375 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
376 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
380 // Now make the transformation.
381 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
383 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl),
385 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
387 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32));
388 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
389 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32));
390 CurDAG->UpdateNodeOperands(N, N0, N1);
394 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
395 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
396 /// least on current ARM implementations) which should be avoidded.
397 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
398 if (OptLevel == CodeGenOpt::None)
401 if (!Subtarget->hasVMLxHazards())
407 SDNode *Use = *N->use_begin();
408 if (Use->getOpcode() == ISD::CopyToReg)
410 if (Use->isMachineOpcode()) {
411 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
412 CurDAG->getSubtarget().getInstrInfo());
414 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
417 unsigned Opcode = MCID.getOpcode();
418 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
420 // vmlx feeding into another vmlx. We actually want to unfold
421 // the use later in the MLxExpansion pass. e.g.
423 // vmla (stall 8 cycles)
428 // This adds up to about 18 - 19 cycles.
431 // vmul (stall 4 cycles)
432 // vadd adds up to about 14 cycles.
433 return TII->isFpMLxInstruction(Opcode);
439 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
440 ARM_AM::ShiftOpc ShOpcVal,
442 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
444 if (Shift.hasOneUse())
447 return ShOpcVal == ARM_AM::lsl &&
448 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
451 unsigned ARMDAGToDAGISel::ConstantMaterializationCost(unsigned Val) const {
452 if (Subtarget->isThumb()) {
453 if (Val <= 255) return 1; // MOV
454 if (Subtarget->hasV6T2Ops() &&
455 (Val <= 0xffff || ARM_AM::getT2SOImmValSplatVal(Val) != -1))
457 if (Val <= 510) return 2; // MOV + ADDi8
458 if (~Val <= 255) return 2; // MOV + MVN
459 if (ARM_AM::isThumbImmShiftedVal(Val)) return 2; // MOV + LSL
461 if (ARM_AM::getSOImmVal(Val) != -1) return 1; // MOV
462 if (ARM_AM::getSOImmVal(~Val) != -1) return 1; // MVN
463 if (Subtarget->hasV6T2Ops() && Val <= 0xffff) return 1; // MOVW
464 if (ARM_AM::isSOImmTwoPartVal(Val)) return 2; // two instrs
466 if (Subtarget->useMovt(*MF)) return 2; // MOVW + MOVT
467 return 3; // Literal pool load
470 bool ARMDAGToDAGISel::canExtractShiftFromMul(const SDValue &N,
472 unsigned &PowerOfTwo,
473 SDValue &NewMulConst) const {
474 assert(N.getOpcode() == ISD::MUL);
475 assert(MaxShift > 0);
477 // If the multiply is used in more than one place then changing the constant
478 // will make other uses incorrect, so don't.
479 if (!N.hasOneUse()) return false;
480 // Check if the multiply is by a constant
481 ConstantSDNode *MulConst = dyn_cast<ConstantSDNode>(N.getOperand(1));
482 if (!MulConst) return false;
483 // If the constant is used in more than one place then modifying it will mean
484 // we need to materialize two constants instead of one, which is a bad idea.
485 if (!MulConst->hasOneUse()) return false;
486 unsigned MulConstVal = MulConst->getZExtValue();
487 if (MulConstVal == 0) return false;
489 // Find the largest power of 2 that MulConstVal is a multiple of
490 PowerOfTwo = MaxShift;
491 while ((MulConstVal % (1 << PowerOfTwo)) != 0) {
493 if (PowerOfTwo == 0) return false;
496 // Only optimise if the new cost is better
497 unsigned NewMulConstVal = MulConstVal / (1 << PowerOfTwo);
498 NewMulConst = CurDAG->getConstant(NewMulConstVal, SDLoc(N), MVT::i32);
499 unsigned OldCost = ConstantMaterializationCost(MulConstVal);
500 unsigned NewCost = ConstantMaterializationCost(NewMulConstVal);
501 return NewCost < OldCost;
504 void ARMDAGToDAGISel::replaceDAGValue(const SDValue &N, SDValue M) {
505 CurDAG->RepositionNode(N.getNode()->getIterator(), M.getNode());
509 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
512 bool CheckProfitability) {
513 if (DisableShifterOp)
516 // If N is a multiply-by-constant and it's profitable to extract a shift and
517 // use it in a shifted operand do so.
518 if (N.getOpcode() == ISD::MUL) {
519 unsigned PowerOfTwo = 0;
521 if (canExtractShiftFromMul(N, 31, PowerOfTwo, NewMulConst)) {
522 HandleSDNode Handle(N);
524 replaceDAGValue(N.getOperand(1), NewMulConst);
525 BaseReg = Handle.getValue();
526 Opc = CurDAG->getTargetConstant(
527 ARM_AM::getSORegOpc(ARM_AM::lsl, PowerOfTwo), Loc, MVT::i32);
532 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
534 // Don't match base register only case. That is matched to a separate
535 // lower complexity pattern with explicit register operand.
536 if (ShOpcVal == ARM_AM::no_shift) return false;
538 BaseReg = N.getOperand(0);
539 unsigned ShImmVal = 0;
540 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
541 if (!RHS) return false;
542 ShImmVal = RHS->getZExtValue() & 31;
543 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
548 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
552 bool CheckProfitability) {
553 if (DisableShifterOp)
556 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
558 // Don't match base register only case. That is matched to a separate
559 // lower complexity pattern with explicit register operand.
560 if (ShOpcVal == ARM_AM::no_shift) return false;
562 BaseReg = N.getOperand(0);
563 unsigned ShImmVal = 0;
564 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
565 if (RHS) return false;
567 ShReg = N.getOperand(1);
568 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
570 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
575 // Determine whether an ISD::OR's operands are suitable to turn the operation
576 // into an addition, which often has more compact encodings.
577 bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
578 assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
580 return CurDAG->haveNoCommonBitsSet(N, Parent->getOperand(1));
584 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
587 // Match simple R + imm12 operands.
590 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
591 !CurDAG->isBaseWithConstantOffset(N)) {
592 if (N.getOpcode() == ISD::FrameIndex) {
593 // Match frame index.
594 int FI = cast<FrameIndexSDNode>(N)->getIndex();
595 Base = CurDAG->getTargetFrameIndex(
596 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
597 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
601 if (N.getOpcode() == ARMISD::Wrapper &&
602 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
603 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
604 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
605 Base = N.getOperand(0);
608 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
612 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
613 int RHSC = (int)RHS->getSExtValue();
614 if (N.getOpcode() == ISD::SUB)
617 if (RHSC > -0x1000 && RHSC < 0x1000) { // 12 bits
618 Base = N.getOperand(0);
619 if (Base.getOpcode() == ISD::FrameIndex) {
620 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
621 Base = CurDAG->getTargetFrameIndex(
622 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
624 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
631 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
637 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
639 if (N.getOpcode() == ISD::MUL &&
640 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
641 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
642 // X * [3,5,9] -> X + X * [2,4,8] etc.
643 int RHSC = (int)RHS->getZExtValue();
646 ARM_AM::AddrOpc AddSub = ARM_AM::add;
648 AddSub = ARM_AM::sub;
651 if (isPowerOf2_32(RHSC)) {
652 unsigned ShAmt = Log2_32(RHSC);
653 Base = Offset = N.getOperand(0);
654 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
663 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
664 // ISD::OR that is equivalent to an ISD::ADD.
665 !CurDAG->isBaseWithConstantOffset(N))
668 // Leave simple R +/- imm12 operands for LDRi12
669 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
671 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
672 -0x1000+1, 0x1000, RHSC)) // 12 bits.
676 // Otherwise this is R +/- [possibly shifted] R.
677 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
678 ARM_AM::ShiftOpc ShOpcVal =
679 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
682 Base = N.getOperand(0);
683 Offset = N.getOperand(1);
685 if (ShOpcVal != ARM_AM::no_shift) {
686 // Check to see if the RHS of the shift is a constant, if not, we can't fold
688 if (ConstantSDNode *Sh =
689 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
690 ShAmt = Sh->getZExtValue();
691 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
692 Offset = N.getOperand(1).getOperand(0);
695 ShOpcVal = ARM_AM::no_shift;
698 ShOpcVal = ARM_AM::no_shift;
702 // Try matching (R shl C) + (R).
703 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
704 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
705 N.getOperand(0).hasOneUse())) {
706 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
707 if (ShOpcVal != ARM_AM::no_shift) {
708 // Check to see if the RHS of the shift is a constant, if not, we can't
710 if (ConstantSDNode *Sh =
711 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
712 ShAmt = Sh->getZExtValue();
713 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
714 Offset = N.getOperand(0).getOperand(0);
715 Base = N.getOperand(1);
718 ShOpcVal = ARM_AM::no_shift;
721 ShOpcVal = ARM_AM::no_shift;
726 // If Offset is a multiply-by-constant and it's profitable to extract a shift
727 // and use it in a shifted operand do so.
728 if (Offset.getOpcode() == ISD::MUL && N.hasOneUse()) {
729 unsigned PowerOfTwo = 0;
731 if (canExtractShiftFromMul(Offset, 31, PowerOfTwo, NewMulConst)) {
732 HandleSDNode Handle(Offset);
733 replaceDAGValue(Offset.getOperand(1), NewMulConst);
734 Offset = Handle.getValue();
736 ShOpcVal = ARM_AM::lsl;
740 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
745 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
746 SDValue &Offset, SDValue &Opc) {
747 unsigned Opcode = Op->getOpcode();
748 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
749 ? cast<LoadSDNode>(Op)->getAddressingMode()
750 : cast<StoreSDNode>(Op)->getAddressingMode();
751 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
752 ? ARM_AM::add : ARM_AM::sub;
754 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
758 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
760 if (ShOpcVal != ARM_AM::no_shift) {
761 // Check to see if the RHS of the shift is a constant, if not, we can't fold
763 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
764 ShAmt = Sh->getZExtValue();
765 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
766 Offset = N.getOperand(0);
769 ShOpcVal = ARM_AM::no_shift;
772 ShOpcVal = ARM_AM::no_shift;
776 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
781 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
782 SDValue &Offset, SDValue &Opc) {
783 unsigned Opcode = Op->getOpcode();
784 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
785 ? cast<LoadSDNode>(Op)->getAddressingMode()
786 : cast<StoreSDNode>(Op)->getAddressingMode();
787 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
788 ? ARM_AM::add : ARM_AM::sub;
790 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
791 if (AddSub == ARM_AM::sub) Val *= -1;
792 Offset = CurDAG->getRegister(0, MVT::i32);
793 Opc = CurDAG->getTargetConstant(Val, SDLoc(Op), MVT::i32);
801 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
802 SDValue &Offset, SDValue &Opc) {
803 unsigned Opcode = Op->getOpcode();
804 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
805 ? cast<LoadSDNode>(Op)->getAddressingMode()
806 : cast<StoreSDNode>(Op)->getAddressingMode();
807 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
808 ? ARM_AM::add : ARM_AM::sub;
810 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
811 Offset = CurDAG->getRegister(0, MVT::i32);
812 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
814 SDLoc(Op), MVT::i32);
821 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
826 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
827 SDValue &Base, SDValue &Offset,
829 if (N.getOpcode() == ISD::SUB) {
830 // X - C is canonicalize to X + -C, no need to handle it here.
831 Base = N.getOperand(0);
832 Offset = N.getOperand(1);
833 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0), SDLoc(N),
838 if (!CurDAG->isBaseWithConstantOffset(N)) {
840 if (N.getOpcode() == ISD::FrameIndex) {
841 int FI = cast<FrameIndexSDNode>(N)->getIndex();
842 Base = CurDAG->getTargetFrameIndex(
843 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
845 Offset = CurDAG->getRegister(0, MVT::i32);
846 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N),
851 // If the RHS is +/- imm8, fold into addr mode.
853 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
854 -256 + 1, 256, RHSC)) { // 8 bits.
855 Base = N.getOperand(0);
856 if (Base.getOpcode() == ISD::FrameIndex) {
857 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
858 Base = CurDAG->getTargetFrameIndex(
859 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
861 Offset = CurDAG->getRegister(0, MVT::i32);
863 ARM_AM::AddrOpc AddSub = ARM_AM::add;
865 AddSub = ARM_AM::sub;
868 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC), SDLoc(N),
873 Base = N.getOperand(0);
874 Offset = N.getOperand(1);
875 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N),
880 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
881 SDValue &Offset, SDValue &Opc) {
882 unsigned Opcode = Op->getOpcode();
883 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
884 ? cast<LoadSDNode>(Op)->getAddressingMode()
885 : cast<StoreSDNode>(Op)->getAddressingMode();
886 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
887 ? ARM_AM::add : ARM_AM::sub;
889 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
890 Offset = CurDAG->getRegister(0, MVT::i32);
891 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), SDLoc(Op),
897 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), SDLoc(Op),
902 bool ARMDAGToDAGISel::IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
903 int Lwb, int Upb, bool FP16) {
904 if (!CurDAG->isBaseWithConstantOffset(N)) {
906 if (N.getOpcode() == ISD::FrameIndex) {
907 int FI = cast<FrameIndexSDNode>(N)->getIndex();
908 Base = CurDAG->getTargetFrameIndex(
909 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
910 } else if (N.getOpcode() == ARMISD::Wrapper &&
911 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
912 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
913 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
914 Base = N.getOperand(0);
916 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
921 // If the RHS is +/- imm8, fold into addr mode.
923 const int Scale = FP16 ? 2 : 4;
925 if (isScaledConstantInRange(N.getOperand(1), Scale, Lwb, Upb, RHSC)) {
926 Base = N.getOperand(0);
927 if (Base.getOpcode() == ISD::FrameIndex) {
928 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
929 Base = CurDAG->getTargetFrameIndex(
930 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
933 ARM_AM::AddrOpc AddSub = ARM_AM::add;
935 AddSub = ARM_AM::sub;
940 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5FP16Opc(AddSub, RHSC),
943 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
952 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5FP16Opc(ARM_AM::add, 0),
955 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
961 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
962 SDValue &Base, SDValue &Offset) {
965 return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ false);
968 bool ARMDAGToDAGISel::SelectAddrMode5FP16(SDValue N,
969 SDValue &Base, SDValue &Offset) {
972 return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ true);
975 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
979 unsigned Alignment = 0;
981 MemSDNode *MemN = cast<MemSDNode>(Parent);
983 if (isa<LSBaseSDNode>(MemN) ||
984 ((MemN->getOpcode() == ARMISD::VST1_UPD ||
985 MemN->getOpcode() == ARMISD::VLD1_UPD) &&
986 MemN->getConstantOperandVal(MemN->getNumOperands() - 1) == 1)) {
987 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
988 // The maximum alignment is equal to the memory size being referenced.
989 unsigned MMOAlign = MemN->getAlignment();
990 unsigned MemSize = MemN->getMemoryVT().getSizeInBits() / 8;
991 if (MMOAlign >= MemSize && MemSize > 1)
994 // All other uses of addrmode6 are for intrinsics. For now just record
995 // the raw alignment value; it will be refined later based on the legal
996 // alignment operands for the intrinsic.
997 Alignment = MemN->getAlignment();
1000 Align = CurDAG->getTargetConstant(Alignment, SDLoc(N), MVT::i32);
1004 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1006 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1007 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1008 if (AM != ISD::POST_INC)
1011 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1012 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1013 Offset = CurDAG->getRegister(0, MVT::i32);
1018 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1019 SDValue &Offset, SDValue &Label) {
1020 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1021 Offset = N.getOperand(0);
1022 SDValue N1 = N.getOperand(1);
1023 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1024 SDLoc(N), MVT::i32);
1032 //===----------------------------------------------------------------------===//
1033 // Thumb Addressing Modes
1034 //===----------------------------------------------------------------------===//
1036 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1037 SDValue &Base, SDValue &Offset){
1038 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1039 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1040 if (!NC || !NC->isNullValue())
1047 Base = N.getOperand(0);
1048 Offset = N.getOperand(1);
1053 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1054 SDValue &Base, SDValue &OffImm) {
1055 if (!CurDAG->isBaseWithConstantOffset(N)) {
1056 if (N.getOpcode() == ISD::ADD) {
1057 return false; // We want to select register offset instead
1058 } else if (N.getOpcode() == ARMISD::Wrapper &&
1059 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
1060 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
1061 N.getOperand(0).getOpcode() != ISD::TargetConstantPool &&
1062 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
1063 Base = N.getOperand(0);
1068 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1072 // If the RHS is + imm5 * scale, fold into addr mode.
1074 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1075 Base = N.getOperand(0);
1076 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1080 // Offset is too large, so use register offset instead.
1085 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1087 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1091 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1093 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1097 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1099 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1102 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1103 SDValue &Base, SDValue &OffImm) {
1104 if (N.getOpcode() == ISD::FrameIndex) {
1105 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1106 // Only multiples of 4 are allowed for the offset, so the frame object
1107 // alignment must be at least 4.
1108 MachineFrameInfo &MFI = MF->getFrameInfo();
1109 if (MFI.getObjectAlignment(FI) < 4)
1110 MFI.setObjectAlignment(FI, 4);
1111 Base = CurDAG->getTargetFrameIndex(
1112 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1113 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1117 if (!CurDAG->isBaseWithConstantOffset(N))
1120 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1121 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1122 (LHSR && LHSR->getReg() == ARM::SP)) {
1123 // If the RHS is + imm8 * scale, fold into addr mode.
1125 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1126 Base = N.getOperand(0);
1127 if (Base.getOpcode() == ISD::FrameIndex) {
1128 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1129 // For LHS+RHS to result in an offset that's a multiple of 4 the object
1130 // indexed by the LHS must be 4-byte aligned.
1131 MachineFrameInfo &MFI = MF->getFrameInfo();
1132 if (MFI.getObjectAlignment(FI) < 4)
1133 MFI.setObjectAlignment(FI, 4);
1134 Base = CurDAG->getTargetFrameIndex(
1135 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1137 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1146 //===----------------------------------------------------------------------===//
1147 // Thumb 2 Addressing Modes
1148 //===----------------------------------------------------------------------===//
1151 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1152 SDValue &Base, SDValue &OffImm) {
1153 // Match simple R + imm12 operands.
1156 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1157 !CurDAG->isBaseWithConstantOffset(N)) {
1158 if (N.getOpcode() == ISD::FrameIndex) {
1159 // Match frame index.
1160 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1161 Base = CurDAG->getTargetFrameIndex(
1162 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1163 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1167 if (N.getOpcode() == ARMISD::Wrapper &&
1168 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
1169 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
1170 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
1171 Base = N.getOperand(0);
1172 if (Base.getOpcode() == ISD::TargetConstantPool)
1173 return false; // We want to select t2LDRpci instead.
1176 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1180 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1181 if (SelectT2AddrModeImm8(N, Base, OffImm))
1182 // Let t2LDRi8 handle (R - imm8).
1185 int RHSC = (int)RHS->getZExtValue();
1186 if (N.getOpcode() == ISD::SUB)
1189 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1190 Base = N.getOperand(0);
1191 if (Base.getOpcode() == ISD::FrameIndex) {
1192 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1193 Base = CurDAG->getTargetFrameIndex(
1194 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1196 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1203 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1207 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1208 SDValue &Base, SDValue &OffImm) {
1209 // Match simple R - imm8 operands.
1210 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1211 !CurDAG->isBaseWithConstantOffset(N))
1214 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1215 int RHSC = (int)RHS->getSExtValue();
1216 if (N.getOpcode() == ISD::SUB)
1219 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1220 Base = N.getOperand(0);
1221 if (Base.getOpcode() == ISD::FrameIndex) {
1222 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1223 Base = CurDAG->getTargetFrameIndex(
1224 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1226 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1234 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1236 unsigned Opcode = Op->getOpcode();
1237 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1238 ? cast<LoadSDNode>(Op)->getAddressingMode()
1239 : cast<StoreSDNode>(Op)->getAddressingMode();
1241 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1242 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1243 ? CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32)
1244 : CurDAG->getTargetConstant(-RHSC, SDLoc(N), MVT::i32);
1251 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1253 SDValue &OffReg, SDValue &ShImm) {
1254 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1255 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1258 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1259 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1260 int RHSC = (int)RHS->getZExtValue();
1261 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1263 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1267 // Look for (R + R) or (R + (R << [1,2,3])).
1269 Base = N.getOperand(0);
1270 OffReg = N.getOperand(1);
1272 // Swap if it is ((R << c) + R).
1273 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1274 if (ShOpcVal != ARM_AM::lsl) {
1275 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1276 if (ShOpcVal == ARM_AM::lsl)
1277 std::swap(Base, OffReg);
1280 if (ShOpcVal == ARM_AM::lsl) {
1281 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1283 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1284 ShAmt = Sh->getZExtValue();
1285 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1286 OffReg = OffReg.getOperand(0);
1293 // If OffReg is a multiply-by-constant and it's profitable to extract a shift
1294 // and use it in a shifted operand do so.
1295 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) {
1296 unsigned PowerOfTwo = 0;
1297 SDValue NewMulConst;
1298 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) {
1299 HandleSDNode Handle(OffReg);
1300 replaceDAGValue(OffReg.getOperand(1), NewMulConst);
1301 OffReg = Handle.getValue();
1306 ShImm = CurDAG->getTargetConstant(ShAmt, SDLoc(N), MVT::i32);
1311 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1313 // This *must* succeed since it's used for the irreplaceable ldrex and strex
1316 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1318 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1321 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1325 uint32_t RHSC = (int)RHS->getZExtValue();
1326 if (RHSC > 1020 || RHSC % 4 != 0)
1329 Base = N.getOperand(0);
1330 if (Base.getOpcode() == ISD::FrameIndex) {
1331 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1332 Base = CurDAG->getTargetFrameIndex(
1333 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1336 OffImm = CurDAG->getTargetConstant(RHSC/4, SDLoc(N), MVT::i32);
1340 //===--------------------------------------------------------------------===//
1342 /// getAL - Returns a ARMCC::AL immediate node.
1343 static inline SDValue getAL(SelectionDAG *CurDAG, const SDLoc &dl) {
1344 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, dl, MVT::i32);
1347 void ARMDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
1348 MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
1349 CurDAG->setNodeMemRefs(cast<MachineSDNode>(Result), {MemOp});
1352 bool ARMDAGToDAGISel::tryARMIndexedLoad(SDNode *N) {
1353 LoadSDNode *LD = cast<LoadSDNode>(N);
1354 ISD::MemIndexedMode AM = LD->getAddressingMode();
1355 if (AM == ISD::UNINDEXED)
1358 EVT LoadedVT = LD->getMemoryVT();
1359 SDValue Offset, AMOpc;
1360 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1361 unsigned Opcode = 0;
1363 if (LoadedVT == MVT::i32 && isPre &&
1364 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1365 Opcode = ARM::LDR_PRE_IMM;
1367 } else if (LoadedVT == MVT::i32 && !isPre &&
1368 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1369 Opcode = ARM::LDR_POST_IMM;
1371 } else if (LoadedVT == MVT::i32 &&
1372 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1373 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1376 } else if (LoadedVT == MVT::i16 &&
1377 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1379 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1380 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1381 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1382 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1383 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1384 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1386 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1390 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1392 Opcode = ARM::LDRB_PRE_IMM;
1393 } else if (!isPre &&
1394 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1396 Opcode = ARM::LDRB_POST_IMM;
1397 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1399 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1405 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1406 SDValue Chain = LD->getChain();
1407 SDValue Base = LD->getBasePtr();
1408 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)),
1409 CurDAG->getRegister(0, MVT::i32), Chain };
1410 SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1412 transferMemOperands(N, New);
1413 ReplaceNode(N, New);
1416 SDValue Chain = LD->getChain();
1417 SDValue Base = LD->getBasePtr();
1418 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)),
1419 CurDAG->getRegister(0, MVT::i32), Chain };
1420 SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1422 transferMemOperands(N, New);
1423 ReplaceNode(N, New);
1431 bool ARMDAGToDAGISel::tryT1IndexedLoad(SDNode *N) {
1432 LoadSDNode *LD = cast<LoadSDNode>(N);
1433 EVT LoadedVT = LD->getMemoryVT();
1434 ISD::MemIndexedMode AM = LD->getAddressingMode();
1435 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD ||
1436 LoadedVT.getSimpleVT().SimpleTy != MVT::i32)
1439 auto *COffs = dyn_cast<ConstantSDNode>(LD->getOffset());
1440 if (!COffs || COffs->getZExtValue() != 4)
1443 // A T1 post-indexed load is just a single register LDM: LDM r0!, {r1}.
1444 // The encoding of LDM is not how the rest of ISel expects a post-inc load to
1445 // look however, so we use a pseudo here and switch it for a tLDMIA_UPD after
1447 SDValue Chain = LD->getChain();
1448 SDValue Base = LD->getBasePtr();
1449 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)),
1450 CurDAG->getRegister(0, MVT::i32), Chain };
1451 SDNode *New = CurDAG->getMachineNode(ARM::tLDR_postidx, SDLoc(N), MVT::i32,
1452 MVT::i32, MVT::Other, Ops);
1453 transferMemOperands(N, New);
1454 ReplaceNode(N, New);
1458 bool ARMDAGToDAGISel::tryT2IndexedLoad(SDNode *N) {
1459 LoadSDNode *LD = cast<LoadSDNode>(N);
1460 ISD::MemIndexedMode AM = LD->getAddressingMode();
1461 if (AM == ISD::UNINDEXED)
1464 EVT LoadedVT = LD->getMemoryVT();
1465 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1467 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1468 unsigned Opcode = 0;
1470 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1471 switch (LoadedVT.getSimpleVT().SimpleTy) {
1473 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1477 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1479 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1484 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1486 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1495 SDValue Chain = LD->getChain();
1496 SDValue Base = LD->getBasePtr();
1497 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)),
1498 CurDAG->getRegister(0, MVT::i32), Chain };
1499 SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1501 transferMemOperands(N, New);
1502 ReplaceNode(N, New);
1509 /// Form a GPRPair pseudo register from a pair of GPR regs.
1510 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1511 SDLoc dl(V0.getNode());
1513 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32);
1514 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
1515 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
1516 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1517 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1520 /// Form a D register from a pair of S registers.
1521 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1522 SDLoc dl(V0.getNode());
1524 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32);
1525 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1526 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1527 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1528 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1531 /// Form a quad register from a pair of D registers.
1532 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1533 SDLoc dl(V0.getNode());
1534 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl,
1536 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1537 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1538 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1539 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1542 /// Form 4 consecutive D registers from a pair of Q registers.
1543 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1544 SDLoc dl(V0.getNode());
1545 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1547 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1548 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1549 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1550 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1553 /// Form 4 consecutive S registers.
1554 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1555 SDValue V2, SDValue V3) {
1556 SDLoc dl(V0.getNode());
1558 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32);
1559 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1560 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1561 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32);
1562 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32);
1563 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1564 V2, SubReg2, V3, SubReg3 };
1565 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1568 /// Form 4 consecutive D registers.
1569 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1570 SDValue V2, SDValue V3) {
1571 SDLoc dl(V0.getNode());
1572 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1574 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1575 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1576 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32);
1577 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32);
1578 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1579 V2, SubReg2, V3, SubReg3 };
1580 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1583 /// Form 4 consecutive Q registers.
1584 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1585 SDValue V2, SDValue V3) {
1586 SDLoc dl(V0.getNode());
1587 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl,
1589 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1590 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1591 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32);
1592 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32);
1593 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1594 V2, SubReg2, V3, SubReg3 };
1595 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1598 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1599 /// of a NEON VLD or VST instruction. The supported values depend on the
1600 /// number of registers being loaded.
1601 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, const SDLoc &dl,
1602 unsigned NumVecs, bool is64BitVector) {
1603 unsigned NumRegs = NumVecs;
1604 if (!is64BitVector && NumVecs < 3)
1607 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1608 if (Alignment >= 32 && NumRegs == 4)
1610 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1612 else if (Alignment >= 8)
1617 return CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
1620 static bool isVLDfixed(unsigned Opc)
1623 default: return false;
1624 case ARM::VLD1d8wb_fixed : return true;
1625 case ARM::VLD1d16wb_fixed : return true;
1626 case ARM::VLD1d64Qwb_fixed : return true;
1627 case ARM::VLD1d32wb_fixed : return true;
1628 case ARM::VLD1d64wb_fixed : return true;
1629 case ARM::VLD1d64TPseudoWB_fixed : return true;
1630 case ARM::VLD1d64QPseudoWB_fixed : return true;
1631 case ARM::VLD1q8wb_fixed : return true;
1632 case ARM::VLD1q16wb_fixed : return true;
1633 case ARM::VLD1q32wb_fixed : return true;
1634 case ARM::VLD1q64wb_fixed : return true;
1635 case ARM::VLD1DUPd8wb_fixed : return true;
1636 case ARM::VLD1DUPd16wb_fixed : return true;
1637 case ARM::VLD1DUPd32wb_fixed : return true;
1638 case ARM::VLD1DUPq8wb_fixed : return true;
1639 case ARM::VLD1DUPq16wb_fixed : return true;
1640 case ARM::VLD1DUPq32wb_fixed : return true;
1641 case ARM::VLD2d8wb_fixed : return true;
1642 case ARM::VLD2d16wb_fixed : return true;
1643 case ARM::VLD2d32wb_fixed : return true;
1644 case ARM::VLD2q8PseudoWB_fixed : return true;
1645 case ARM::VLD2q16PseudoWB_fixed : return true;
1646 case ARM::VLD2q32PseudoWB_fixed : return true;
1647 case ARM::VLD2DUPd8wb_fixed : return true;
1648 case ARM::VLD2DUPd16wb_fixed : return true;
1649 case ARM::VLD2DUPd32wb_fixed : return true;
1653 static bool isVSTfixed(unsigned Opc)
1656 default: return false;
1657 case ARM::VST1d8wb_fixed : return true;
1658 case ARM::VST1d16wb_fixed : return true;
1659 case ARM::VST1d32wb_fixed : return true;
1660 case ARM::VST1d64wb_fixed : return true;
1661 case ARM::VST1q8wb_fixed : return true;
1662 case ARM::VST1q16wb_fixed : return true;
1663 case ARM::VST1q32wb_fixed : return true;
1664 case ARM::VST1q64wb_fixed : return true;
1665 case ARM::VST1d64TPseudoWB_fixed : return true;
1666 case ARM::VST1d64QPseudoWB_fixed : return true;
1667 case ARM::VST2d8wb_fixed : return true;
1668 case ARM::VST2d16wb_fixed : return true;
1669 case ARM::VST2d32wb_fixed : return true;
1670 case ARM::VST2q8PseudoWB_fixed : return true;
1671 case ARM::VST2q16PseudoWB_fixed : return true;
1672 case ARM::VST2q32PseudoWB_fixed : return true;
1676 // Get the register stride update opcode of a VLD/VST instruction that
1677 // is otherwise equivalent to the given fixed stride updating instruction.
1678 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1679 assert((isVLDfixed(Opc) || isVSTfixed(Opc))
1680 && "Incorrect fixed stride updating instruction.");
1683 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1684 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1685 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1686 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1687 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1688 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1689 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1690 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1691 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1692 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1693 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1694 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1695 case ARM::VLD1DUPd8wb_fixed : return ARM::VLD1DUPd8wb_register;
1696 case ARM::VLD1DUPd16wb_fixed : return ARM::VLD1DUPd16wb_register;
1697 case ARM::VLD1DUPd32wb_fixed : return ARM::VLD1DUPd32wb_register;
1698 case ARM::VLD1DUPq8wb_fixed : return ARM::VLD1DUPq8wb_register;
1699 case ARM::VLD1DUPq16wb_fixed : return ARM::VLD1DUPq16wb_register;
1700 case ARM::VLD1DUPq32wb_fixed : return ARM::VLD1DUPq32wb_register;
1702 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1703 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1704 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1705 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1706 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1707 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1708 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1709 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1710 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1711 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1713 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1714 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1715 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1716 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1717 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1718 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1720 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1721 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1722 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1723 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1724 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1725 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1727 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1728 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1729 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1731 return Opc; // If not one we handle, return it unchanged.
1734 /// Returns true if the given increment is a Constant known to be equal to the
1735 /// access size performed by a NEON load/store. This means the "[rN]!" form can
1737 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {
1738 auto C = dyn_cast<ConstantSDNode>(Inc);
1739 return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;
1742 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1743 const uint16_t *DOpcodes,
1744 const uint16_t *QOpcodes0,
1745 const uint16_t *QOpcodes1) {
1746 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1749 SDValue MemAddr, Align;
1750 bool IsIntrinsic = !isUpdating; // By coincidence, all supported updating
1751 // nodes are not intrinsics.
1752 unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
1753 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1756 SDValue Chain = N->getOperand(0);
1757 EVT VT = N->getValueType(0);
1758 bool is64BitVector = VT.is64BitVector();
1759 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1761 unsigned OpcodeIndex;
1762 switch (VT.getSimpleVT().SimpleTy) {
1763 default: llvm_unreachable("unhandled vld type");
1764 // Double-register operations:
1765 case MVT::v8i8: OpcodeIndex = 0; break;
1767 case MVT::v4i16: OpcodeIndex = 1; break;
1769 case MVT::v2i32: OpcodeIndex = 2; break;
1770 case MVT::v1i64: OpcodeIndex = 3; break;
1771 // Quad-register operations:
1772 case MVT::v16i8: OpcodeIndex = 0; break;
1774 case MVT::v8i16: OpcodeIndex = 1; break;
1776 case MVT::v4i32: OpcodeIndex = 2; break;
1778 case MVT::v2i64: OpcodeIndex = 3; break;
1785 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1788 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1790 std::vector<EVT> ResTys;
1791 ResTys.push_back(ResTy);
1793 ResTys.push_back(MVT::i32);
1794 ResTys.push_back(MVT::Other);
1796 SDValue Pred = getAL(CurDAG, dl);
1797 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1799 SmallVector<SDValue, 7> Ops;
1801 // Double registers and VLD1/VLD2 quad registers are directly supported.
1802 if (is64BitVector || NumVecs <= 2) {
1803 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1804 QOpcodes0[OpcodeIndex]);
1805 Ops.push_back(MemAddr);
1806 Ops.push_back(Align);
1808 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1809 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
1811 // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1812 // check for the opcode rather than the number of vector elements.
1813 if (isVLDfixed(Opc))
1814 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1816 // VLD1/VLD2 fixed increment does not need Reg0 so only include it in
1817 // the operands if not such an opcode.
1818 } else if (!isVLDfixed(Opc))
1819 Ops.push_back(Reg0);
1821 Ops.push_back(Pred);
1822 Ops.push_back(Reg0);
1823 Ops.push_back(Chain);
1824 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1827 // Otherwise, quad registers are loaded with two separate instructions,
1828 // where one loads the even registers and the other loads the odd registers.
1829 EVT AddrTy = MemAddr.getValueType();
1831 // Load the even subregs. This is always an updating load, so that it
1832 // provides the address to the second load for the odd subregs.
1834 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1835 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1836 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1837 ResTy, AddrTy, MVT::Other, OpsA);
1838 Chain = SDValue(VLdA, 2);
1840 // Load the odd subregs.
1841 Ops.push_back(SDValue(VLdA, 1));
1842 Ops.push_back(Align);
1844 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1845 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1846 "only constant post-increment update allowed for VLD3/4");
1848 Ops.push_back(Reg0);
1850 Ops.push_back(SDValue(VLdA, 0));
1851 Ops.push_back(Pred);
1852 Ops.push_back(Reg0);
1853 Ops.push_back(Chain);
1854 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1857 // Transfer memoperands.
1858 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1859 CurDAG->setNodeMemRefs(cast<MachineSDNode>(VLd), {MemOp});
1862 ReplaceNode(N, VLd);
1866 // Extract out the subregisters.
1867 SDValue SuperReg = SDValue(VLd, 0);
1868 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
1869 ARM::qsub_3 == ARM::qsub_0 + 3,
1870 "Unexpected subreg numbering");
1871 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1872 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1873 ReplaceUses(SDValue(N, Vec),
1874 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1875 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1877 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1878 CurDAG->RemoveDeadNode(N);
1881 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1882 const uint16_t *DOpcodes,
1883 const uint16_t *QOpcodes0,
1884 const uint16_t *QOpcodes1) {
1885 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1888 SDValue MemAddr, Align;
1889 bool IsIntrinsic = !isUpdating; // By coincidence, all supported updating
1890 // nodes are not intrinsics.
1891 unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
1892 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1893 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1896 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1898 SDValue Chain = N->getOperand(0);
1899 EVT VT = N->getOperand(Vec0Idx).getValueType();
1900 bool is64BitVector = VT.is64BitVector();
1901 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1903 unsigned OpcodeIndex;
1904 switch (VT.getSimpleVT().SimpleTy) {
1905 default: llvm_unreachable("unhandled vst type");
1906 // Double-register operations:
1907 case MVT::v8i8: OpcodeIndex = 0; break;
1909 case MVT::v4i16: OpcodeIndex = 1; break;
1911 case MVT::v2i32: OpcodeIndex = 2; break;
1912 case MVT::v1i64: OpcodeIndex = 3; break;
1913 // Quad-register operations:
1914 case MVT::v16i8: OpcodeIndex = 0; break;
1916 case MVT::v8i16: OpcodeIndex = 1; break;
1918 case MVT::v4i32: OpcodeIndex = 2; break;
1920 case MVT::v2i64: OpcodeIndex = 3; break;
1923 std::vector<EVT> ResTys;
1925 ResTys.push_back(MVT::i32);
1926 ResTys.push_back(MVT::Other);
1928 SDValue Pred = getAL(CurDAG, dl);
1929 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1930 SmallVector<SDValue, 7> Ops;
1932 // Double registers and VST1/VST2 quad registers are directly supported.
1933 if (is64BitVector || NumVecs <= 2) {
1936 SrcReg = N->getOperand(Vec0Idx);
1937 } else if (is64BitVector) {
1938 // Form a REG_SEQUENCE to force register allocation.
1939 SDValue V0 = N->getOperand(Vec0Idx + 0);
1940 SDValue V1 = N->getOperand(Vec0Idx + 1);
1942 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1944 SDValue V2 = N->getOperand(Vec0Idx + 2);
1945 // If it's a vst3, form a quad D-register and leave the last part as
1947 SDValue V3 = (NumVecs == 3)
1948 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1949 : N->getOperand(Vec0Idx + 3);
1950 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1953 // Form a QQ register.
1954 SDValue Q0 = N->getOperand(Vec0Idx);
1955 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1956 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1959 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1960 QOpcodes0[OpcodeIndex]);
1961 Ops.push_back(MemAddr);
1962 Ops.push_back(Align);
1964 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1965 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
1967 // We use a VST1 for v1i64 even if the pseudo says VST2/3/4, so
1968 // check for the opcode rather than the number of vector elements.
1969 if (isVSTfixed(Opc))
1970 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1973 // VST1/VST2 fixed increment does not need Reg0 so only include it in
1974 // the operands if not such an opcode.
1975 else if (!isVSTfixed(Opc))
1976 Ops.push_back(Reg0);
1978 Ops.push_back(SrcReg);
1979 Ops.push_back(Pred);
1980 Ops.push_back(Reg0);
1981 Ops.push_back(Chain);
1982 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1984 // Transfer memoperands.
1985 CurDAG->setNodeMemRefs(cast<MachineSDNode>(VSt), {MemOp});
1987 ReplaceNode(N, VSt);
1991 // Otherwise, quad registers are stored with two separate instructions,
1992 // where one stores the even registers and the other stores the odd registers.
1994 // Form the QQQQ REG_SEQUENCE.
1995 SDValue V0 = N->getOperand(Vec0Idx + 0);
1996 SDValue V1 = N->getOperand(Vec0Idx + 1);
1997 SDValue V2 = N->getOperand(Vec0Idx + 2);
1998 SDValue V3 = (NumVecs == 3)
1999 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2000 : N->getOperand(Vec0Idx + 3);
2001 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2003 // Store the even D registers. This is always an updating store, so that it
2004 // provides the address to the second store for the odd subregs.
2005 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2006 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
2007 MemAddr.getValueType(),
2009 CurDAG->setNodeMemRefs(cast<MachineSDNode>(VStA), {MemOp});
2010 Chain = SDValue(VStA, 1);
2012 // Store the odd D registers.
2013 Ops.push_back(SDValue(VStA, 0));
2014 Ops.push_back(Align);
2016 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2017 assert(isa<ConstantSDNode>(Inc.getNode()) &&
2018 "only constant post-increment update allowed for VST3/4");
2020 Ops.push_back(Reg0);
2022 Ops.push_back(RegSeq);
2023 Ops.push_back(Pred);
2024 Ops.push_back(Reg0);
2025 Ops.push_back(Chain);
2026 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
2028 CurDAG->setNodeMemRefs(cast<MachineSDNode>(VStB), {MemOp});
2029 ReplaceNode(N, VStB);
2032 void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
2034 const uint16_t *DOpcodes,
2035 const uint16_t *QOpcodes) {
2036 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2039 SDValue MemAddr, Align;
2040 bool IsIntrinsic = !isUpdating; // By coincidence, all supported updating
2041 // nodes are not intrinsics.
2042 unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
2043 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
2044 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2047 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2049 SDValue Chain = N->getOperand(0);
2051 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2052 EVT VT = N->getOperand(Vec0Idx).getValueType();
2053 bool is64BitVector = VT.is64BitVector();
2055 unsigned Alignment = 0;
2057 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2058 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
2059 if (Alignment > NumBytes)
2060 Alignment = NumBytes;
2061 if (Alignment < 8 && Alignment < NumBytes)
2063 // Alignment must be a power of two; make sure of that.
2064 Alignment = (Alignment & -Alignment);
2068 Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
2070 unsigned OpcodeIndex;
2071 switch (VT.getSimpleVT().SimpleTy) {
2072 default: llvm_unreachable("unhandled vld/vst lane type");
2073 // Double-register operations:
2074 case MVT::v8i8: OpcodeIndex = 0; break;
2075 case MVT::v4i16: OpcodeIndex = 1; break;
2077 case MVT::v2i32: OpcodeIndex = 2; break;
2078 // Quad-register operations:
2079 case MVT::v8i16: OpcodeIndex = 0; break;
2081 case MVT::v4i32: OpcodeIndex = 1; break;
2084 std::vector<EVT> ResTys;
2086 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2089 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2090 MVT::i64, ResTyElts));
2093 ResTys.push_back(MVT::i32);
2094 ResTys.push_back(MVT::Other);
2096 SDValue Pred = getAL(CurDAG, dl);
2097 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2099 SmallVector<SDValue, 8> Ops;
2100 Ops.push_back(MemAddr);
2101 Ops.push_back(Align);
2103 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2105 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
2106 Ops.push_back(IsImmUpdate ? Reg0 : Inc);
2110 SDValue V0 = N->getOperand(Vec0Idx + 0);
2111 SDValue V1 = N->getOperand(Vec0Idx + 1);
2114 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2116 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2118 SDValue V2 = N->getOperand(Vec0Idx + 2);
2119 SDValue V3 = (NumVecs == 3)
2120 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2121 : N->getOperand(Vec0Idx + 3);
2123 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2125 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2127 Ops.push_back(SuperReg);
2128 Ops.push_back(getI32Imm(Lane, dl));
2129 Ops.push_back(Pred);
2130 Ops.push_back(Reg0);
2131 Ops.push_back(Chain);
2133 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2134 QOpcodes[OpcodeIndex]);
2135 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2136 CurDAG->setNodeMemRefs(cast<MachineSDNode>(VLdLn), {MemOp});
2138 ReplaceNode(N, VLdLn);
2142 // Extract the subregisters.
2143 SuperReg = SDValue(VLdLn, 0);
2144 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
2145 ARM::qsub_3 == ARM::qsub_0 + 3,
2146 "Unexpected subreg numbering");
2147 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2148 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2149 ReplaceUses(SDValue(N, Vec),
2150 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2151 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2153 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2154 CurDAG->RemoveDeadNode(N);
2157 void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool IsIntrinsic,
2158 bool isUpdating, unsigned NumVecs,
2159 const uint16_t *DOpcodes,
2160 const uint16_t *QOpcodes0,
2161 const uint16_t *QOpcodes1) {
2162 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2165 SDValue MemAddr, Align;
2166 unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
2167 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2170 SDValue Chain = N->getOperand(0);
2171 EVT VT = N->getValueType(0);
2172 bool is64BitVector = VT.is64BitVector();
2174 unsigned Alignment = 0;
2176 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2177 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
2178 if (Alignment > NumBytes)
2179 Alignment = NumBytes;
2180 if (Alignment < 8 && Alignment < NumBytes)
2182 // Alignment must be a power of two; make sure of that.
2183 Alignment = (Alignment & -Alignment);
2187 Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
2189 unsigned OpcodeIndex;
2190 switch (VT.getSimpleVT().SimpleTy) {
2191 default: llvm_unreachable("unhandled vld-dup type");
2193 case MVT::v16i8: OpcodeIndex = 0; break;
2195 case MVT::v8i16: OpcodeIndex = 1; break;
2199 case MVT::v4i32: OpcodeIndex = 2; break;
2201 case MVT::v1i64: OpcodeIndex = 3; break;
2204 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2207 EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
2209 std::vector<EVT> ResTys;
2210 ResTys.push_back(ResTy);
2212 ResTys.push_back(MVT::i32);
2213 ResTys.push_back(MVT::Other);
2215 SDValue Pred = getAL(CurDAG, dl);
2216 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2219 if (is64BitVector || NumVecs == 1) {
2220 SmallVector<SDValue, 6> Ops;
2221 Ops.push_back(MemAddr);
2222 Ops.push_back(Align);
2223 unsigned Opc = is64BitVector ? DOpcodes[OpcodeIndex] :
2224 QOpcodes0[OpcodeIndex];
2226 // fixed-stride update instructions don't have an explicit writeback
2227 // operand. It's implicit in the opcode itself.
2228 SDValue Inc = N->getOperand(2);
2230 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
2231 if (NumVecs <= 2 && !IsImmUpdate)
2232 Opc = getVLDSTRegisterUpdateOpcode(Opc);
2235 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2236 else if (NumVecs > 2)
2237 Ops.push_back(Reg0);
2239 Ops.push_back(Pred);
2240 Ops.push_back(Reg0);
2241 Ops.push_back(Chain);
2242 VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2243 } else if (NumVecs == 2) {
2244 const SDValue OpsA[] = { MemAddr, Align, Pred, Reg0, Chain };
2245 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex],
2248 Chain = SDValue(VLdA, 1);
2249 const SDValue OpsB[] = { MemAddr, Align, Pred, Reg0, Chain };
2250 VLdDup = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, OpsB);
2253 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
2254 const SDValue OpsA[] = { MemAddr, Align, ImplDef, Pred, Reg0, Chain };
2255 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex],
2258 SDValue SuperReg = SDValue(VLdA, 0);
2259 Chain = SDValue(VLdA, 1);
2260 const SDValue OpsB[] = { MemAddr, Align, SuperReg, Pred, Reg0, Chain };
2261 VLdDup = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, OpsB);
2264 // Transfer memoperands.
2265 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2266 CurDAG->setNodeMemRefs(cast<MachineSDNode>(VLdDup), {MemOp});
2268 // Extract the subregisters.
2270 ReplaceUses(SDValue(N, 0), SDValue(VLdDup, 0));
2272 SDValue SuperReg = SDValue(VLdDup, 0);
2273 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering");
2274 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2275 for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {
2276 ReplaceUses(SDValue(N, Vec),
2277 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2280 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2282 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2283 CurDAG->RemoveDeadNode(N);
2286 bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) {
2287 if (!Subtarget->hasV6T2Ops())
2290 unsigned Opc = isSigned
2291 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2292 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2295 // For unsigned extracts, check for a shift right and mask
2296 unsigned And_imm = 0;
2297 if (N->getOpcode() == ISD::AND) {
2298 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2300 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2301 if (And_imm & (And_imm + 1))
2304 unsigned Srl_imm = 0;
2305 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2307 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2309 // Mask off the unnecessary bits of the AND immediate; normally
2310 // DAGCombine will do this, but that might not happen if
2311 // targetShrinkDemandedConstant chooses a different immediate.
2312 And_imm &= -1U >> Srl_imm;
2314 // Note: The width operand is encoded as width-1.
2315 unsigned Width = countTrailingOnes(And_imm) - 1;
2316 unsigned LSB = Srl_imm;
2318 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2320 if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2321 // It's cheaper to use a right shift to extract the top bits.
2322 if (Subtarget->isThumb()) {
2323 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2324 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2325 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2326 getAL(CurDAG, dl), Reg0, Reg0 };
2327 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2331 // ARM models shift instructions as MOVsi with shifter operand.
2332 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2334 CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB), dl,
2336 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2337 getAL(CurDAG, dl), Reg0, Reg0 };
2338 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
2342 assert(LSB + Width + 1 <= 32 && "Shouldn't create an invalid ubfx");
2343 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2344 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2345 CurDAG->getTargetConstant(Width, dl, MVT::i32),
2346 getAL(CurDAG, dl), Reg0 };
2347 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2354 // Otherwise, we're looking for a shift of a shift
2355 unsigned Shl_imm = 0;
2356 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2357 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2358 unsigned Srl_imm = 0;
2359 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2360 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2361 // Note: The width operand is encoded as width-1.
2362 unsigned Width = 32 - Srl_imm - 1;
2363 int LSB = Srl_imm - Shl_imm;
2366 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2367 assert(LSB + Width + 1 <= 32 && "Shouldn't create an invalid ubfx");
2368 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2369 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2370 CurDAG->getTargetConstant(Width, dl, MVT::i32),
2371 getAL(CurDAG, dl), Reg0 };
2372 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2377 // Or we are looking for a shift of an and, with a mask operand
2378 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_imm) &&
2379 isShiftedMask_32(And_imm)) {
2380 unsigned Srl_imm = 0;
2381 unsigned LSB = countTrailingZeros(And_imm);
2382 // Shift must be the same as the ands lsb
2383 if (isInt32Immediate(N->getOperand(1), Srl_imm) && Srl_imm == LSB) {
2384 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2385 unsigned MSB = 31 - countLeadingZeros(And_imm);
2386 // Note: The width operand is encoded as width-1.
2387 unsigned Width = MSB - LSB;
2388 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2389 assert(Srl_imm + Width + 1 <= 32 && "Shouldn't create an invalid ubfx");
2390 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2391 CurDAG->getTargetConstant(Srl_imm, dl, MVT::i32),
2392 CurDAG->getTargetConstant(Width, dl, MVT::i32),
2393 getAL(CurDAG, dl), Reg0 };
2394 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2399 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2400 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
2402 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
2403 !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
2406 if (LSB + Width > 32)
2409 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2410 assert(LSB + Width <= 32 && "Shouldn't create an invalid ubfx");
2411 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2412 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2413 CurDAG->getTargetConstant(Width - 1, dl, MVT::i32),
2414 getAL(CurDAG, dl), Reg0 };
2415 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2422 /// Target-specific DAG combining for ISD::XOR.
2423 /// Target-independent combining lowers SELECT_CC nodes of the form
2424 /// select_cc setg[ge] X, 0, X, -X
2425 /// select_cc setgt X, -1, X, -X
2426 /// select_cc setl[te] X, 0, -X, X
2427 /// select_cc setlt X, 1, -X, X
2428 /// which represent Integer ABS into:
2429 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2430 /// ARM instruction selection detects the latter and matches it to
2431 /// ARM::ABS or ARM::t2ABS machine node.
2432 bool ARMDAGToDAGISel::tryABSOp(SDNode *N){
2433 SDValue XORSrc0 = N->getOperand(0);
2434 SDValue XORSrc1 = N->getOperand(1);
2435 EVT VT = N->getValueType(0);
2437 if (Subtarget->isThumb1Only())
2440 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2443 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2444 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2445 SDValue SRASrc0 = XORSrc1.getOperand(0);
2446 SDValue SRASrc1 = XORSrc1.getOperand(1);
2447 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2448 EVT XType = SRASrc0.getValueType();
2449 unsigned Size = XType.getSizeInBits() - 1;
2451 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2452 XType.isInteger() && SRAConstant != nullptr &&
2453 Size == SRAConstant->getZExtValue()) {
2454 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2455 CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2462 /// We've got special pseudo-instructions for these
2463 void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
2465 EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();
2466 if (MemTy == MVT::i8)
2467 Opcode = ARM::CMP_SWAP_8;
2468 else if (MemTy == MVT::i16)
2469 Opcode = ARM::CMP_SWAP_16;
2470 else if (MemTy == MVT::i32)
2471 Opcode = ARM::CMP_SWAP_32;
2473 llvm_unreachable("Unknown AtomicCmpSwap type");
2475 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
2477 SDNode *CmpSwap = CurDAG->getMachineNode(
2479 CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops);
2481 MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
2482 CurDAG->setNodeMemRefs(cast<MachineSDNode>(CmpSwap), {MemOp});
2484 ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
2485 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
2486 CurDAG->RemoveDeadNode(N);
2489 static Optional<std::pair<unsigned, unsigned>>
2490 getContiguousRangeOfSetBits(const APInt &A) {
2491 unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
2492 unsigned LastOne = A.countTrailingZeros();
2493 if (A.countPopulation() != (FirstOne - LastOne + 1))
2494 return Optional<std::pair<unsigned,unsigned>>();
2495 return std::make_pair(FirstOne, LastOne);
2498 void ARMDAGToDAGISel::SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI) {
2499 assert(N->getOpcode() == ARMISD::CMPZ);
2500 SwitchEQNEToPLMI = false;
2502 if (!Subtarget->isThumb())
2503 // FIXME: Work out whether it is profitable to do this in A32 mode - LSL and
2504 // LSR don't exist as standalone instructions - they need the barrel shifter.
2507 // select (cmpz (and X, C), #0) -> (LSLS X) or (LSRS X) or (LSRS (LSLS X))
2508 SDValue And = N->getOperand(0);
2509 if (!And->hasOneUse())
2512 SDValue Zero = N->getOperand(1);
2513 if (!isa<ConstantSDNode>(Zero) || !cast<ConstantSDNode>(Zero)->isNullValue() ||
2514 And->getOpcode() != ISD::AND)
2516 SDValue X = And.getOperand(0);
2517 auto C = dyn_cast<ConstantSDNode>(And.getOperand(1));
2521 auto Range = getContiguousRangeOfSetBits(C->getAPIntValue());
2525 // There are several ways to lower this:
2529 auto EmitShift = [&](unsigned Opc, SDValue Src, unsigned Imm) -> SDNode* {
2530 if (Subtarget->isThumb2()) {
2531 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri;
2532 SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32),
2533 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2534 CurDAG->getRegister(0, MVT::i32) };
2535 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
2537 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
2538 CurDAG->getTargetConstant(Imm, dl, MVT::i32),
2539 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};
2540 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
2544 if (Range->second == 0) {
2545 // 1. Mask includes the LSB -> Simply shift the top N bits off
2546 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
2547 ReplaceNode(And.getNode(), NewN);
2548 } else if (Range->first == 31) {
2549 // 2. Mask includes the MSB -> Simply shift the bottom N bits off
2550 NewN = EmitShift(ARM::tLSRri, X, Range->second);
2551 ReplaceNode(And.getNode(), NewN);
2552 } else if (Range->first == Range->second) {
2553 // 3. Only one bit is set. We can shift this into the sign bit and use a
2554 // PL/MI comparison.
2555 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
2556 ReplaceNode(And.getNode(), NewN);
2558 SwitchEQNEToPLMI = true;
2559 } else if (!Subtarget->hasV6T2Ops()) {
2560 // 4. Do a double shift to clear bottom and top bits, but only in
2561 // thumb-1 mode as in thumb-2 we can use UBFX.
2562 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
2563 NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0),
2564 Range->second + (31 - Range->first));
2565 ReplaceNode(And.getNode(), NewN);
2570 void ARMDAGToDAGISel::Select(SDNode *N) {
2573 if (N->isMachineOpcode()) {
2575 return; // Already selected.
2578 switch (N->getOpcode()) {
2580 case ISD::WRITE_REGISTER:
2581 if (tryWriteRegister(N))
2584 case ISD::READ_REGISTER:
2585 if (tryReadRegister(N))
2588 case ISD::INLINEASM:
2589 if (tryInlineAsm(N))
2593 // Select special operations if XOR node forms integer ABS pattern
2596 // Other cases are autogenerated.
2598 case ISD::Constant: {
2599 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2600 // If we can't materialize the constant we need to use a literal pool
2601 if (ConstantMaterializationCost(Val) > 2) {
2602 SDValue CPIdx = CurDAG->getTargetConstantPool(
2603 ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
2604 TLI->getPointerTy(CurDAG->getDataLayout()));
2607 if (Subtarget->isThumb()) {
2611 CurDAG->getRegister(0, MVT::i32),
2612 CurDAG->getEntryNode()
2614 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2619 CurDAG->getTargetConstant(0, dl, MVT::i32),
2621 CurDAG->getRegister(0, MVT::i32),
2622 CurDAG->getEntryNode()
2624 ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2627 // Annotate the Node with memory operand information so that MachineInstr
2628 // queries work properly. This e.g. gives the register allocation the
2629 // required information for rematerialization.
2630 MachineFunction& MF = CurDAG->getMachineFunction();
2631 MachineMemOperand *MemOp =
2632 MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
2633 MachineMemOperand::MOLoad, 4, 4);
2635 CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {MemOp});
2637 ReplaceNode(N, ResNode);
2641 // Other cases are autogenerated.
2644 case ISD::FrameIndex: {
2645 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2646 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2647 SDValue TFI = CurDAG->getTargetFrameIndex(
2648 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
2649 if (Subtarget->isThumb1Only()) {
2650 // Set the alignment of the frame object to 4, to avoid having to generate
2651 // more than one ADD
2652 MachineFrameInfo &MFI = MF->getFrameInfo();
2653 if (MFI.getObjectAlignment(FI) < 4)
2654 MFI.setObjectAlignment(FI, 4);
2655 CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
2656 CurDAG->getTargetConstant(0, dl, MVT::i32));
2659 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2660 ARM::t2ADDri : ARM::ADDri);
2661 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32),
2662 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2663 CurDAG->getRegister(0, MVT::i32) };
2664 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2669 if (tryV6T2BitfieldExtractOp(N, false))
2672 case ISD::SIGN_EXTEND_INREG:
2674 if (tryV6T2BitfieldExtractOp(N, true))
2678 if (Subtarget->isThumb1Only())
2680 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2681 unsigned RHSV = C->getZExtValue();
2683 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2684 unsigned ShImm = Log2_32(RHSV-1);
2687 SDValue V = N->getOperand(0);
2688 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2689 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
2690 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2691 if (Subtarget->isThumb()) {
2692 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2693 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
2696 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2698 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
2702 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2703 unsigned ShImm = Log2_32(RHSV+1);
2706 SDValue V = N->getOperand(0);
2707 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2708 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
2709 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2710 if (Subtarget->isThumb()) {
2711 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2712 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
2715 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2717 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
2724 // Check for unsigned bitfield extract
2725 if (tryV6T2BitfieldExtractOp(N, false))
2728 // If an immediate is used in an AND node, it is possible that the immediate
2729 // can be more optimally materialized when negated. If this is the case we
2730 // can negate the immediate and use a BIC instead.
2731 auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2732 if (N1C && N1C->hasOneUse() && Subtarget->isThumb()) {
2733 uint32_t Imm = (uint32_t) N1C->getZExtValue();
2735 // In Thumb2 mode, an AND can take a 12-bit immediate. If this
2736 // immediate can be negated and fit in the immediate operand of
2737 // a t2BIC, don't do any manual transform here as this can be
2738 // handled by the generic ISel machinery.
2739 bool PreferImmediateEncoding =
2740 Subtarget->hasThumb2() && (is_t2_so_imm(Imm) || is_t2_so_imm_not(Imm));
2741 if (!PreferImmediateEncoding &&
2742 ConstantMaterializationCost(Imm) >
2743 ConstantMaterializationCost(~Imm)) {
2744 // The current immediate costs more to materialize than a negated
2745 // immediate, so negate the immediate and use a BIC.
2747 CurDAG->getConstant(~N1C->getZExtValue(), dl, MVT::i32);
2748 // If the new constant didn't exist before, reposition it in the topological
2749 // ordering so it is just before N. Otherwise, don't touch its location.
2750 if (NewImm->getNodeId() == -1)
2751 CurDAG->RepositionNode(N->getIterator(), NewImm.getNode());
2753 if (!Subtarget->hasThumb2()) {
2754 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
2755 N->getOperand(0), NewImm, getAL(CurDAG, dl),
2756 CurDAG->getRegister(0, MVT::i32)};
2757 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops));
2760 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl),
2761 CurDAG->getRegister(0, MVT::i32),
2762 CurDAG->getRegister(0, MVT::i32)};
2764 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops));
2770 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2771 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2772 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2773 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2774 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2775 EVT VT = N->getValueType(0);
2778 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2780 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2783 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2784 N1C = dyn_cast<ConstantSDNode>(N1);
2787 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2788 SDValue N2 = N0.getOperand(1);
2789 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2792 unsigned N1CVal = N1C->getZExtValue();
2793 unsigned N2CVal = N2C->getZExtValue();
2794 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2795 (N1CVal & 0xffffU) == 0xffffU &&
2796 (N2CVal & 0xffffU) == 0x0U) {
2797 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2799 SDValue Ops[] = { N0.getOperand(0), Imm16,
2800 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
2801 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
2808 case ARMISD::UMAAL: {
2809 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL;
2810 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2811 N->getOperand(2), N->getOperand(3),
2813 CurDAG->getRegister(0, MVT::i32) };
2814 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops));
2817 case ARMISD::UMLAL:{
2818 if (Subtarget->isThumb()) {
2819 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2820 N->getOperand(3), getAL(CurDAG, dl),
2821 CurDAG->getRegister(0, MVT::i32)};
2823 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops));
2826 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2827 N->getOperand(3), getAL(CurDAG, dl),
2828 CurDAG->getRegister(0, MVT::i32),
2829 CurDAG->getRegister(0, MVT::i32) };
2830 ReplaceNode(N, CurDAG->getMachineNode(
2831 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl,
2832 MVT::i32, MVT::i32, Ops));
2836 case ARMISD::SMLAL:{
2837 if (Subtarget->isThumb()) {
2838 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2839 N->getOperand(3), getAL(CurDAG, dl),
2840 CurDAG->getRegister(0, MVT::i32)};
2842 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops));
2845 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2846 N->getOperand(3), getAL(CurDAG, dl),
2847 CurDAG->getRegister(0, MVT::i32),
2848 CurDAG->getRegister(0, MVT::i32) };
2849 ReplaceNode(N, CurDAG->getMachineNode(
2850 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl,
2851 MVT::i32, MVT::i32, Ops));
2855 case ARMISD::SUBE: {
2856 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
2858 // Look for a pattern to match SMMLS
2859 // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b))))
2860 if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
2861 N->getOperand(2).getOpcode() != ARMISD::SUBC ||
2862 !SDValue(N, 1).use_empty())
2865 if (Subtarget->isThumb())
2866 assert(Subtarget->hasThumb2() &&
2867 "This pattern should not be generated for Thumb");
2869 SDValue SmulLoHi = N->getOperand(1);
2870 SDValue Subc = N->getOperand(2);
2871 auto *Zero = dyn_cast<ConstantSDNode>(Subc.getOperand(0));
2873 if (!Zero || Zero->getZExtValue() != 0 ||
2874 Subc.getOperand(1) != SmulLoHi.getValue(0) ||
2875 N->getOperand(1) != SmulLoHi.getValue(1) ||
2876 N->getOperand(2) != Subc.getValue(1))
2879 unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS;
2880 SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
2881 N->getOperand(0), getAL(CurDAG, dl),
2882 CurDAG->getRegister(0, MVT::i32) };
2883 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
2887 if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
2888 if (tryT2IndexedLoad(N))
2890 } else if (Subtarget->isThumb()) {
2891 if (tryT1IndexedLoad(N))
2893 } else if (tryARMIndexedLoad(N))
2895 // Other cases are autogenerated.
2898 case ARMISD::BRCOND: {
2899 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2900 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2901 // Pattern complexity = 6 cost = 1 size = 0
2903 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2904 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2905 // Pattern complexity = 6 cost = 1 size = 0
2907 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2908 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2909 // Pattern complexity = 6 cost = 1 size = 0
2911 unsigned Opc = Subtarget->isThumb() ?
2912 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2913 SDValue Chain = N->getOperand(0);
2914 SDValue N1 = N->getOperand(1);
2915 SDValue N2 = N->getOperand(2);
2916 SDValue N3 = N->getOperand(3);
2917 SDValue InFlag = N->getOperand(4);
2918 assert(N1.getOpcode() == ISD::BasicBlock);
2919 assert(N2.getOpcode() == ISD::Constant);
2920 assert(N3.getOpcode() == ISD::Register);
2922 unsigned CC = (unsigned) cast<ConstantSDNode>(N2)->getZExtValue();
2924 if (InFlag.getOpcode() == ARMISD::CMPZ) {
2925 bool SwitchEQNEToPLMI;
2926 SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);
2927 InFlag = N->getOperand(4);
2929 if (SwitchEQNEToPLMI) {
2930 switch ((ARMCC::CondCodes)CC) {
2931 default: llvm_unreachable("CMPZ must be either NE or EQ!");
2933 CC = (unsigned)ARMCC::MI;
2936 CC = (unsigned)ARMCC::PL;
2942 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32);
2943 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2944 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2946 Chain = SDValue(ResNode, 0);
2947 if (N->getNumValues() == 2) {
2948 InFlag = SDValue(ResNode, 1);
2949 ReplaceUses(SDValue(N, 1), InFlag);
2951 ReplaceUses(SDValue(N, 0),
2952 SDValue(Chain.getNode(), Chain.getResNo()));
2953 CurDAG->RemoveDeadNode(N);
2957 case ARMISD::CMPZ: {
2958 // select (CMPZ X, #-C) -> (CMPZ (ADDS X, #C), #0)
2959 // This allows us to avoid materializing the expensive negative constant.
2960 // The CMPZ #0 is useless and will be peepholed away but we need to keep it
2961 // for its glue output.
2962 SDValue X = N->getOperand(0);
2963 auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1).getNode());
2964 if (C && C->getSExtValue() < 0 && Subtarget->isThumb()) {
2965 int64_t Addend = -C->getSExtValue();
2967 SDNode *Add = nullptr;
2968 // ADDS can be better than CMN if the immediate fits in a
2969 // 16-bit ADDS, which means either [0,256) for tADDi8 or [0,8) for tADDi3.
2970 // Outside that range we can just use a CMN which is 32-bit but has a
2971 // 12-bit immediate range.
2972 if (Addend < 1<<8) {
2973 if (Subtarget->isThumb2()) {
2974 SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32),
2975 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2976 CurDAG->getRegister(0, MVT::i32) };
2977 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops);
2979 unsigned Opc = (Addend < 1<<3) ? ARM::tADDi3 : ARM::tADDi8;
2980 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
2981 CurDAG->getTargetConstant(Addend, dl, MVT::i32),
2982 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};
2983 Add = CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
2987 SDValue Ops2[] = {SDValue(Add, 0), CurDAG->getConstant(0, dl, MVT::i32)};
2988 CurDAG->MorphNodeTo(N, ARMISD::CMPZ, CurDAG->getVTList(MVT::Glue), Ops2);
2991 // Other cases are autogenerated.
2995 case ARMISD::CMOV: {
2996 SDValue InFlag = N->getOperand(4);
2998 if (InFlag.getOpcode() == ARMISD::CMPZ) {
2999 bool SwitchEQNEToPLMI;
3000 SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);
3002 if (SwitchEQNEToPLMI) {
3003 SDValue ARMcc = N->getOperand(2);
3004 ARMCC::CondCodes CC =
3005 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
3008 default: llvm_unreachable("CMPZ must be either NE or EQ!");
3016 SDValue NewARMcc = CurDAG->getConstant((unsigned)CC, dl, MVT::i32);
3017 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,
3018 N->getOperand(3), N->getOperand(4)};
3019 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);
3023 // Other cases are autogenerated.
3027 case ARMISD::VZIP: {
3029 EVT VT = N->getValueType(0);
3030 switch (VT.getSimpleVT().SimpleTy) {
3032 case MVT::v8i8: Opc = ARM::VZIPd8; break;
3034 case MVT::v4i16: Opc = ARM::VZIPd16; break;
3036 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
3037 case MVT::v2i32: Opc = ARM::VTRNd32; break;
3038 case MVT::v16i8: Opc = ARM::VZIPq8; break;
3040 case MVT::v8i16: Opc = ARM::VZIPq16; break;
3042 case MVT::v4i32: Opc = ARM::VZIPq32; break;
3044 SDValue Pred = getAL(CurDAG, dl);
3045 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3046 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3047 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
3050 case ARMISD::VUZP: {
3052 EVT VT = N->getValueType(0);
3053 switch (VT.getSimpleVT().SimpleTy) {
3055 case MVT::v8i8: Opc = ARM::VUZPd8; break;
3057 case MVT::v4i16: Opc = ARM::VUZPd16; break;
3059 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
3060 case MVT::v2i32: Opc = ARM::VTRNd32; break;
3061 case MVT::v16i8: Opc = ARM::VUZPq8; break;
3063 case MVT::v8i16: Opc = ARM::VUZPq16; break;
3065 case MVT::v4i32: Opc = ARM::VUZPq32; break;
3067 SDValue Pred = getAL(CurDAG, dl);
3068 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3069 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3070 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
3073 case ARMISD::VTRN: {
3075 EVT VT = N->getValueType(0);
3076 switch (VT.getSimpleVT().SimpleTy) {
3078 case MVT::v8i8: Opc = ARM::VTRNd8; break;
3080 case MVT::v4i16: Opc = ARM::VTRNd16; break;
3082 case MVT::v2i32: Opc = ARM::VTRNd32; break;
3083 case MVT::v16i8: Opc = ARM::VTRNq8; break;
3085 case MVT::v8i16: Opc = ARM::VTRNq16; break;
3087 case MVT::v4i32: Opc = ARM::VTRNq32; break;
3089 SDValue Pred = getAL(CurDAG, dl);
3090 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3091 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3092 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
3095 case ARMISD::BUILD_VECTOR: {
3096 EVT VecVT = N->getValueType(0);
3097 EVT EltVT = VecVT.getVectorElementType();
3098 unsigned NumElts = VecVT.getVectorNumElements();
3099 if (EltVT == MVT::f64) {
3100 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
3102 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3105 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
3108 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
3111 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
3113 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
3114 N->getOperand(2), N->getOperand(3)));
3118 case ARMISD::VLD1DUP: {
3119 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8, ARM::VLD1DUPd16,
3121 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8, ARM::VLD1DUPq16,
3123 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 1, DOpcodes, QOpcodes);
3127 case ARMISD::VLD2DUP: {
3128 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
3130 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 2, Opcodes);
3134 case ARMISD::VLD3DUP: {
3135 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
3136 ARM::VLD3DUPd16Pseudo,
3137 ARM::VLD3DUPd32Pseudo };
3138 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 3, Opcodes);
3142 case ARMISD::VLD4DUP: {
3143 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
3144 ARM::VLD4DUPd16Pseudo,
3145 ARM::VLD4DUPd32Pseudo };
3146 SelectVLDDup(N, /* IsIntrinsic= */ false, false, 4, Opcodes);
3150 case ARMISD::VLD1DUP_UPD: {
3151 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8wb_fixed,
3152 ARM::VLD1DUPd16wb_fixed,
3153 ARM::VLD1DUPd32wb_fixed };
3154 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8wb_fixed,
3155 ARM::VLD1DUPq16wb_fixed,
3156 ARM::VLD1DUPq32wb_fixed };
3157 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 1, DOpcodes, QOpcodes);
3161 case ARMISD::VLD2DUP_UPD: {
3162 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
3163 ARM::VLD2DUPd16wb_fixed,
3164 ARM::VLD2DUPd32wb_fixed };
3165 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 2, Opcodes);
3169 case ARMISD::VLD3DUP_UPD: {
3170 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
3171 ARM::VLD3DUPd16Pseudo_UPD,
3172 ARM::VLD3DUPd32Pseudo_UPD };
3173 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 3, Opcodes);
3177 case ARMISD::VLD4DUP_UPD: {
3178 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
3179 ARM::VLD4DUPd16Pseudo_UPD,
3180 ARM::VLD4DUPd32Pseudo_UPD };
3181 SelectVLDDup(N, /* IsIntrinsic= */ false, true, 4, Opcodes);
3185 case ARMISD::VLD1_UPD: {
3186 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
3187 ARM::VLD1d16wb_fixed,
3188 ARM::VLD1d32wb_fixed,
3189 ARM::VLD1d64wb_fixed };
3190 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
3191 ARM::VLD1q16wb_fixed,
3192 ARM::VLD1q32wb_fixed,
3193 ARM::VLD1q64wb_fixed };
3194 SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
3198 case ARMISD::VLD2_UPD: {
3199 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
3200 ARM::VLD2d16wb_fixed,
3201 ARM::VLD2d32wb_fixed,
3202 ARM::VLD1q64wb_fixed};
3203 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
3204 ARM::VLD2q16PseudoWB_fixed,
3205 ARM::VLD2q32PseudoWB_fixed };
3206 SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
3210 case ARMISD::VLD3_UPD: {
3211 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
3212 ARM::VLD3d16Pseudo_UPD,
3213 ARM::VLD3d32Pseudo_UPD,
3214 ARM::VLD1d64TPseudoWB_fixed};
3215 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3216 ARM::VLD3q16Pseudo_UPD,
3217 ARM::VLD3q32Pseudo_UPD };
3218 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
3219 ARM::VLD3q16oddPseudo_UPD,
3220 ARM::VLD3q32oddPseudo_UPD };
3221 SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
3225 case ARMISD::VLD4_UPD: {
3226 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
3227 ARM::VLD4d16Pseudo_UPD,
3228 ARM::VLD4d32Pseudo_UPD,
3229 ARM::VLD1d64QPseudoWB_fixed};
3230 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3231 ARM::VLD4q16Pseudo_UPD,
3232 ARM::VLD4q32Pseudo_UPD };
3233 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
3234 ARM::VLD4q16oddPseudo_UPD,
3235 ARM::VLD4q32oddPseudo_UPD };
3236 SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
3240 case ARMISD::VLD2LN_UPD: {
3241 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
3242 ARM::VLD2LNd16Pseudo_UPD,
3243 ARM::VLD2LNd32Pseudo_UPD };
3244 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
3245 ARM::VLD2LNq32Pseudo_UPD };
3246 SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
3250 case ARMISD::VLD3LN_UPD: {
3251 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
3252 ARM::VLD3LNd16Pseudo_UPD,
3253 ARM::VLD3LNd32Pseudo_UPD };
3254 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
3255 ARM::VLD3LNq32Pseudo_UPD };
3256 SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
3260 case ARMISD::VLD4LN_UPD: {
3261 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
3262 ARM::VLD4LNd16Pseudo_UPD,
3263 ARM::VLD4LNd32Pseudo_UPD };
3264 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
3265 ARM::VLD4LNq32Pseudo_UPD };
3266 SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
3270 case ARMISD::VST1_UPD: {
3271 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
3272 ARM::VST1d16wb_fixed,
3273 ARM::VST1d32wb_fixed,
3274 ARM::VST1d64wb_fixed };
3275 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
3276 ARM::VST1q16wb_fixed,
3277 ARM::VST1q32wb_fixed,
3278 ARM::VST1q64wb_fixed };
3279 SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
3283 case ARMISD::VST2_UPD: {
3284 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
3285 ARM::VST2d16wb_fixed,
3286 ARM::VST2d32wb_fixed,
3287 ARM::VST1q64wb_fixed};
3288 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
3289 ARM::VST2q16PseudoWB_fixed,
3290 ARM::VST2q32PseudoWB_fixed };
3291 SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
3295 case ARMISD::VST3_UPD: {
3296 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
3297 ARM::VST3d16Pseudo_UPD,
3298 ARM::VST3d32Pseudo_UPD,
3299 ARM::VST1d64TPseudoWB_fixed};
3300 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3301 ARM::VST3q16Pseudo_UPD,
3302 ARM::VST3q32Pseudo_UPD };
3303 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
3304 ARM::VST3q16oddPseudo_UPD,
3305 ARM::VST3q32oddPseudo_UPD };
3306 SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
3310 case ARMISD::VST4_UPD: {
3311 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
3312 ARM::VST4d16Pseudo_UPD,
3313 ARM::VST4d32Pseudo_UPD,
3314 ARM::VST1d64QPseudoWB_fixed};
3315 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3316 ARM::VST4q16Pseudo_UPD,
3317 ARM::VST4q32Pseudo_UPD };
3318 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
3319 ARM::VST4q16oddPseudo_UPD,
3320 ARM::VST4q32oddPseudo_UPD };
3321 SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
3325 case ARMISD::VST2LN_UPD: {
3326 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
3327 ARM::VST2LNd16Pseudo_UPD,
3328 ARM::VST2LNd32Pseudo_UPD };
3329 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
3330 ARM::VST2LNq32Pseudo_UPD };
3331 SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
3335 case ARMISD::VST3LN_UPD: {
3336 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
3337 ARM::VST3LNd16Pseudo_UPD,
3338 ARM::VST3LNd32Pseudo_UPD };
3339 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
3340 ARM::VST3LNq32Pseudo_UPD };
3341 SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
3345 case ARMISD::VST4LN_UPD: {
3346 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
3347 ARM::VST4LNd16Pseudo_UPD,
3348 ARM::VST4LNd32Pseudo_UPD };
3349 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3350 ARM::VST4LNq32Pseudo_UPD };
3351 SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
3355 case ISD::INTRINSIC_VOID:
3356 case ISD::INTRINSIC_W_CHAIN: {
3357 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3362 case Intrinsic::arm_mrrc:
3363 case Intrinsic::arm_mrrc2: {
3365 SDValue Chain = N->getOperand(0);
3368 if (Subtarget->isThumb())
3369 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2);
3371 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2);
3373 SmallVector<SDValue, 5> Ops;
3374 Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(), dl)); /* coproc */
3375 Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(3))->getZExtValue(), dl)); /* opc */
3376 Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(4))->getZExtValue(), dl)); /* CRm */
3378 // The mrrc2 instruction in ARM doesn't allow predicates, the top 4 bits of the encoded
3379 // instruction will always be '1111' but it is possible in assembly language to specify
3380 // AL as a predicate to mrrc2 but it doesn't make any difference to the encoded instruction.
3381 if (Opc != ARM::MRRC2) {
3382 Ops.push_back(getAL(CurDAG, dl));
3383 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3386 Ops.push_back(Chain);
3388 // Writes to two registers.
3389 const EVT RetType[] = {MVT::i32, MVT::i32, MVT::Other};
3391 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops));
3394 case Intrinsic::arm_ldaexd:
3395 case Intrinsic::arm_ldrexd: {
3397 SDValue Chain = N->getOperand(0);
3398 SDValue MemAddr = N->getOperand(2);
3399 bool isThumb = Subtarget->isThumb() && Subtarget->hasV8MBaselineOps();
3401 bool IsAcquire = IntNo == Intrinsic::arm_ldaexd;
3402 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD)
3403 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD);
3405 // arm_ldrexd returns a i64 value in {i32, i32}
3406 std::vector<EVT> ResTys;
3408 ResTys.push_back(MVT::i32);
3409 ResTys.push_back(MVT::i32);
3411 ResTys.push_back(MVT::Untyped);
3412 ResTys.push_back(MVT::Other);
3414 // Place arguments in the right order.
3415 SDValue Ops[] = {MemAddr, getAL(CurDAG, dl),
3416 CurDAG->getRegister(0, MVT::i32), Chain};
3417 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3418 // Transfer memoperands.
3419 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3420 CurDAG->setNodeMemRefs(cast<MachineSDNode>(Ld), {MemOp});
3423 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
3424 if (!SDValue(N, 0).use_empty()) {
3427 Result = SDValue(Ld, 0);
3430 CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
3431 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3432 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3433 Result = SDValue(ResNode,0);
3435 ReplaceUses(SDValue(N, 0), Result);
3437 if (!SDValue(N, 1).use_empty()) {
3440 Result = SDValue(Ld, 1);
3443 CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
3444 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3445 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3446 Result = SDValue(ResNode,0);
3448 ReplaceUses(SDValue(N, 1), Result);
3450 ReplaceUses(SDValue(N, 2), OutChain);
3451 CurDAG->RemoveDeadNode(N);
3454 case Intrinsic::arm_stlexd:
3455 case Intrinsic::arm_strexd: {
3457 SDValue Chain = N->getOperand(0);
3458 SDValue Val0 = N->getOperand(2);
3459 SDValue Val1 = N->getOperand(3);
3460 SDValue MemAddr = N->getOperand(4);
3462 // Store exclusive double return a i32 value which is the return status
3463 // of the issued store.
3464 const EVT ResTys[] = {MVT::i32, MVT::Other};
3466 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3467 // Place arguments in the right order.
3468 SmallVector<SDValue, 7> Ops;
3470 Ops.push_back(Val0);
3471 Ops.push_back(Val1);
3473 // arm_strexd uses GPRPair.
3474 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3475 Ops.push_back(MemAddr);
3476 Ops.push_back(getAL(CurDAG, dl));
3477 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3478 Ops.push_back(Chain);
3480 bool IsRelease = IntNo == Intrinsic::arm_stlexd;
3481 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD)
3482 : (IsRelease ? ARM::STLEXD : ARM::STREXD);
3484 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3485 // Transfer memoperands.
3486 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3487 CurDAG->setNodeMemRefs(cast<MachineSDNode>(St), {MemOp});
3493 case Intrinsic::arm_neon_vld1: {
3494 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3495 ARM::VLD1d32, ARM::VLD1d64 };
3496 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3497 ARM::VLD1q32, ARM::VLD1q64};
3498 SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
3502 case Intrinsic::arm_neon_vld1x2: {
3503 static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3504 ARM::VLD1q32, ARM::VLD1q64 };
3505 static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo,
3506 ARM::VLD1d16QPseudo,
3507 ARM::VLD1d32QPseudo,
3508 ARM::VLD1d64QPseudo };
3509 SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
3513 case Intrinsic::arm_neon_vld1x3: {
3514 static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo,
3515 ARM::VLD1d16TPseudo,
3516 ARM::VLD1d32TPseudo,
3517 ARM::VLD1d64TPseudo };
3518 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD,
3519 ARM::VLD1q16LowTPseudo_UPD,
3520 ARM::VLD1q32LowTPseudo_UPD,
3521 ARM::VLD1q64LowTPseudo_UPD };
3522 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo,
3523 ARM::VLD1q16HighTPseudo,
3524 ARM::VLD1q32HighTPseudo,
3525 ARM::VLD1q64HighTPseudo };
3526 SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3530 case Intrinsic::arm_neon_vld1x4: {
3531 static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo,
3532 ARM::VLD1d16QPseudo,
3533 ARM::VLD1d32QPseudo,
3534 ARM::VLD1d64QPseudo };
3535 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD,
3536 ARM::VLD1q16LowQPseudo_UPD,
3537 ARM::VLD1q32LowQPseudo_UPD,
3538 ARM::VLD1q64LowQPseudo_UPD };
3539 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo,
3540 ARM::VLD1q16HighQPseudo,
3541 ARM::VLD1q32HighQPseudo,
3542 ARM::VLD1q64HighQPseudo };
3543 SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3547 case Intrinsic::arm_neon_vld2: {
3548 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3549 ARM::VLD2d32, ARM::VLD1q64 };
3550 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3551 ARM::VLD2q32Pseudo };
3552 SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
3556 case Intrinsic::arm_neon_vld3: {
3557 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3560 ARM::VLD1d64TPseudo };
3561 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3562 ARM::VLD3q16Pseudo_UPD,
3563 ARM::VLD3q32Pseudo_UPD };
3564 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3565 ARM::VLD3q16oddPseudo,
3566 ARM::VLD3q32oddPseudo };
3567 SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3571 case Intrinsic::arm_neon_vld4: {
3572 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3575 ARM::VLD1d64QPseudo };
3576 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3577 ARM::VLD4q16Pseudo_UPD,
3578 ARM::VLD4q32Pseudo_UPD };
3579 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3580 ARM::VLD4q16oddPseudo,
3581 ARM::VLD4q32oddPseudo };
3582 SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3586 case Intrinsic::arm_neon_vld2dup: {
3587 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
3588 ARM::VLD2DUPd32, ARM::VLD1q64 };
3589 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo,
3590 ARM::VLD2DUPq16EvenPseudo,
3591 ARM::VLD2DUPq32EvenPseudo };
3592 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudo,
3593 ARM::VLD2DUPq16OddPseudo,
3594 ARM::VLD2DUPq32OddPseudo };
3595 SelectVLDDup(N, /* IsIntrinsic= */ true, false, 2,
3596 DOpcodes, QOpcodes0, QOpcodes1);
3600 case Intrinsic::arm_neon_vld3dup: {
3601 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo,
3602 ARM::VLD3DUPd16Pseudo,
3603 ARM::VLD3DUPd32Pseudo,
3604 ARM::VLD1d64TPseudo };
3605 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo,
3606 ARM::VLD3DUPq16EvenPseudo,
3607 ARM::VLD3DUPq32EvenPseudo };
3608 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo,
3609 ARM::VLD3DUPq16OddPseudo,
3610 ARM::VLD3DUPq32OddPseudo };
3611 SelectVLDDup(N, /* IsIntrinsic= */ true, false, 3,
3612 DOpcodes, QOpcodes0, QOpcodes1);
3616 case Intrinsic::arm_neon_vld4dup: {
3617 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo,
3618 ARM::VLD4DUPd16Pseudo,
3619 ARM::VLD4DUPd32Pseudo,
3620 ARM::VLD1d64QPseudo };
3621 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo,
3622 ARM::VLD4DUPq16EvenPseudo,
3623 ARM::VLD4DUPq32EvenPseudo };
3624 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo,
3625 ARM::VLD4DUPq16OddPseudo,
3626 ARM::VLD4DUPq32OddPseudo };
3627 SelectVLDDup(N, /* IsIntrinsic= */ true, false, 4,
3628 DOpcodes, QOpcodes0, QOpcodes1);
3632 case Intrinsic::arm_neon_vld2lane: {
3633 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3634 ARM::VLD2LNd16Pseudo,
3635 ARM::VLD2LNd32Pseudo };
3636 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3637 ARM::VLD2LNq32Pseudo };
3638 SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3642 case Intrinsic::arm_neon_vld3lane: {
3643 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3644 ARM::VLD3LNd16Pseudo,
3645 ARM::VLD3LNd32Pseudo };
3646 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3647 ARM::VLD3LNq32Pseudo };
3648 SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3652 case Intrinsic::arm_neon_vld4lane: {
3653 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3654 ARM::VLD4LNd16Pseudo,
3655 ARM::VLD4LNd32Pseudo };
3656 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3657 ARM::VLD4LNq32Pseudo };
3658 SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3662 case Intrinsic::arm_neon_vst1: {
3663 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3664 ARM::VST1d32, ARM::VST1d64 };
3665 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3666 ARM::VST1q32, ARM::VST1q64 };
3667 SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
3671 case Intrinsic::arm_neon_vst1x2: {
3672 static const uint16_t DOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3673 ARM::VST1q32, ARM::VST1q64 };
3674 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudo,
3675 ARM::VST1d16QPseudo,
3676 ARM::VST1d32QPseudo,
3677 ARM::VST1d64QPseudo };
3678 SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
3682 case Intrinsic::arm_neon_vst1x3: {
3683 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudo,
3684 ARM::VST1d16TPseudo,
3685 ARM::VST1d32TPseudo,
3686 ARM::VST1d64TPseudo };
3687 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD,
3688 ARM::VST1q16LowTPseudo_UPD,
3689 ARM::VST1q32LowTPseudo_UPD,
3690 ARM::VST1q64LowTPseudo_UPD };
3691 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo,
3692 ARM::VST1q16HighTPseudo,
3693 ARM::VST1q32HighTPseudo,
3694 ARM::VST1q64HighTPseudo };
3695 SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3699 case Intrinsic::arm_neon_vst1x4: {
3700 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudo,
3701 ARM::VST1d16QPseudo,
3702 ARM::VST1d32QPseudo,
3703 ARM::VST1d64QPseudo };
3704 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD,
3705 ARM::VST1q16LowQPseudo_UPD,
3706 ARM::VST1q32LowQPseudo_UPD,
3707 ARM::VST1q64LowQPseudo_UPD };
3708 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo,
3709 ARM::VST1q16HighQPseudo,
3710 ARM::VST1q32HighQPseudo,
3711 ARM::VST1q64HighQPseudo };
3712 SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3716 case Intrinsic::arm_neon_vst2: {
3717 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3718 ARM::VST2d32, ARM::VST1q64 };
3719 static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3720 ARM::VST2q32Pseudo };
3721 SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
3725 case Intrinsic::arm_neon_vst3: {
3726 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3729 ARM::VST1d64TPseudo };
3730 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3731 ARM::VST3q16Pseudo_UPD,
3732 ARM::VST3q32Pseudo_UPD };
3733 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3734 ARM::VST3q16oddPseudo,
3735 ARM::VST3q32oddPseudo };
3736 SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3740 case Intrinsic::arm_neon_vst4: {
3741 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3744 ARM::VST1d64QPseudo };
3745 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3746 ARM::VST4q16Pseudo_UPD,
3747 ARM::VST4q32Pseudo_UPD };
3748 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3749 ARM::VST4q16oddPseudo,
3750 ARM::VST4q32oddPseudo };
3751 SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3755 case Intrinsic::arm_neon_vst2lane: {
3756 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3757 ARM::VST2LNd16Pseudo,
3758 ARM::VST2LNd32Pseudo };
3759 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3760 ARM::VST2LNq32Pseudo };
3761 SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3765 case Intrinsic::arm_neon_vst3lane: {
3766 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3767 ARM::VST3LNd16Pseudo,
3768 ARM::VST3LNd32Pseudo };
3769 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3770 ARM::VST3LNq32Pseudo };
3771 SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3775 case Intrinsic::arm_neon_vst4lane: {
3776 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3777 ARM::VST4LNd16Pseudo,
3778 ARM::VST4LNd32Pseudo };
3779 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3780 ARM::VST4LNq32Pseudo };
3781 SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3788 case ISD::ATOMIC_CMP_SWAP:
3796 // Inspect a register string of the form
3797 // cp<coprocessor>:<opc1>:c<CRn>:c<CRm>:<opc2> (32bit) or
3798 // cp<coprocessor>:<opc1>:c<CRm> (64bit) inspect the fields of the string
3799 // and obtain the integer operands from them, adding these operands to the
3801 static void getIntOperandsFromRegisterString(StringRef RegString,
3802 SelectionDAG *CurDAG,
3804 std::vector<SDValue> &Ops) {
3805 SmallVector<StringRef, 5> Fields;
3806 RegString.split(Fields, ':');
3808 if (Fields.size() > 1) {
3809 bool AllIntFields = true;
3811 for (StringRef Field : Fields) {
3812 // Need to trim out leading 'cp' characters and get the integer field.
3814 AllIntFields &= !Field.trim("CPcp").getAsInteger(10, IntField);
3815 Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32));
3818 assert(AllIntFields &&
3819 "Unexpected non-integer value in special register string.");
3823 // Maps a Banked Register string to its mask value. The mask value returned is
3824 // for use in the MRSbanked / MSRbanked instruction nodes as the Banked Register
3825 // mask operand, which expresses which register is to be used, e.g. r8, and in
3826 // which mode it is to be used, e.g. usr. Returns -1 to signify that the string
3828 static inline int getBankedRegisterMask(StringRef RegString) {
3829 auto TheReg = ARMBankedReg::lookupBankedRegByName(RegString.lower());
3832 return TheReg->Encoding;
3835 // The flags here are common to those allowed for apsr in the A class cores and
3836 // those allowed for the special registers in the M class cores. Returns a
3837 // value representing which flags were present, -1 if invalid.
3838 static inline int getMClassFlagsMask(StringRef Flags) {
3839 return StringSwitch<int>(Flags)
3840 .Case("", 0x2) // no flags means nzcvq for psr registers, and 0x2 is
3841 // correct when flags are not permitted
3844 .Case("nzcvqg", 0x3)
3848 // Maps MClass special registers string to its value for use in the
3849 // t2MRS_M/t2MSR_M instruction nodes as the SYSm value operand.
3850 // Returns -1 to signify that the string was invalid.
3851 static int getMClassRegisterMask(StringRef Reg, const ARMSubtarget *Subtarget) {
3852 auto TheReg = ARMSysReg::lookupMClassSysRegByName(Reg);
3853 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits();
3854 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits))
3856 return (int)(TheReg->Encoding & 0xFFF); // SYSm value
3859 static int getARClassRegisterMask(StringRef Reg, StringRef Flags) {
3860 // The mask operand contains the special register (R Bit) in bit 4, whether
3861 // the register is spsr (R bit is 1) or one of cpsr/apsr (R bit is 0), and
3862 // bits 3-0 contains the fields to be accessed in the special register, set by
3863 // the flags provided with the register.
3865 if (Reg == "apsr") {
3866 // The flags permitted for apsr are the same flags that are allowed in
3867 // M class registers. We get the flag value and then shift the flags into
3868 // the correct place to combine with the mask.
3869 Mask = getMClassFlagsMask(Flags);
3875 if (Reg != "cpsr" && Reg != "spsr") {
3879 // This is the same as if the flags were "fc"
3880 if (Flags.empty() || Flags == "all")
3883 // Inspect the supplied flags string and set the bits in the mask for
3884 // the relevant and valid flags allowed for cpsr and spsr.
3885 for (char Flag : Flags) {
3904 // This avoids allowing strings where the same flag bit appears twice.
3905 if (!FlagVal || (Mask & FlagVal))
3910 // If the register is spsr then we need to set the R bit.
3917 // Lower the read_register intrinsic to ARM specific DAG nodes
3918 // using the supplied metadata string to select the instruction node to use
3919 // and the registers/masks to construct as operands for the node.
3920 bool ARMDAGToDAGISel::tryReadRegister(SDNode *N){
3921 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
3922 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
3923 bool IsThumb2 = Subtarget->isThumb2();
3926 std::vector<SDValue> Ops;
3927 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
3930 // If the special register string was constructed of fields (as defined
3931 // in the ACLE) then need to lower to MRC node (32 bit) or
3932 // MRRC node(64 bit), we can make the distinction based on the number of
3933 // operands we have.
3935 SmallVector<EVT, 3> ResTypes;
3936 if (Ops.size() == 5){
3937 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC;
3938 ResTypes.append({ MVT::i32, MVT::Other });
3940 assert(Ops.size() == 3 &&
3941 "Invalid number of fields in special register string.");
3942 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC;
3943 ResTypes.append({ MVT::i32, MVT::i32, MVT::Other });
3946 Ops.push_back(getAL(CurDAG, DL));
3947 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3948 Ops.push_back(N->getOperand(0));
3949 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops));
3953 std::string SpecialReg = RegString->getString().lower();
3955 int BankedReg = getBankedRegisterMask(SpecialReg);
3956 if (BankedReg != -1) {
3957 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32),
3958 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3961 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked,
3962 DL, MVT::i32, MVT::Other, Ops));
3966 // The VFP registers are read by creating SelectionDAG nodes with opcodes
3967 // corresponding to the register that is being read from. So we switch on the
3968 // string to find which opcode we need to use.
3969 unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
3970 .Case("fpscr", ARM::VMRS)
3971 .Case("fpexc", ARM::VMRS_FPEXC)
3972 .Case("fpsid", ARM::VMRS_FPSID)
3973 .Case("mvfr0", ARM::VMRS_MVFR0)
3974 .Case("mvfr1", ARM::VMRS_MVFR1)
3975 .Case("mvfr2", ARM::VMRS_MVFR2)
3976 .Case("fpinst", ARM::VMRS_FPINST)
3977 .Case("fpinst2", ARM::VMRS_FPINST2)
3980 // If an opcode was found then we can lower the read to a VFP instruction.
3982 if (!Subtarget->hasVFP2())
3984 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8())
3987 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3990 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops));
3994 // If the target is M Class then need to validate that the register string
3995 // is an acceptable value, so check that a mask can be constructed from the
3997 if (Subtarget->isMClass()) {
3998 int SYSmValue = getMClassRegisterMask(SpecialReg, Subtarget);
3999 if (SYSmValue == -1)
4002 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
4003 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4006 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops));
4010 // Here we know the target is not M Class so we need to check if it is one
4011 // of the remaining possible values which are apsr, cpsr or spsr.
4012 if (SpecialReg == "apsr" || SpecialReg == "cpsr") {
4013 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4015 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS,
4016 DL, MVT::i32, MVT::Other, Ops));
4020 if (SpecialReg == "spsr") {
4021 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4024 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL,
4025 MVT::i32, MVT::Other, Ops));
4032 // Lower the write_register intrinsic to ARM specific DAG nodes
4033 // using the supplied metadata string to select the instruction node to use
4034 // and the registers/masks to use in the nodes
4035 bool ARMDAGToDAGISel::tryWriteRegister(SDNode *N){
4036 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
4037 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
4038 bool IsThumb2 = Subtarget->isThumb2();
4041 std::vector<SDValue> Ops;
4042 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
4045 // If the special register string was constructed of fields (as defined
4046 // in the ACLE) then need to lower to MCR node (32 bit) or
4047 // MCRR node(64 bit), we can make the distinction based on the number of
4048 // operands we have.
4050 if (Ops.size() == 5) {
4051 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR;
4052 Ops.insert(Ops.begin()+2, N->getOperand(2));
4054 assert(Ops.size() == 3 &&
4055 "Invalid number of fields in special register string.");
4056 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR;
4057 SDValue WriteValue[] = { N->getOperand(2), N->getOperand(3) };
4058 Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2);
4061 Ops.push_back(getAL(CurDAG, DL));
4062 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4063 Ops.push_back(N->getOperand(0));
4065 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
4069 std::string SpecialReg = RegString->getString().lower();
4070 int BankedReg = getBankedRegisterMask(SpecialReg);
4071 if (BankedReg != -1) {
4072 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2),
4073 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4076 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked,
4077 DL, MVT::Other, Ops));
4081 // The VFP registers are written to by creating SelectionDAG nodes with
4082 // opcodes corresponding to the register that is being written. So we switch
4083 // on the string to find which opcode we need to use.
4084 unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
4085 .Case("fpscr", ARM::VMSR)
4086 .Case("fpexc", ARM::VMSR_FPEXC)
4087 .Case("fpsid", ARM::VMSR_FPSID)
4088 .Case("fpinst", ARM::VMSR_FPINST)
4089 .Case("fpinst2", ARM::VMSR_FPINST2)
4093 if (!Subtarget->hasVFP2())
4095 Ops = { N->getOperand(2), getAL(CurDAG, DL),
4096 CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
4097 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
4101 std::pair<StringRef, StringRef> Fields;
4102 Fields = StringRef(SpecialReg).rsplit('_');
4103 std::string Reg = Fields.first.str();
4104 StringRef Flags = Fields.second;
4106 // If the target was M Class then need to validate the special register value
4107 // and retrieve the mask for use in the instruction node.
4108 if (Subtarget->isMClass()) {
4109 int SYSmValue = getMClassRegisterMask(SpecialReg, Subtarget);
4110 if (SYSmValue == -1)
4113 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
4114 N->getOperand(2), getAL(CurDAG, DL),
4115 CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
4116 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops));
4120 // We then check to see if a valid mask can be constructed for one of the
4121 // register string values permitted for the A and R class cores. These values
4122 // are apsr, spsr and cpsr; these are also valid on older cores.
4123 int Mask = getARClassRegisterMask(Reg, Flags);
4125 Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2),
4126 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
4128 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR,
4129 DL, MVT::Other, Ops));
4136 bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
4137 std::vector<SDValue> AsmNodeOperands;
4138 unsigned Flag, Kind;
4139 bool Changed = false;
4140 unsigned NumOps = N->getNumOperands();
4142 // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
4143 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
4144 // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
4145 // respectively. Since there is no constraint to explicitly specify a
4146 // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
4147 // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
4148 // them into a GPRPair.
4151 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
4152 : SDValue(nullptr,0);
4154 SmallVector<bool, 8> OpChanged;
4155 // Glue node will be appended late.
4156 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
4157 SDValue op = N->getOperand(i);
4158 AsmNodeOperands.push_back(op);
4160 if (i < InlineAsm::Op_FirstOperand)
4163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
4164 Flag = C->getZExtValue();
4165 Kind = InlineAsm::getKind(Flag);
4170 // Immediate operands to inline asm in the SelectionDAG are modeled with
4171 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
4172 // the second is a constant with the value of the immediate. If we get here
4173 // and we have a Kind_Imm, skip the next operand, and continue.
4174 if (Kind == InlineAsm::Kind_Imm) {
4175 SDValue op = N->getOperand(++i);
4176 AsmNodeOperands.push_back(op);
4180 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
4182 OpChanged.push_back(false);
4184 unsigned DefIdx = 0;
4185 bool IsTiedToChangedOp = false;
4186 // If it's a use that is tied with a previous def, it has no
4187 // reg class constraint.
4188 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
4189 IsTiedToChangedOp = OpChanged[DefIdx];
4191 // Memory operands to inline asm in the SelectionDAG are modeled with two
4192 // operands: a constant of value InlineAsm::Kind_Mem followed by the input
4193 // operand. If we get here and we have a Kind_Mem, skip the next operand (so
4194 // it doesn't get misinterpreted), and continue. We do this here because
4195 // it's important to update the OpChanged array correctly before moving on.
4196 if (Kind == InlineAsm::Kind_Mem) {
4197 SDValue op = N->getOperand(++i);
4198 AsmNodeOperands.push_back(op);
4202 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
4203 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
4207 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
4208 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
4212 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
4213 SDValue V0 = N->getOperand(i+1);
4214 SDValue V1 = N->getOperand(i+2);
4215 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
4216 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
4218 MachineRegisterInfo &MRI = MF->getRegInfo();
4220 if (Kind == InlineAsm::Kind_RegDef ||
4221 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
4222 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
4223 // the original GPRs.
4225 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
4226 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
4227 SDValue Chain = SDValue(N,0);
4229 SDNode *GU = N->getGluedUser();
4230 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
4233 // Extract values from a GPRPair reg and copy to the original GPR reg.
4234 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
4236 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
4238 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
4239 RegCopy.getValue(1));
4240 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
4242 // Update the original glue user.
4243 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
4244 Ops.push_back(T1.getValue(1));
4245 CurDAG->UpdateNodeOperands(GU, Ops);
4248 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
4249 // GPRPair and then pass the GPRPair to the inline asm.
4250 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
4252 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
4253 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
4255 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
4257 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
4259 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
4260 // i32 VRs of inline asm with it.
4261 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
4262 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
4263 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
4265 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
4266 Glue = Chain.getValue(1);
4271 if(PairedReg.getNode()) {
4272 OpChanged[OpChanged.size() -1 ] = true;
4273 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
4274 if (IsTiedToChangedOp)
4275 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
4277 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
4278 // Replace the current flag.
4279 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
4280 Flag, dl, MVT::i32);
4281 // Add the new register node and skip the original two GPRs.
4282 AsmNodeOperands.push_back(PairedReg);
4283 // Skip the next two GPRs.
4289 AsmNodeOperands.push_back(Glue);
4293 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
4294 CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
4296 ReplaceNode(N, New.getNode());
4301 bool ARMDAGToDAGISel::
4302 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
4303 std::vector<SDValue> &OutOps) {
4304 switch(ConstraintID) {
4306 llvm_unreachable("Unexpected asm memory constraint");
4307 case InlineAsm::Constraint_i:
4308 // FIXME: It seems strange that 'i' is needed here since it's supposed to
4309 // be an immediate and not a memory constraint.
4311 case InlineAsm::Constraint_m:
4312 case InlineAsm::Constraint_o:
4313 case InlineAsm::Constraint_Q:
4314 case InlineAsm::Constraint_Um:
4315 case InlineAsm::Constraint_Un:
4316 case InlineAsm::Constraint_Uq:
4317 case InlineAsm::Constraint_Us:
4318 case InlineAsm::Constraint_Ut:
4319 case InlineAsm::Constraint_Uv:
4320 case InlineAsm::Constraint_Uy:
4321 // Require the address to be in a register. That is safe for all ARM
4322 // variants and it is hard to do anything much smarter without knowing
4323 // how the operand is used.
4324 OutOps.push_back(Op);
4330 /// createARMISelDag - This pass converts a legalized DAG into a
4331 /// ARM-specific DAG, ready for instruction scheduling.
4333 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
4334 CodeGenOpt::Level OptLevel) {
4335 return new ARMDAGToDAGISel(TM, OptLevel);