1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSelectionDAGInfo.h"
24 #include "ARMSubtarget.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMBaseInfo.h"
27 #include "Utils/ARMBaseInfo.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/APInt.h"
30 #include "llvm/ADT/ArrayRef.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/ADT/SmallPtrSet.h"
35 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/StringExtras.h"
38 #include "llvm/ADT/StringRef.h"
39 #include "llvm/ADT/StringSwitch.h"
40 #include "llvm/ADT/Triple.h"
41 #include "llvm/ADT/Twine.h"
42 #include "llvm/Analysis/VectorUtils.h"
43 #include "llvm/CodeGen/CallingConvLower.h"
44 #include "llvm/CodeGen/ISDOpcodes.h"
45 #include "llvm/CodeGen/IntrinsicLowering.h"
46 #include "llvm/CodeGen/MachineBasicBlock.h"
47 #include "llvm/CodeGen/MachineConstantPool.h"
48 #include "llvm/CodeGen/MachineFrameInfo.h"
49 #include "llvm/CodeGen/MachineFunction.h"
50 #include "llvm/CodeGen/MachineInstr.h"
51 #include "llvm/CodeGen/MachineInstrBuilder.h"
52 #include "llvm/CodeGen/MachineJumpTableInfo.h"
53 #include "llvm/CodeGen/MachineMemOperand.h"
54 #include "llvm/CodeGen/MachineOperand.h"
55 #include "llvm/CodeGen/MachineRegisterInfo.h"
56 #include "llvm/CodeGen/RuntimeLibcalls.h"
57 #include "llvm/CodeGen/SelectionDAG.h"
58 #include "llvm/CodeGen/SelectionDAGNodes.h"
59 #include "llvm/CodeGen/TargetInstrInfo.h"
60 #include "llvm/CodeGen/TargetLowering.h"
61 #include "llvm/CodeGen/TargetOpcodes.h"
62 #include "llvm/CodeGen/TargetRegisterInfo.h"
63 #include "llvm/CodeGen/TargetSubtargetInfo.h"
64 #include "llvm/CodeGen/ValueTypes.h"
65 #include "llvm/IR/Attributes.h"
66 #include "llvm/IR/CallingConv.h"
67 #include "llvm/IR/Constant.h"
68 #include "llvm/IR/Constants.h"
69 #include "llvm/IR/DataLayout.h"
70 #include "llvm/IR/DebugLoc.h"
71 #include "llvm/IR/DerivedTypes.h"
72 #include "llvm/IR/Function.h"
73 #include "llvm/IR/GlobalAlias.h"
74 #include "llvm/IR/GlobalValue.h"
75 #include "llvm/IR/GlobalVariable.h"
76 #include "llvm/IR/IRBuilder.h"
77 #include "llvm/IR/InlineAsm.h"
78 #include "llvm/IR/Instruction.h"
79 #include "llvm/IR/Instructions.h"
80 #include "llvm/IR/IntrinsicInst.h"
81 #include "llvm/IR/Intrinsics.h"
82 #include "llvm/IR/Module.h"
83 #include "llvm/IR/Type.h"
84 #include "llvm/IR/User.h"
85 #include "llvm/IR/Value.h"
86 #include "llvm/MC/MCInstrDesc.h"
87 #include "llvm/MC/MCInstrItineraries.h"
88 #include "llvm/MC/MCRegisterInfo.h"
89 #include "llvm/MC/MCSchedule.h"
90 #include "llvm/Support/AtomicOrdering.h"
91 #include "llvm/Support/BranchProbability.h"
92 #include "llvm/Support/Casting.h"
93 #include "llvm/Support/CodeGen.h"
94 #include "llvm/Support/CommandLine.h"
95 #include "llvm/Support/Compiler.h"
96 #include "llvm/Support/Debug.h"
97 #include "llvm/Support/ErrorHandling.h"
98 #include "llvm/Support/KnownBits.h"
99 #include "llvm/Support/MachineValueType.h"
100 #include "llvm/Support/MathExtras.h"
101 #include "llvm/Support/raw_ostream.h"
102 #include "llvm/Target/TargetMachine.h"
103 #include "llvm/Target/TargetOptions.h"
115 using namespace llvm;
117 #define DEBUG_TYPE "arm-isel"
119 STATISTIC(NumTailCalls, "Number of tail calls");
120 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
121 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
122 STATISTIC(NumConstpoolPromoted,
123 "Number of constants with their storage promoted into constant pools");
126 ARMInterworking("arm-interworking", cl::Hidden,
127 cl::desc("Enable / disable ARM interworking (for debugging only)"),
130 static cl::opt<bool> EnableConstpoolPromotion(
131 "arm-promote-constant", cl::Hidden,
132 cl::desc("Enable / disable promotion of unnamed_addr constants into "
134 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
135 static cl::opt<unsigned> ConstpoolPromotionMaxSize(
136 "arm-promote-constant-max-size", cl::Hidden,
137 cl::desc("Maximum size of constant to promote into a constant pool"),
139 static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
140 "arm-promote-constant-max-total", cl::Hidden,
141 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
144 // The APCS parameter registers.
145 static const MCPhysReg GPRArgRegs[] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
149 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150 MVT PromotedBitwiseVT) {
151 if (VT != PromotedLdStVT) {
152 setOperationAction(ISD::LOAD, VT, Promote);
153 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
155 setOperationAction(ISD::STORE, VT, Promote);
156 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
159 MVT ElemTy = VT.getVectorElementType();
160 if (ElemTy != MVT::f64)
161 setOperationAction(ISD::SETCC, VT, Custom);
162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
164 if (ElemTy == MVT::i32) {
165 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
166 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
168 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
171 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
173 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
175 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
179 setOperationAction(ISD::SELECT, VT, Expand);
180 setOperationAction(ISD::SELECT_CC, VT, Expand);
181 setOperationAction(ISD::VSELECT, VT, Expand);
182 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
183 if (VT.isInteger()) {
184 setOperationAction(ISD::SHL, VT, Custom);
185 setOperationAction(ISD::SRA, VT, Custom);
186 setOperationAction(ISD::SRL, VT, Custom);
189 // Promote all bit-wise operations.
190 if (VT.isInteger() && VT != PromotedBitwiseVT) {
191 setOperationAction(ISD::AND, VT, Promote);
192 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
193 setOperationAction(ISD::OR, VT, Promote);
194 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
195 setOperationAction(ISD::XOR, VT, Promote);
196 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
199 // Neon does not support vector divide/remainder operations.
200 setOperationAction(ISD::SDIV, VT, Expand);
201 setOperationAction(ISD::UDIV, VT, Expand);
202 setOperationAction(ISD::FDIV, VT, Expand);
203 setOperationAction(ISD::SREM, VT, Expand);
204 setOperationAction(ISD::UREM, VT, Expand);
205 setOperationAction(ISD::FREM, VT, Expand);
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
213 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214 addRegisterClass(VT, &ARM::DPRRegClass);
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
218 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219 addRegisterClass(VT, &ARM::DPairRegClass);
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
223 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
224 const ARMSubtarget &STI)
225 : TargetLowering(TM), Subtarget(&STI) {
226 RegInfo = Subtarget->getRegisterInfo();
227 Itins = Subtarget->getInstrItineraryData();
229 setBooleanContents(ZeroOrOneBooleanContent);
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233 !Subtarget->isTargetWatchOS()) {
234 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
238 : CallingConv::ARM_AAPCS);
241 if (Subtarget->isTargetMachO()) {
242 // Uses VFP for Thumb libfuncs if available.
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245 static const struct {
246 const RTLIB::Libcall Op;
247 const char * const Name;
248 const ISD::CondCode Cond;
250 // Single-precision floating-point arithmetic.
251 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
256 // Double-precision floating-point arithmetic.
257 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
262 // Single-precision comparisons.
263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
272 // Double-precision comparisons.
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
282 // Floating-point to integer conversions.
283 // i64 conversions are done via library routines even when generating VFP
284 // instructions, so use the same ones.
285 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
290 // Conversions between floating types.
291 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
294 // Integer to floating-point conversions.
295 // i64 conversions are done via library routines even when generating VFP
296 // instructions, so use the same ones.
297 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298 // e.g., __floatunsidf vs. __floatunssidfvfp.
299 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
305 for (const auto &LC : LibraryCalls) {
306 setLibcallName(LC.Op, LC.Name);
307 if (LC.Cond != ISD::SETCC_INVALID)
308 setCmpLibcallCC(LC.Op, LC.Cond);
313 // These libcalls are not available in 32-bit.
314 setLibcallName(RTLIB::SHL_I128, nullptr);
315 setLibcallName(RTLIB::SRL_I128, nullptr);
316 setLibcallName(RTLIB::SRA_I128, nullptr);
319 if (Subtarget->isAAPCS_ABI() &&
320 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
321 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
322 static const struct {
323 const RTLIB::Libcall Op;
324 const char * const Name;
325 const CallingConv::ID CC;
326 const ISD::CondCode Cond;
328 // Double-precision floating-point arithmetic helper functions
329 // RTABI chapter 4.1.2, Table 2
330 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
331 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 // Double-precision floating-point comparison helper functions
336 // RTABI chapter 4.1.2, Table 3
337 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
338 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
339 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
340 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
341 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
342 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
343 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
344 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
346 // Single-precision floating-point arithmetic helper functions
347 // RTABI chapter 4.1.2, Table 4
348 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
349 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
351 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
353 // Single-precision floating-point comparison helper functions
354 // RTABI chapter 4.1.2, Table 5
355 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
356 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
357 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
358 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
359 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
360 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
361 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
362 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
364 // Floating-point to integer conversions.
365 // RTABI chapter 4.1.2, Table 6
366 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
367 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
368 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
369 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
370 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
371 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
372 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
373 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
375 // Conversions between floating types.
376 // RTABI chapter 4.1.2, Table 7
377 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
381 // Integer to floating-point conversions.
382 // RTABI chapter 4.1.2, Table 8
383 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
384 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
388 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
389 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
390 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
392 // Long long helper functions
393 // RTABI chapter 4.2, Table 9
394 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
399 // Integer division functions
400 // RTABI chapter 4.3.1
401 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
406 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
407 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
408 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
411 for (const auto &LC : LibraryCalls) {
412 setLibcallName(LC.Op, LC.Name);
413 setLibcallCallingConv(LC.Op, LC.CC);
414 if (LC.Cond != ISD::SETCC_INVALID)
415 setCmpLibcallCC(LC.Op, LC.Cond);
418 // EABI dependent RTLIB
419 if (TM.Options.EABIVersion == EABI::EABI4 ||
420 TM.Options.EABIVersion == EABI::EABI5) {
421 static const struct {
422 const RTLIB::Libcall Op;
423 const char *const Name;
424 const CallingConv::ID CC;
425 const ISD::CondCode Cond;
426 } MemOpsLibraryCalls[] = {
428 // RTABI chapter 4.3.4
429 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
430 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
431 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
434 for (const auto &LC : MemOpsLibraryCalls) {
435 setLibcallName(LC.Op, LC.Name);
436 setLibcallCallingConv(LC.Op, LC.CC);
437 if (LC.Cond != ISD::SETCC_INVALID)
438 setCmpLibcallCC(LC.Op, LC.Cond);
443 if (Subtarget->isTargetWindows()) {
444 static const struct {
445 const RTLIB::Libcall Op;
446 const char * const Name;
447 const CallingConv::ID CC;
449 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
450 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
451 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
452 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
453 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
454 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
455 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
456 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
459 for (const auto &LC : LibraryCalls) {
460 setLibcallName(LC.Op, LC.Name);
461 setLibcallCallingConv(LC.Op, LC.CC);
465 // Use divmod compiler-rt calls for iOS 5.0 and later.
466 if (Subtarget->isTargetMachO() &&
467 !(Subtarget->isTargetIOS() &&
468 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
469 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
470 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
473 // The half <-> float conversion functions are always soft-float on
474 // non-watchos platforms, but are needed for some targets which use a
475 // hard-float calling convention by default.
476 if (!Subtarget->isTargetWatchABI()) {
477 if (Subtarget->isAAPCS_ABI()) {
478 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
479 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
480 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
482 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
483 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
484 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
488 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
489 // a __gnu_ prefix (which is the default).
490 if (Subtarget->isTargetAEABI()) {
491 static const struct {
492 const RTLIB::Libcall Op;
493 const char * const Name;
494 const CallingConv::ID CC;
496 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
497 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
498 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
501 for (const auto &LC : LibraryCalls) {
502 setLibcallName(LC.Op, LC.Name);
503 setLibcallCallingConv(LC.Op, LC.CC);
507 if (Subtarget->isThumb1Only())
508 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
510 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
512 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
513 !Subtarget->isThumb1Only()) {
514 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
515 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
518 if (Subtarget->hasFullFP16()) {
519 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
520 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
521 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
522 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
524 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
525 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
528 for (MVT VT : MVT::vector_valuetypes()) {
529 for (MVT InnerVT : MVT::vector_valuetypes()) {
530 setTruncStoreAction(VT, InnerVT, Expand);
531 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
532 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
533 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
536 setOperationAction(ISD::MULHS, VT, Expand);
537 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
538 setOperationAction(ISD::MULHU, VT, Expand);
539 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
541 setOperationAction(ISD::BSWAP, VT, Expand);
544 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
545 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
547 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
548 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
550 if (Subtarget->hasNEON()) {
551 addDRTypeForNEON(MVT::v2f32);
552 addDRTypeForNEON(MVT::v8i8);
553 addDRTypeForNEON(MVT::v4i16);
554 addDRTypeForNEON(MVT::v2i32);
555 addDRTypeForNEON(MVT::v1i64);
557 addQRTypeForNEON(MVT::v4f32);
558 addQRTypeForNEON(MVT::v2f64);
559 addQRTypeForNEON(MVT::v16i8);
560 addQRTypeForNEON(MVT::v8i16);
561 addQRTypeForNEON(MVT::v4i32);
562 addQRTypeForNEON(MVT::v2i64);
564 if (Subtarget->hasFullFP16()) {
565 addQRTypeForNEON(MVT::v8f16);
566 addDRTypeForNEON(MVT::v4f16);
569 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
570 // neither Neon nor VFP support any arithmetic operations on it.
571 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
572 // supported for v4f32.
573 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
574 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
575 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
576 // FIXME: Code duplication: FDIV and FREM are expanded always, see
577 // ARMTargetLowering::addTypeForNEON method for details.
578 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
579 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
580 // FIXME: Create unittest.
581 // In another words, find a way when "copysign" appears in DAG with vector
583 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
584 // FIXME: Code duplication: SETCC has custom operation action, see
585 // ARMTargetLowering::addTypeForNEON method for details.
586 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
587 // FIXME: Create unittest for FNEG and for FABS.
588 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
589 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
590 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
591 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
592 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
593 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
594 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
595 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
596 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
597 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
598 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
599 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
600 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
601 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
602 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
603 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
604 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
605 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
607 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
608 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
609 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
610 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
611 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
612 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
613 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
614 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
615 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
616 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
617 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
618 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
619 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
620 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
622 // Mark v2f32 intrinsics.
623 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
624 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
625 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
626 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
627 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
628 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
629 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
630 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
631 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
632 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
633 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
634 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
635 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
636 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
638 // Neon does not support some operations on v1i64 and v2i64 types.
639 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
640 // Custom handling for some quad-vector types to detect VMULL.
641 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
642 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
643 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
644 // Custom handling for some vector types to avoid expensive expansions
645 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
646 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
647 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
648 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
649 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
650 // a destination type that is wider than the source, and nor does
651 // it have a FP_TO_[SU]INT instruction with a narrower destination than
653 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
654 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
655 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
656 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
657 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
658 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
659 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
660 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
662 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
663 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
665 // NEON does not have single instruction CTPOP for vectors with element
666 // types wider than 8-bits. However, custom lowering can leverage the
667 // v8i8/v16i8 vcnt instruction.
668 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
669 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
670 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
671 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
672 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
673 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
675 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
676 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
678 // NEON does not have single instruction CTTZ for vectors.
679 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
680 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
681 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
682 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
684 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
685 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
686 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
687 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
689 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
694 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
695 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
696 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
697 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
699 // NEON only has FMA instructions as of VFP4.
700 if (!Subtarget->hasVFP4()) {
701 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
702 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
705 setTargetDAGCombine(ISD::INTRINSIC_VOID);
706 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
707 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
708 setTargetDAGCombine(ISD::SHL);
709 setTargetDAGCombine(ISD::SRL);
710 setTargetDAGCombine(ISD::SRA);
711 setTargetDAGCombine(ISD::SIGN_EXTEND);
712 setTargetDAGCombine(ISD::ZERO_EXTEND);
713 setTargetDAGCombine(ISD::ANY_EXTEND);
714 setTargetDAGCombine(ISD::BUILD_VECTOR);
715 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
716 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
717 setTargetDAGCombine(ISD::STORE);
718 setTargetDAGCombine(ISD::FP_TO_SINT);
719 setTargetDAGCombine(ISD::FP_TO_UINT);
720 setTargetDAGCombine(ISD::FDIV);
721 setTargetDAGCombine(ISD::LOAD);
723 // It is legal to extload from v4i8 to v4i16 or v4i32.
724 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
726 for (MVT VT : MVT::integer_vector_valuetypes()) {
727 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
728 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
729 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
734 if (Subtarget->isFPOnlySP()) {
735 // When targeting a floating-point unit with only single-precision
736 // operations, f64 is legal for the few double-precision instructions which
737 // are present However, no double-precision operations other than moves,
738 // loads and stores are provided by the hardware.
739 setOperationAction(ISD::FADD, MVT::f64, Expand);
740 setOperationAction(ISD::FSUB, MVT::f64, Expand);
741 setOperationAction(ISD::FMUL, MVT::f64, Expand);
742 setOperationAction(ISD::FMA, MVT::f64, Expand);
743 setOperationAction(ISD::FDIV, MVT::f64, Expand);
744 setOperationAction(ISD::FREM, MVT::f64, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
747 setOperationAction(ISD::FNEG, MVT::f64, Expand);
748 setOperationAction(ISD::FABS, MVT::f64, Expand);
749 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
750 setOperationAction(ISD::FSIN, MVT::f64, Expand);
751 setOperationAction(ISD::FCOS, MVT::f64, Expand);
752 setOperationAction(ISD::FPOW, MVT::f64, Expand);
753 setOperationAction(ISD::FLOG, MVT::f64, Expand);
754 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
755 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
756 setOperationAction(ISD::FEXP, MVT::f64, Expand);
757 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
758 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
760 setOperationAction(ISD::FRINT, MVT::f64, Expand);
761 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
762 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
763 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
764 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
765 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
766 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
767 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
768 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
769 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
770 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
773 computeRegisterProperties(Subtarget->getRegisterInfo());
775 // ARM does not have floating-point extending loads.
776 for (MVT VT : MVT::fp_valuetypes()) {
777 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
778 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
781 // ... or truncating stores
782 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
783 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
784 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
786 // ARM does not have i1 sign extending load.
787 for (MVT VT : MVT::integer_valuetypes())
788 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
790 // ARM supports all 4 flavors of integer indexed load / store.
791 if (!Subtarget->isThumb1Only()) {
792 for (unsigned im = (unsigned)ISD::PRE_INC;
793 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
794 setIndexedLoadAction(im, MVT::i1, Legal);
795 setIndexedLoadAction(im, MVT::i8, Legal);
796 setIndexedLoadAction(im, MVT::i16, Legal);
797 setIndexedLoadAction(im, MVT::i32, Legal);
798 setIndexedStoreAction(im, MVT::i1, Legal);
799 setIndexedStoreAction(im, MVT::i8, Legal);
800 setIndexedStoreAction(im, MVT::i16, Legal);
801 setIndexedStoreAction(im, MVT::i32, Legal);
804 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
805 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
806 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
809 setOperationAction(ISD::SADDO, MVT::i32, Custom);
810 setOperationAction(ISD::UADDO, MVT::i32, Custom);
811 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
812 setOperationAction(ISD::USUBO, MVT::i32, Custom);
814 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
815 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
817 // i64 operation support.
818 setOperationAction(ISD::MUL, MVT::i64, Expand);
819 setOperationAction(ISD::MULHU, MVT::i32, Expand);
820 if (Subtarget->isThumb1Only()) {
821 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
822 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
824 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
825 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
826 setOperationAction(ISD::MULHS, MVT::i32, Expand);
828 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
829 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
830 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
831 setOperationAction(ISD::SRL, MVT::i64, Custom);
832 setOperationAction(ISD::SRA, MVT::i64, Custom);
833 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
835 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
836 if (Subtarget->isThumb1Only()) {
837 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
838 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
839 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
842 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
843 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
845 // ARM does not have ROTL.
846 setOperationAction(ISD::ROTL, MVT::i32, Expand);
847 for (MVT VT : MVT::vector_valuetypes()) {
848 setOperationAction(ISD::ROTL, VT, Expand);
849 setOperationAction(ISD::ROTR, VT, Expand);
851 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
853 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
854 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
858 // @llvm.readcyclecounter requires the Performance Monitors extension.
859 // Default to the 0 expansion on unsupported platforms.
860 // FIXME: Technically there are older ARM CPUs that have
861 // implementation-specific ways of obtaining this information.
862 if (Subtarget->hasPerfMon())
863 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
865 // Only ARMv6 has BSWAP.
866 if (!Subtarget->hasV6Ops())
867 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
869 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
870 : Subtarget->hasDivideInARMMode();
872 // These are expanded into libcalls if the cpu doesn't have HW divider.
873 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
874 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
877 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
878 setOperationAction(ISD::SDIV, MVT::i32, Custom);
879 setOperationAction(ISD::UDIV, MVT::i32, Custom);
881 setOperationAction(ISD::SDIV, MVT::i64, Custom);
882 setOperationAction(ISD::UDIV, MVT::i64, Custom);
885 setOperationAction(ISD::SREM, MVT::i32, Expand);
886 setOperationAction(ISD::UREM, MVT::i32, Expand);
888 // Register based DivRem for AEABI (RTABI 4.2)
889 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
890 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
891 Subtarget->isTargetWindows()) {
892 setOperationAction(ISD::SREM, MVT::i64, Custom);
893 setOperationAction(ISD::UREM, MVT::i64, Custom);
894 HasStandaloneRem = false;
896 if (Subtarget->isTargetWindows()) {
898 const RTLIB::Libcall Op;
899 const char * const Name;
900 const CallingConv::ID CC;
902 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
903 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
904 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
905 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
907 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
908 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
909 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
910 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
913 for (const auto &LC : LibraryCalls) {
914 setLibcallName(LC.Op, LC.Name);
915 setLibcallCallingConv(LC.Op, LC.CC);
919 const RTLIB::Libcall Op;
920 const char * const Name;
921 const CallingConv::ID CC;
923 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
924 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
925 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
926 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
928 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
929 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
930 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
931 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
934 for (const auto &LC : LibraryCalls) {
935 setLibcallName(LC.Op, LC.Name);
936 setLibcallCallingConv(LC.Op, LC.CC);
940 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
941 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
942 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
943 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
945 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
946 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
949 if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
950 for (auto &VT : {MVT::f32, MVT::f64})
951 setOperationAction(ISD::FPOWI, VT, Custom);
953 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
954 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
955 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
956 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
958 setOperationAction(ISD::TRAP, MVT::Other, Legal);
959 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
961 // Use the default implementation.
962 setOperationAction(ISD::VASTART, MVT::Other, Custom);
963 setOperationAction(ISD::VAARG, MVT::Other, Expand);
964 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
965 setOperationAction(ISD::VAEND, MVT::Other, Expand);
966 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
967 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
969 if (Subtarget->isTargetWindows())
970 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
972 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
974 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
975 // the default expansion.
976 InsertFencesForAtomic = false;
977 if (Subtarget->hasAnyDataBarrier() &&
978 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
979 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
980 // to ldrex/strex loops already.
981 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
982 if (!Subtarget->isThumb() || !Subtarget->isMClass())
983 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
985 // On v8, we have particularly efficient implementations of atomic fences
986 // if they can be combined with nearby atomic loads and stores.
987 if (!Subtarget->hasAcquireRelease() ||
988 getTargetMachine().getOptLevel() == 0) {
989 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
990 InsertFencesForAtomic = true;
993 // If there's anything we can use as a barrier, go through custom lowering
995 // If target has DMB in thumb, Fences can be inserted.
996 if (Subtarget->hasDataBarrier())
997 InsertFencesForAtomic = true;
999 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1000 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1002 // Set them all for expansion, which will force libcalls.
1003 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1004 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1005 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1006 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1007 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1008 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1009 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1010 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1011 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1012 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1013 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1014 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1015 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1016 // Unordered/Monotonic case.
1017 if (!InsertFencesForAtomic) {
1018 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1019 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1023 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1025 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1026 if (!Subtarget->hasV6Ops()) {
1027 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1028 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1030 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1032 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1033 !Subtarget->isThumb1Only()) {
1034 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1035 // iff target supports vfp2.
1036 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1037 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1040 // We want to custom lower some of our intrinsics.
1041 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1042 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1043 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1044 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1045 if (Subtarget->useSjLjEH())
1046 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1048 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1049 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1050 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1051 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1052 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1053 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1054 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1055 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1056 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1057 if (Subtarget->hasFullFP16()) {
1058 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1059 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1060 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1063 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1065 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1066 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1067 if (Subtarget->hasFullFP16())
1068 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1069 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1070 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1071 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1073 // We don't support sin/cos/fmod/copysign/pow
1074 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1075 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1076 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1077 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1078 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1079 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1080 setOperationAction(ISD::FREM, MVT::f64, Expand);
1081 setOperationAction(ISD::FREM, MVT::f32, Expand);
1082 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1083 !Subtarget->isThumb1Only()) {
1084 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1085 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1087 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1088 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1090 if (!Subtarget->hasVFP4()) {
1091 setOperationAction(ISD::FMA, MVT::f64, Expand);
1092 setOperationAction(ISD::FMA, MVT::f32, Expand);
1095 // Various VFP goodness
1096 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1097 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1098 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1099 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1100 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1103 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1104 if (!Subtarget->hasFP16()) {
1105 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1106 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1110 // Use __sincos_stret if available.
1111 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1112 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1113 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1114 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1117 // FP-ARMv8 implements a lot of rounding-like FP operations.
1118 if (Subtarget->hasFPARMv8()) {
1119 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1120 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1121 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1122 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1123 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1124 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1125 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1126 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1127 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1128 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1129 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1130 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1132 if (!Subtarget->isFPOnlySP()) {
1133 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1135 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1136 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1138 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1139 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1140 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1144 if (Subtarget->hasNEON()) {
1145 // vmin and vmax aren't available in a scalar form, so we use
1146 // a NEON instruction with an undef lane instead.
1147 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1148 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1149 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1150 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1151 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1152 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1153 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1154 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1156 if (Subtarget->hasFullFP16()) {
1157 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1158 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1159 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1160 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1162 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1163 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1164 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1165 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1169 // We have target-specific dag combine patterns for the following nodes:
1170 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1171 setTargetDAGCombine(ISD::ADD);
1172 setTargetDAGCombine(ISD::SUB);
1173 setTargetDAGCombine(ISD::MUL);
1174 setTargetDAGCombine(ISD::AND);
1175 setTargetDAGCombine(ISD::OR);
1176 setTargetDAGCombine(ISD::XOR);
1178 if (Subtarget->hasV6Ops())
1179 setTargetDAGCombine(ISD::SRL);
1181 setStackPointerRegisterToSaveRestore(ARM::SP);
1183 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1184 !Subtarget->hasVFP2())
1185 setSchedulingPreference(Sched::RegPressure);
1187 setSchedulingPreference(Sched::Hybrid);
1189 //// temporary - rewrite interface to use type
1190 MaxStoresPerMemset = 8;
1191 MaxStoresPerMemsetOptSize = 4;
1192 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1193 MaxStoresPerMemcpyOptSize = 2;
1194 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1195 MaxStoresPerMemmoveOptSize = 2;
1197 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1198 // are at least 4 bytes aligned.
1199 setMinStackArgumentAlignment(4);
1201 // Prefer likely predicted branches to selects on out-of-order cores.
1202 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1204 setPrefLoopAlignment(Subtarget->getPrefLoopAlignment());
1206 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1209 bool ARMTargetLowering::useSoftFloat() const {
1210 return Subtarget->useSoftFloat();
1213 // FIXME: It might make sense to define the representative register class as the
1214 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1215 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1216 // SPR's representative would be DPR_VFP2. This should work well if register
1217 // pressure tracking were modified such that a register use would increment the
1218 // pressure of the register class's representative and all of it's super
1219 // classes' representatives transitively. We have not implemented this because
1220 // of the difficulty prior to coalescing of modeling operand register classes
1221 // due to the common occurrence of cross class copies and subregister insertions
1223 std::pair<const TargetRegisterClass *, uint8_t>
1224 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1226 const TargetRegisterClass *RRC = nullptr;
1228 switch (VT.SimpleTy) {
1230 return TargetLowering::findRepresentativeClass(TRI, VT);
1231 // Use DPR as representative register class for all floating point
1232 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1233 // the cost is 1 for both f32 and f64.
1234 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1235 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1236 RRC = &ARM::DPRRegClass;
1237 // When NEON is used for SP, only half of the register file is available
1238 // because operations that define both SP and DP results will be constrained
1239 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1240 // coalescing by double-counting the SP regs. See the FIXME above.
1241 if (Subtarget->useNEONForSinglePrecisionFP())
1244 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1245 case MVT::v4f32: case MVT::v2f64:
1246 RRC = &ARM::DPRRegClass;
1250 RRC = &ARM::DPRRegClass;
1254 RRC = &ARM::DPRRegClass;
1258 return std::make_pair(RRC, Cost);
1261 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1262 switch ((ARMISD::NodeType)Opcode) {
1263 case ARMISD::FIRST_NUMBER: break;
1264 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1265 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1266 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1267 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1268 case ARMISD::CALL: return "ARMISD::CALL";
1269 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1270 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1271 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1272 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1273 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1274 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1275 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1276 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1277 case ARMISD::CMP: return "ARMISD::CMP";
1278 case ARMISD::CMN: return "ARMISD::CMN";
1279 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1280 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1281 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1282 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1283 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1285 case ARMISD::CMOV: return "ARMISD::CMOV";
1286 case ARMISD::SUBS: return "ARMISD::SUBS";
1288 case ARMISD::SSAT: return "ARMISD::SSAT";
1289 case ARMISD::USAT: return "ARMISD::USAT";
1291 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1292 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1293 case ARMISD::RRX: return "ARMISD::RRX";
1295 case ARMISD::ADDC: return "ARMISD::ADDC";
1296 case ARMISD::ADDE: return "ARMISD::ADDE";
1297 case ARMISD::SUBC: return "ARMISD::SUBC";
1298 case ARMISD::SUBE: return "ARMISD::SUBE";
1300 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1301 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1302 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1303 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1304 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1306 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1307 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1308 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1310 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1312 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1314 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1316 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1318 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1320 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1321 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1323 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1324 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1325 case ARMISD::VCGE: return "ARMISD::VCGE";
1326 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1327 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1328 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1329 case ARMISD::VCGT: return "ARMISD::VCGT";
1330 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1331 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1332 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1333 case ARMISD::VTST: return "ARMISD::VTST";
1335 case ARMISD::VSHL: return "ARMISD::VSHL";
1336 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1337 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1338 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1339 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1340 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1341 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1342 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1343 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1344 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1345 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1346 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1347 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1348 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1349 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1350 case ARMISD::VSLI: return "ARMISD::VSLI";
1351 case ARMISD::VSRI: return "ARMISD::VSRI";
1352 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1353 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1354 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1355 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1356 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1357 case ARMISD::VDUP: return "ARMISD::VDUP";
1358 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1359 case ARMISD::VEXT: return "ARMISD::VEXT";
1360 case ARMISD::VREV64: return "ARMISD::VREV64";
1361 case ARMISD::VREV32: return "ARMISD::VREV32";
1362 case ARMISD::VREV16: return "ARMISD::VREV16";
1363 case ARMISD::VZIP: return "ARMISD::VZIP";
1364 case ARMISD::VUZP: return "ARMISD::VUZP";
1365 case ARMISD::VTRN: return "ARMISD::VTRN";
1366 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1367 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1368 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1369 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1370 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1371 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1372 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1373 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1374 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1375 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1376 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1377 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1378 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1379 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1380 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1381 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1382 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1383 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1384 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1385 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1386 case ARMISD::BFI: return "ARMISD::BFI";
1387 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1388 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1389 case ARMISD::VBSL: return "ARMISD::VBSL";
1390 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1391 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1392 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1393 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1394 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1395 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1396 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1397 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1398 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1399 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1400 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1401 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1402 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1403 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1404 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1405 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1406 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1407 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1408 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1409 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1410 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1411 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1412 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1417 EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1420 return getPointerTy(DL);
1421 return VT.changeVectorElementTypeToInteger();
1424 /// getRegClassFor - Return the register class that should be used for the
1425 /// specified value type.
1426 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1427 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1428 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1429 // load / store 4 to 8 consecutive D registers.
1430 if (Subtarget->hasNEON()) {
1431 if (VT == MVT::v4i64)
1432 return &ARM::QQPRRegClass;
1433 if (VT == MVT::v8i64)
1434 return &ARM::QQQQPRRegClass;
1436 return TargetLowering::getRegClassFor(VT);
1439 // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1440 // source/dest is aligned and the copy size is large enough. We therefore want
1441 // to align such objects passed to memory intrinsics.
1442 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1443 unsigned &PrefAlign) const {
1444 if (!isa<MemIntrinsic>(CI))
1447 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1448 // cycle faster than 4-byte aligned LDM.
1449 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1453 // Create a fast isel object.
1455 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1456 const TargetLibraryInfo *libInfo) const {
1457 return ARM::createFastISel(funcInfo, libInfo);
1460 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1461 unsigned NumVals = N->getNumValues();
1463 return Sched::RegPressure;
1465 for (unsigned i = 0; i != NumVals; ++i) {
1466 EVT VT = N->getValueType(i);
1467 if (VT == MVT::Glue || VT == MVT::Other)
1469 if (VT.isFloatingPoint() || VT.isVector())
1473 if (!N->isMachineOpcode())
1474 return Sched::RegPressure;
1476 // Load are scheduled for latency even if there instruction itinerary
1477 // is not available.
1478 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1479 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1481 if (MCID.getNumDefs() == 0)
1482 return Sched::RegPressure;
1483 if (!Itins->isEmpty() &&
1484 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1487 return Sched::RegPressure;
1490 //===----------------------------------------------------------------------===//
1492 //===----------------------------------------------------------------------===//
1494 static bool isSRL16(const SDValue &Op) {
1495 if (Op.getOpcode() != ISD::SRL)
1497 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1498 return Const->getZExtValue() == 16;
1502 static bool isSRA16(const SDValue &Op) {
1503 if (Op.getOpcode() != ISD::SRA)
1505 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1506 return Const->getZExtValue() == 16;
1510 static bool isSHL16(const SDValue &Op) {
1511 if (Op.getOpcode() != ISD::SHL)
1513 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1514 return Const->getZExtValue() == 16;
1518 // Check for a signed 16-bit value. We special case SRA because it makes it
1519 // more simple when also looking for SRAs that aren't sign extending a
1520 // smaller value. Without the check, we'd need to take extra care with
1521 // checking order for some operations.
1522 static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1524 return isSHL16(Op.getOperand(0));
1525 return DAG.ComputeNumSignBits(Op) == 17;
1528 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1529 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1531 default: llvm_unreachable("Unknown condition code!");
1532 case ISD::SETNE: return ARMCC::NE;
1533 case ISD::SETEQ: return ARMCC::EQ;
1534 case ISD::SETGT: return ARMCC::GT;
1535 case ISD::SETGE: return ARMCC::GE;
1536 case ISD::SETLT: return ARMCC::LT;
1537 case ISD::SETLE: return ARMCC::LE;
1538 case ISD::SETUGT: return ARMCC::HI;
1539 case ISD::SETUGE: return ARMCC::HS;
1540 case ISD::SETULT: return ARMCC::LO;
1541 case ISD::SETULE: return ARMCC::LS;
1545 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1546 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1547 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1548 CondCode2 = ARMCC::AL;
1549 InvalidOnQNaN = true;
1551 default: llvm_unreachable("Unknown FP condition!");
1554 CondCode = ARMCC::EQ;
1555 InvalidOnQNaN = false;
1558 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1560 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1561 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1562 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1564 CondCode = ARMCC::MI;
1565 CondCode2 = ARMCC::GT;
1566 InvalidOnQNaN = false;
1568 case ISD::SETO: CondCode = ARMCC::VC; break;
1569 case ISD::SETUO: CondCode = ARMCC::VS; break;
1571 CondCode = ARMCC::EQ;
1572 CondCode2 = ARMCC::VS;
1573 InvalidOnQNaN = false;
1575 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1576 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1578 case ISD::SETULT: CondCode = ARMCC::LT; break;
1580 case ISD::SETULE: CondCode = ARMCC::LE; break;
1583 CondCode = ARMCC::NE;
1584 InvalidOnQNaN = false;
1589 //===----------------------------------------------------------------------===//
1590 // Calling Convention Implementation
1591 //===----------------------------------------------------------------------===//
1593 #include "ARMGenCallingConv.inc"
1595 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1596 /// account presence of floating point hardware and calling convention
1597 /// limitations, such as support for variadic functions.
1599 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1600 bool isVarArg) const {
1603 report_fatal_error("Unsupported calling convention");
1604 case CallingConv::ARM_AAPCS:
1605 case CallingConv::ARM_APCS:
1606 case CallingConv::GHC:
1608 case CallingConv::PreserveMost:
1609 return CallingConv::PreserveMost;
1610 case CallingConv::ARM_AAPCS_VFP:
1611 case CallingConv::Swift:
1612 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1613 case CallingConv::C:
1614 if (!Subtarget->isAAPCS_ABI())
1615 return CallingConv::ARM_APCS;
1616 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1617 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1619 return CallingConv::ARM_AAPCS_VFP;
1621 return CallingConv::ARM_AAPCS;
1622 case CallingConv::Fast:
1623 case CallingConv::CXX_FAST_TLS:
1624 if (!Subtarget->isAAPCS_ABI()) {
1625 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1626 return CallingConv::Fast;
1627 return CallingConv::ARM_APCS;
1628 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1629 return CallingConv::ARM_AAPCS_VFP;
1631 return CallingConv::ARM_AAPCS;
1635 CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1636 bool isVarArg) const {
1637 return CCAssignFnForNode(CC, false, isVarArg);
1640 CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1641 bool isVarArg) const {
1642 return CCAssignFnForNode(CC, true, isVarArg);
1645 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1646 /// CallingConvention.
1647 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1649 bool isVarArg) const {
1650 switch (getEffectiveCallingConv(CC, isVarArg)) {
1652 report_fatal_error("Unsupported calling convention");
1653 case CallingConv::ARM_APCS:
1654 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1655 case CallingConv::ARM_AAPCS:
1656 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1657 case CallingConv::ARM_AAPCS_VFP:
1658 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1659 case CallingConv::Fast:
1660 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1661 case CallingConv::GHC:
1662 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1663 case CallingConv::PreserveMost:
1664 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1668 /// LowerCallResult - Lower the result values of a call into the
1669 /// appropriate copies out of appropriate physical registers.
1670 SDValue ARMTargetLowering::LowerCallResult(
1671 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1672 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1673 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1674 SDValue ThisVal) const {
1675 // Assign locations to each value returned by this call.
1676 SmallVector<CCValAssign, 16> RVLocs;
1677 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1679 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1681 // Copy all of the result registers out of their specified physreg.
1682 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1683 CCValAssign VA = RVLocs[i];
1685 // Pass 'this' value directly from the argument to return value, to avoid
1686 // reg unit interference
1687 if (i == 0 && isThisReturn) {
1688 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1689 "unexpected return calling convention register assignment");
1690 InVals.push_back(ThisVal);
1695 if (VA.needsCustom()) {
1696 // Handle f64 or half of a v2f64.
1697 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1699 Chain = Lo.getValue(1);
1700 InFlag = Lo.getValue(2);
1701 VA = RVLocs[++i]; // skip ahead to next loc
1702 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1704 Chain = Hi.getValue(1);
1705 InFlag = Hi.getValue(2);
1706 if (!Subtarget->isLittle())
1708 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1710 if (VA.getLocVT() == MVT::v2f64) {
1711 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1712 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1713 DAG.getConstant(0, dl, MVT::i32));
1715 VA = RVLocs[++i]; // skip ahead to next loc
1716 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1717 Chain = Lo.getValue(1);
1718 InFlag = Lo.getValue(2);
1719 VA = RVLocs[++i]; // skip ahead to next loc
1720 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1721 Chain = Hi.getValue(1);
1722 InFlag = Hi.getValue(2);
1723 if (!Subtarget->isLittle())
1725 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1726 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1727 DAG.getConstant(1, dl, MVT::i32));
1730 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1732 Chain = Val.getValue(1);
1733 InFlag = Val.getValue(2);
1736 switch (VA.getLocInfo()) {
1737 default: llvm_unreachable("Unknown loc info!");
1738 case CCValAssign::Full: break;
1739 case CCValAssign::BCvt:
1740 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1744 InVals.push_back(Val);
1750 /// LowerMemOpCallTo - Store the argument to the stack.
1751 SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1752 SDValue Arg, const SDLoc &dl,
1754 const CCValAssign &VA,
1755 ISD::ArgFlagsTy Flags) const {
1756 unsigned LocMemOffset = VA.getLocMemOffset();
1757 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1758 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1760 return DAG.getStore(
1761 Chain, dl, Arg, PtrOff,
1762 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1765 void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1766 SDValue Chain, SDValue &Arg,
1767 RegsToPassVector &RegsToPass,
1768 CCValAssign &VA, CCValAssign &NextVA,
1770 SmallVectorImpl<SDValue> &MemOpChains,
1771 ISD::ArgFlagsTy Flags) const {
1772 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1773 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1774 unsigned id = Subtarget->isLittle() ? 0 : 1;
1775 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1777 if (NextVA.isRegLoc())
1778 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1780 assert(NextVA.isMemLoc());
1781 if (!StackPtr.getNode())
1782 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1783 getPointerTy(DAG.getDataLayout()));
1785 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1791 /// LowerCall - Lowering a call into a callseq_start <-
1792 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1795 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1796 SmallVectorImpl<SDValue> &InVals) const {
1797 SelectionDAG &DAG = CLI.DAG;
1799 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1800 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1801 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1802 SDValue Chain = CLI.Chain;
1803 SDValue Callee = CLI.Callee;
1804 bool &isTailCall = CLI.IsTailCall;
1805 CallingConv::ID CallConv = CLI.CallConv;
1806 bool doesNotRet = CLI.DoesNotReturn;
1807 bool isVarArg = CLI.IsVarArg;
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1811 bool isThisReturn = false;
1812 bool isSibCall = false;
1813 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1815 // Disable tail calls if they're not supported.
1816 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1820 // Check if it's really possible to do a tail call.
1821 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1822 isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1823 Outs, OutVals, Ins, DAG);
1824 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1825 report_fatal_error("failed to perform tail call elimination on a call "
1826 "site marked musttail");
1827 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1828 // detected sibcalls.
1835 // Analyze operands of the call, assigning locations to each operand.
1836 SmallVector<CCValAssign, 16> ArgLocs;
1837 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1839 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1841 // Get a count of how many bytes are to be pushed on the stack.
1842 unsigned NumBytes = CCInfo.getNextStackOffset();
1844 // For tail calls, memory operands are available in our caller's stack.
1848 // Adjust the stack pointer for the new arguments...
1849 // These operations are automatically eliminated by the prolog/epilog pass
1851 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1854 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1856 RegsToPassVector RegsToPass;
1857 SmallVector<SDValue, 8> MemOpChains;
1859 // Walk the register/memloc assignments, inserting copies/loads. In the case
1860 // of tail call optimization, arguments are handled later.
1861 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1863 ++i, ++realArgIdx) {
1864 CCValAssign &VA = ArgLocs[i];
1865 SDValue Arg = OutVals[realArgIdx];
1866 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1867 bool isByVal = Flags.isByVal();
1869 // Promote the value if needed.
1870 switch (VA.getLocInfo()) {
1871 default: llvm_unreachable("Unknown loc info!");
1872 case CCValAssign::Full: break;
1873 case CCValAssign::SExt:
1874 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1876 case CCValAssign::ZExt:
1877 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1879 case CCValAssign::AExt:
1880 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1882 case CCValAssign::BCvt:
1883 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1887 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1888 if (VA.needsCustom()) {
1889 if (VA.getLocVT() == MVT::v2f64) {
1890 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1891 DAG.getConstant(0, dl, MVT::i32));
1892 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1893 DAG.getConstant(1, dl, MVT::i32));
1895 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1896 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1898 VA = ArgLocs[++i]; // skip ahead to next loc
1899 if (VA.isRegLoc()) {
1900 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1901 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1903 assert(VA.isMemLoc());
1905 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1906 dl, DAG, VA, Flags));
1909 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1910 StackPtr, MemOpChains, Flags);
1912 } else if (VA.isRegLoc()) {
1913 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1914 Outs[0].VT == MVT::i32) {
1915 assert(VA.getLocVT() == MVT::i32 &&
1916 "unexpected calling convention register assignment");
1917 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1918 "unexpected use of 'returned'");
1919 isThisReturn = true;
1921 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1922 } else if (isByVal) {
1923 assert(VA.isMemLoc());
1924 unsigned offset = 0;
1926 // True if this byval aggregate will be split between registers
1928 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1929 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1931 if (CurByValIdx < ByValArgsCount) {
1933 unsigned RegBegin, RegEnd;
1934 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1937 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1939 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1940 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1941 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1942 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1943 MachinePointerInfo(),
1944 DAG.InferPtrAlignment(AddArg));
1945 MemOpChains.push_back(Load.getValue(1));
1946 RegsToPass.push_back(std::make_pair(j, Load));
1949 // If parameter size outsides register area, "offset" value
1950 // helps us to calculate stack slot for remained part properly.
1951 offset = RegEnd - RegBegin;
1953 CCInfo.nextInRegsParam();
1956 if (Flags.getByValSize() > 4*offset) {
1957 auto PtrVT = getPointerTy(DAG.getDataLayout());
1958 unsigned LocMemOffset = VA.getLocMemOffset();
1959 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1960 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1961 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1962 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1963 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1965 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1968 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1969 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1970 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1973 } else if (!isSibCall) {
1974 assert(VA.isMemLoc());
1976 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1977 dl, DAG, VA, Flags));
1981 if (!MemOpChains.empty())
1982 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1984 // Build a sequence of copy-to-reg nodes chained together with token chain
1985 // and flag operands which copy the outgoing args into the appropriate regs.
1987 // Tail call byval lowering might overwrite argument registers so in case of
1988 // tail call optimization the copies to registers are lowered later.
1990 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1991 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1992 RegsToPass[i].second, InFlag);
1993 InFlag = Chain.getValue(1);
1996 // For tail calls lower the arguments to the 'real' stack slot.
1998 // Force all the incoming stack arguments to be loaded from the stack
1999 // before any new outgoing arguments are stored to the stack, because the
2000 // outgoing stack slots may alias the incoming argument stack slots, and
2001 // the alias isn't otherwise explicit. This is slightly more conservative
2002 // than necessary, because it means that each store effectively depends
2003 // on every argument instead of just those arguments it would clobber.
2005 // Do not flag preceding copytoreg stuff together with the following stuff.
2007 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2008 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2009 RegsToPass[i].second, InFlag);
2010 InFlag = Chain.getValue(1);
2015 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2016 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2017 // node so that legalize doesn't hack it.
2018 bool isDirect = false;
2020 const TargetMachine &TM = getTargetMachine();
2021 const Module *Mod = MF.getFunction().getParent();
2022 const GlobalValue *GV = nullptr;
2023 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2024 GV = G->getGlobal();
2026 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2028 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2029 bool isLocalARMFunc = false;
2030 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2031 auto PtrVt = getPointerTy(DAG.getDataLayout());
2033 if (Subtarget->genLongCalls()) {
2034 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&
2035 "long-calls codegen is not position independent!");
2036 // Handle a global address or an external symbol. If it's not one of
2037 // those, the target's already in a register, so we don't need to do
2039 if (isa<GlobalAddressSDNode>(Callee)) {
2040 // Create a constant pool entry for the callee address
2041 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2042 ARMConstantPoolValue *CPV =
2043 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2045 // Get the address of the callee into a register
2046 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2047 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2048 Callee = DAG.getLoad(
2049 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2050 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2051 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2052 const char *Sym = S->getSymbol();
2054 // Create a constant pool entry for the callee address
2055 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2056 ARMConstantPoolValue *CPV =
2057 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2058 ARMPCLabelIndex, 0);
2059 // Get the address of the callee into a register
2060 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2061 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2062 Callee = DAG.getLoad(
2063 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2064 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2066 } else if (isa<GlobalAddressSDNode>(Callee)) {
2067 // If we're optimizing for minimum size and the function is called three or
2068 // more times in this block, we can improve codesize by calling indirectly
2069 // as BLXr has a 16-bit encoding.
2070 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2071 auto *BB = CLI.CS.getParent();
2072 bool PreferIndirect =
2073 Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2074 count_if(GV->users(), [&BB](const User *U) {
2075 return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2078 if (!PreferIndirect) {
2080 bool isDef = GV->isStrongDefinitionForLinker();
2082 // ARM call to a local ARM function is predicable.
2083 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2084 // tBX takes a register source operand.
2085 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2086 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
2087 Callee = DAG.getNode(
2088 ARMISD::WrapperPIC, dl, PtrVt,
2089 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2090 Callee = DAG.getLoad(
2091 PtrVt, dl, DAG.getEntryNode(), Callee,
2092 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2093 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2094 MachineMemOperand::MOInvariant);
2095 } else if (Subtarget->isTargetCOFF()) {
2096 assert(Subtarget->isTargetWindows() &&
2097 "Windows is the only supported COFF target");
2098 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2099 ? ARMII::MO_DLLIMPORT
2100 : ARMII::MO_NO_FLAG;
2101 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2103 if (GV->hasDLLImportStorageClass())
2105 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2106 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2107 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2109 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2112 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2114 // tBX takes a register source operand.
2115 const char *Sym = S->getSymbol();
2116 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2117 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2118 ARMConstantPoolValue *CPV =
2119 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2120 ARMPCLabelIndex, 4);
2121 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2122 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2123 Callee = DAG.getLoad(
2124 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2125 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2126 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2127 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2129 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2133 // FIXME: handle tail calls differently.
2135 if (Subtarget->isThumb()) {
2136 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2137 CallOpc = ARMISD::CALL_NOLINK;
2139 CallOpc = ARMISD::CALL;
2141 if (!isDirect && !Subtarget->hasV5TOps())
2142 CallOpc = ARMISD::CALL_NOLINK;
2143 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2144 // Emit regular call when code size is the priority
2145 !MF.getFunction().optForMinSize())
2146 // "mov lr, pc; b _foo" to avoid confusing the RSP
2147 CallOpc = ARMISD::CALL_NOLINK;
2149 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2152 std::vector<SDValue> Ops;
2153 Ops.push_back(Chain);
2154 Ops.push_back(Callee);
2156 // Add argument registers to the end of the list so that they are known live
2158 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2159 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2160 RegsToPass[i].second.getValueType()));
2162 // Add a register mask operand representing the call-preserved registers.
2164 const uint32_t *Mask;
2165 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2167 // For 'this' returns, use the R0-preserving mask if applicable
2168 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2170 // Set isThisReturn to false if the calling convention is not one that
2171 // allows 'returned' to be modeled in this way, so LowerCallResult does
2172 // not try to pass 'this' straight through
2173 isThisReturn = false;
2174 Mask = ARI->getCallPreservedMask(MF, CallConv);
2177 Mask = ARI->getCallPreservedMask(MF, CallConv);
2179 assert(Mask && "Missing call preserved mask for calling convention");
2180 Ops.push_back(DAG.getRegisterMask(Mask));
2183 if (InFlag.getNode())
2184 Ops.push_back(InFlag);
2186 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2188 MF.getFrameInfo().setHasTailCall();
2189 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2192 // Returns a chain and a flag for retval copy to use.
2193 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2194 InFlag = Chain.getValue(1);
2196 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2197 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2199 InFlag = Chain.getValue(1);
2201 // Handle result values, copying them out of physregs into vregs that we
2203 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2204 InVals, isThisReturn,
2205 isThisReturn ? OutVals[0] : SDValue());
2208 /// HandleByVal - Every parameter *after* a byval parameter is passed
2209 /// on the stack. Remember the next parameter register to allocate,
2210 /// and then confiscate the rest of the parameter registers to insure
2212 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2213 unsigned Align) const {
2214 // Byval (as with any stack) slots are always at least 4 byte aligned.
2215 Align = std::max(Align, 4U);
2217 unsigned Reg = State->AllocateReg(GPRArgRegs);
2221 unsigned AlignInRegs = Align / 4;
2222 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2223 for (unsigned i = 0; i < Waste; ++i)
2224 Reg = State->AllocateReg(GPRArgRegs);
2229 unsigned Excess = 4 * (ARM::R4 - Reg);
2231 // Special case when NSAA != SP and parameter size greater than size of
2232 // all remained GPR regs. In that case we can't split parameter, we must
2233 // send it to stack. We also must set NCRN to R4, so waste all
2234 // remained registers.
2235 const unsigned NSAAOffset = State->getNextStackOffset();
2236 if (NSAAOffset != 0 && Size > Excess) {
2237 while (State->AllocateReg(GPRArgRegs))
2242 // First register for byval parameter is the first register that wasn't
2243 // allocated before this method call, so it would be "reg".
2244 // If parameter is small enough to be saved in range [reg, r4), then
2245 // the end (first after last) register would be reg + param-size-in-regs,
2246 // else parameter would be splitted between registers and stack,
2247 // end register would be r4 in this case.
2248 unsigned ByValRegBegin = Reg;
2249 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2250 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2251 // Note, first register is allocated in the beginning of function already,
2252 // allocate remained amount of registers we need.
2253 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2254 State->AllocateReg(GPRArgRegs);
2255 // A byval parameter that is split between registers and memory needs its
2256 // size truncated here.
2257 // In the case where the entire structure fits in registers, we set the
2258 // size in memory to zero.
2259 Size = std::max<int>(Size - Excess, 0);
2262 /// MatchingStackOffset - Return true if the given stack call argument is
2263 /// already available in the same position (relatively) of the caller's
2264 /// incoming argument stack.
2266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2267 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2268 const TargetInstrInfo *TII) {
2269 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2270 int FI = std::numeric_limits<int>::max();
2271 if (Arg.getOpcode() == ISD::CopyFromReg) {
2272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2273 if (!TargetRegisterInfo::isVirtualRegister(VR))
2275 MachineInstr *Def = MRI->getVRegDef(VR);
2278 if (!Flags.isByVal()) {
2279 if (!TII->isLoadFromStackSlot(*Def, FI))
2284 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2285 if (Flags.isByVal())
2286 // ByVal argument is passed in as a pointer but it's now being
2287 // dereferenced. e.g.
2288 // define @foo(%struct.X* %A) {
2289 // tail call @bar(%struct.X* byval %A)
2292 SDValue Ptr = Ld->getBasePtr();
2293 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2296 FI = FINode->getIndex();
2300 assert(FI != std::numeric_limits<int>::max());
2301 if (!MFI.isFixedObjectIndex(FI))
2303 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2306 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2307 /// for tail call optimization. Targets which want to do tail call
2308 /// optimization should implement this function.
2310 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2311 CallingConv::ID CalleeCC,
2313 bool isCalleeStructRet,
2314 bool isCallerStructRet,
2315 const SmallVectorImpl<ISD::OutputArg> &Outs,
2316 const SmallVectorImpl<SDValue> &OutVals,
2317 const SmallVectorImpl<ISD::InputArg> &Ins,
2318 SelectionDAG& DAG) const {
2319 MachineFunction &MF = DAG.getMachineFunction();
2320 const Function &CallerF = MF.getFunction();
2321 CallingConv::ID CallerCC = CallerF.getCallingConv();
2323 assert(Subtarget->supportsTailCall());
2325 // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2326 // to the call take up r0-r3. The reason is that there are no legal registers
2327 // left to hold the pointer to the function to be called.
2328 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2329 !isa<GlobalAddressSDNode>(Callee.getNode()))
2332 // Look for obvious safe cases to perform tail call optimization that do not
2333 // require ABI changes. This is what gcc calls sibcall.
2335 // Exception-handling functions need a special set of instructions to indicate
2336 // a return to the hardware. Tail-calling another function would probably
2338 if (CallerF.hasFnAttribute("interrupt"))
2341 // Also avoid sibcall optimization if either caller or callee uses struct
2342 // return semantics.
2343 if (isCalleeStructRet || isCallerStructRet)
2346 // Externally-defined functions with weak linkage should not be
2347 // tail-called on ARM when the OS does not support dynamic
2348 // pre-emption of symbols, as the AAELF spec requires normal calls
2349 // to undefined weak functions to be replaced with a NOP or jump to the
2350 // next instruction. The behaviour of branch instructions in this
2351 // situation (as used for tail calls) is implementation-defined, so we
2352 // cannot rely on the linker replacing the tail call with a return.
2353 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2354 const GlobalValue *GV = G->getGlobal();
2355 const Triple &TT = getTargetMachine().getTargetTriple();
2356 if (GV->hasExternalWeakLinkage() &&
2357 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2361 // Check that the call results are passed in the same way.
2362 LLVMContext &C = *DAG.getContext();
2363 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2364 CCAssignFnForReturn(CalleeCC, isVarArg),
2365 CCAssignFnForReturn(CallerCC, isVarArg)))
2367 // The callee has to preserve all registers the caller needs to preserve.
2368 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2369 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2370 if (CalleeCC != CallerCC) {
2371 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2372 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2376 // If Caller's vararg or byval argument has been split between registers and
2377 // stack, do not perform tail call, since part of the argument is in caller's
2379 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2380 if (AFI_Caller->getArgRegsSaveSize())
2383 // If the callee takes no arguments then go on to check the results of the
2385 if (!Outs.empty()) {
2386 // Check if stack adjustment is needed. For now, do not do this if any
2387 // argument is passed on the stack.
2388 SmallVector<CCValAssign, 16> ArgLocs;
2389 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2390 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2391 if (CCInfo.getNextStackOffset()) {
2392 // Check if the arguments are already laid out in the right way as
2393 // the caller's fixed stack objects.
2394 MachineFrameInfo &MFI = MF.getFrameInfo();
2395 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2396 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2397 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2399 ++i, ++realArgIdx) {
2400 CCValAssign &VA = ArgLocs[i];
2401 EVT RegVT = VA.getLocVT();
2402 SDValue Arg = OutVals[realArgIdx];
2403 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2404 if (VA.getLocInfo() == CCValAssign::Indirect)
2406 if (VA.needsCustom()) {
2407 // f64 and vector types are split into multiple registers or
2408 // register/stack-slot combinations. The types will not match
2409 // the registers; give up on memory f64 refs until we figure
2410 // out what to do about this.
2413 if (!ArgLocs[++i].isRegLoc())
2415 if (RegVT == MVT::v2f64) {
2416 if (!ArgLocs[++i].isRegLoc())
2418 if (!ArgLocs[++i].isRegLoc())
2421 } else if (!VA.isRegLoc()) {
2422 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2429 const MachineRegisterInfo &MRI = MF.getRegInfo();
2430 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2438 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2439 MachineFunction &MF, bool isVarArg,
2440 const SmallVectorImpl<ISD::OutputArg> &Outs,
2441 LLVMContext &Context) const {
2442 SmallVector<CCValAssign, 16> RVLocs;
2443 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2444 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2447 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2448 const SDLoc &DL, SelectionDAG &DAG) {
2449 const MachineFunction &MF = DAG.getMachineFunction();
2450 const Function &F = MF.getFunction();
2452 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2454 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2455 // version of the "preferred return address". These offsets affect the return
2456 // instruction if this is a return from PL1 without hypervisor extensions.
2457 // IRQ/FIQ: +4 "subs pc, lr, #4"
2458 // SWI: 0 "subs pc, lr, #0"
2459 // ABORT: +4 "subs pc, lr, #4"
2460 // UNDEF: +4/+2 "subs pc, lr, #0"
2461 // UNDEF varies depending on where the exception came from ARM or Thumb
2462 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2465 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2468 else if (IntKind == "SWI" || IntKind == "UNDEF")
2471 report_fatal_error("Unsupported interrupt attribute. If present, value "
2472 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2474 RetOps.insert(RetOps.begin() + 1,
2475 DAG.getConstant(LROffset, DL, MVT::i32, false));
2477 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2481 ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2483 const SmallVectorImpl<ISD::OutputArg> &Outs,
2484 const SmallVectorImpl<SDValue> &OutVals,
2485 const SDLoc &dl, SelectionDAG &DAG) const {
2486 // CCValAssign - represent the assignment of the return value to a location.
2487 SmallVector<CCValAssign, 16> RVLocs;
2489 // CCState - Info about the registers and stack slots.
2490 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2493 // Analyze outgoing return values.
2494 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2497 SmallVector<SDValue, 4> RetOps;
2498 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2499 bool isLittleEndian = Subtarget->isLittle();
2501 MachineFunction &MF = DAG.getMachineFunction();
2502 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2503 AFI->setReturnRegsCount(RVLocs.size());
2505 // Copy the result values into the output registers.
2506 for (unsigned i = 0, realRVLocIdx = 0;
2508 ++i, ++realRVLocIdx) {
2509 CCValAssign &VA = RVLocs[i];
2510 assert(VA.isRegLoc() && "Can only return in registers!");
2512 SDValue Arg = OutVals[realRVLocIdx];
2513 bool ReturnF16 = false;
2515 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2516 // Half-precision return values can be returned like this:
2518 // t11 f16 = fadd ...
2519 // t12: i16 = bitcast t11
2520 // t13: i32 = zero_extend t12
2521 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2523 // to avoid code generation for bitcasts, we simply set Arg to the node
2524 // that produces the f16 value, t11 in this case.
2526 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2527 SDValue ZE = Arg.getOperand(0);
2528 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2529 SDValue BC = ZE.getOperand(0);
2530 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2531 Arg = BC.getOperand(0);
2538 switch (VA.getLocInfo()) {
2539 default: llvm_unreachable("Unknown loc info!");
2540 case CCValAssign::Full: break;
2541 case CCValAssign::BCvt:
2543 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2547 if (VA.needsCustom()) {
2548 if (VA.getLocVT() == MVT::v2f64) {
2549 // Extract the first half and return it in two registers.
2550 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2551 DAG.getConstant(0, dl, MVT::i32));
2552 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2553 DAG.getVTList(MVT::i32, MVT::i32), Half);
2555 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2556 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2558 Flag = Chain.getValue(1);
2559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2560 VA = RVLocs[++i]; // skip ahead to next loc
2561 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2562 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2564 Flag = Chain.getValue(1);
2565 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2566 VA = RVLocs[++i]; // skip ahead to next loc
2568 // Extract the 2nd half and fall through to handle it as an f64 value.
2569 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2570 DAG.getConstant(1, dl, MVT::i32));
2572 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2574 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2575 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2576 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2577 fmrrd.getValue(isLittleEndian ? 0 : 1),
2579 Flag = Chain.getValue(1);
2580 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2581 VA = RVLocs[++i]; // skip ahead to next loc
2582 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2583 fmrrd.getValue(isLittleEndian ? 1 : 0),
2586 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2588 // Guarantee that all emitted copies are
2589 // stuck together, avoiding something bad.
2590 Flag = Chain.getValue(1);
2591 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2592 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2594 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2595 const MCPhysReg *I =
2596 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2599 if (ARM::GPRRegClass.contains(*I))
2600 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2601 else if (ARM::DPRRegClass.contains(*I))
2602 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2604 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2608 // Update chain and glue.
2611 RetOps.push_back(Flag);
2613 // CPUs which aren't M-class use a special sequence to return from
2614 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2615 // though we use "subs pc, lr, #N").
2617 // M-class CPUs actually use a normal return sequence with a special
2618 // (hardware-provided) value in LR, so the normal code path works.
2619 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2620 !Subtarget->isMClass()) {
2621 if (Subtarget->isThumb1Only())
2622 report_fatal_error("interrupt attribute is not supported in Thumb1");
2623 return LowerInterruptReturn(RetOps, dl, DAG);
2626 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2629 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2630 if (N->getNumValues() != 1)
2632 if (!N->hasNUsesOfValue(1, 0))
2635 SDValue TCChain = Chain;
2636 SDNode *Copy = *N->use_begin();
2637 if (Copy->getOpcode() == ISD::CopyToReg) {
2638 // If the copy has a glue operand, we conservatively assume it isn't safe to
2639 // perform a tail call.
2640 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2642 TCChain = Copy->getOperand(0);
2643 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2644 SDNode *VMov = Copy;
2645 // f64 returned in a pair of GPRs.
2646 SmallPtrSet<SDNode*, 2> Copies;
2647 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2649 if (UI->getOpcode() != ISD::CopyToReg)
2653 if (Copies.size() > 2)
2656 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2658 SDValue UseChain = UI->getOperand(0);
2659 if (Copies.count(UseChain.getNode()))
2663 // We are at the top of this chain.
2664 // If the copy has a glue operand, we conservatively assume it
2665 // isn't safe to perform a tail call.
2666 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2672 } else if (Copy->getOpcode() == ISD::BITCAST) {
2673 // f32 returned in a single GPR.
2674 if (!Copy->hasOneUse())
2676 Copy = *Copy->use_begin();
2677 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2679 // If the copy has a glue operand, we conservatively assume it isn't safe to
2680 // perform a tail call.
2681 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2683 TCChain = Copy->getOperand(0);
2688 bool HasRet = false;
2689 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2691 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2692 UI->getOpcode() != ARMISD::INTRET_FLAG)
2704 bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2705 if (!Subtarget->supportsTailCall())
2709 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2710 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2716 // Trying to write a 64 bit value so need to split into two 32 bit values first,
2717 // and pass the lower and high parts through.
2718 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2720 SDValue WriteValue = Op->getOperand(2);
2722 // This function is only supposed to be called for i64 type argument.
2723 assert(WriteValue.getValueType() == MVT::i64
2724 && "LowerWRITE_REGISTER called for non-i64 type argument.");
2726 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2727 DAG.getConstant(0, DL, MVT::i32));
2728 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2729 DAG.getConstant(1, DL, MVT::i32));
2730 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2731 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2734 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2735 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2736 // one of the above mentioned nodes. It has to be wrapped because otherwise
2737 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2738 // be used to form addressing mode. These wrapped nodes will be selected
2740 SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2741 SelectionDAG &DAG) const {
2742 EVT PtrVT = Op.getValueType();
2743 // FIXME there is no actual debug info here
2745 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2748 // When generating execute-only code Constant Pools must be promoted to the
2749 // global data section. It's a bit ugly that we can't share them across basic
2750 // blocks, but this way we guarantee that execute-only behaves correct with
2751 // position-independent addressing modes.
2752 if (Subtarget->genExecuteOnly()) {
2753 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2754 auto T = const_cast<Type*>(CP->getType());
2755 auto C = const_cast<Constant*>(CP->getConstVal());
2756 auto M = const_cast<Module*>(DAG.getMachineFunction().
2757 getFunction().getParent());
2758 auto GV = new GlobalVariable(
2759 *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2760 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2761 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2762 Twine(AFI->createPICLabelUId())
2764 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2766 return LowerGlobalAddress(GA, DAG);
2769 if (CP->isMachineConstantPoolEntry())
2770 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2771 CP->getAlignment());
2773 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2774 CP->getAlignment());
2775 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2778 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2779 return MachineJumpTableInfo::EK_Inline;
2782 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2783 SelectionDAG &DAG) const {
2784 MachineFunction &MF = DAG.getMachineFunction();
2785 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2786 unsigned ARMPCLabelIndex = 0;
2788 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2789 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2791 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2792 if (!IsPositionIndependent) {
2793 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2795 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2796 ARMPCLabelIndex = AFI->createPICLabelUId();
2797 ARMConstantPoolValue *CPV =
2798 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2799 ARMCP::CPBlockAddress, PCAdj);
2800 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2802 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2803 SDValue Result = DAG.getLoad(
2804 PtrVT, DL, DAG.getEntryNode(), CPAddr,
2805 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2806 if (!IsPositionIndependent)
2808 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2809 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2812 /// Convert a TLS address reference into the correct sequence of loads
2813 /// and calls to compute the variable's address for Darwin, and return an
2814 /// SDValue containing the final node.
2816 /// Darwin only has one TLS scheme which must be capable of dealing with the
2817 /// fully general situation, in the worst case. This means:
2818 /// + "extern __thread" declaration.
2819 /// + Defined in a possibly unknown dynamic library.
2821 /// The general system is that each __thread variable has a [3 x i32] descriptor
2822 /// which contains information used by the runtime to calculate the address. The
2823 /// only part of this the compiler needs to know about is the first word, which
2824 /// contains a function pointer that must be called with the address of the
2825 /// entire descriptor in "r0".
2827 /// Since this descriptor may be in a different unit, in general access must
2828 /// proceed along the usual ARM rules. A common sequence to produce is:
2830 /// movw rT1, :lower16:_var$non_lazy_ptr
2831 /// movt rT1, :upper16:_var$non_lazy_ptr
2835 /// [...address now in r0...]
2837 ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2838 SelectionDAG &DAG) const {
2839 assert(Subtarget->isTargetDarwin() &&
2840 "This function expects a Darwin target");
2843 // First step is to get the address of the actua global symbol. This is where
2844 // the TLS descriptor lives.
2845 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2847 // The first entry in the descriptor is a function pointer that we must call
2848 // to obtain the address of the variable.
2849 SDValue Chain = DAG.getEntryNode();
2850 SDValue FuncTLVGet = DAG.getLoad(
2851 MVT::i32, DL, Chain, DescAddr,
2852 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2853 /* Alignment = */ 4,
2854 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
2855 MachineMemOperand::MOInvariant);
2856 Chain = FuncTLVGet.getValue(1);
2858 MachineFunction &F = DAG.getMachineFunction();
2859 MachineFrameInfo &MFI = F.getFrameInfo();
2860 MFI.setAdjustsStack(true);
2862 // TLS calls preserve all registers except those that absolutely must be
2863 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2866 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2867 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2868 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2870 // Finally, we can make the call. This is just a degenerate version of a
2871 // normal AArch64 call node: r0 takes the address of the descriptor, and
2872 // returns the address of the variable in this thread.
2873 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2875 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2876 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2877 DAG.getRegisterMask(Mask), Chain.getValue(1));
2878 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2882 ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2883 SelectionDAG &DAG) const {
2884 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering");
2886 SDValue Chain = DAG.getEntryNode();
2887 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2890 // Load the current TEB (thread environment block)
2891 SDValue Ops[] = {Chain,
2892 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2893 DAG.getConstant(15, DL, MVT::i32),
2894 DAG.getConstant(0, DL, MVT::i32),
2895 DAG.getConstant(13, DL, MVT::i32),
2896 DAG.getConstant(0, DL, MVT::i32),
2897 DAG.getConstant(2, DL, MVT::i32)};
2898 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2899 DAG.getVTList(MVT::i32, MVT::Other), Ops);
2901 SDValue TEB = CurrentTEB.getValue(0);
2902 Chain = CurrentTEB.getValue(1);
2904 // Load the ThreadLocalStoragePointer from the TEB
2905 // A pointer to the TLS array is located at offset 0x2c from the TEB.
2907 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2908 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2910 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2911 // offset into the TLSArray.
2913 // Load the TLS index from the C runtime
2915 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2916 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2917 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2919 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2920 DAG.getConstant(2, DL, MVT::i32));
2921 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2922 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2923 MachinePointerInfo());
2925 // Get the offset of the start of the .tls section (section base)
2926 const auto *GA = cast<GlobalAddressSDNode>(Op);
2927 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2928 SDValue Offset = DAG.getLoad(
2929 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2930 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2931 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2933 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2936 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2938 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2939 SelectionDAG &DAG) const {
2941 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2942 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2943 MachineFunction &MF = DAG.getMachineFunction();
2944 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2945 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2946 ARMConstantPoolValue *CPV =
2947 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2948 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2949 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2950 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2951 Argument = DAG.getLoad(
2952 PtrVT, dl, DAG.getEntryNode(), Argument,
2953 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2954 SDValue Chain = Argument.getValue(1);
2956 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2957 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2959 // call __tls_get_addr.
2962 Entry.Node = Argument;
2963 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2964 Args.push_back(Entry);
2966 // FIXME: is there useful debug info available here?
2967 TargetLowering::CallLoweringInfo CLI(DAG);
2968 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2969 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2970 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2972 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2973 return CallResult.first;
2976 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2977 // "local exec" model.
2979 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2981 TLSModel::Model model) const {
2982 const GlobalValue *GV = GA->getGlobal();
2985 SDValue Chain = DAG.getEntryNode();
2986 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2987 // Get the Thread Pointer
2988 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2990 if (model == TLSModel::InitialExec) {
2991 MachineFunction &MF = DAG.getMachineFunction();
2992 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2993 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2994 // Initial exec model.
2995 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2996 ARMConstantPoolValue *CPV =
2997 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2998 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3000 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3001 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3002 Offset = DAG.getLoad(
3003 PtrVT, dl, Chain, Offset,
3004 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3005 Chain = Offset.getValue(1);
3007 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3008 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3010 Offset = DAG.getLoad(
3011 PtrVT, dl, Chain, Offset,
3012 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3015 assert(model == TLSModel::LocalExec);
3016 ARMConstantPoolValue *CPV =
3017 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3018 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3019 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3020 Offset = DAG.getLoad(
3021 PtrVT, dl, Chain, Offset,
3022 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3025 // The address of the thread local variable is the add of the thread
3026 // pointer with the offset of the variable.
3027 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3031 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3032 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3033 if (DAG.getTarget().useEmulatedTLS())
3034 return LowerToTLSEmulatedModel(GA, DAG);
3036 if (Subtarget->isTargetDarwin())
3037 return LowerGlobalTLSAddressDarwin(Op, DAG);
3039 if (Subtarget->isTargetWindows())
3040 return LowerGlobalTLSAddressWindows(Op, DAG);
3042 // TODO: implement the "local dynamic" model
3043 assert(Subtarget->isTargetELF() && "Only ELF implemented here");
3044 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3047 case TLSModel::GeneralDynamic:
3048 case TLSModel::LocalDynamic:
3049 return LowerToTLSGeneralDynamicModel(GA, DAG);
3050 case TLSModel::InitialExec:
3051 case TLSModel::LocalExec:
3052 return LowerToTLSExecModels(GA, DAG, model);
3054 llvm_unreachable("bogus TLS model");
3057 /// Return true if all users of V are within function F, looking through
3059 static bool allUsersAreInFunction(const Value *V, const Function *F) {
3060 SmallVector<const User*,4> Worklist;
3061 for (auto *U : V->users())
3062 Worklist.push_back(U);
3063 while (!Worklist.empty()) {
3064 auto *U = Worklist.pop_back_val();
3065 if (isa<ConstantExpr>(U)) {
3066 for (auto *UU : U->users())
3067 Worklist.push_back(UU);
3071 auto *I = dyn_cast<Instruction>(U);
3072 if (!I || I->getParent()->getParent() != F)
3078 static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3079 const GlobalValue *GV, SelectionDAG &DAG,
3080 EVT PtrVT, const SDLoc &dl) {
3081 // If we're creating a pool entry for a constant global with unnamed address,
3082 // and the global is small enough, we can emit it inline into the constant pool
3083 // to save ourselves an indirection.
3085 // This is a win if the constant is only used in one function (so it doesn't
3086 // need to be duplicated) or duplicating the constant wouldn't increase code
3087 // size (implying the constant is no larger than 4 bytes).
3088 const Function &F = DAG.getMachineFunction().getFunction();
3090 // We rely on this decision to inline being idemopotent and unrelated to the
3091 // use-site. We know that if we inline a variable at one use site, we'll
3092 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3093 // doesn't know about this optimization, so bail out if it's enabled else
3094 // we could decide to inline here (and thus never emit the GV) but require
3095 // the GV from fast-isel generated code.
3096 if (!EnableConstpoolPromotion ||
3097 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3100 auto *GVar = dyn_cast<GlobalVariable>(GV);
3101 if (!GVar || !GVar->hasInitializer() ||
3102 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3103 !GVar->hasLocalLinkage())
3106 // If we inline a value that contains relocations, we move the relocations
3107 // from .data to .text. This is not allowed in position-independent code.
3108 auto *Init = GVar->getInitializer();
3109 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3110 Init->needsRelocation())
3113 // The constant islands pass can only really deal with alignment requests
3114 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3115 // any type wanting greater alignment requirements than 4 bytes. We also
3116 // can only promote constants that are multiples of 4 bytes in size or
3117 // are paddable to a multiple of 4. Currently we only try and pad constants
3118 // that are strings for simplicity.
3119 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3120 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3121 unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar);
3122 unsigned RequiredPadding = 4 - (Size % 4);
3123 bool PaddingPossible =
3124 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3125 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3129 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3130 MachineFunction &MF = DAG.getMachineFunction();
3131 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3133 // We can't bloat the constant pool too much, else the ConstantIslands pass
3134 // may fail to converge. If we haven't promoted this global yet (it may have
3135 // multiple uses), and promoting it would increase the constant pool size (Sz
3136 // > 4), ensure we have space to do so up to MaxTotal.
3137 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3138 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3139 ConstpoolPromotionMaxTotal)
3142 // This is only valid if all users are in a single function; we can't clone
3143 // the constant in general. The LLVM IR unnamed_addr allows merging
3144 // constants, but not cloning them.
3146 // We could potentially allow cloning if we could prove all uses of the
3147 // constant in the current function don't care about the address, like
3148 // printf format strings. But that isn't implemented for now.
3149 if (!allUsersAreInFunction(GVar, &F))
3152 // We're going to inline this global. Pad it out if needed.
3153 if (RequiredPadding != 4) {
3154 StringRef S = CDAInit->getAsString();
3156 SmallVector<uint8_t,16> V(S.size());
3157 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3158 while (RequiredPadding--)
3160 Init = ConstantDataArray::get(*DAG.getContext(), V);
3163 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3165 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3166 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3167 AFI->markGlobalAsPromotedToConstantPool(GVar);
3168 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3171 ++NumConstpoolPromoted;
3172 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3175 bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3176 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3177 if (!(GV = GA->getBaseObject()))
3179 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3180 return V->isConstant();
3181 return isa<Function>(GV);
3184 SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3185 SelectionDAG &DAG) const {
3186 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3187 default: llvm_unreachable("unknown object format");
3189 return LowerGlobalAddressWindows(Op, DAG);
3191 return LowerGlobalAddressELF(Op, DAG);
3193 return LowerGlobalAddressDarwin(Op, DAG);
3197 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3198 SelectionDAG &DAG) const {
3199 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3201 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3202 const TargetMachine &TM = getTargetMachine();
3203 bool IsRO = isReadOnly(GV);
3205 // promoteToConstantPool only if not generating XO text section
3206 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3207 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3210 if (isPositionIndependent()) {
3211 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3212 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3213 UseGOT_PREL ? ARMII::MO_GOT : 0);
3214 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3217 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3218 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3220 } else if (Subtarget->isROPI() && IsRO) {
3222 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3223 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3225 } else if (Subtarget->isRWPI() && !IsRO) {
3228 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3230 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3231 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3232 } else { // use literal pool for address constant
3233 ARMConstantPoolValue *CPV =
3234 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3235 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3236 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3237 RelAddr = DAG.getLoad(
3238 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3239 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3241 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3242 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3246 // If we have T2 ops, we can materialize the address directly via movt/movw
3247 // pair. This is always cheaper.
3248 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3250 // FIXME: Once remat is capable of dealing with instructions with register
3251 // operands, expand this into two nodes.
3252 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3253 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3255 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3256 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3258 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3259 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3263 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3264 SelectionDAG &DAG) const {
3265 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
3266 "ROPI/RWPI not currently supported for Darwin");
3267 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3269 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3271 if (Subtarget->useMovt(DAG.getMachineFunction()))
3274 // FIXME: Once remat is capable of dealing with instructions with register
3275 // operands, expand this into multiple nodes
3277 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3279 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3280 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3282 if (Subtarget->isGVIndirectSymbol(GV))
3283 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3284 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3288 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3289 SelectionDAG &DAG) const {
3290 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
3291 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
3292 "Windows on ARM expects to use movw/movt");
3293 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
3294 "ROPI/RWPI not currently supported for Windows");
3296 const TargetMachine &TM = getTargetMachine();
3297 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3298 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3299 if (GV->hasDLLImportStorageClass())
3300 TargetFlags = ARMII::MO_DLLIMPORT;
3301 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3302 TargetFlags = ARMII::MO_COFFSTUB;
3303 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3309 // FIXME: Once remat is capable of dealing with instructions with register
3310 // operands, expand this into two nodes.
3311 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3312 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3314 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3315 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3316 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3321 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3323 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3324 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3325 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3326 Op.getOperand(1), Val);
3330 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3332 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3333 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3336 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3337 SelectionDAG &DAG) const {
3339 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3344 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3345 const ARMSubtarget *Subtarget) const {
3346 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3349 default: return SDValue(); // Don't custom lower most intrinsics.
3350 case Intrinsic::thread_pointer: {
3351 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3352 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3354 case Intrinsic::eh_sjlj_lsda: {
3355 MachineFunction &MF = DAG.getMachineFunction();
3356 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3357 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3358 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3360 bool IsPositionIndependent = isPositionIndependent();
3361 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3362 ARMConstantPoolValue *CPV =
3363 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3364 ARMCP::CPLSDA, PCAdj);
3365 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3366 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3367 SDValue Result = DAG.getLoad(
3368 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3369 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3371 if (IsPositionIndependent) {
3372 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3373 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3377 case Intrinsic::arm_neon_vabs:
3378 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3380 case Intrinsic::arm_neon_vmulls:
3381 case Intrinsic::arm_neon_vmullu: {
3382 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3383 ? ARMISD::VMULLs : ARMISD::VMULLu;
3384 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3385 Op.getOperand(1), Op.getOperand(2));
3387 case Intrinsic::arm_neon_vminnm:
3388 case Intrinsic::arm_neon_vmaxnm: {
3389 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3390 ? ISD::FMINNUM : ISD::FMAXNUM;
3391 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3392 Op.getOperand(1), Op.getOperand(2));
3394 case Intrinsic::arm_neon_vminu:
3395 case Intrinsic::arm_neon_vmaxu: {
3396 if (Op.getValueType().isFloatingPoint())
3398 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3399 ? ISD::UMIN : ISD::UMAX;
3400 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3401 Op.getOperand(1), Op.getOperand(2));
3403 case Intrinsic::arm_neon_vmins:
3404 case Intrinsic::arm_neon_vmaxs: {
3405 // v{min,max}s is overloaded between signed integers and floats.
3406 if (!Op.getValueType().isFloatingPoint()) {
3407 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3408 ? ISD::SMIN : ISD::SMAX;
3409 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3410 Op.getOperand(1), Op.getOperand(2));
3412 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3413 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3414 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3415 Op.getOperand(1), Op.getOperand(2));
3417 case Intrinsic::arm_neon_vtbl1:
3418 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3419 Op.getOperand(1), Op.getOperand(2));
3420 case Intrinsic::arm_neon_vtbl2:
3421 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3422 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3426 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3427 const ARMSubtarget *Subtarget) {
3429 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3430 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3431 if (SSID == SyncScope::SingleThread)
3434 if (!Subtarget->hasDataBarrier()) {
3435 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3436 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3438 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
3439 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
3440 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3441 DAG.getConstant(0, dl, MVT::i32));
3444 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3445 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3446 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3447 if (Subtarget->isMClass()) {
3448 // Only a full system barrier exists in the M-class architectures.
3449 Domain = ARM_MB::SY;
3450 } else if (Subtarget->preferISHSTBarriers() &&
3451 Ord == AtomicOrdering::Release) {
3452 // Swift happens to implement ISHST barriers in a way that's compatible with
3453 // Release semantics but weaker than ISH so we'd be fools not to use
3454 // it. Beware: other processors probably don't!
3455 Domain = ARM_MB::ISHST;
3458 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3459 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3460 DAG.getConstant(Domain, dl, MVT::i32));
3463 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3464 const ARMSubtarget *Subtarget) {
3465 // ARM pre v5TE and Thumb1 does not have preload instructions.
3466 if (!(Subtarget->isThumb2() ||
3467 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3468 // Just preserve the chain.
3469 return Op.getOperand(0);
3472 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3474 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3475 // ARMv7 with MP extension has PLDW.
3476 return Op.getOperand(0);
3478 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3479 if (Subtarget->isThumb()) {
3481 isRead = ~isRead & 1;
3482 isData = ~isData & 1;
3485 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3486 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3487 DAG.getConstant(isData, dl, MVT::i32));
3490 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3491 MachineFunction &MF = DAG.getMachineFunction();
3492 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3494 // vastart just stores the address of the VarArgsFrameIndex slot into the
3495 // memory location argument.
3497 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3498 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3499 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3500 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3501 MachinePointerInfo(SV));
3504 SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3505 CCValAssign &NextVA,
3508 const SDLoc &dl) const {
3509 MachineFunction &MF = DAG.getMachineFunction();
3510 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3512 const TargetRegisterClass *RC;
3513 if (AFI->isThumb1OnlyFunction())
3514 RC = &ARM::tGPRRegClass;
3516 RC = &ARM::GPRRegClass;
3518 // Transform the arguments stored in physical registers into virtual ones.
3519 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3520 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3523 if (NextVA.isMemLoc()) {
3524 MachineFrameInfo &MFI = MF.getFrameInfo();
3525 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3527 // Create load node to retrieve arguments from the stack.
3528 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3529 ArgValue2 = DAG.getLoad(
3530 MVT::i32, dl, Root, FIN,
3531 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3533 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3534 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3536 if (!Subtarget->isLittle())
3537 std::swap (ArgValue, ArgValue2);
3538 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3541 // The remaining GPRs hold either the beginning of variable-argument
3542 // data, or the beginning of an aggregate passed by value (usually
3543 // byval). Either way, we allocate stack slots adjacent to the data
3544 // provided by our caller, and store the unallocated registers there.
3545 // If this is a variadic function, the va_list pointer will begin with
3546 // these values; otherwise, this reassembles a (byval) structure that
3547 // was split between registers and memory.
3548 // Return: The frame index registers were stored into.
3549 int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3550 const SDLoc &dl, SDValue &Chain,
3551 const Value *OrigArg,
3552 unsigned InRegsParamRecordIdx,
3553 int ArgOffset, unsigned ArgSize) const {
3554 // Currently, two use-cases possible:
3555 // Case #1. Non-var-args function, and we meet first byval parameter.
3556 // Setup first unallocated register as first byval register;
3557 // eat all remained registers
3558 // (these two actions are performed by HandleByVal method).
3559 // Then, here, we initialize stack frame with
3560 // "store-reg" instructions.
3561 // Case #2. Var-args function, that doesn't contain byval parameters.
3562 // The same: eat all remained unallocated registers,
3563 // initialize stack frame.
3565 MachineFunction &MF = DAG.getMachineFunction();
3566 MachineFrameInfo &MFI = MF.getFrameInfo();
3567 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3568 unsigned RBegin, REnd;
3569 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3570 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3572 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3573 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3578 ArgOffset = -4 * (ARM::R4 - RBegin);
3580 auto PtrVT = getPointerTy(DAG.getDataLayout());
3581 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3582 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3584 SmallVector<SDValue, 4> MemOps;
3585 const TargetRegisterClass *RC =
3586 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3588 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3589 unsigned VReg = MF.addLiveIn(Reg, RC);
3590 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3591 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3592 MachinePointerInfo(OrigArg, 4 * i));
3593 MemOps.push_back(Store);
3594 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3597 if (!MemOps.empty())
3598 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3602 // Setup stack frame, the va_list pointer will start from.
3603 void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3604 const SDLoc &dl, SDValue &Chain,
3606 unsigned TotalArgRegsSaveSize,
3607 bool ForceMutable) const {
3608 MachineFunction &MF = DAG.getMachineFunction();
3609 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3611 // Try to store any remaining integer argument regs
3612 // to their spots on the stack so that they may be loaded by dereferencing
3613 // the result of va_next.
3614 // If there is no regs to be stored, just point address after last
3615 // argument passed via stack.
3616 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3617 CCInfo.getInRegsParamsCount(),
3618 CCInfo.getNextStackOffset(), 4);
3619 AFI->setVarArgsFrameIndex(FrameIndex);
3622 SDValue ARMTargetLowering::LowerFormalArguments(
3623 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3624 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3625 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 MachineFrameInfo &MFI = MF.getFrameInfo();
3629 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3631 // Assign locations to all of the incoming arguments.
3632 SmallVector<CCValAssign, 16> ArgLocs;
3633 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3635 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3637 SmallVector<SDValue, 16> ArgValues;
3639 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3640 unsigned CurArgIdx = 0;
3642 // Initially ArgRegsSaveSize is zero.
3643 // Then we increase this value each time we meet byval parameter.
3644 // We also increase this value in case of varargs function.
3645 AFI->setArgRegsSaveSize(0);
3647 // Calculate the amount of stack space that we need to allocate to store
3648 // byval and variadic arguments that are passed in registers.
3649 // We need to know this before we allocate the first byval or variadic
3650 // argument, as they will be allocated a stack slot below the CFA (Canonical
3651 // Frame Address, the stack pointer at entry to the function).
3652 unsigned ArgRegBegin = ARM::R4;
3653 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3654 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3657 CCValAssign &VA = ArgLocs[i];
3658 unsigned Index = VA.getValNo();
3659 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3660 if (!Flags.isByVal())
3663 assert(VA.isMemLoc() && "unexpected byval pointer in reg");
3664 unsigned RBegin, REnd;
3665 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3666 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3668 CCInfo.nextInRegsParam();
3670 CCInfo.rewindByValRegsInfo();
3672 int lastInsIndex = -1;
3673 if (isVarArg && MFI.hasVAStart()) {
3674 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3675 if (RegIdx != array_lengthof(GPRArgRegs))
3676 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3679 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3680 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3681 auto PtrVT = getPointerTy(DAG.getDataLayout());
3683 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3684 CCValAssign &VA = ArgLocs[i];
3685 if (Ins[VA.getValNo()].isOrigArg()) {
3686 std::advance(CurOrigArg,
3687 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3688 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3690 // Arguments stored in registers.
3691 if (VA.isRegLoc()) {
3692 EVT RegVT = VA.getLocVT();
3694 if (VA.needsCustom()) {
3695 // f64 and vector types are split up into multiple registers or
3696 // combinations of registers and stack slots.
3697 if (VA.getLocVT() == MVT::v2f64) {
3698 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3700 VA = ArgLocs[++i]; // skip ahead to next loc
3702 if (VA.isMemLoc()) {
3703 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3704 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3705 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3706 MachinePointerInfo::getFixedStack(
3707 DAG.getMachineFunction(), FI));
3709 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3712 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3713 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3714 ArgValue, ArgValue1,
3715 DAG.getIntPtrConstant(0, dl));
3716 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3717 ArgValue, ArgValue2,
3718 DAG.getIntPtrConstant(1, dl));
3720 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3722 const TargetRegisterClass *RC;
3725 if (RegVT == MVT::f16)
3726 RC = &ARM::HPRRegClass;
3727 else if (RegVT == MVT::f32)
3728 RC = &ARM::SPRRegClass;
3729 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
3730 RC = &ARM::DPRRegClass;
3731 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
3732 RC = &ARM::QPRRegClass;
3733 else if (RegVT == MVT::i32)
3734 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3735 : &ARM::GPRRegClass;
3737 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3739 // Transform the arguments in physical registers into virtual ones.
3740 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3741 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3744 // If this is an 8 or 16-bit value, it is really passed promoted
3745 // to 32 bits. Insert an assert[sz]ext to capture this, then
3746 // truncate to the right size.
3747 switch (VA.getLocInfo()) {
3748 default: llvm_unreachable("Unknown loc info!");
3749 case CCValAssign::Full: break;
3750 case CCValAssign::BCvt:
3751 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3753 case CCValAssign::SExt:
3754 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3755 DAG.getValueType(VA.getValVT()));
3756 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3758 case CCValAssign::ZExt:
3759 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3760 DAG.getValueType(VA.getValVT()));
3761 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3765 InVals.push_back(ArgValue);
3766 } else { // VA.isRegLoc()
3768 assert(VA.isMemLoc());
3769 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3771 int index = VA.getValNo();
3773 // Some Ins[] entries become multiple ArgLoc[] entries.
3774 // Process them only once.
3775 if (index != lastInsIndex)
3777 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3778 // FIXME: For now, all byval parameter objects are marked mutable.
3779 // This can be changed with more analysis.
3780 // In case of tail call optimization mark all arguments mutable.
3781 // Since they could be overwritten by lowering of arguments in case of
3783 if (Flags.isByVal()) {
3784 assert(Ins[index].isOrigArg() &&
3785 "Byval arguments cannot be implicit");
3786 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3788 int FrameIndex = StoreByValRegs(
3789 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3790 VA.getLocMemOffset(), Flags.getByValSize());
3791 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3792 CCInfo.nextInRegsParam();
3794 unsigned FIOffset = VA.getLocMemOffset();
3795 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3798 // Create load nodes to retrieve arguments from the stack.
3799 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3800 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3801 MachinePointerInfo::getFixedStack(
3802 DAG.getMachineFunction(), FI)));
3804 lastInsIndex = index;
3810 if (isVarArg && MFI.hasVAStart())
3811 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3812 CCInfo.getNextStackOffset(),
3813 TotalArgRegsSaveSize);
3815 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3820 /// isFloatingPointZero - Return true if this is +0.0.
3821 static bool isFloatingPointZero(SDValue Op) {
3822 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3823 return CFP->getValueAPF().isPosZero();
3824 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3825 // Maybe this has already been legalized into the constant pool?
3826 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3827 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3828 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3829 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3830 return CFP->getValueAPF().isPosZero();
3832 } else if (Op->getOpcode() == ISD::BITCAST &&
3833 Op->getValueType(0) == MVT::f64) {
3834 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3835 // created by LowerConstantFP().
3836 SDValue BitcastOp = Op->getOperand(0);
3837 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3838 isNullConstant(BitcastOp->getOperand(0)))
3844 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3845 /// the given operands.
3846 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3847 SDValue &ARMcc, SelectionDAG &DAG,
3848 const SDLoc &dl) const {
3849 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3850 unsigned C = RHSC->getZExtValue();
3851 if (!isLegalICmpImmediate((int32_t)C)) {
3852 // Constant does not fit, try adjusting it by one.
3857 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3858 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3859 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3864 if (C != 0 && isLegalICmpImmediate(C-1)) {
3865 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3866 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3871 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3872 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3873 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3878 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3879 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3880 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3885 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3886 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
3887 // In ARM and Thumb-2, the compare instructions can shift their second
3889 CC = ISD::getSetCCSwappedOperands(CC);
3890 std::swap(LHS, RHS);
3893 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3894 ARMISD::NodeType CompareType;
3897 CompareType = ARMISD::CMP;
3902 CompareType = ARMISD::CMPZ;
3905 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3906 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3909 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3910 SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3911 SelectionDAG &DAG, const SDLoc &dl,
3912 bool InvalidOnQNaN) const {
3913 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3915 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3916 if (!isFloatingPointZero(RHS))
3917 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3919 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3920 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3923 /// duplicateCmp - Glue values can have only one use, so this function
3924 /// duplicates a comparison node.
3926 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3927 unsigned Opc = Cmp.getOpcode();
3929 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3930 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3932 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3933 Cmp = Cmp.getOperand(0);
3934 Opc = Cmp.getOpcode();
3935 if (Opc == ARMISD::CMPFP)
3936 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3937 Cmp.getOperand(1), Cmp.getOperand(2));
3939 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3940 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3943 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3946 // This function returns three things: the arithmetic computation itself
3947 // (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3948 // comparison and the condition code define the case in which the arithmetic
3949 // computation *does not* overflow.
3950 std::pair<SDValue, SDValue>
3951 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3952 SDValue &ARMcc) const {
3953 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3955 SDValue Value, OverflowCmp;
3956 SDValue LHS = Op.getOperand(0);
3957 SDValue RHS = Op.getOperand(1);
3960 // FIXME: We are currently always generating CMPs because we don't support
3961 // generating CMN through the backend. This is not as good as the natural
3962 // CMP case because it causes a register dependency and cannot be folded
3965 switch (Op.getOpcode()) {
3967 llvm_unreachable("Unknown overflow instruction!");
3969 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3970 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3971 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3974 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3975 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3976 // We do not use it in the USUBO case as Value may not be used.
3977 Value = DAG.getNode(ARMISD::ADDC, dl,
3978 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3980 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3983 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3984 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3985 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3988 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3989 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3990 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3993 // We generate a UMUL_LOHI and then check if the high word is 0.
3994 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
3995 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
3996 DAG.getVTList(Op.getValueType(), Op.getValueType()),
3998 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
3999 DAG.getConstant(0, dl, MVT::i32));
4000 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4003 // We generate a SMUL_LOHI and then check if all the bits of the high word
4004 // are the same as the sign bit of the low word.
4005 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4006 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4007 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4009 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4010 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4012 DAG.getConstant(31, dl, MVT::i32)));
4013 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4017 return std::make_pair(Value, OverflowCmp);
4021 ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4022 // Let legalize expand this if it isn't a legal type yet.
4023 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4026 SDValue Value, OverflowCmp;
4028 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4029 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4031 // We use 0 and 1 as false and true values.
4032 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4033 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4034 EVT VT = Op.getValueType();
4036 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4037 ARMcc, CCR, OverflowCmp);
4039 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4040 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4043 static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4044 SelectionDAG &DAG) {
4045 SDLoc DL(BoolCarry);
4046 EVT CarryVT = BoolCarry.getValueType();
4048 // This converts the boolean value carry into the carry flag by doing
4049 // ARMISD::SUBC Carry, 1
4050 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4051 DAG.getVTList(CarryVT, MVT::i32),
4052 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4053 return Carry.getValue(1);
4056 static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4057 SelectionDAG &DAG) {
4060 // Now convert the carry flag into a boolean carry. We do this
4061 // using ARMISD:ADDE 0, 0, Carry
4062 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4063 DAG.getConstant(0, DL, MVT::i32),
4064 DAG.getConstant(0, DL, MVT::i32), Flags);
4067 SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4068 SelectionDAG &DAG) const {
4069 // Let legalize expand this if it isn't a legal type yet.
4070 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4073 SDValue LHS = Op.getOperand(0);
4074 SDValue RHS = Op.getOperand(1);
4077 EVT VT = Op.getValueType();
4078 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4081 switch (Op.getOpcode()) {
4083 llvm_unreachable("Unknown overflow instruction!");
4085 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4086 // Convert the carry flag into a boolean value.
4087 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4090 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4091 // Convert the carry flag into a boolean value.
4092 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4093 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4094 // value. So compute 1 - C.
4095 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4096 DAG.getConstant(1, dl, MVT::i32), Overflow);
4101 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4104 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4105 SDValue Cond = Op.getOperand(0);
4106 SDValue SelectTrue = Op.getOperand(1);
4107 SDValue SelectFalse = Op.getOperand(2);
4109 unsigned Opc = Cond.getOpcode();
4111 if (Cond.getResNo() == 1 &&
4112 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4113 Opc == ISD::USUBO)) {
4114 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4117 SDValue Value, OverflowCmp;
4119 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4120 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4121 EVT VT = Op.getValueType();
4123 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4129 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4130 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4132 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4133 const ConstantSDNode *CMOVTrue =
4134 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4135 const ConstantSDNode *CMOVFalse =
4136 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4138 if (CMOVTrue && CMOVFalse) {
4139 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4140 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4144 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4146 False = SelectFalse;
4147 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4152 if (True.getNode() && False.getNode()) {
4153 EVT VT = Op.getValueType();
4154 SDValue ARMcc = Cond.getOperand(2);
4155 SDValue CCR = Cond.getOperand(3);
4156 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4157 assert(True.getValueType() == VT);
4158 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4163 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4164 // undefined bits before doing a full-word comparison with zero.
4165 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4166 DAG.getConstant(1, dl, Cond.getValueType()));
4168 return DAG.getSelectCC(dl, Cond,
4169 DAG.getConstant(0, dl, Cond.getValueType()),
4170 SelectTrue, SelectFalse, ISD::SETNE);
4173 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4174 bool &swpCmpOps, bool &swpVselOps) {
4175 // Start by selecting the GE condition code for opcodes that return true for
4177 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4179 CondCode = ARMCC::GE;
4181 // and GT for opcodes that return false for 'equality'.
4182 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4184 CondCode = ARMCC::GT;
4186 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4187 // to swap the compare operands.
4188 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4192 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4193 // If we have an unordered opcode, we need to swap the operands to the VSEL
4194 // instruction (effectively negating the condition).
4196 // This also has the effect of swapping which one of 'less' or 'greater'
4197 // returns true, so we also swap the compare operands. It also switches
4198 // whether we return true for 'equality', so we compensate by picking the
4199 // opposite condition code to our original choice.
4200 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4201 CC == ISD::SETUGT) {
4202 swpCmpOps = !swpCmpOps;
4203 swpVselOps = !swpVselOps;
4204 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4207 // 'ordered' is 'anything but unordered', so use the VS condition code and
4208 // swap the VSEL operands.
4209 if (CC == ISD::SETO) {
4210 CondCode = ARMCC::VS;
4214 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4215 // code and swap the VSEL operands.
4216 if (CC == ISD::SETUNE) {
4217 CondCode = ARMCC::EQ;
4222 SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4223 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4224 SDValue Cmp, SelectionDAG &DAG) const {
4225 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
4226 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4227 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4228 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4229 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4231 SDValue TrueLow = TrueVal.getValue(0);
4232 SDValue TrueHigh = TrueVal.getValue(1);
4233 SDValue FalseLow = FalseVal.getValue(0);
4234 SDValue FalseHigh = FalseVal.getValue(1);
4236 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4238 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4239 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4241 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4243 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4248 static bool isGTorGE(ISD::CondCode CC) {
4249 return CC == ISD::SETGT || CC == ISD::SETGE;
4252 static bool isLTorLE(ISD::CondCode CC) {
4253 return CC == ISD::SETLT || CC == ISD::SETLE;
4256 // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4257 // All of these conditions (and their <= and >= counterparts) will do:
4262 static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4263 const SDValue TrueVal, const SDValue FalseVal,
4264 const ISD::CondCode CC, const SDValue K) {
4265 return (isGTorGE(CC) &&
4266 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4268 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4271 // Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4272 static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4273 const SDValue TrueVal, const SDValue FalseVal,
4274 const ISD::CondCode CC, const SDValue K) {
4275 return (isGTorGE(CC) &&
4276 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4278 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4281 // Check if two chained conditionals could be converted into SSAT or USAT.
4283 // SSAT can replace a set of two conditional selectors that bound a number to an
4284 // interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4286 // x < -k ? -k : (x > k ? k : x)
4287 // x < -k ? -k : (x < k ? x : k)
4288 // x > -k ? (x > k ? k : x) : -k
4289 // x < k ? (x < -k ? -k : x) : k
4292 // USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4295 // It returns true if the conversion can be done, false otherwise.
4296 // Additionally, the variable is returned in parameter V, the constant in K and
4297 // usat is set to true if the conditional represents an unsigned saturation
4298 static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4299 uint64_t &K, bool &usat) {
4300 SDValue LHS1 = Op.getOperand(0);
4301 SDValue RHS1 = Op.getOperand(1);
4302 SDValue TrueVal1 = Op.getOperand(2);
4303 SDValue FalseVal1 = Op.getOperand(3);
4304 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4306 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4307 if (Op2.getOpcode() != ISD::SELECT_CC)
4310 SDValue LHS2 = Op2.getOperand(0);
4311 SDValue RHS2 = Op2.getOperand(1);
4312 SDValue TrueVal2 = Op2.getOperand(2);
4313 SDValue FalseVal2 = Op2.getOperand(3);
4314 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4316 // Find out which are the constants and which are the variables
4317 // in each conditional
4318 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4321 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4324 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4325 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4326 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4327 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4329 // We must detect cases where the original operations worked with 16- or
4330 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4331 // must work with sign-extended values but the select operations return
4332 // the original non-extended value.
4333 SDValue V2TmpReg = V2Tmp;
4334 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4335 V2TmpReg = V2Tmp->getOperand(0);
4337 // Check that the registers and the constants have the correct values
4338 // in both conditionals
4339 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4343 // Figure out which conditional is saturating the lower/upper bound.
4344 const SDValue *LowerCheckOp =
4345 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4347 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4350 const SDValue *UpperCheckOp =
4351 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4353 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4357 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4360 // Check that the constant in the lower-bound check is
4361 // the opposite of the constant in the upper-bound check
4362 // in 1's complement.
4363 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4364 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4365 int64_t PosVal = std::max(Val1, Val2);
4366 int64_t NegVal = std::min(Val1, Val2);
4368 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4369 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4370 isPowerOf2_64(PosVal + 1)) {
4372 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4375 else if (NegVal == 0)
4381 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4389 // Check if a condition of the type x < k ? k : x can be converted into a
4390 // bit operation instead of conditional moves.
4391 // Currently this is allowed given:
4392 // - The conditions and values match up
4393 // - k is 0 or -1 (all ones)
4394 // This function will not check the last condition, thats up to the caller
4395 // It returns true if the transformation can be made, and in such case
4396 // returns x in V, and k in SatK.
4397 static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4400 SDValue LHS = Op.getOperand(0);
4401 SDValue RHS = Op.getOperand(1);
4402 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4403 SDValue TrueVal = Op.getOperand(2);
4404 SDValue FalseVal = Op.getOperand(3);
4406 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4410 // No constant operation in comparison, early out
4414 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4415 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4416 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4418 // If the constant on left and right side, or variable on left and right,
4419 // does not match, early out
4420 if (*K != KTmp || V != VTmp)
4423 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4431 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4432 EVT VT = Op.getValueType();
4435 // Try to convert two saturating conditional selects into a single SSAT
4437 uint64_t SatConstant;
4439 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4440 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4442 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4443 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4445 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4446 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4449 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4450 // into more efficient bit operations, which is possible when k is 0 or -1
4451 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4452 // single instructions. On Thumb the shift and the bit operation will be two
4454 // Only allow this transformation on full-width (32-bit) operations
4455 SDValue LowerSatConstant;
4456 if (VT == MVT::i32 &&
4457 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4458 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4459 DAG.getConstant(31, dl, VT));
4460 if (isNullConstant(LowerSatConstant)) {
4461 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4462 DAG.getAllOnesConstant(dl, VT));
4463 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4464 } else if (isAllOnesConstant(LowerSatConstant))
4465 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4468 SDValue LHS = Op.getOperand(0);
4469 SDValue RHS = Op.getOperand(1);
4470 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4471 SDValue TrueVal = Op.getOperand(2);
4472 SDValue FalseVal = Op.getOperand(3);
4474 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4475 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4478 // If softenSetCCOperands only returned one value, we should compare it to
4480 if (!RHS.getNode()) {
4481 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4486 if (LHS.getValueType() == MVT::i32) {
4487 // Try to generate VSEL on ARMv8.
4488 // The VSEL instruction can't use all the usual ARM condition
4489 // codes: it only has two bits to select the condition code, so it's
4490 // constrained to use only GE, GT, VS and EQ.
4492 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4493 // swap the operands of the previous compare instruction (effectively
4494 // inverting the compare condition, swapping 'less' and 'greater') and
4495 // sometimes need to swap the operands to the VSEL (which inverts the
4496 // condition in the sense of firing whenever the previous condition didn't)
4497 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4498 TrueVal.getValueType() == MVT::f64)) {
4499 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4500 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
4501 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
4502 CC = ISD::getSetCCInverse(CC, true);
4503 std::swap(TrueVal, FalseVal);
4508 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4509 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4510 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4513 ARMCC::CondCodes CondCode, CondCode2;
4515 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4517 // Normalize the fp compare. If RHS is zero we keep it there so we match
4518 // CMPFPw0 instead of CMPFP.
4519 if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
4520 (TrueVal.getValueType() == MVT::f16 ||
4521 TrueVal.getValueType() == MVT::f32 ||
4522 TrueVal.getValueType() == MVT::f64)) {
4523 bool swpCmpOps = false;
4524 bool swpVselOps = false;
4525 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4527 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
4528 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
4530 std::swap(LHS, RHS);
4532 std::swap(TrueVal, FalseVal);
4536 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4537 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4538 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4539 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4540 if (CondCode2 != ARMCC::AL) {
4541 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
4542 // FIXME: Needs another CMP because flag can have but one use.
4543 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4544 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
4549 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
4550 /// to morph to an integer compare sequence.
4551 static bool canChangeToInt(SDValue Op, bool &SeenZero,
4552 const ARMSubtarget *Subtarget) {
4553 SDNode *N = Op.getNode();
4554 if (!N->hasOneUse())
4555 // Otherwise it requires moving the value from fp to integer registers.
4557 if (!N->getNumValues())
4559 EVT VT = Op.getValueType();
4560 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
4561 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
4562 // vmrs are very slow, e.g. cortex-a8.
4565 if (isFloatingPointZero(Op)) {
4569 return ISD::isNormalLoad(N);
4572 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
4573 if (isFloatingPointZero(Op))
4574 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
4576 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
4577 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
4578 Ld->getPointerInfo(), Ld->getAlignment(),
4579 Ld->getMemOperand()->getFlags());
4581 llvm_unreachable("Unknown VFP cmp argument!");
4584 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
4585 SDValue &RetVal1, SDValue &RetVal2) {
4588 if (isFloatingPointZero(Op)) {
4589 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
4590 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
4594 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4595 SDValue Ptr = Ld->getBasePtr();
4597 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
4598 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
4600 EVT PtrType = Ptr.getValueType();
4601 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
4602 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4603 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
4604 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
4605 Ld->getPointerInfo().getWithOffset(4), NewAlign,
4606 Ld->getMemOperand()->getFlags());
4610 llvm_unreachable("Unknown VFP cmp argument!");
4613 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
4614 /// f32 and even f64 comparisons to integer ones.
4616 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4617 SDValue Chain = Op.getOperand(0);
4618 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4619 SDValue LHS = Op.getOperand(2);
4620 SDValue RHS = Op.getOperand(3);
4621 SDValue Dest = Op.getOperand(4);
4624 bool LHSSeenZero = false;
4625 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
4626 bool RHSSeenZero = false;
4627 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
4628 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
4629 // If unsafe fp math optimization is enabled and there are no other uses of
4630 // the CMP operands, and the condition code is EQ or NE, we can optimize it
4631 // to an integer comparison.
4632 if (CC == ISD::SETOEQ)
4634 else if (CC == ISD::SETUNE)
4637 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4639 if (LHS.getValueType() == MVT::f32) {
4640 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4641 bitcastf32Toi32(LHS, DAG), Mask);
4642 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4643 bitcastf32Toi32(RHS, DAG), Mask);
4644 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4645 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4646 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4647 Chain, Dest, ARMcc, CCR, Cmp);
4652 expandf64Toi32(LHS, DAG, LHS1, LHS2);
4653 expandf64Toi32(RHS, DAG, RHS1, RHS2);
4654 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
4655 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
4656 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4657 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4658 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4659 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
4660 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4666 SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
4667 SDValue Chain = Op.getOperand(0);
4668 SDValue Cond = Op.getOperand(1);
4669 SDValue Dest = Op.getOperand(2);
4672 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4674 unsigned Opc = Cond.getOpcode();
4675 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4676 !Subtarget->isThumb1Only();
4677 if (Cond.getResNo() == 1 &&
4678 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4679 Opc == ISD::USUBO || OptimizeMul)) {
4680 // Only lower legal XALUO ops.
4681 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4684 // The actual operation with overflow check.
4685 SDValue Value, OverflowCmp;
4687 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4689 // Reverse the condition code.
4690 ARMCC::CondCodes CondCode =
4691 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4692 CondCode = ARMCC::getOppositeCondition(CondCode);
4693 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4694 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4696 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4703 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4704 SDValue Chain = Op.getOperand(0);
4705 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4706 SDValue LHS = Op.getOperand(2);
4707 SDValue RHS = Op.getOperand(3);
4708 SDValue Dest = Op.getOperand(4);
4711 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4712 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4715 // If softenSetCCOperands only returned one value, we should compare it to
4717 if (!RHS.getNode()) {
4718 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4723 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4725 unsigned Opc = LHS.getOpcode();
4726 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4727 !Subtarget->isThumb1Only();
4728 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
4729 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4730 Opc == ISD::USUBO || OptimizeMul) &&
4731 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4732 // Only lower legal XALUO ops.
4733 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4736 // The actual operation with overflow check.
4737 SDValue Value, OverflowCmp;
4739 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
4741 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
4742 // Reverse the condition code.
4743 ARMCC::CondCodes CondCode =
4744 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4745 CondCode = ARMCC::getOppositeCondition(CondCode);
4746 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4748 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4750 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4754 if (LHS.getValueType() == MVT::i32) {
4756 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4757 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4758 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4759 Chain, Dest, ARMcc, CCR, Cmp);
4762 if (getTargetMachine().Options.UnsafeFPMath &&
4763 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4764 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4765 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4769 ARMCC::CondCodes CondCode, CondCode2;
4771 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4773 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4774 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4775 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4776 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4777 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
4778 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4779 if (CondCode2 != ARMCC::AL) {
4780 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
4781 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
4782 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4787 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4788 SDValue Chain = Op.getOperand(0);
4789 SDValue Table = Op.getOperand(1);
4790 SDValue Index = Op.getOperand(2);
4793 EVT PTy = getPointerTy(DAG.getDataLayout());
4794 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
4795 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
4796 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4797 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
4798 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
4799 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
4800 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
4801 // which does another jump to the destination. This also makes it easier
4802 // to translate it to TBB / TBH later (Thumb2 only).
4803 // FIXME: This might not work if the function is extremely large.
4804 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4805 Addr, Op.getOperand(2), JTI);
4807 if (isPositionIndependent() || Subtarget->isROPI()) {
4809 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
4810 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4811 Chain = Addr.getValue(1);
4812 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
4813 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4816 DAG.getLoad(PTy, dl, Chain, Addr,
4817 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4818 Chain = Addr.getValue(1);
4819 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4823 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4824 EVT VT = Op.getValueType();
4827 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4828 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4830 return DAG.UnrollVectorOp(Op.getNode());
4833 const bool HasFullFP16 =
4834 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
4837 const EVT OpTy = Op.getOperand(0).getValueType();
4838 if (OpTy == MVT::v4f32)
4840 else if (OpTy == MVT::v4f16 && HasFullFP16)
4842 else if (OpTy == MVT::v8f16 && HasFullFP16)
4845 llvm_unreachable("Invalid type for custom lowering!");
4847 if (VT != MVT::v4i16 && VT != MVT::v8i16)
4848 return DAG.UnrollVectorOp(Op.getNode());
4850 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
4851 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4854 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4855 EVT VT = Op.getValueType();
4857 return LowerVectorFP_TO_INT(Op, DAG);
4858 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4860 if (Op.getOpcode() == ISD::FP_TO_SINT)
4861 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4864 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4866 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4867 /*isSigned*/ false, SDLoc(Op)).first;
4873 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4874 EVT VT = Op.getValueType();
4877 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4878 if (VT.getVectorElementType() == MVT::f32)
4880 return DAG.UnrollVectorOp(Op.getNode());
4883 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||
4884 Op.getOperand(0).getValueType() == MVT::v8i16) &&
4885 "Invalid type for custom lowering!");
4887 const bool HasFullFP16 =
4888 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
4891 if (VT == MVT::v4f32)
4892 DestVecType = MVT::v4i32;
4893 else if (VT == MVT::v4f16 && HasFullFP16)
4894 DestVecType = MVT::v4i16;
4895 else if (VT == MVT::v8f16 && HasFullFP16)
4896 DestVecType = MVT::v8i16;
4898 return DAG.UnrollVectorOp(Op.getNode());
4902 switch (Op.getOpcode()) {
4903 default: llvm_unreachable("Invalid opcode!");
4904 case ISD::SINT_TO_FP:
4905 CastOpc = ISD::SIGN_EXTEND;
4906 Opc = ISD::SINT_TO_FP;
4908 case ISD::UINT_TO_FP:
4909 CastOpc = ISD::ZERO_EXTEND;
4910 Opc = ISD::UINT_TO_FP;
4914 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
4915 return DAG.getNode(Opc, dl, VT, Op);
4918 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4919 EVT VT = Op.getValueType();
4921 return LowerVectorINT_TO_FP(Op, DAG);
4922 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4924 if (Op.getOpcode() == ISD::SINT_TO_FP)
4925 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4928 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4930 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4931 /*isSigned*/ false, SDLoc(Op)).first;
4937 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4938 // Implement fcopysign with a fabs and a conditional fneg.
4939 SDValue Tmp0 = Op.getOperand(0);
4940 SDValue Tmp1 = Op.getOperand(1);
4942 EVT VT = Op.getValueType();
4943 EVT SrcVT = Tmp1.getValueType();
4944 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4945 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4946 bool UseNEON = !InGPR && Subtarget->hasNEON();
4949 // Use VBSL to copy the sign bit.
4950 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4951 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4952 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4953 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4955 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4956 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4957 DAG.getConstant(32, dl, MVT::i32));
4958 else /*if (VT == MVT::f32)*/
4959 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4960 if (SrcVT == MVT::f32) {
4961 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4963 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4964 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4965 DAG.getConstant(32, dl, MVT::i32));
4966 } else if (VT == MVT::f32)
4967 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4968 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4969 DAG.getConstant(32, dl, MVT::i32));
4970 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4971 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4973 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4975 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4976 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4977 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4979 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4980 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4981 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4982 if (VT == MVT::f32) {
4983 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4984 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4985 DAG.getConstant(0, dl, MVT::i32));
4987 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4993 // Bitcast operand 1 to i32.
4994 if (SrcVT == MVT::f64)
4995 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4997 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4999 // Or in the signbit with integer operations.
5000 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5001 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5002 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5003 if (VT == MVT::f32) {
5004 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5005 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5006 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5007 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5010 // f64: Or the high part with signbit and then combine two parts.
5011 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5013 SDValue Lo = Tmp0.getValue(0);
5014 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5015 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5016 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5019 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5020 MachineFunction &MF = DAG.getMachineFunction();
5021 MachineFrameInfo &MFI = MF.getFrameInfo();
5022 MFI.setReturnAddressIsTaken(true);
5024 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5027 EVT VT = Op.getValueType();
5029 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5031 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5032 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5033 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5034 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5035 MachinePointerInfo());
5038 // Return LR, which contains the return address. Mark it an implicit live-in.
5039 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5040 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5043 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5044 const ARMBaseRegisterInfo &ARI =
5045 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5046 MachineFunction &MF = DAG.getMachineFunction();
5047 MachineFrameInfo &MFI = MF.getFrameInfo();
5048 MFI.setFrameAddressIsTaken(true);
5050 EVT VT = Op.getValueType();
5051 SDLoc dl(Op); // FIXME probably not meaningful
5052 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5053 unsigned FrameReg = ARI.getFrameRegister(MF);
5054 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5056 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5057 MachinePointerInfo());
5061 // FIXME? Maybe this could be a TableGen attribute on some registers and
5062 // this table could be generated automatically from RegInfo.
5063 unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
5064 SelectionDAG &DAG) const {
5065 unsigned Reg = StringSwitch<unsigned>(RegName)
5066 .Case("sp", ARM::SP)
5070 report_fatal_error(Twine("Invalid register name \""
5071 + StringRef(RegName) + "\"."));
5074 // Result is 64 bit value so split into two 32 bit values and return as a
5076 static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5077 SelectionDAG &DAG) {
5080 // This function is only supposed to be called for i64 type destination.
5081 assert(N->getValueType(0) == MVT::i64
5082 && "ExpandREAD_REGISTER called for non-i64 type result.");
5084 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5085 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5089 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5091 Results.push_back(Read.getOperand(0));
5094 /// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5095 /// When \p DstVT, the destination type of \p BC, is on the vector
5096 /// register bank and the source of bitcast, \p Op, operates on the same bank,
5097 /// it might be possible to combine them, such that everything stays on the
5098 /// vector register bank.
5099 /// \p return The node that would replace \p BT, if the combine
5101 static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5102 SelectionDAG &DAG) {
5103 SDValue Op = BC->getOperand(0);
5104 EVT DstVT = BC->getValueType(0);
5106 // The only vector instruction that can produce a scalar (remember,
5107 // since the bitcast was about to be turned into VMOVDRR, the source
5108 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5109 // Moreover, we can do this combine only if there is one use.
5110 // Finally, if the destination type is not a vector, there is not
5111 // much point on forcing everything on the vector bank.
5112 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5116 // If the index is not constant, we will introduce an additional
5117 // multiply that will stick.
5118 // Give up in that case.
5119 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5122 unsigned DstNumElt = DstVT.getVectorNumElements();
5124 // Compute the new index.
5125 const APInt &APIntIndex = Index->getAPIntValue();
5126 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5127 NewIndex *= APIntIndex;
5128 // Check if the new constant index fits into i32.
5129 if (NewIndex.getBitWidth() > 32)
5132 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5133 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5135 SDValue ExtractSrc = Op.getOperand(0);
5136 EVT VecVT = EVT::getVectorVT(
5137 *DAG.getContext(), DstVT.getScalarType(),
5138 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5139 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5140 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5141 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5144 /// ExpandBITCAST - If the target supports VFP, this function is called to
5145 /// expand a bit convert where either the source or destination type is i64 to
5146 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5147 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
5148 /// vectors), since the legalizer won't know what to do with that.
5149 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5150 const ARMSubtarget *Subtarget) {
5151 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5153 SDValue Op = N->getOperand(0);
5155 // This function is only supposed to be called for i64 types, either as the
5156 // source or destination of the bit convert.
5157 EVT SrcVT = Op.getValueType();
5158 EVT DstVT = N->getValueType(0);
5159 const bool HasFullFP16 = Subtarget->hasFullFP16();
5161 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5162 // FullFP16: half values are passed in S-registers, and we don't
5163 // need any of the bitcast and moves:
5165 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5166 // t5: i32 = bitcast t2
5167 // t18: f16 = ARMISD::VMOVhr t5
5168 if (Op.getOpcode() != ISD::CopyFromReg ||
5169 Op.getValueType() != MVT::f32)
5172 auto Move = N->use_begin();
5173 if (Move->getOpcode() != ARMISD::VMOVhr)
5176 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5177 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5178 DAG.ReplaceAllUsesWith(*Move, &Copy);
5182 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5185 // SoftFP: read half-precision arguments:
5188 // t7: i16 = truncate t2 <~~~~ Op
5189 // t8: f16 = bitcast t7 <~~~~ N
5191 if (Op.getOperand(0).getValueType() == MVT::i32)
5192 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5193 MVT::f16, Op.getOperand(0));
5198 // Half-precision return values
5199 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5203 // t11: f16 = fadd t8, t10
5204 // t12: i16 = bitcast t11 <~~~ SDNode N
5205 // t13: i32 = zero_extend t12
5206 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5207 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5209 // transform this into:
5211 // t20: i32 = ARMISD::VMOVrh t11
5212 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5214 auto ZeroExtend = N->use_begin();
5215 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5216 ZeroExtend->getValueType(0) != MVT::i32)
5219 auto Copy = ZeroExtend->use_begin();
5220 if (Copy->getOpcode() == ISD::CopyToReg &&
5221 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5222 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5223 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5229 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5232 // Turn i64->f64 into VMOVDRR.
5233 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5234 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5235 // if we can combine the bitcast with its source.
5236 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5239 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5240 DAG.getConstant(0, dl, MVT::i32));
5241 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5242 DAG.getConstant(1, dl, MVT::i32));
5243 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5244 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5247 // Turn f64->i64 into VMOVRRD.
5248 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5250 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5251 SrcVT.getVectorNumElements() > 1)
5252 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5253 DAG.getVTList(MVT::i32, MVT::i32),
5254 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5256 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5257 DAG.getVTList(MVT::i32, MVT::i32), Op);
5258 // Merge the pieces into a single i64 value.
5259 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5265 /// getZeroVector - Returns a vector of specified type with all zero elements.
5266 /// Zero vectors are used to represent vector negation and in those cases
5267 /// will be implemented with the NEON VNEG instruction. However, VNEG does
5268 /// not support i64 elements, so sometimes the zero vectors will need to be
5269 /// explicitly constructed. Regardless, use a canonical VMOV to create the
5271 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5272 assert(VT.isVector() && "Expected a vector type");
5273 // The canonical modified immediate encoding of a zero vector is....0!
5274 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5275 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5276 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5277 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5280 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5281 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
5282 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5283 SelectionDAG &DAG) const {
5284 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5285 EVT VT = Op.getValueType();
5286 unsigned VTBits = VT.getSizeInBits();
5288 SDValue ShOpLo = Op.getOperand(0);
5289 SDValue ShOpHi = Op.getOperand(1);
5290 SDValue ShAmt = Op.getOperand(2);
5292 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5293 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5295 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
5297 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5298 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5299 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5300 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5301 DAG.getConstant(VTBits, dl, MVT::i32));
5302 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5303 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5304 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5305 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5306 ISD::SETGE, ARMcc, DAG, dl);
5307 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5310 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5311 SDValue HiBigShift = Opc == ISD::SRA
5312 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5313 DAG.getConstant(VTBits - 1, dl, VT))
5314 : DAG.getConstant(0, dl, VT);
5315 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5316 ISD::SETGE, ARMcc, DAG, dl);
5317 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5320 SDValue Ops[2] = { Lo, Hi };
5321 return DAG.getMergeValues(Ops, dl);
5324 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5325 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
5326 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5327 SelectionDAG &DAG) const {
5328 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5329 EVT VT = Op.getValueType();
5330 unsigned VTBits = VT.getSizeInBits();
5332 SDValue ShOpLo = Op.getOperand(0);
5333 SDValue ShOpHi = Op.getOperand(1);
5334 SDValue ShAmt = Op.getOperand(2);
5336 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5338 assert(Op.getOpcode() == ISD::SHL_PARTS);
5339 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5340 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5341 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5342 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5343 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5345 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5346 DAG.getConstant(VTBits, dl, MVT::i32));
5347 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5348 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5349 ISD::SETGE, ARMcc, DAG, dl);
5350 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5353 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5354 ISD::SETGE, ARMcc, DAG, dl);
5355 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5356 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5357 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5359 SDValue Ops[2] = { Lo, Hi };
5360 return DAG.getMergeValues(Ops, dl);
5363 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5364 SelectionDAG &DAG) const {
5365 // The rounding mode is in bits 23:22 of the FPSCR.
5366 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5367 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5368 // so that the shift + and get folded into a bitfield extract.
5370 SDValue Ops[] = { DAG.getEntryNode(),
5371 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5373 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5374 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5375 DAG.getConstant(1U << 22, dl, MVT::i32));
5376 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5377 DAG.getConstant(22, dl, MVT::i32));
5378 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5379 DAG.getConstant(3, dl, MVT::i32));
5382 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5383 const ARMSubtarget *ST) {
5385 EVT VT = N->getValueType(0);
5386 if (VT.isVector()) {
5387 assert(ST->hasNEON());
5389 // Compute the least significant set bit: LSB = X & -X
5390 SDValue X = N->getOperand(0);
5391 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5392 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5394 EVT ElemTy = VT.getVectorElementType();
5396 if (ElemTy == MVT::i8) {
5397 // Compute with: cttz(x) = ctpop(lsb - 1)
5398 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5399 DAG.getTargetConstant(1, dl, ElemTy));
5400 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5401 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5404 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5405 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5406 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5407 unsigned NumBits = ElemTy.getSizeInBits();
5408 SDValue WidthMinus1 =
5409 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5410 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5411 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5412 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5415 // Compute with: cttz(x) = ctpop(lsb - 1)
5419 if (ElemTy == MVT::i64) {
5420 // Load constant 0xffff'ffff'ffff'ffff to register.
5421 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5422 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5423 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5425 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5426 DAG.getTargetConstant(1, dl, ElemTy));
5427 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5429 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5432 if (!ST->hasV6T2Ops())
5435 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5436 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5439 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5440 const ARMSubtarget *ST) {
5441 EVT VT = N->getValueType(0);
5444 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
5445 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
5446 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
5447 "Unexpected type for custom ctpop lowering");
5449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5450 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5451 SDValue Res = DAG.getBitcast(VT8Bit, N->getOperand(0));
5452 Res = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Res);
5454 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
5455 unsigned EltSize = 8;
5456 unsigned NumElts = VT.is64BitVector() ? 8 : 16;
5457 while (EltSize != VT.getScalarSizeInBits()) {
5458 SmallVector<SDValue, 8> Ops;
5459 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddlu, DL,
5460 TLI.getPointerTy(DAG.getDataLayout())));
5465 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts);
5466 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WidenVT, Ops);
5472 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
5473 const ARMSubtarget *ST) {
5474 EVT VT = N->getValueType(0);
5480 // Lower vector shifts on NEON to use VSHL.
5481 assert(ST->hasNEON() && "unexpected vector shift");
5483 // Left shifts translate directly to the vshiftu intrinsic.
5484 if (N->getOpcode() == ISD::SHL)
5485 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5486 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
5488 N->getOperand(0), N->getOperand(1));
5490 assert((N->getOpcode() == ISD::SRA ||
5491 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
5493 // NEON uses the same intrinsics for both left and right shifts. For
5494 // right shifts, the shift amounts are negative, so negate the vector of
5496 EVT ShiftVT = N->getOperand(1).getValueType();
5497 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
5498 getZeroVector(ShiftVT, DAG, dl),
5500 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
5501 Intrinsic::arm_neon_vshifts :
5502 Intrinsic::arm_neon_vshiftu);
5503 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5504 DAG.getConstant(vshiftInt, dl, MVT::i32),
5505 N->getOperand(0), NegatedCount);
5508 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
5509 const ARMSubtarget *ST) {
5510 EVT VT = N->getValueType(0);
5513 // We can get here for a node like i32 = ISD::SHL i32, i64
5517 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
5518 "Unknown shift to lower!");
5520 // We only lower SRA, SRL of 1 here, all others use generic lowering.
5521 if (!isOneConstant(N->getOperand(1)))
5524 // If we are in thumb mode, we don't have RRX.
5525 if (ST->isThumb1Only()) return SDValue();
5527 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5528 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5529 DAG.getConstant(0, dl, MVT::i32));
5530 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5531 DAG.getConstant(1, dl, MVT::i32));
5533 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
5534 // captures the result into a carry flag.
5535 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
5536 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
5538 // The low part is an ARMISD::RRX operand, which shifts the carry in.
5539 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
5541 // Merge the pieces into a single i64 value.
5542 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5545 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5546 SDValue TmpOp0, TmpOp1;
5547 bool Invert = false;
5551 SDValue Op0 = Op.getOperand(0);
5552 SDValue Op1 = Op.getOperand(1);
5553 SDValue CC = Op.getOperand(2);
5554 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5555 EVT VT = Op.getValueType();
5556 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5559 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
5560 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
5561 // Special-case integer 64-bit equality comparisons. They aren't legal,
5562 // but they can be lowered with a few vector instructions.
5563 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
5564 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
5565 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
5566 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
5567 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
5568 DAG.getCondCode(ISD::SETEQ));
5569 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
5570 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
5571 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
5572 if (SetCCOpcode == ISD::SETNE)
5573 Merged = DAG.getNOT(dl, Merged, CmpVT);
5574 Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
5578 if (CmpVT.getVectorElementType() == MVT::i64)
5579 // 64-bit comparisons are not legal in general.
5582 if (Op1.getValueType().isFloatingPoint()) {
5583 switch (SetCCOpcode) {
5584 default: llvm_unreachable("Illegal FP comparison");
5586 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH;
5588 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5590 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
5592 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5594 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH;
5596 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5597 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH;
5598 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
5599 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH;
5600 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
5601 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH;
5603 // Expand this to (OLT | OGT).
5607 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5608 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
5614 // Expand this to (OLT | OGE).
5618 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5619 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
5623 // Integer comparisons.
5624 switch (SetCCOpcode) {
5625 default: llvm_unreachable("Illegal integer comparison");
5626 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH;
5627 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5628 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
5629 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5630 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH;
5631 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5632 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH;
5633 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
5634 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH;
5635 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
5638 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5639 if (Opc == ARMISD::VCEQ) {
5641 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5643 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
5646 // Ignore bitconvert.
5647 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
5648 AndOp = AndOp.getOperand(0);
5650 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
5652 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
5653 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
5660 std::swap(Op0, Op1);
5662 // If one of the operands is a constant vector zero, attempt to fold the
5663 // comparison to a specialized compare-against-zero form.
5665 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5667 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5668 if (Opc == ARMISD::VCGE)
5669 Opc = ARMISD::VCLEZ;
5670 else if (Opc == ARMISD::VCGT)
5671 Opc = ARMISD::VCLTZ;
5676 if (SingleOp.getNode()) {
5679 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
5681 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
5683 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
5685 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
5687 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5689 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5692 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5695 Result = DAG.getSExtOrTrunc(Result, dl, VT);
5698 Result = DAG.getNOT(dl, Result, VT);
5703 static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
5704 SDValue LHS = Op.getOperand(0);
5705 SDValue RHS = Op.getOperand(1);
5706 SDValue Carry = Op.getOperand(2);
5707 SDValue Cond = Op.getOperand(3);
5710 assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
5712 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
5713 // have to invert the carry first.
5714 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
5715 DAG.getConstant(1, DL, MVT::i32), Carry);
5716 // This converts the boolean value carry into the carry flag.
5717 Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
5719 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
5720 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5722 SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
5723 SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
5724 SDValue ARMcc = DAG.getConstant(
5725 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
5726 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5727 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
5728 Cmp.getValue(1), SDValue());
5729 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5730 CCR, Chain.getValue(1));
5733 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
5734 /// valid vector constant for a NEON instruction with a "modified immediate"
5735 /// operand (e.g., VMOV). If so, return the encoded value.
5736 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
5737 unsigned SplatBitSize, SelectionDAG &DAG,
5738 const SDLoc &dl, EVT &VT, bool is128Bits,
5739 NEONModImmType type) {
5740 unsigned OpCmode, Imm;
5742 // SplatBitSize is set to the smallest size that splats the vector, so a
5743 // zero vector will always have SplatBitSize == 8. However, NEON modified
5744 // immediate instructions others than VMOV do not support the 8-bit encoding
5745 // of a zero vector, and the default encoding of zero is supposed to be the
5750 switch (SplatBitSize) {
5752 if (type != VMOVModImm)
5754 // Any 1-byte value is OK. Op=0, Cmode=1110.
5755 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
5758 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
5762 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
5763 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5764 if ((SplatBits & ~0xff) == 0) {
5765 // Value = 0x00nn: Op=x, Cmode=100x.
5770 if ((SplatBits & ~0xff00) == 0) {
5771 // Value = 0xnn00: Op=x, Cmode=101x.
5773 Imm = SplatBits >> 8;
5779 // NEON's 32-bit VMOV supports splat values where:
5780 // * only one byte is nonzero, or
5781 // * the least significant byte is 0xff and the second byte is nonzero, or
5782 // * the least significant 2 bytes are 0xff and the third is nonzero.
5783 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
5784 if ((SplatBits & ~0xff) == 0) {
5785 // Value = 0x000000nn: Op=x, Cmode=000x.
5790 if ((SplatBits & ~0xff00) == 0) {
5791 // Value = 0x0000nn00: Op=x, Cmode=001x.
5793 Imm = SplatBits >> 8;
5796 if ((SplatBits & ~0xff0000) == 0) {
5797 // Value = 0x00nn0000: Op=x, Cmode=010x.
5799 Imm = SplatBits >> 16;
5802 if ((SplatBits & ~0xff000000) == 0) {
5803 // Value = 0xnn000000: Op=x, Cmode=011x.
5805 Imm = SplatBits >> 24;
5809 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
5810 if (type == OtherModImm) return SDValue();
5812 if ((SplatBits & ~0xffff) == 0 &&
5813 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
5814 // Value = 0x0000nnff: Op=x, Cmode=1100.
5816 Imm = SplatBits >> 8;
5820 if ((SplatBits & ~0xffffff) == 0 &&
5821 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
5822 // Value = 0x00nnffff: Op=x, Cmode=1101.
5824 Imm = SplatBits >> 16;
5828 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
5829 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
5830 // VMOV.I32. A (very) minor optimization would be to replicate the value
5831 // and fall through here to test for a valid 64-bit splat. But, then the
5832 // caller would also need to check and handle the change in size.
5836 if (type != VMOVModImm)
5838 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
5839 uint64_t BitMask = 0xff;
5841 unsigned ImmMask = 1;
5843 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
5844 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
5847 } else if ((SplatBits & BitMask) != 0) {
5854 if (DAG.getDataLayout().isBigEndian())
5855 // swap higher and lower 32 bit word
5856 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
5858 // Op=1, Cmode=1110.
5860 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
5865 llvm_unreachable("unexpected size for isNEONModifiedImm");
5868 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
5869 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
5872 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5873 const ARMSubtarget *ST) const {
5874 EVT VT = Op.getValueType();
5875 bool IsDouble = (VT == MVT::f64);
5876 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5877 const APFloat &FPVal = CFP->getValueAPF();
5879 // Prevent floating-point constants from using literal loads
5880 // when execute-only is enabled.
5881 if (ST->genExecuteOnly()) {
5882 // If we can represent the constant as an immediate, don't lower it
5883 if (isFPImmLegal(FPVal, VT))
5885 // Otherwise, construct as integer, and move to float register
5886 APInt INTVal = FPVal.bitcastToAPInt();
5888 switch (VT.getSimpleVT().SimpleTy) {
5890 llvm_unreachable("Unknown floating point type!");
5893 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
5894 SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
5895 if (!ST->isLittle())
5897 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
5900 return DAG.getNode(ARMISD::VMOVSR, DL, VT,
5901 DAG.getConstant(INTVal, DL, MVT::i32));
5908 // Use the default (constant pool) lowering for double constants when we have
5910 if (IsDouble && Subtarget->isFPOnlySP())
5913 // Try splatting with a VMOV.f32...
5914 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
5917 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
5918 // We have code in place to select a valid ConstantFP already, no need to
5923 // It's a float and we are trying to use NEON operations where
5924 // possible. Lower it to a splat followed by an extract.
5926 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
5927 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
5929 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
5930 DAG.getConstant(0, DL, MVT::i32));
5933 // The rest of our options are NEON only, make sure that's allowed before
5935 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
5939 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
5941 // It wouldn't really be worth bothering for doubles except for one very
5942 // important value, which does happen to match: 0.0. So make sure we don't do
5944 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
5947 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
5948 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
5949 VMovVT, false, VMOVModImm);
5950 if (NewVal != SDValue()) {
5952 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
5955 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5957 // It's a float: cast and extract a vector element.
5958 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5960 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5961 DAG.getConstant(0, DL, MVT::i32));
5964 // Finally, try a VMVN.i32
5965 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
5967 if (NewVal != SDValue()) {
5969 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
5972 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5974 // It's a float: cast and extract a vector element.
5975 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5977 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5978 DAG.getConstant(0, DL, MVT::i32));
5984 // check if an VEXT instruction can handle the shuffle mask when the
5985 // vector sources of the shuffle are the same.
5986 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
5987 unsigned NumElts = VT.getVectorNumElements();
5989 // Assume that the first shuffle index is not UNDEF. Fail if it is.
5995 // If this is a VEXT shuffle, the immediate value is the index of the first
5996 // element. The other shuffle indices must be the successive elements after
5998 unsigned ExpectedElt = Imm;
5999 for (unsigned i = 1; i < NumElts; ++i) {
6000 // Increment the expected index. If it wraps around, just follow it
6001 // back to index zero and keep going.
6003 if (ExpectedElt == NumElts)
6006 if (M[i] < 0) continue; // ignore UNDEF indices
6007 if (ExpectedElt != static_cast<unsigned>(M[i]))
6014 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
6015 bool &ReverseVEXT, unsigned &Imm) {
6016 unsigned NumElts = VT.getVectorNumElements();
6017 ReverseVEXT = false;
6019 // Assume that the first shuffle index is not UNDEF. Fail if it is.
6025 // If this is a VEXT shuffle, the immediate value is the index of the first
6026 // element. The other shuffle indices must be the successive elements after
6028 unsigned ExpectedElt = Imm;
6029 for (unsigned i = 1; i < NumElts; ++i) {
6030 // Increment the expected index. If it wraps around, it may still be
6031 // a VEXT but the source vectors must be swapped.
6033 if (ExpectedElt == NumElts * 2) {
6038 if (M[i] < 0) continue; // ignore UNDEF indices
6039 if (ExpectedElt != static_cast<unsigned>(M[i]))
6043 // Adjust the index value if the source operands will be swapped.
6050 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
6051 /// instruction with the specified blocksize. (The order of the elements
6052 /// within each block of the vector is reversed.)
6053 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
6054 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
6055 "Only possible block sizes for VREV are: 16, 32, 64");
6057 unsigned EltSz = VT.getScalarSizeInBits();
6061 unsigned NumElts = VT.getVectorNumElements();
6062 unsigned BlockElts = M[0] + 1;
6063 // If the first shuffle index is UNDEF, be optimistic.
6065 BlockElts = BlockSize / EltSz;
6067 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
6070 for (unsigned i = 0; i < NumElts; ++i) {
6071 if (M[i] < 0) continue; // ignore UNDEF indices
6072 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
6079 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
6080 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
6081 // range, then 0 is placed into the resulting vector. So pretty much any mask
6082 // of 8 elements can work here.
6083 return VT == MVT::v8i8 && M.size() == 8;
6086 static unsigned SelectPairHalf(unsigned Elements, ArrayRef<int> Mask,
6088 if (Mask.size() == Elements * 2)
6089 return Index / Elements;
6090 return Mask[Index] == 0 ? 0 : 1;
6093 // Checks whether the shuffle mask represents a vector transpose (VTRN) by
6094 // checking that pairs of elements in the shuffle mask represent the same index
6095 // in each vector, incrementing the expected index by 2 at each step.
6096 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6]
6097 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,c,g}
6099 // WhichResult gives the offset for each element in the mask based on which
6100 // of the two results it belongs to.
6102 // The transpose can be represented either as:
6103 // result1 = shufflevector v1, v2, result1_shuffle_mask
6104 // result2 = shufflevector v1, v2, result2_shuffle_mask
6105 // where v1/v2 and the shuffle masks have the same number of elements
6106 // (here WhichResult (see below) indicates which result is being checked)
6109 // results = shufflevector v1, v2, shuffle_mask
6110 // where both results are returned in one vector and the shuffle mask has twice
6111 // as many elements as v1/v2 (here WhichResult will always be 0 if true) here we
6112 // want to check the low half and high half of the shuffle mask as if it were
6114 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
6115 unsigned EltSz = VT.getScalarSizeInBits();
6119 unsigned NumElts = VT.getVectorNumElements();
6120 if (M.size() != NumElts && M.size() != NumElts*2)
6123 // If the mask is twice as long as the input vector then we need to check the
6124 // upper and lower parts of the mask with a matching value for WhichResult
6125 // FIXME: A mask with only even values will be rejected in case the first
6126 // element is undefined, e.g. [-1, 4, 2, 6] will be rejected, because only
6127 // M[0] is used to determine WhichResult
6128 for (unsigned i = 0; i < M.size(); i += NumElts) {
6129 WhichResult = SelectPairHalf(NumElts, M, i);
6130 for (unsigned j = 0; j < NumElts; j += 2) {
6131 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
6132 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + NumElts + WhichResult))
6137 if (M.size() == NumElts*2)
6143 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
6144 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
6145 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
6146 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
6147 unsigned EltSz = VT.getScalarSizeInBits();
6151 unsigned NumElts = VT.getVectorNumElements();
6152 if (M.size() != NumElts && M.size() != NumElts*2)
6155 for (unsigned i = 0; i < M.size(); i += NumElts) {
6156 WhichResult = SelectPairHalf(NumElts, M, i);
6157 for (unsigned j = 0; j < NumElts; j += 2) {
6158 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
6159 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + WhichResult))
6164 if (M.size() == NumElts*2)
6170 // Checks whether the shuffle mask represents a vector unzip (VUZP) by checking
6171 // that the mask elements are either all even and in steps of size 2 or all odd
6172 // and in steps of size 2.
6173 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6]
6174 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,c,e,g}
6176 // Requires similar checks to that of isVTRNMask with
6177 // respect the how results are returned.
6178 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
6179 unsigned EltSz = VT.getScalarSizeInBits();
6183 unsigned NumElts = VT.getVectorNumElements();
6184 if (M.size() != NumElts && M.size() != NumElts*2)
6187 for (unsigned i = 0; i < M.size(); i += NumElts) {
6188 WhichResult = SelectPairHalf(NumElts, M, i);
6189 for (unsigned j = 0; j < NumElts; ++j) {
6190 if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult)
6195 if (M.size() == NumElts*2)
6198 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
6199 if (VT.is64BitVector() && EltSz == 32)
6205 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
6206 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
6207 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
6208 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
6209 unsigned EltSz = VT.getScalarSizeInBits();
6213 unsigned NumElts = VT.getVectorNumElements();
6214 if (M.size() != NumElts && M.size() != NumElts*2)
6217 unsigned Half = NumElts / 2;
6218 for (unsigned i = 0; i < M.size(); i += NumElts) {
6219 WhichResult = SelectPairHalf(NumElts, M, i);
6220 for (unsigned j = 0; j < NumElts; j += Half) {
6221 unsigned Idx = WhichResult;
6222 for (unsigned k = 0; k < Half; ++k) {
6223 int MIdx = M[i + j + k];
6224 if (MIdx >= 0 && (unsigned) MIdx != Idx)
6231 if (M.size() == NumElts*2)
6234 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
6235 if (VT.is64BitVector() && EltSz == 32)
6241 // Checks whether the shuffle mask represents a vector zip (VZIP) by checking
6242 // that pairs of elements of the shufflemask represent the same index in each
6243 // vector incrementing sequentially through the vectors.
6244 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
6245 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f}
6247 // Requires similar checks to that of isVTRNMask with respect the how results
6249 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
6250 unsigned EltSz = VT.getScalarSizeInBits();
6254 unsigned NumElts = VT.getVectorNumElements();
6255 if (M.size() != NumElts && M.size() != NumElts*2)
6258 for (unsigned i = 0; i < M.size(); i += NumElts) {
6259 WhichResult = SelectPairHalf(NumElts, M, i);
6260 unsigned Idx = WhichResult * NumElts / 2;
6261 for (unsigned j = 0; j < NumElts; j += 2) {
6262 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
6263 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx + NumElts))
6269 if (M.size() == NumElts*2)
6272 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
6273 if (VT.is64BitVector() && EltSz == 32)
6279 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
6280 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
6281 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
6282 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
6283 unsigned EltSz = VT.getScalarSizeInBits();
6287 unsigned NumElts = VT.getVectorNumElements();
6288 if (M.size() != NumElts && M.size() != NumElts*2)
6291 for (unsigned i = 0; i < M.size(); i += NumElts) {
6292 WhichResult = SelectPairHalf(NumElts, M, i);
6293 unsigned Idx = WhichResult * NumElts / 2;
6294 for (unsigned j = 0; j < NumElts; j += 2) {
6295 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
6296 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx))
6302 if (M.size() == NumElts*2)
6305 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
6306 if (VT.is64BitVector() && EltSz == 32)
6312 /// Check if \p ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN),
6313 /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
6314 static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT,
6315 unsigned &WhichResult,
6318 if (isVTRNMask(ShuffleMask, VT, WhichResult))
6319 return ARMISD::VTRN;
6320 if (isVUZPMask(ShuffleMask, VT, WhichResult))
6321 return ARMISD::VUZP;
6322 if (isVZIPMask(ShuffleMask, VT, WhichResult))
6323 return ARMISD::VZIP;
6326 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
6327 return ARMISD::VTRN;
6328 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
6329 return ARMISD::VUZP;
6330 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
6331 return ARMISD::VZIP;
6336 /// \return true if this is a reverse operation on an vector.
6337 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
6338 unsigned NumElts = VT.getVectorNumElements();
6339 // Make sure the mask has the right size.
6340 if (NumElts != M.size())
6343 // Look for <15, ..., 3, -1, 1, 0>.
6344 for (unsigned i = 0; i != NumElts; ++i)
6345 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
6351 // If N is an integer constant that can be moved into a register in one
6352 // instruction, return an SDValue of such a constant (will become a MOV
6353 // instruction). Otherwise return null.
6354 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
6355 const ARMSubtarget *ST, const SDLoc &dl) {
6357 if (!isa<ConstantSDNode>(N))
6359 Val = cast<ConstantSDNode>(N)->getZExtValue();
6361 if (ST->isThumb1Only()) {
6362 if (Val <= 255 || ~Val <= 255)
6363 return DAG.getConstant(Val, dl, MVT::i32);
6365 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
6366 return DAG.getConstant(Val, dl, MVT::i32);
6371 // If this is a case we can't handle, return null and let the default
6372 // expansion code take care of it.
6373 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
6374 const ARMSubtarget *ST) const {
6375 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
6377 EVT VT = Op.getValueType();
6379 APInt SplatBits, SplatUndef;
6380 unsigned SplatBitSize;
6382 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6383 if (SplatUndef.isAllOnesValue())
6384 return DAG.getUNDEF(VT);
6386 if (SplatBitSize <= 64) {
6387 // Check if an immediate VMOV works.
6389 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
6390 SplatUndef.getZExtValue(), SplatBitSize,
6391 DAG, dl, VmovVT, VT.is128BitVector(),
6393 if (Val.getNode()) {
6394 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
6395 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
6398 // Try an immediate VMVN.
6399 uint64_t NegatedImm = (~SplatBits).getZExtValue();
6400 Val = isNEONModifiedImm(NegatedImm,
6401 SplatUndef.getZExtValue(), SplatBitSize,
6402 DAG, dl, VmovVT, VT.is128BitVector(),
6404 if (Val.getNode()) {
6405 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
6406 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
6409 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
6410 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
6411 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
6413 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32);
6414 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
6420 // Scan through the operands to see if only one value is used.
6422 // As an optimisation, even if more than one value is used it may be more
6423 // profitable to splat with one value then change some lanes.
6425 // Heuristically we decide to do this if the vector has a "dominant" value,
6426 // defined as splatted to more than half of the lanes.
6427 unsigned NumElts = VT.getVectorNumElements();
6428 bool isOnlyLowElement = true;
6429 bool usesOnlyOneValue = true;
6430 bool hasDominantValue = false;
6431 bool isConstant = true;
6433 // Map of the number of times a particular SDValue appears in the
6435 DenseMap<SDValue, unsigned> ValueCounts;
6437 for (unsigned i = 0; i < NumElts; ++i) {
6438 SDValue V = Op.getOperand(i);
6442 isOnlyLowElement = false;
6443 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
6446 ValueCounts.insert(std::make_pair(V, 0));
6447 unsigned &Count = ValueCounts[V];
6449 // Is this value dominant? (takes up more than half of the lanes)
6450 if (++Count > (NumElts / 2)) {
6451 hasDominantValue = true;
6455 if (ValueCounts.size() != 1)
6456 usesOnlyOneValue = false;
6457 if (!Value.getNode() && !ValueCounts.empty())
6458 Value = ValueCounts.begin()->first;
6460 if (ValueCounts.empty())
6461 return DAG.getUNDEF(VT);
6463 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
6464 // Keep going if we are hitting this case.
6465 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
6466 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6468 unsigned EltSize = VT.getScalarSizeInBits();
6470 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
6471 // i32 and try again.
6472 if (hasDominantValue && EltSize <= 32) {
6476 // If we are VDUPing a value that comes directly from a vector, that will
6477 // cause an unnecessary move to and from a GPR, where instead we could
6478 // just use VDUPLANE. We can only do this if the lane being extracted
6479 // is at a constant index, as the VDUP from lane instructions only have
6480 // constant-index forms.
6481 ConstantSDNode *constIndex;
6482 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6483 (constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1)))) {
6484 // We need to create a new undef vector to use for the VDUPLANE if the
6485 // size of the vector from which we get the value is different than the
6486 // size of the vector that we need to create. We will insert the element
6487 // such that the register coalescer will remove unnecessary copies.
6488 if (VT != Value->getOperand(0).getValueType()) {
6489 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
6490 VT.getVectorNumElements();
6491 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
6492 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
6493 Value, DAG.getConstant(index, dl, MVT::i32)),
6494 DAG.getConstant(index, dl, MVT::i32));
6496 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
6497 Value->getOperand(0), Value->getOperand(1));
6499 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
6501 if (!usesOnlyOneValue) {
6502 // The dominant value was splatted as 'N', but we now have to insert
6503 // all differing elements.
6504 for (unsigned I = 0; I < NumElts; ++I) {
6505 if (Op.getOperand(I) == Value)
6507 SmallVector<SDValue, 3> Ops;
6509 Ops.push_back(Op.getOperand(I));
6510 Ops.push_back(DAG.getConstant(I, dl, MVT::i32));
6511 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
6516 if (VT.getVectorElementType().isFloatingPoint()) {
6517 SmallVector<SDValue, 8> Ops;
6518 for (unsigned i = 0; i < NumElts; ++i)
6519 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
6521 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
6522 SDValue Val = DAG.getBuildVector(VecVT, dl, Ops);
6523 Val = LowerBUILD_VECTOR(Val, DAG, ST);
6525 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6527 if (usesOnlyOneValue) {
6528 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
6529 if (isConstant && Val.getNode())
6530 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
6534 // If all elements are constants and the case above didn't get hit, fall back
6535 // to the default expansion, which will generate a load from the constant
6540 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6542 SDValue shuffle = ReconstructShuffle(Op, DAG);
6543 if (shuffle != SDValue())
6547 if (VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) {
6548 // If we haven't found an efficient lowering, try splitting a 128-bit vector
6549 // into two 64-bit vectors; we might discover a better way to lower it.
6550 SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElts);
6551 EVT ExtVT = VT.getVectorElementType();
6552 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElts / 2);
6554 DAG.getBuildVector(HVT, dl, makeArrayRef(&Ops[0], NumElts / 2));
6555 if (Lower.getOpcode() == ISD::BUILD_VECTOR)
6556 Lower = LowerBUILD_VECTOR(Lower, DAG, ST);
6557 SDValue Upper = DAG.getBuildVector(
6558 HVT, dl, makeArrayRef(&Ops[NumElts / 2], NumElts / 2));
6559 if (Upper.getOpcode() == ISD::BUILD_VECTOR)
6560 Upper = LowerBUILD_VECTOR(Upper, DAG, ST);
6562 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper);
6565 // Vectors with 32- or 64-bit elements can be built by directly assigning
6566 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
6567 // will be legalized.
6568 if (EltSize >= 32) {
6569 // Do the expansion with floating-point types, since that is what the VFP
6570 // registers are defined to use, and since i64 is not legal.
6571 EVT EltVT = EVT::getFloatingPointVT(EltSize);
6572 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
6573 SmallVector<SDValue, 8> Ops;
6574 for (unsigned i = 0; i < NumElts; ++i)
6575 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
6576 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
6577 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6580 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6581 // know the default expansion would otherwise fall back on something even
6582 // worse. For a vector with one or two non-undef values, that's
6583 // scalar_to_vector for the elements followed by a shuffle (provided the
6584 // shuffle is valid for the target) and materialization element by element
6585 // on the stack followed by a load for everything else.
6586 if (!isConstant && !usesOnlyOneValue) {
6587 SDValue Vec = DAG.getUNDEF(VT);
6588 for (unsigned i = 0 ; i < NumElts; ++i) {
6589 SDValue V = Op.getOperand(i);
6592 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32);
6593 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6601 // Gather data to see if the operation can be modelled as a
6602 // shuffle in combination with VEXTs.
6603 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
6604 SelectionDAG &DAG) const {
6605 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
6607 EVT VT = Op.getValueType();
6608 unsigned NumElts = VT.getVectorNumElements();
6610 struct ShuffleSourceInfo {
6612 unsigned MinElt = std::numeric_limits<unsigned>::max();
6613 unsigned MaxElt = 0;
6615 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
6616 // be compatible with the shuffle we intend to construct. As a result
6617 // ShuffleVec will be some sliding window into the original Vec.
6620 // Code should guarantee that element i in Vec starts at element "WindowBase
6621 // + i * WindowScale in ShuffleVec".
6623 int WindowScale = 1;
6625 ShuffleSourceInfo(SDValue Vec) : Vec(Vec), ShuffleVec(Vec) {}
6627 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
6630 // First gather all vectors used as an immediate source for this BUILD_VECTOR
6632 SmallVector<ShuffleSourceInfo, 2> Sources;
6633 for (unsigned i = 0; i < NumElts; ++i) {
6634 SDValue V = Op.getOperand(i);
6637 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
6638 // A shuffle can only come from building a vector from various
6639 // elements of other vectors.
6641 } else if (!isa<ConstantSDNode>(V.getOperand(1))) {
6642 // Furthermore, shuffles require a constant mask, whereas extractelts
6643 // accept variable indices.
6647 // Add this element source to the list if it's not already there.
6648 SDValue SourceVec = V.getOperand(0);
6649 auto Source = llvm::find(Sources, SourceVec);
6650 if (Source == Sources.end())
6651 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
6653 // Update the minimum and maximum lane number seen.
6654 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
6655 Source->MinElt = std::min(Source->MinElt, EltNo);
6656 Source->MaxElt = std::max(Source->MaxElt, EltNo);
6659 // Currently only do something sane when at most two source vectors
6661 if (Sources.size() > 2)
6664 // Find out the smallest element size among result and two sources, and use
6665 // it as element size to build the shuffle_vector.
6666 EVT SmallestEltTy = VT.getVectorElementType();
6667 for (auto &Source : Sources) {
6668 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
6669 if (SrcEltTy.bitsLT(SmallestEltTy))
6670 SmallestEltTy = SrcEltTy;
6672 unsigned ResMultiplier =
6673 VT.getScalarSizeInBits() / SmallestEltTy.getSizeInBits();
6674 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
6675 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
6677 // If the source vector is too wide or too narrow, we may nevertheless be able
6678 // to construct a compatible shuffle either by concatenating it with UNDEF or
6679 // extracting a suitable range of elements.
6680 for (auto &Src : Sources) {
6681 EVT SrcVT = Src.ShuffleVec.getValueType();
6683 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
6686 // This stage of the search produces a source with the same element type as
6687 // the original, but with a total width matching the BUILD_VECTOR output.
6688 EVT EltVT = SrcVT.getVectorElementType();
6689 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
6690 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
6692 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
6693 if (2 * SrcVT.getSizeInBits() != VT.getSizeInBits())
6695 // We can pad out the smaller vector for free, so if it's part of a
6698 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
6699 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
6703 if (SrcVT.getSizeInBits() != 2 * VT.getSizeInBits())
6706 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
6707 // Span too large for a VEXT to cope
6711 if (Src.MinElt >= NumSrcElts) {
6712 // The extraction can just take the second half
6714 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
6715 DAG.getConstant(NumSrcElts, dl, MVT::i32));
6716 Src.WindowBase = -NumSrcElts;
6717 } else if (Src.MaxElt < NumSrcElts) {
6718 // The extraction can just take the first half
6720 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
6721 DAG.getConstant(0, dl, MVT::i32));
6723 // An actual VEXT is needed
6725 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
6726 DAG.getConstant(0, dl, MVT::i32));
6728 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
6729 DAG.getConstant(NumSrcElts, dl, MVT::i32));
6731 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
6733 DAG.getConstant(Src.MinElt, dl, MVT::i32));
6734 Src.WindowBase = -Src.MinElt;
6738 // Another possible incompatibility occurs from the vector element types. We
6739 // can fix this by bitcasting the source vectors to the same type we intend
6741 for (auto &Src : Sources) {
6742 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
6743 if (SrcEltTy == SmallestEltTy)
6745 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
6746 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
6747 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
6748 Src.WindowBase *= Src.WindowScale;
6751 // Final sanity check before we try to actually produce a shuffle.
6752 LLVM_DEBUG(for (auto Src
6754 assert(Src.ShuffleVec.getValueType() == ShuffleVT););
6756 // The stars all align, our next step is to produce the mask for the shuffle.
6757 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
6758 int BitsPerShuffleLane = ShuffleVT.getScalarSizeInBits();
6759 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
6760 SDValue Entry = Op.getOperand(i);
6761 if (Entry.isUndef())
6764 auto Src = llvm::find(Sources, Entry.getOperand(0));
6765 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
6767 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
6768 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
6770 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
6771 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
6772 VT.getScalarSizeInBits());
6773 int LanesDefined = BitsDefined / BitsPerShuffleLane;
6775 // This source is expected to fill ResMultiplier lanes of the final shuffle,
6776 // starting at the appropriate offset.
6777 int *LaneMask = &Mask[i * ResMultiplier];
6779 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
6780 ExtractBase += NumElts * (Src - Sources.begin());
6781 for (int j = 0; j < LanesDefined; ++j)
6782 LaneMask[j] = ExtractBase + j;
6785 // Final check before we try to produce nonsense...
6786 if (!isShuffleMaskLegal(Mask, ShuffleVT))
6789 // We can't handle more than two sources. This should have already
6790 // been checked before this point.
6791 assert(Sources.size() <= 2 && "Too many sources!");
6793 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
6794 for (unsigned i = 0; i < Sources.size(); ++i)
6795 ShuffleOps[i] = Sources[i].ShuffleVec;
6797 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
6798 ShuffleOps[1], Mask);
6799 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
6802 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6803 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6804 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6805 /// are assumed to be legal.
6806 bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
6807 if (VT.getVectorNumElements() == 4 &&
6808 (VT.is128BitVector() || VT.is64BitVector())) {
6809 unsigned PFIndexes[4];
6810 for (unsigned i = 0; i != 4; ++i) {
6814 PFIndexes[i] = M[i];
6817 // Compute the index in the perfect shuffle table.
6818 unsigned PFTableIndex =
6819 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6820 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6821 unsigned Cost = (PFEntry >> 30);
6827 bool ReverseVEXT, isV_UNDEF;
6828 unsigned Imm, WhichResult;
6830 unsigned EltSize = VT.getScalarSizeInBits();
6831 return (EltSize >= 32 ||
6832 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
6833 isVREVMask(M, VT, 64) ||
6834 isVREVMask(M, VT, 32) ||
6835 isVREVMask(M, VT, 16) ||
6836 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
6837 isVTBLMask(M, VT) ||
6838 isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF) ||
6839 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
6842 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6843 /// the specified operations to build the shuffle.
6844 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6845 SDValue RHS, SelectionDAG &DAG,
6847 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6848 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6849 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6852 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6861 OP_VUZPL, // VUZP, left result
6862 OP_VUZPR, // VUZP, right result
6863 OP_VZIPL, // VZIP, left result
6864 OP_VZIPR, // VZIP, right result
6865 OP_VTRNL, // VTRN, left result
6866 OP_VTRNR // VTRN, right result
6869 if (OpNum == OP_COPY) {
6870 if (LHSID == (1*9+2)*9+3) return LHS;
6871 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6875 SDValue OpLHS, OpRHS;
6876 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6877 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6878 EVT VT = OpLHS.getValueType();
6881 default: llvm_unreachable("Unknown shuffle opcode!");
6883 // VREV divides the vector in half and swaps within the half.
6884 if (VT.getVectorElementType() == MVT::i32 ||
6885 VT.getVectorElementType() == MVT::f32)
6886 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
6887 // vrev <4 x i16> -> VREV32
6888 if (VT.getVectorElementType() == MVT::i16)
6889 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
6890 // vrev <4 x i8> -> VREV16
6891 assert(VT.getVectorElementType() == MVT::i8);
6892 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
6897 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
6898 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
6902 return DAG.getNode(ARMISD::VEXT, dl, VT,
6904 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
6907 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
6908 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
6911 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
6912 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
6915 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
6916 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
6920 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
6921 ArrayRef<int> ShuffleMask,
6922 SelectionDAG &DAG) {
6923 // Check to see if we can use the VTBL instruction.
6924 SDValue V1 = Op.getOperand(0);
6925 SDValue V2 = Op.getOperand(1);
6928 SmallVector<SDValue, 8> VTBLMask;
6929 for (ArrayRef<int>::iterator
6930 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
6931 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
6933 if (V2.getNode()->isUndef())
6934 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
6935 DAG.getBuildVector(MVT::v8i8, DL, VTBLMask));
6937 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
6938 DAG.getBuildVector(MVT::v8i8, DL, VTBLMask));
6941 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
6942 SelectionDAG &DAG) {
6944 SDValue OpLHS = Op.getOperand(0);
6945 EVT VT = OpLHS.getValueType();
6947 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
6948 "Expect an v8i16/v16i8 type");
6949 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
6950 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
6951 // extract the first 8 bytes into the top double word and the last 8 bytes
6952 // into the bottom double word. The v8i16 case is similar.
6953 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
6954 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
6955 DAG.getConstant(ExtractNum, DL, MVT::i32));
6958 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
6959 SDValue V1 = Op.getOperand(0);
6960 SDValue V2 = Op.getOperand(1);
6962 EVT VT = Op.getValueType();
6963 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
6965 // Convert shuffles that are directly supported on NEON to target-specific
6966 // DAG nodes, instead of keeping them as shuffles and matching them again
6967 // during code selection. This is more efficient and avoids the possibility
6968 // of inconsistencies between legalization and selection.
6969 // FIXME: floating-point vectors should be canonicalized to integer vectors
6970 // of the same time so that they get CSEd properly.
6971 ArrayRef<int> ShuffleMask = SVN->getMask();
6973 unsigned EltSize = VT.getScalarSizeInBits();
6974 if (EltSize <= 32) {
6975 if (SVN->isSplat()) {
6976 int Lane = SVN->getSplatIndex();
6977 // If this is undef splat, generate it via "just" vdup, if possible.
6978 if (Lane == -1) Lane = 0;
6980 // Test if V1 is a SCALAR_TO_VECTOR.
6981 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6982 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
6984 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
6985 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
6987 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
6988 !isa<ConstantSDNode>(V1.getOperand(0))) {
6989 bool IsScalarToVector = true;
6990 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
6991 if (!V1.getOperand(i).isUndef()) {
6992 IsScalarToVector = false;
6995 if (IsScalarToVector)
6996 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
6998 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
6999 DAG.getConstant(Lane, dl, MVT::i32));
7004 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
7007 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
7008 DAG.getConstant(Imm, dl, MVT::i32));
7011 if (isVREVMask(ShuffleMask, VT, 64))
7012 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
7013 if (isVREVMask(ShuffleMask, VT, 32))
7014 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
7015 if (isVREVMask(ShuffleMask, VT, 16))
7016 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
7018 if (V2->isUndef() && isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
7019 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
7020 DAG.getConstant(Imm, dl, MVT::i32));
7023 // Check for Neon shuffles that modify both input vectors in place.
7024 // If both results are used, i.e., if there are two shuffles with the same
7025 // source operands and with masks corresponding to both results of one of
7026 // these operations, DAG memoization will ensure that a single node is
7027 // used for both shuffles.
7028 unsigned WhichResult;
7030 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
7031 ShuffleMask, VT, WhichResult, isV_UNDEF)) {
7034 return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2)
7035 .getValue(WhichResult);
7038 // Also check for these shuffles through CONCAT_VECTORS: we canonicalize
7039 // shuffles that produce a result larger than their operands with:
7040 // shuffle(concat(v1, undef), concat(v2, undef))
7042 // shuffle(concat(v1, v2), undef)
7043 // because we can access quad vectors (see PerformVECTOR_SHUFFLECombine).
7045 // This is useful in the general case, but there are special cases where
7046 // native shuffles produce larger results: the two-result ops.
7048 // Look through the concat when lowering them:
7049 // shuffle(concat(v1, v2), undef)
7051 // concat(VZIP(v1, v2):0, :1)
7053 if (V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
7054 SDValue SubV1 = V1->getOperand(0);
7055 SDValue SubV2 = V1->getOperand(1);
7056 EVT SubVT = SubV1.getValueType();
7058 // We expect these to have been canonicalized to -1.
7059 assert(llvm::all_of(ShuffleMask, [&](int i) {
7060 return i < (int)VT.getVectorNumElements();
7061 }) && "Unexpected shuffle index into UNDEF operand!");
7063 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
7064 ShuffleMask, SubVT, WhichResult, isV_UNDEF)) {
7067 assert((WhichResult == 0) &&
7068 "In-place shuffle of concat can only have one result!");
7069 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
7071 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
7077 // If the shuffle is not directly supported and it has 4 elements, use
7078 // the PerfectShuffle-generated table to synthesize it from other shuffles.
7079 unsigned NumElts = VT.getVectorNumElements();
7081 unsigned PFIndexes[4];
7082 for (unsigned i = 0; i != 4; ++i) {
7083 if (ShuffleMask[i] < 0)
7086 PFIndexes[i] = ShuffleMask[i];
7089 // Compute the index in the perfect shuffle table.
7090 unsigned PFTableIndex =
7091 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7092 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7093 unsigned Cost = (PFEntry >> 30);
7096 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7099 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
7100 if (EltSize >= 32) {
7101 // Do the expansion with floating-point types, since that is what the VFP
7102 // registers are defined to use, and since i64 is not legal.
7103 EVT EltVT = EVT::getFloatingPointVT(EltSize);
7104 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
7105 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
7106 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
7107 SmallVector<SDValue, 8> Ops;
7108 for (unsigned i = 0; i < NumElts; ++i) {
7109 if (ShuffleMask[i] < 0)
7110 Ops.push_back(DAG.getUNDEF(EltVT));
7112 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
7113 ShuffleMask[i] < (int)NumElts ? V1 : V2,
7114 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
7117 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
7118 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
7121 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
7122 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
7124 if (VT == MVT::v8i8)
7125 if (SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG))
7131 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
7132 // INSERT_VECTOR_ELT is legal only for immediate indexes.
7133 SDValue Lane = Op.getOperand(2);
7134 if (!isa<ConstantSDNode>(Lane))
7140 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
7141 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
7142 SDValue Lane = Op.getOperand(1);
7143 if (!isa<ConstantSDNode>(Lane))
7146 SDValue Vec = Op.getOperand(0);
7147 if (Op.getValueType() == MVT::i32 && Vec.getScalarValueSizeInBits() < 32) {
7149 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
7155 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7156 // The only time a CONCAT_VECTORS operation can have legal types is when
7157 // two 64-bit vectors are concatenated to a 128-bit vector.
7158 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
7159 "unexpected CONCAT_VECTORS");
7161 SDValue Val = DAG.getUNDEF(MVT::v2f64);
7162 SDValue Op0 = Op.getOperand(0);
7163 SDValue Op1 = Op.getOperand(1);
7165 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
7166 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
7167 DAG.getIntPtrConstant(0, dl));
7169 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
7170 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
7171 DAG.getIntPtrConstant(1, dl));
7172 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
7175 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
7176 /// element has been zero/sign-extended, depending on the isSigned parameter,
7177 /// from an integer type half its size.
7178 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
7180 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
7181 EVT VT = N->getValueType(0);
7182 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
7183 SDNode *BVN = N->getOperand(0).getNode();
7184 if (BVN->getValueType(0) != MVT::v4i32 ||
7185 BVN->getOpcode() != ISD::BUILD_VECTOR)
7187 unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
7188 unsigned HiElt = 1 - LoElt;
7189 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
7190 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
7191 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
7192 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
7193 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
7196 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
7197 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
7200 if (Hi0->isNullValue() && Hi1->isNullValue())
7206 if (N->getOpcode() != ISD::BUILD_VECTOR)
7209 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
7210 SDNode *Elt = N->getOperand(i).getNode();
7211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
7212 unsigned EltSize = VT.getScalarSizeInBits();
7213 unsigned HalfSize = EltSize / 2;
7215 if (!isIntN(HalfSize, C->getSExtValue()))
7218 if (!isUIntN(HalfSize, C->getZExtValue()))
7229 /// isSignExtended - Check if a node is a vector value that is sign-extended
7230 /// or a constant BUILD_VECTOR with sign-extended elements.
7231 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
7232 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
7234 if (isExtendedBUILD_VECTOR(N, DAG, true))
7239 /// isZeroExtended - Check if a node is a vector value that is zero-extended
7240 /// or a constant BUILD_VECTOR with zero-extended elements.
7241 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
7242 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
7244 if (isExtendedBUILD_VECTOR(N, DAG, false))
7249 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
7250 if (OrigVT.getSizeInBits() >= 64)
7253 assert(OrigVT.isSimple() && "Expecting a simple value type");
7255 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
7256 switch (OrigSimpleTy) {
7257 default: llvm_unreachable("Unexpected Vector Type");
7266 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
7267 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
7268 /// We insert the required extension here to get the vector to fill a D register.
7269 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
7272 unsigned ExtOpcode) {
7273 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
7274 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
7275 // 64-bits we need to insert a new extension so that it will be 64-bits.
7276 assert(ExtTy.is128BitVector() && "Unexpected extension size");
7277 if (OrigTy.getSizeInBits() >= 64)
7280 // Must extend size to at least 64 bits to be used as an operand for VMULL.
7281 EVT NewVT = getExtensionTo64Bits(OrigTy);
7283 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
7286 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
7287 /// does not do any sign/zero extension. If the original vector is less
7288 /// than 64 bits, an appropriate extension will be added after the load to
7289 /// reach a total size of 64 bits. We have to add the extension separately
7290 /// because ARM does not have a sign/zero extending load for vectors.
7291 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
7292 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
7294 // The load already has the right type.
7295 if (ExtendedTy == LD->getMemoryVT())
7296 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
7297 LD->getBasePtr(), LD->getPointerInfo(),
7298 LD->getAlignment(), LD->getMemOperand()->getFlags());
7300 // We need to create a zextload/sextload. We cannot just create a load
7301 // followed by a zext/zext node because LowerMUL is also run during normal
7302 // operation legalization where we can't create illegal types.
7303 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
7304 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
7305 LD->getMemoryVT(), LD->getAlignment(),
7306 LD->getMemOperand()->getFlags());
7309 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
7310 /// extending load, or BUILD_VECTOR with extended elements, return the
7311 /// unextended value. The unextended vector should be 64 bits so that it can
7312 /// be used as an operand to a VMULL instruction. If the original vector size
7313 /// before extension is less than 64 bits we add a an extension to resize
7314 /// the vector to 64 bits.
7315 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
7316 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
7317 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
7318 N->getOperand(0)->getValueType(0),
7322 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7323 assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) &&
7324 "Expected extending load");
7326 SDValue newLoad = SkipLoadExtensionForVMULL(LD, DAG);
7327 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), newLoad.getValue(1));
7328 unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
7330 DAG.getNode(Opcode, SDLoc(newLoad), LD->getValueType(0), newLoad);
7331 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 0), extLoad);
7336 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
7337 // have been legalized as a BITCAST from v4i32.
7338 if (N->getOpcode() == ISD::BITCAST) {
7339 SDNode *BVN = N->getOperand(0).getNode();
7340 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
7341 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
7342 unsigned LowElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
7343 return DAG.getBuildVector(
7344 MVT::v2i32, SDLoc(N),
7345 {BVN->getOperand(LowElt), BVN->getOperand(LowElt + 2)});
7347 // Construct a new BUILD_VECTOR with elements truncated to half the size.
7348 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
7349 EVT VT = N->getValueType(0);
7350 unsigned EltSize = VT.getScalarSizeInBits() / 2;
7351 unsigned NumElts = VT.getVectorNumElements();
7352 MVT TruncVT = MVT::getIntegerVT(EltSize);
7353 SmallVector<SDValue, 8> Ops;
7355 for (unsigned i = 0; i != NumElts; ++i) {
7356 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
7357 const APInt &CInt = C->getAPIntValue();
7358 // Element types smaller than 32 bits are not legal, so use i32 elements.
7359 // The values are implicitly truncated so sext vs. zext doesn't matter.
7360 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
7362 return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops);
7365 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
7366 unsigned Opcode = N->getOpcode();
7367 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
7368 SDNode *N0 = N->getOperand(0).getNode();
7369 SDNode *N1 = N->getOperand(1).getNode();
7370 return N0->hasOneUse() && N1->hasOneUse() &&
7371 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
7376 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
7377 unsigned Opcode = N->getOpcode();
7378 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
7379 SDNode *N0 = N->getOperand(0).getNode();
7380 SDNode *N1 = N->getOperand(1).getNode();
7381 return N0->hasOneUse() && N1->hasOneUse() &&
7382 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
7387 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
7388 // Multiplications are only custom-lowered for 128-bit vectors so that
7389 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
7390 EVT VT = Op.getValueType();
7391 assert(VT.is128BitVector() && VT.isInteger() &&
7392 "unexpected type for custom-lowering ISD::MUL");
7393 SDNode *N0 = Op.getOperand(0).getNode();
7394 SDNode *N1 = Op.getOperand(1).getNode();
7395 unsigned NewOpc = 0;
7397 bool isN0SExt = isSignExtended(N0, DAG);
7398 bool isN1SExt = isSignExtended(N1, DAG);
7399 if (isN0SExt && isN1SExt)
7400 NewOpc = ARMISD::VMULLs;
7402 bool isN0ZExt = isZeroExtended(N0, DAG);
7403 bool isN1ZExt = isZeroExtended(N1, DAG);
7404 if (isN0ZExt && isN1ZExt)
7405 NewOpc = ARMISD::VMULLu;
7406 else if (isN1SExt || isN1ZExt) {
7407 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
7408 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
7409 if (isN1SExt && isAddSubSExt(N0, DAG)) {
7410 NewOpc = ARMISD::VMULLs;
7412 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
7413 NewOpc = ARMISD::VMULLu;
7415 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
7417 NewOpc = ARMISD::VMULLu;
7423 if (VT == MVT::v2i64)
7424 // Fall through to expand this. It is not legal.
7427 // Other vector multiplications are legal.
7432 // Legalize to a VMULL instruction.
7435 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
7437 Op0 = SkipExtensionForVMULL(N0, DAG);
7438 assert(Op0.getValueType().is64BitVector() &&
7439 Op1.getValueType().is64BitVector() &&
7440 "unexpected types for extended operands to VMULL");
7441 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
7444 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
7445 // isel lowering to take advantage of no-stall back to back vmul + vmla.
7452 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
7453 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
7454 EVT Op1VT = Op1.getValueType();
7455 return DAG.getNode(N0->getOpcode(), DL, VT,
7456 DAG.getNode(NewOpc, DL, VT,
7457 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
7458 DAG.getNode(NewOpc, DL, VT,
7459 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
7462 static SDValue LowerSDIV_v4i8(SDValue X, SDValue Y, const SDLoc &dl,
7463 SelectionDAG &DAG) {
7464 // TODO: Should this propagate fast-math-flags?
7467 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
7468 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
7469 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
7470 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
7471 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
7472 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
7473 // Get reciprocal estimate.
7474 // float4 recip = vrecpeq_f32(yf);
7475 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
7476 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
7478 // Because char has a smaller range than uchar, we can actually get away
7479 // without any newton steps. This requires that we use a weird bias
7480 // of 0xb000, however (again, this has been exhaustively tested).
7481 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
7482 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
7483 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
7484 Y = DAG.getConstant(0xb000, dl, MVT::v4i32);
7485 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
7486 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
7487 // Convert back to short.
7488 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
7489 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
7493 static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl,
7494 SelectionDAG &DAG) {
7495 // TODO: Should this propagate fast-math-flags?
7498 // Convert to float.
7499 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
7500 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
7501 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
7502 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
7503 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
7504 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
7506 // Use reciprocal estimate and one refinement step.
7507 // float4 recip = vrecpeq_f32(yf);
7508 // recip *= vrecpsq_f32(yf, recip);
7509 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
7510 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
7512 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
7513 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
7515 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
7516 // Because short has a smaller range than ushort, we can actually get away
7517 // with only a single newton step. This requires that we use a weird bias
7518 // of 89, however (again, this has been exhaustively tested).
7519 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
7520 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
7521 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
7522 N1 = DAG.getConstant(0x89, dl, MVT::v4i32);
7523 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
7524 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
7525 // Convert back to integer and return.
7526 // return vmovn_s32(vcvt_s32_f32(result));
7527 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
7528 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
7532 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
7533 EVT VT = Op.getValueType();
7534 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
7535 "unexpected type for custom-lowering ISD::SDIV");
7538 SDValue N0 = Op.getOperand(0);
7539 SDValue N1 = Op.getOperand(1);
7542 if (VT == MVT::v8i8) {
7543 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
7544 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
7546 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
7547 DAG.getIntPtrConstant(4, dl));
7548 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
7549 DAG.getIntPtrConstant(4, dl));
7550 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
7551 DAG.getIntPtrConstant(0, dl));
7552 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
7553 DAG.getIntPtrConstant(0, dl));
7555 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
7556 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
7558 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
7559 N0 = LowerCONCAT_VECTORS(N0, DAG);
7561 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
7564 return LowerSDIV_v4i16(N0, N1, dl, DAG);
7567 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
7568 // TODO: Should this propagate fast-math-flags?
7569 EVT VT = Op.getValueType();
7570 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
7571 "unexpected type for custom-lowering ISD::UDIV");
7574 SDValue N0 = Op.getOperand(0);
7575 SDValue N1 = Op.getOperand(1);
7578 if (VT == MVT::v8i8) {
7579 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
7580 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
7582 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
7583 DAG.getIntPtrConstant(4, dl));
7584 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
7585 DAG.getIntPtrConstant(4, dl));
7586 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
7587 DAG.getIntPtrConstant(0, dl));
7588 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
7589 DAG.getIntPtrConstant(0, dl));
7591 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
7592 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
7594 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
7595 N0 = LowerCONCAT_VECTORS(N0, DAG);
7597 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
7598 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl,
7604 // v4i16 sdiv ... Convert to float.
7605 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
7606 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
7607 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
7608 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
7609 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
7610 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
7612 // Use reciprocal estimate and two refinement steps.
7613 // float4 recip = vrecpeq_f32(yf);
7614 // recip *= vrecpsq_f32(yf, recip);
7615 // recip *= vrecpsq_f32(yf, recip);
7616 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
7617 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
7619 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
7620 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
7622 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
7623 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
7624 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
7626 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
7627 // Simply multiplying by the reciprocal estimate can leave us a few ulps
7628 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
7629 // and that it will never cause us to return an answer too large).
7630 // float4 result = as_float4(as_int4(xf*recip) + 2);
7631 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
7632 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
7633 N1 = DAG.getConstant(2, dl, MVT::v4i32);
7634 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
7635 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
7636 // Convert back to integer and return.
7637 // return vmovn_u32(vcvt_s32_f32(result));
7638 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
7639 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
7643 static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
7644 SDNode *N = Op.getNode();
7645 EVT VT = N->getValueType(0);
7646 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
7648 SDValue Carry = Op.getOperand(2);
7653 if (Op.getOpcode() == ISD::ADDCARRY) {
7654 // This converts the boolean value carry into the carry flag.
7655 Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
7657 // Do the addition proper using the carry flag we wanted.
7658 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0),
7659 Op.getOperand(1), Carry);
7661 // Now convert the carry flag into a boolean value.
7662 Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
7664 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
7665 // have to invert the carry first.
7666 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
7667 DAG.getConstant(1, DL, MVT::i32), Carry);
7668 // This converts the boolean value carry into the carry flag.
7669 Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
7671 // Do the subtraction proper using the carry flag we wanted.
7672 Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0),
7673 Op.getOperand(1), Carry);
7675 // Now convert the carry flag into a boolean value.
7676 Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
7677 // But the carry returned by ARMISD::SUBE is not a borrow as expected
7678 // by ISD::SUBCARRY, so compute 1 - C.
7679 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
7680 DAG.getConstant(1, DL, MVT::i32), Carry);
7683 // Return both values.
7684 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry);
7687 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
7688 assert(Subtarget->isTargetDarwin());
7690 // For iOS, we want to call an alternative entry point: __sincos_stret,
7691 // return values are passed via sret.
7693 SDValue Arg = Op.getOperand(0);
7694 EVT ArgVT = Arg.getValueType();
7695 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
7696 auto PtrVT = getPointerTy(DAG.getDataLayout());
7698 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
7699 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7701 // Pair of floats / doubles used to pass the result.
7702 Type *RetTy = StructType::get(ArgTy, ArgTy);
7703 auto &DL = DAG.getDataLayout();
7706 bool ShouldUseSRet = Subtarget->isAPCS_ABI();
7708 if (ShouldUseSRet) {
7709 // Create stack object for sret.
7710 const uint64_t ByteSize = DL.getTypeAllocSize(RetTy);
7711 const unsigned StackAlign = DL.getPrefTypeAlignment(RetTy);
7712 int FrameIdx = MFI.CreateStackObject(ByteSize, StackAlign, false);
7713 SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy(DL));
7717 Entry.Ty = RetTy->getPointerTo();
7718 Entry.IsSExt = false;
7719 Entry.IsZExt = false;
7720 Entry.IsSRet = true;
7721 Args.push_back(Entry);
7722 RetTy = Type::getVoidTy(*DAG.getContext());
7728 Entry.IsSExt = false;
7729 Entry.IsZExt = false;
7730 Args.push_back(Entry);
7733 (ArgVT == MVT::f64) ? RTLIB::SINCOS_STRET_F64 : RTLIB::SINCOS_STRET_F32;
7734 const char *LibcallName = getLibcallName(LC);
7735 CallingConv::ID CC = getLibcallCallingConv(LC);
7736 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy(DL));
7738 TargetLowering::CallLoweringInfo CLI(DAG);
7740 .setChain(DAG.getEntryNode())
7741 .setCallee(CC, RetTy, Callee, std::move(Args))
7742 .setDiscardResult(ShouldUseSRet);
7743 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
7746 return CallResult.first;
7749 DAG.getLoad(ArgVT, dl, CallResult.second, SRet, MachinePointerInfo());
7751 // Address of cos field.
7752 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet,
7753 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl));
7755 DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add, MachinePointerInfo());
7757 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
7758 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
7759 LoadSin.getValue(0), LoadCos.getValue(0));
7762 SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
7764 SDValue &Chain) const {
7765 EVT VT = Op.getValueType();
7766 assert((VT == MVT::i32 || VT == MVT::i64) &&
7767 "unexpected type for custom lowering DIV");
7770 const auto &DL = DAG.getDataLayout();
7771 const auto &TLI = DAG.getTargetLoweringInfo();
7773 const char *Name = nullptr;
7775 Name = (VT == MVT::i32) ? "__rt_sdiv" : "__rt_sdiv64";
7777 Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64";
7779 SDValue ES = DAG.getExternalSymbol(Name, TLI.getPointerTy(DL));
7781 ARMTargetLowering::ArgListTy Args;
7783 for (auto AI : {1, 0}) {
7785 Arg.Node = Op.getOperand(AI);
7786 Arg.Ty = Arg.Node.getValueType().getTypeForEVT(*DAG.getContext());
7787 Args.push_back(Arg);
7790 CallLoweringInfo CLI(DAG);
7793 .setCallee(CallingConv::ARM_AAPCS_VFP, VT.getTypeForEVT(*DAG.getContext()),
7794 ES, std::move(Args));
7796 return LowerCallTo(CLI).first;
7799 // This is a code size optimisation: return the original SDIV node to
7800 // DAGCombiner when we don't want to expand SDIV into a sequence of
7801 // instructions, and an empty node otherwise which will cause the
7802 // SDIV to be expanded in DAGCombine.
7804 ARMTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7806 SmallVectorImpl<SDNode *> &Created) const {
7807 // TODO: Support SREM
7808 if (N->getOpcode() != ISD::SDIV)
7811 const auto &ST = static_cast<const ARMSubtarget&>(DAG.getSubtarget());
7812 const auto &MF = DAG.getMachineFunction();
7813 const bool MinSize = MF.getFunction().optForMinSize();
7814 const bool HasDivide = ST.isThumb() ? ST.hasDivideInThumbMode()
7815 : ST.hasDivideInARMMode();
7817 // Don't touch vector types; rewriting this may lead to scalarizing
7819 if (N->getOperand(0).getValueType().isVector())
7822 // Bail if MinSize is not set, and also for both ARM and Thumb mode we need
7823 // hwdiv support for this to be really profitable.
7824 if (!(MinSize && HasDivide))
7827 // ARM mode is a bit simpler than Thumb: we can handle large power
7828 // of 2 immediates with 1 mov instruction; no further checks required,
7829 // just return the sdiv node.
7831 return SDValue(N, 0);
7833 // In Thumb mode, immediates larger than 128 need a wide 4-byte MOV,
7834 // and thus lose the code size benefits of a MOVS that requires only 2.
7835 // TargetTransformInfo and 'getIntImmCodeSizeCost' could be helpful here,
7836 // but as it's doing exactly this, it's not worth the trouble to get TTI.
7837 if (Divisor.sgt(128))
7840 return SDValue(N, 0);
7843 SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
7844 bool Signed) const {
7845 assert(Op.getValueType() == MVT::i32 &&
7846 "unexpected type for custom lowering DIV");
7849 SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other,
7850 DAG.getEntryNode(), Op.getOperand(1));
7852 return LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
7855 static SDValue WinDBZCheckDenominator(SelectionDAG &DAG, SDNode *N, SDValue InChain) {
7857 SDValue Op = N->getOperand(1);
7858 if (N->getValueType(0) == MVT::i32)
7859 return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain, Op);
7860 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op,
7861 DAG.getConstant(0, DL, MVT::i32));
7862 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op,
7863 DAG.getConstant(1, DL, MVT::i32));
7864 return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain,
7865 DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi));
7868 void ARMTargetLowering::ExpandDIV_Windows(
7869 SDValue Op, SelectionDAG &DAG, bool Signed,
7870 SmallVectorImpl<SDValue> &Results) const {
7871 const auto &DL = DAG.getDataLayout();
7872 const auto &TLI = DAG.getTargetLoweringInfo();
7874 assert(Op.getValueType() == MVT::i64 &&
7875 "unexpected type for custom lowering DIV");
7878 SDValue DBZCHK = WinDBZCheckDenominator(DAG, Op.getNode(), DAG.getEntryNode());
7880 SDValue Result = LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
7882 SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result);
7883 SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result,
7884 DAG.getConstant(32, dl, TLI.getPointerTy(DL)));
7885 Upper = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Upper);
7887 Results.push_back(Lower);
7888 Results.push_back(Upper);
7891 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
7892 if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getOrdering()))
7893 // Acquire/Release load/store is not legal for targets without a dmb or
7894 // equivalent available.
7897 // Monotonic load/store is legal for all targets.
7901 static void ReplaceREADCYCLECOUNTER(SDNode *N,
7902 SmallVectorImpl<SDValue> &Results,
7904 const ARMSubtarget *Subtarget) {
7906 // Under Power Management extensions, the cycle-count is:
7907 // mrc p15, #0, <Rt>, c9, c13, #0
7908 SDValue Ops[] = { N->getOperand(0), // Chain
7909 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
7910 DAG.getConstant(15, DL, MVT::i32),
7911 DAG.getConstant(0, DL, MVT::i32),
7912 DAG.getConstant(9, DL, MVT::i32),
7913 DAG.getConstant(13, DL, MVT::i32),
7914 DAG.getConstant(0, DL, MVT::i32)
7917 SDValue Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
7918 DAG.getVTList(MVT::i32, MVT::Other), Ops);
7919 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32,
7920 DAG.getConstant(0, DL, MVT::i32)));
7921 Results.push_back(Cycles32.getValue(1));
7924 static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) {
7925 SDLoc dl(V.getNode());
7926 SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i32);
7927 SDValue VHi = DAG.getAnyExtOrTrunc(
7928 DAG.getNode(ISD::SRL, dl, MVT::i64, V, DAG.getConstant(32, dl, MVT::i32)),
7930 bool isBigEndian = DAG.getDataLayout().isBigEndian();
7932 std::swap (VLo, VHi);
7934 DAG.getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32);
7935 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32);
7936 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32);
7937 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
7939 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0);
7942 static void ReplaceCMP_SWAP_64Results(SDNode *N,
7943 SmallVectorImpl<SDValue> & Results,
7944 SelectionDAG &DAG) {
7945 assert(N->getValueType(0) == MVT::i64 &&
7946 "AtomicCmpSwap on types less than 64 should be legal");
7947 SDValue Ops[] = {N->getOperand(1),
7948 createGPRPairNode(DAG, N->getOperand(2)),
7949 createGPRPairNode(DAG, N->getOperand(3)),
7951 SDNode *CmpSwap = DAG.getMachineNode(
7952 ARM::CMP_SWAP_64, SDLoc(N),
7953 DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other), Ops);
7955 MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
7956 DAG.setNodeMemRefs(cast<MachineSDNode>(CmpSwap), {MemOp});
7958 bool isBigEndian = DAG.getDataLayout().isBigEndian();
7961 DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_1 : ARM::gsub_0,
7962 SDLoc(N), MVT::i32, SDValue(CmpSwap, 0)));
7964 DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_0 : ARM::gsub_1,
7965 SDLoc(N), MVT::i32, SDValue(CmpSwap, 0)));
7966 Results.push_back(SDValue(CmpSwap, 2));
7969 static SDValue LowerFPOWI(SDValue Op, const ARMSubtarget &Subtarget,
7970 SelectionDAG &DAG) {
7971 const auto &TLI = DAG.getTargetLoweringInfo();
7973 assert(Subtarget.getTargetTriple().isOSMSVCRT() &&
7974 "Custom lowering is MSVCRT specific!");
7977 SDValue Val = Op.getOperand(0);
7978 MVT Ty = Val->getSimpleValueType(0);
7979 SDValue Exponent = DAG.getNode(ISD::SINT_TO_FP, dl, Ty, Op.getOperand(1));
7980 SDValue Callee = DAG.getExternalSymbol(Ty == MVT::f32 ? "powf" : "pow",
7981 TLI.getPointerTy(DAG.getDataLayout()));
7983 TargetLowering::ArgListTy Args;
7984 TargetLowering::ArgListEntry Entry;
7987 Entry.Ty = Val.getValueType().getTypeForEVT(*DAG.getContext());
7988 Entry.IsZExt = true;
7989 Args.push_back(Entry);
7991 Entry.Node = Exponent;
7992 Entry.Ty = Exponent.getValueType().getTypeForEVT(*DAG.getContext());
7993 Entry.IsZExt = true;
7994 Args.push_back(Entry);
7996 Type *LCRTy = Val.getValueType().getTypeForEVT(*DAG.getContext());
7998 // In the in-chain to the call is the entry node If we are emitting a
7999 // tailcall, the chain will be mutated if the node has a non-entry input
8001 SDValue InChain = DAG.getEntryNode();
8002 SDValue TCChain = InChain;
8004 const Function &F = DAG.getMachineFunction().getFunction();
8005 bool IsTC = TLI.isInTailCallPosition(DAG, Op.getNode(), TCChain) &&
8006 F.getReturnType() == LCRTy;
8010 TargetLowering::CallLoweringInfo CLI(DAG);
8013 .setCallee(CallingConv::ARM_AAPCS_VFP, LCRTy, Callee, std::move(Args))
8015 std::pair<SDValue, SDValue> CI = TLI.LowerCallTo(CLI);
8017 // Return the chain (the DAG root) if it is a tail call
8018 return !CI.second.getNode() ? DAG.getRoot() : CI.first;
8021 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8022 LLVM_DEBUG(dbgs() << "Lowering node: "; Op.dump());
8023 switch (Op.getOpcode()) {
8024 default: llvm_unreachable("Don't know how to custom lower this!");
8025 case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
8026 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8027 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8028 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8029 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8030 case ISD::SELECT: return LowerSELECT(Op, DAG);
8031 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
8032 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8033 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
8034 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
8035 case ISD::VASTART: return LowerVASTART(Op, DAG);
8036 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
8037 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
8038 case ISD::SINT_TO_FP:
8039 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
8040 case ISD::FP_TO_SINT:
8041 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
8042 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8043 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8044 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8045 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
8046 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
8047 case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
8048 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
8050 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG, Subtarget);
8053 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
8054 case ISD::SREM: return LowerREM(Op.getNode(), DAG);
8055 case ISD::UREM: return LowerREM(Op.getNode(), DAG);
8056 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
8057 case ISD::SRL_PARTS:
8058 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
8060 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
8061 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
8062 case ISD::SETCC: return LowerVSETCC(Op, DAG);
8063 case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG);
8064 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
8065 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
8066 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8067 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8068 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8069 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8070 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8071 case ISD::MUL: return LowerMUL(Op, DAG);
8073 if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
8074 return LowerDIV_Windows(Op, DAG, /* Signed */ true);
8075 return LowerSDIV(Op, DAG);
8077 if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
8078 return LowerDIV_Windows(Op, DAG, /* Signed */ false);
8079 return LowerUDIV(Op, DAG);
8081 case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG);
8084 return LowerSignedALUO(Op, DAG);
8087 return LowerUnsignedALUO(Op, DAG);
8088 case ISD::ATOMIC_LOAD:
8089 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
8090 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
8092 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
8093 case ISD::DYNAMIC_STACKALLOC:
8094 if (Subtarget->isTargetWindows())
8095 return LowerDYNAMIC_STACKALLOC(Op, DAG);
8096 llvm_unreachable("Don't know how to custom lower this!");
8097 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
8098 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
8099 case ISD::FPOWI: return LowerFPOWI(Op, *Subtarget, DAG);
8100 case ARMISD::WIN__DBZCHK: return SDValue();
8104 static void ReplaceLongIntrinsic(SDNode *N, SmallVectorImpl<SDValue> &Results,
8105 SelectionDAG &DAG) {
8106 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
8108 if (IntNo == Intrinsic::arm_smlald)
8109 Opc = ARMISD::SMLALD;
8110 else if (IntNo == Intrinsic::arm_smlaldx)
8111 Opc = ARMISD::SMLALDX;
8112 else if (IntNo == Intrinsic::arm_smlsld)
8113 Opc = ARMISD::SMLSLD;
8114 else if (IntNo == Intrinsic::arm_smlsldx)
8115 Opc = ARMISD::SMLSLDX;
8120 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8122 DAG.getConstant(0, dl, MVT::i32));
8123 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8125 DAG.getConstant(1, dl, MVT::i32));
8127 SDValue LongMul = DAG.getNode(Opc, dl,
8128 DAG.getVTList(MVT::i32, MVT::i32),
8129 N->getOperand(1), N->getOperand(2),
8131 Results.push_back(LongMul.getValue(0));
8132 Results.push_back(LongMul.getValue(1));
8135 /// ReplaceNodeResults - Replace the results of node with an illegal result
8136 /// type with new values built out of custom code.
8137 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
8138 SmallVectorImpl<SDValue> &Results,
8139 SelectionDAG &DAG) const {
8141 switch (N->getOpcode()) {
8143 llvm_unreachable("Don't know how to custom expand this!");
8144 case ISD::READ_REGISTER:
8145 ExpandREAD_REGISTER(N, Results, DAG);
8148 Res = ExpandBITCAST(N, DAG, Subtarget);
8152 Res = Expand64BitShift(N, DAG, Subtarget);
8156 Res = LowerREM(N, DAG);
8160 Res = LowerDivRem(SDValue(N, 0), DAG);
8161 assert(Res.getNumOperands() == 2 && "DivRem needs two values");
8162 Results.push_back(Res.getValue(0));
8163 Results.push_back(Res.getValue(1));
8165 case ISD::READCYCLECOUNTER:
8166 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
8170 assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows");
8171 return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
8173 case ISD::ATOMIC_CMP_SWAP:
8174 ReplaceCMP_SWAP_64Results(N, Results, DAG);
8176 case ISD::INTRINSIC_WO_CHAIN:
8177 return ReplaceLongIntrinsic(N, Results, DAG);
8180 Results.push_back(Res);
8183 //===----------------------------------------------------------------------===//
8184 // ARM Scheduler Hooks
8185 //===----------------------------------------------------------------------===//
8187 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
8188 /// registers the function context.
8189 void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,
8190 MachineBasicBlock *MBB,
8191 MachineBasicBlock *DispatchBB,
8193 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
8194 "ROPI/RWPI not currently supported with SjLj");
8195 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
8196 DebugLoc dl = MI.getDebugLoc();
8197 MachineFunction *MF = MBB->getParent();
8198 MachineRegisterInfo *MRI = &MF->getRegInfo();
8199 MachineConstantPool *MCP = MF->getConstantPool();
8200 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
8201 const Function &F = MF->getFunction();
8203 bool isThumb = Subtarget->isThumb();
8204 bool isThumb2 = Subtarget->isThumb2();
8206 unsigned PCLabelId = AFI->createPICLabelUId();
8207 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
8208 ARMConstantPoolValue *CPV =
8209 ARMConstantPoolMBB::Create(F.getContext(), DispatchBB, PCLabelId, PCAdj);
8210 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
8212 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
8213 : &ARM::GPRRegClass;
8215 // Grab constant pool and fixed stack memory operands.
8216 MachineMemOperand *CPMMO =
8217 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
8218 MachineMemOperand::MOLoad, 4, 4);
8220 MachineMemOperand *FIMMOSt =
8221 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI),
8222 MachineMemOperand::MOStore, 4, 4);
8224 // Load the address of the dispatch MBB into the jump buffer.
8226 // Incoming value: jbuf
8227 // ldr.n r5, LCPI1_1
8230 // str r5, [$jbuf, #+4] ; &jbuf[1]
8231 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
8232 BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
8233 .addConstantPoolIndex(CPI)
8234 .addMemOperand(CPMMO)
8235 .add(predOps(ARMCC::AL));
8236 // Set the low bit because of thumb mode.
8237 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
8238 BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
8239 .addReg(NewVReg1, RegState::Kill)
8241 .add(predOps(ARMCC::AL))
8243 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
8244 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
8245 .addReg(NewVReg2, RegState::Kill)
8247 BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
8248 .addReg(NewVReg3, RegState::Kill)
8250 .addImm(36) // &jbuf[1] :: pc
8251 .addMemOperand(FIMMOSt)
8252 .add(predOps(ARMCC::AL));
8253 } else if (isThumb) {
8254 // Incoming value: jbuf
8255 // ldr.n r1, LCPI1_4
8259 // add r2, $jbuf, #+4 ; &jbuf[1]
8261 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
8262 BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
8263 .addConstantPoolIndex(CPI)
8264 .addMemOperand(CPMMO)
8265 .add(predOps(ARMCC::AL));
8266 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
8267 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
8268 .addReg(NewVReg1, RegState::Kill)
8270 // Set the low bit because of thumb mode.
8271 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
8272 BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
8273 .addReg(ARM::CPSR, RegState::Define)
8275 .add(predOps(ARMCC::AL));
8276 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
8277 BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
8278 .addReg(ARM::CPSR, RegState::Define)
8279 .addReg(NewVReg2, RegState::Kill)
8280 .addReg(NewVReg3, RegState::Kill)
8281 .add(predOps(ARMCC::AL));
8282 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
8283 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
8285 .addImm(36); // &jbuf[1] :: pc
8286 BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
8287 .addReg(NewVReg4, RegState::Kill)
8288 .addReg(NewVReg5, RegState::Kill)
8290 .addMemOperand(FIMMOSt)
8291 .add(predOps(ARMCC::AL));
8293 // Incoming value: jbuf
8296 // str r1, [$jbuf, #+4] ; &jbuf[1]
8297 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
8298 BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
8299 .addConstantPoolIndex(CPI)
8301 .addMemOperand(CPMMO)
8302 .add(predOps(ARMCC::AL));
8303 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
8304 BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
8305 .addReg(NewVReg1, RegState::Kill)
8307 .add(predOps(ARMCC::AL));
8308 BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
8309 .addReg(NewVReg2, RegState::Kill)
8311 .addImm(36) // &jbuf[1] :: pc
8312 .addMemOperand(FIMMOSt)
8313 .add(predOps(ARMCC::AL));
8317 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
8318 MachineBasicBlock *MBB) const {
8319 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
8320 DebugLoc dl = MI.getDebugLoc();
8321 MachineFunction *MF = MBB->getParent();
8322 MachineRegisterInfo *MRI = &MF->getRegInfo();
8323 MachineFrameInfo &MFI = MF->getFrameInfo();
8324 int FI = MFI.getFunctionContextIndex();
8326 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
8327 : &ARM::GPRnopcRegClass;
8329 // Get a mapping of the call site numbers to all of the landing pads they're
8331 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2>> CallSiteNumToLPad;
8332 unsigned MaxCSNum = 0;
8333 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
8335 if (!BB->isEHPad()) continue;
8337 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
8339 for (MachineBasicBlock::iterator
8340 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
8341 if (!II->isEHLabel()) continue;
8343 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
8344 if (!MF->hasCallSiteLandingPad(Sym)) continue;
8346 SmallVectorImpl<unsigned> &CallSiteIdxs = MF->getCallSiteLandingPad(Sym);
8347 for (SmallVectorImpl<unsigned>::iterator
8348 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
8349 CSI != CSE; ++CSI) {
8350 CallSiteNumToLPad[*CSI].push_back(&*BB);
8351 MaxCSNum = std::max(MaxCSNum, *CSI);
8357 // Get an ordered list of the machine basic blocks for the jump table.
8358 std::vector<MachineBasicBlock*> LPadList;
8359 SmallPtrSet<MachineBasicBlock*, 32> InvokeBBs;
8360 LPadList.reserve(CallSiteNumToLPad.size());
8361 for (unsigned I = 1; I <= MaxCSNum; ++I) {
8362 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
8363 for (SmallVectorImpl<MachineBasicBlock*>::iterator
8364 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
8365 LPadList.push_back(*II);
8366 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
8370 assert(!LPadList.empty() &&
8371 "No landing pad destinations for the dispatch jump table!");
8373 // Create the jump table and associated information.
8374 MachineJumpTableInfo *JTI =
8375 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
8376 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
8378 // Create the MBBs for the dispatch code.
8380 // Shove the dispatch's address into the return slot in the function context.
8381 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
8382 DispatchBB->setIsEHPad();
8384 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
8385 unsigned trap_opcode;
8386 if (Subtarget->isThumb())
8387 trap_opcode = ARM::tTRAP;
8389 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
8391 BuildMI(TrapBB, dl, TII->get(trap_opcode));
8392 DispatchBB->addSuccessor(TrapBB);
8394 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
8395 DispatchBB->addSuccessor(DispContBB);
8398 MF->insert(MF->end(), DispatchBB);
8399 MF->insert(MF->end(), DispContBB);
8400 MF->insert(MF->end(), TrapBB);
8402 // Insert code into the entry block that creates and registers the function
8404 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
8406 MachineMemOperand *FIMMOLd = MF->getMachineMemOperand(
8407 MachinePointerInfo::getFixedStack(*MF, FI),
8408 MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 4, 4);
8410 MachineInstrBuilder MIB;
8411 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
8413 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
8414 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
8416 // Add a register mask with no preserved registers. This results in all
8417 // registers being marked as clobbered. This can't work if the dispatch block
8418 // is in a Thumb1 function and is linked with ARM code which uses the FP
8419 // registers, as there is no way to preserve the FP registers in Thumb1 mode.
8420 MIB.addRegMask(RI.getSjLjDispatchPreservedMask(*MF));
8422 bool IsPositionIndependent = isPositionIndependent();
8423 unsigned NumLPads = LPadList.size();
8424 if (Subtarget->isThumb2()) {
8425 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
8426 BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
8429 .addMemOperand(FIMMOLd)
8430 .add(predOps(ARMCC::AL));
8432 if (NumLPads < 256) {
8433 BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
8435 .addImm(LPadList.size())
8436 .add(predOps(ARMCC::AL));
8438 unsigned VReg1 = MRI->createVirtualRegister(TRC);
8439 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
8440 .addImm(NumLPads & 0xFFFF)
8441 .add(predOps(ARMCC::AL));
8443 unsigned VReg2 = VReg1;
8444 if ((NumLPads & 0xFFFF0000) != 0) {
8445 VReg2 = MRI->createVirtualRegister(TRC);
8446 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
8448 .addImm(NumLPads >> 16)
8449 .add(predOps(ARMCC::AL));
8452 BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
8455 .add(predOps(ARMCC::AL));
8458 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
8463 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
8464 BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg3)
8465 .addJumpTableIndex(MJTI)
8466 .add(predOps(ARMCC::AL));
8468 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
8469 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
8470 .addReg(NewVReg3, RegState::Kill)
8472 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
8473 .add(predOps(ARMCC::AL))
8476 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
8477 .addReg(NewVReg4, RegState::Kill)
8479 .addJumpTableIndex(MJTI);
8480 } else if (Subtarget->isThumb()) {
8481 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
8482 BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
8485 .addMemOperand(FIMMOLd)
8486 .add(predOps(ARMCC::AL));
8488 if (NumLPads < 256) {
8489 BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
8492 .add(predOps(ARMCC::AL));
8494 MachineConstantPool *ConstantPool = MF->getConstantPool();
8495 Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext());
8496 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
8498 // MachineConstantPool wants an explicit alignment.
8499 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
8501 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
8502 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
8504 unsigned VReg1 = MRI->createVirtualRegister(TRC);
8505 BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
8506 .addReg(VReg1, RegState::Define)
8507 .addConstantPoolIndex(Idx)
8508 .add(predOps(ARMCC::AL));
8509 BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
8512 .add(predOps(ARMCC::AL));
8515 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
8520 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
8521 BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
8522 .addReg(ARM::CPSR, RegState::Define)
8525 .add(predOps(ARMCC::AL));
8527 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
8528 BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
8529 .addJumpTableIndex(MJTI)
8530 .add(predOps(ARMCC::AL));
8532 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
8533 BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
8534 .addReg(ARM::CPSR, RegState::Define)
8535 .addReg(NewVReg2, RegState::Kill)
8537 .add(predOps(ARMCC::AL));
8539 MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
8540 MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
8542 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
8543 BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
8544 .addReg(NewVReg4, RegState::Kill)
8546 .addMemOperand(JTMMOLd)
8547 .add(predOps(ARMCC::AL));
8549 unsigned NewVReg6 = NewVReg5;
8550 if (IsPositionIndependent) {
8551 NewVReg6 = MRI->createVirtualRegister(TRC);
8552 BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
8553 .addReg(ARM::CPSR, RegState::Define)
8554 .addReg(NewVReg5, RegState::Kill)
8556 .add(predOps(ARMCC::AL));
8559 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
8560 .addReg(NewVReg6, RegState::Kill)
8561 .addJumpTableIndex(MJTI);
8563 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
8564 BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
8567 .addMemOperand(FIMMOLd)
8568 .add(predOps(ARMCC::AL));
8570 if (NumLPads < 256) {
8571 BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
8574 .add(predOps(ARMCC::AL));
8575 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
8576 unsigned VReg1 = MRI->createVirtualRegister(TRC);
8577 BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
8578 .addImm(NumLPads & 0xFFFF)
8579 .add(predOps(ARMCC::AL));
8581 unsigned VReg2 = VReg1;
8582 if ((NumLPads & 0xFFFF0000) != 0) {
8583 VReg2 = MRI->createVirtualRegister(TRC);
8584 BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
8586 .addImm(NumLPads >> 16)
8587 .add(predOps(ARMCC::AL));
8590 BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
8593 .add(predOps(ARMCC::AL));
8595 MachineConstantPool *ConstantPool = MF->getConstantPool();
8596 Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext());
8597 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
8599 // MachineConstantPool wants an explicit alignment.
8600 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
8602 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
8603 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
8605 unsigned VReg1 = MRI->createVirtualRegister(TRC);
8606 BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
8607 .addReg(VReg1, RegState::Define)
8608 .addConstantPoolIndex(Idx)
8610 .add(predOps(ARMCC::AL));
8611 BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
8613 .addReg(VReg1, RegState::Kill)
8614 .add(predOps(ARMCC::AL));
8617 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
8622 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
8623 BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
8625 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
8626 .add(predOps(ARMCC::AL))
8628 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
8629 BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
8630 .addJumpTableIndex(MJTI)
8631 .add(predOps(ARMCC::AL));
8633 MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
8634 MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
8635 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
8636 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
8637 .addReg(NewVReg3, RegState::Kill)
8640 .addMemOperand(JTMMOLd)
8641 .add(predOps(ARMCC::AL));
8643 if (IsPositionIndependent) {
8644 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
8645 .addReg(NewVReg5, RegState::Kill)
8647 .addJumpTableIndex(MJTI);
8649 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
8650 .addReg(NewVReg5, RegState::Kill)
8651 .addJumpTableIndex(MJTI);
8655 // Add the jump table entries as successors to the MBB.
8656 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
8657 for (std::vector<MachineBasicBlock*>::iterator
8658 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
8659 MachineBasicBlock *CurMBB = *I;
8660 if (SeenMBBs.insert(CurMBB).second)
8661 DispContBB->addSuccessor(CurMBB);
8664 // N.B. the order the invoke BBs are processed in doesn't matter here.
8665 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
8666 SmallVector<MachineBasicBlock*, 64> MBBLPads;
8667 for (MachineBasicBlock *BB : InvokeBBs) {
8669 // Remove the landing pad successor from the invoke block and replace it
8670 // with the new dispatch block.
8671 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
8673 while (!Successors.empty()) {
8674 MachineBasicBlock *SMBB = Successors.pop_back_val();
8675 if (SMBB->isEHPad()) {
8676 BB->removeSuccessor(SMBB);
8677 MBBLPads.push_back(SMBB);
8681 BB->addSuccessor(DispatchBB, BranchProbability::getZero());
8682 BB->normalizeSuccProbs();
8684 // Find the invoke call and mark all of the callee-saved registers as
8685 // 'implicit defined' so that they're spilled. This prevents code from
8686 // moving instructions to before the EH block, where they will never be
8688 for (MachineBasicBlock::reverse_iterator
8689 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
8690 if (!II->isCall()) continue;
8692 DenseMap<unsigned, bool> DefRegs;
8693 for (MachineInstr::mop_iterator
8694 OI = II->operands_begin(), OE = II->operands_end();
8696 if (!OI->isReg()) continue;
8697 DefRegs[OI->getReg()] = true;
8700 MachineInstrBuilder MIB(*MF, &*II);
8702 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
8703 unsigned Reg = SavedRegs[i];
8704 if (Subtarget->isThumb2() &&
8705 !ARM::tGPRRegClass.contains(Reg) &&
8706 !ARM::hGPRRegClass.contains(Reg))
8708 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
8710 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
8713 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
8720 // Mark all former landing pads as non-landing pads. The dispatch is the only
8722 for (SmallVectorImpl<MachineBasicBlock*>::iterator
8723 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
8724 (*I)->setIsEHPad(false);
8726 // The instruction is gone now.
8727 MI.eraseFromParent();
8731 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
8732 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
8733 E = MBB->succ_end(); I != E; ++I)
8736 llvm_unreachable("Expecting a BB with two successors!");
8739 /// Return the load opcode for a given load size. If load size >= 8,
8740 /// neon opcode will be returned.
8741 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
8743 return LdSize == 16 ? ARM::VLD1q32wb_fixed
8744 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
8746 return LdSize == 4 ? ARM::tLDRi
8747 : LdSize == 2 ? ARM::tLDRHi
8748 : LdSize == 1 ? ARM::tLDRBi : 0;
8750 return LdSize == 4 ? ARM::t2LDR_POST
8751 : LdSize == 2 ? ARM::t2LDRH_POST
8752 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
8753 return LdSize == 4 ? ARM::LDR_POST_IMM
8754 : LdSize == 2 ? ARM::LDRH_POST
8755 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
8758 /// Return the store opcode for a given store size. If store size >= 8,
8759 /// neon opcode will be returned.
8760 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
8762 return StSize == 16 ? ARM::VST1q32wb_fixed
8763 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
8765 return StSize == 4 ? ARM::tSTRi
8766 : StSize == 2 ? ARM::tSTRHi
8767 : StSize == 1 ? ARM::tSTRBi : 0;
8769 return StSize == 4 ? ARM::t2STR_POST
8770 : StSize == 2 ? ARM::t2STRH_POST
8771 : StSize == 1 ? ARM::t2STRB_POST : 0;
8772 return StSize == 4 ? ARM::STR_POST_IMM
8773 : StSize == 2 ? ARM::STRH_POST
8774 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
8777 /// Emit a post-increment load operation with given size. The instructions
8778 /// will be added to BB at Pos.
8779 static void emitPostLd(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos,
8780 const TargetInstrInfo *TII, const DebugLoc &dl,
8781 unsigned LdSize, unsigned Data, unsigned AddrIn,
8782 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
8783 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
8784 assert(LdOpc != 0 && "Should have a load opcode");
8786 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
8787 .addReg(AddrOut, RegState::Define)
8790 .add(predOps(ARMCC::AL));
8791 } else if (IsThumb1) {
8792 // load + update AddrIn
8793 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
8796 .add(predOps(ARMCC::AL));
8797 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
8798 .add(t1CondCodeOp())
8801 .add(predOps(ARMCC::AL));
8802 } else if (IsThumb2) {
8803 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
8804 .addReg(AddrOut, RegState::Define)
8807 .add(predOps(ARMCC::AL));
8809 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
8810 .addReg(AddrOut, RegState::Define)
8814 .add(predOps(ARMCC::AL));
8818 /// Emit a post-increment store operation with given size. The instructions
8819 /// will be added to BB at Pos.
8820 static void emitPostSt(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos,
8821 const TargetInstrInfo *TII, const DebugLoc &dl,
8822 unsigned StSize, unsigned Data, unsigned AddrIn,
8823 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
8824 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
8825 assert(StOpc != 0 && "Should have a store opcode");
8827 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
8831 .add(predOps(ARMCC::AL));
8832 } else if (IsThumb1) {
8833 // store + update AddrIn
8834 BuildMI(*BB, Pos, dl, TII->get(StOpc))
8838 .add(predOps(ARMCC::AL));
8839 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
8840 .add(t1CondCodeOp())
8843 .add(predOps(ARMCC::AL));
8844 } else if (IsThumb2) {
8845 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
8849 .add(predOps(ARMCC::AL));
8851 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
8856 .add(predOps(ARMCC::AL));
8861 ARMTargetLowering::EmitStructByval(MachineInstr &MI,
8862 MachineBasicBlock *BB) const {
8863 // This pseudo instruction has 3 operands: dst, src, size
8864 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
8865 // Otherwise, we will generate unrolled scalar copies.
8866 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
8867 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8868 MachineFunction::iterator It = ++BB->getIterator();
8870 unsigned dest = MI.getOperand(0).getReg();
8871 unsigned src = MI.getOperand(1).getReg();
8872 unsigned SizeVal = MI.getOperand(2).getImm();
8873 unsigned Align = MI.getOperand(3).getImm();
8874 DebugLoc dl = MI.getDebugLoc();
8876 MachineFunction *MF = BB->getParent();
8877 MachineRegisterInfo &MRI = MF->getRegInfo();
8878 unsigned UnitSize = 0;
8879 const TargetRegisterClass *TRC = nullptr;
8880 const TargetRegisterClass *VecTRC = nullptr;
8882 bool IsThumb1 = Subtarget->isThumb1Only();
8883 bool IsThumb2 = Subtarget->isThumb2();
8884 bool IsThumb = Subtarget->isThumb();
8888 } else if (Align & 2) {
8891 // Check whether we can use NEON instructions.
8892 if (!MF->getFunction().hasFnAttribute(Attribute::NoImplicitFloat) &&
8893 Subtarget->hasNEON()) {
8894 if ((Align % 16 == 0) && SizeVal >= 16)
8896 else if ((Align % 8 == 0) && SizeVal >= 8)
8899 // Can't use NEON instructions.
8904 // Select the correct opcode and register class for unit size load/store
8905 bool IsNeon = UnitSize >= 8;
8906 TRC = IsThumb ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
8908 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
8909 : UnitSize == 8 ? &ARM::DPRRegClass
8912 unsigned BytesLeft = SizeVal % UnitSize;
8913 unsigned LoopSize = SizeVal - BytesLeft;
8915 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
8916 // Use LDR and STR to copy.
8917 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
8918 // [destOut] = STR_POST(scratch, destIn, UnitSize)
8919 unsigned srcIn = src;
8920 unsigned destIn = dest;
8921 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
8922 unsigned srcOut = MRI.createVirtualRegister(TRC);
8923 unsigned destOut = MRI.createVirtualRegister(TRC);
8924 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
8925 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
8926 IsThumb1, IsThumb2);
8927 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
8928 IsThumb1, IsThumb2);
8933 // Handle the leftover bytes with LDRB and STRB.
8934 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
8935 // [destOut] = STRB_POST(scratch, destIn, 1)
8936 for (unsigned i = 0; i < BytesLeft; i++) {
8937 unsigned srcOut = MRI.createVirtualRegister(TRC);
8938 unsigned destOut = MRI.createVirtualRegister(TRC);
8939 unsigned scratch = MRI.createVirtualRegister(TRC);
8940 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
8941 IsThumb1, IsThumb2);
8942 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
8943 IsThumb1, IsThumb2);
8947 MI.eraseFromParent(); // The instruction is gone now.
8951 // Expand the pseudo op to a loop.
8954 // movw varEnd, # --> with thumb2
8956 // ldrcp varEnd, idx --> without thumb2
8957 // fallthrough --> loopMBB
8959 // PHI varPhi, varEnd, varLoop
8960 // PHI srcPhi, src, srcLoop
8961 // PHI destPhi, dst, destLoop
8962 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
8963 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
8964 // subs varLoop, varPhi, #UnitSize
8966 // fallthrough --> exitMBB
8968 // epilogue to handle left-over bytes
8969 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
8970 // [destOut] = STRB_POST(scratch, destLoop, 1)
8971 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
8972 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
8973 MF->insert(It, loopMBB);
8974 MF->insert(It, exitMBB);
8976 // Transfer the remainder of BB and its successor edges to exitMBB.
8977 exitMBB->splice(exitMBB->begin(), BB,
8978 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8979 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8981 // Load an immediate to varEnd.
8982 unsigned varEnd = MRI.createVirtualRegister(TRC);
8983 if (Subtarget->useMovt(*MF)) {
8984 unsigned Vtmp = varEnd;
8985 if ((LoopSize & 0xFFFF0000) != 0)
8986 Vtmp = MRI.createVirtualRegister(TRC);
8987 BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi16 : ARM::MOVi16), Vtmp)
8988 .addImm(LoopSize & 0xFFFF)
8989 .add(predOps(ARMCC::AL));
8991 if ((LoopSize & 0xFFFF0000) != 0)
8992 BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVTi16 : ARM::MOVTi16), varEnd)
8994 .addImm(LoopSize >> 16)
8995 .add(predOps(ARMCC::AL));
8997 MachineConstantPool *ConstantPool = MF->getConstantPool();
8998 Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext());
8999 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
9001 // MachineConstantPool wants an explicit alignment.
9002 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
9004 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
9005 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
9008 BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci))
9009 .addReg(varEnd, RegState::Define)
9010 .addConstantPoolIndex(Idx)
9011 .add(predOps(ARMCC::AL));
9013 BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp))
9014 .addReg(varEnd, RegState::Define)
9015 .addConstantPoolIndex(Idx)
9017 .add(predOps(ARMCC::AL));
9019 BB->addSuccessor(loopMBB);
9021 // Generate the loop body:
9022 // varPhi = PHI(varLoop, varEnd)
9023 // srcPhi = PHI(srcLoop, src)
9024 // destPhi = PHI(destLoop, dst)
9025 MachineBasicBlock *entryBB = BB;
9027 unsigned varLoop = MRI.createVirtualRegister(TRC);
9028 unsigned varPhi = MRI.createVirtualRegister(TRC);
9029 unsigned srcLoop = MRI.createVirtualRegister(TRC);
9030 unsigned srcPhi = MRI.createVirtualRegister(TRC);
9031 unsigned destLoop = MRI.createVirtualRegister(TRC);
9032 unsigned destPhi = MRI.createVirtualRegister(TRC);
9034 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
9035 .addReg(varLoop).addMBB(loopMBB)
9036 .addReg(varEnd).addMBB(entryBB);
9037 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
9038 .addReg(srcLoop).addMBB(loopMBB)
9039 .addReg(src).addMBB(entryBB);
9040 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
9041 .addReg(destLoop).addMBB(loopMBB)
9042 .addReg(dest).addMBB(entryBB);
9044 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
9045 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
9046 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
9047 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
9048 IsThumb1, IsThumb2);
9049 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
9050 IsThumb1, IsThumb2);
9052 // Decrement loop variable by UnitSize.
9054 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop)
9055 .add(t1CondCodeOp())
9058 .add(predOps(ARMCC::AL));
9060 MachineInstrBuilder MIB =
9061 BuildMI(*BB, BB->end(), dl,
9062 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
9065 .add(predOps(ARMCC::AL))
9067 MIB->getOperand(5).setReg(ARM::CPSR);
9068 MIB->getOperand(5).setIsDef(true);
9070 BuildMI(*BB, BB->end(), dl,
9071 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
9072 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
9074 // loopMBB can loop back to loopMBB or fall through to exitMBB.
9075 BB->addSuccessor(loopMBB);
9076 BB->addSuccessor(exitMBB);
9078 // Add epilogue to handle BytesLeft.
9080 auto StartOfExit = exitMBB->begin();
9082 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
9083 // [destOut] = STRB_POST(scratch, destLoop, 1)
9084 unsigned srcIn = srcLoop;
9085 unsigned destIn = destLoop;
9086 for (unsigned i = 0; i < BytesLeft; i++) {
9087 unsigned srcOut = MRI.createVirtualRegister(TRC);
9088 unsigned destOut = MRI.createVirtualRegister(TRC);
9089 unsigned scratch = MRI.createVirtualRegister(TRC);
9090 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
9091 IsThumb1, IsThumb2);
9092 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
9093 IsThumb1, IsThumb2);
9098 MI.eraseFromParent(); // The instruction is gone now.
9103 ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
9104 MachineBasicBlock *MBB) const {
9105 const TargetMachine &TM = getTargetMachine();
9106 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
9107 DebugLoc DL = MI.getDebugLoc();
9109 assert(Subtarget->isTargetWindows() &&
9110 "__chkstk is only supported on Windows");
9111 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
9113 // __chkstk takes the number of words to allocate on the stack in R4, and
9114 // returns the stack adjustment in number of bytes in R4. This will not
9115 // clober any other registers (other than the obvious lr).
9117 // Although, technically, IP should be considered a register which may be
9118 // clobbered, the call itself will not touch it. Windows on ARM is a pure
9119 // thumb-2 environment, so there is no interworking required. As a result, we
9120 // do not expect a veneer to be emitted by the linker, clobbering IP.
9122 // Each module receives its own copy of __chkstk, so no import thunk is
9123 // required, again, ensuring that IP is not clobbered.
9125 // Finally, although some linkers may theoretically provide a trampoline for
9126 // out of range calls (which is quite common due to a 32M range limitation of
9127 // branches for Thumb), we can generate the long-call version via
9128 // -mcmodel=large, alleviating the need for the trampoline which may clobber
9131 switch (TM.getCodeModel()) {
9132 case CodeModel::Tiny:
9133 llvm_unreachable("Tiny code model not available on ARM.");
9134 case CodeModel::Small:
9135 case CodeModel::Medium:
9136 case CodeModel::Kernel:
9137 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
9138 .add(predOps(ARMCC::AL))
9139 .addExternalSymbol("__chkstk")
9140 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
9141 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
9143 RegState::Implicit | RegState::Define | RegState::Dead)
9145 RegState::Implicit | RegState::Define | RegState::Dead);
9147 case CodeModel::Large: {
9148 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
9149 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
9151 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
9152 .addExternalSymbol("__chkstk");
9153 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
9154 .add(predOps(ARMCC::AL))
9155 .addReg(Reg, RegState::Kill)
9156 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
9157 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
9159 RegState::Implicit | RegState::Define | RegState::Dead)
9161 RegState::Implicit | RegState::Define | RegState::Dead);
9166 BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
9167 .addReg(ARM::SP, RegState::Kill)
9168 .addReg(ARM::R4, RegState::Kill)
9169 .setMIFlags(MachineInstr::FrameSetup)
9170 .add(predOps(ARMCC::AL))
9173 MI.eraseFromParent();
9178 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
9179 MachineBasicBlock *MBB) const {
9180 DebugLoc DL = MI.getDebugLoc();
9181 MachineFunction *MF = MBB->getParent();
9182 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
9184 MachineBasicBlock *ContBB = MF->CreateMachineBasicBlock();
9185 MF->insert(++MBB->getIterator(), ContBB);
9186 ContBB->splice(ContBB->begin(), MBB,
9187 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
9188 ContBB->transferSuccessorsAndUpdatePHIs(MBB);
9189 MBB->addSuccessor(ContBB);
9191 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
9192 BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0));
9193 MF->push_back(TrapBB);
9194 MBB->addSuccessor(TrapBB);
9196 BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8))
9197 .addReg(MI.getOperand(0).getReg())
9199 .add(predOps(ARMCC::AL));
9200 BuildMI(*MBB, MI, DL, TII->get(ARM::t2Bcc))
9205 MI.eraseFromParent();
9209 // The CPSR operand of SelectItr might be missing a kill marker
9210 // because there were multiple uses of CPSR, and ISel didn't know
9211 // which to mark. Figure out whether SelectItr should have had a
9212 // kill marker, and set it if it should. Returns the correct kill
9214 static bool checkAndUpdateCPSRKill(MachineBasicBlock::iterator SelectItr,
9215 MachineBasicBlock* BB,
9216 const TargetRegisterInfo* TRI) {
9217 // Scan forward through BB for a use/def of CPSR.
9218 MachineBasicBlock::iterator miI(std::next(SelectItr));
9219 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
9220 const MachineInstr& mi = *miI;
9221 if (mi.readsRegister(ARM::CPSR))
9223 if (mi.definesRegister(ARM::CPSR))
9224 break; // Should have kill-flag - update below.
9227 // If we hit the end of the block, check whether CPSR is live into a
9229 if (miI == BB->end()) {
9230 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
9231 sEnd = BB->succ_end();
9232 sItr != sEnd; ++sItr) {
9233 MachineBasicBlock* succ = *sItr;
9234 if (succ->isLiveIn(ARM::CPSR))
9239 // We found a def, or hit the end of the basic block and CPSR wasn't live
9240 // out. SelectMI should have a kill flag on CPSR.
9241 SelectItr->addRegisterKilled(ARM::CPSR, TRI);
9246 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
9247 MachineBasicBlock *BB) const {
9248 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
9249 DebugLoc dl = MI.getDebugLoc();
9250 bool isThumb2 = Subtarget->isThumb2();
9251 switch (MI.getOpcode()) {
9254 llvm_unreachable("Unexpected instr type to insert");
9257 // Thumb1 post-indexed loads are really just single-register LDMs.
9258 case ARM::tLDR_postidx: {
9259 MachineOperand Def(MI.getOperand(1));
9260 BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
9262 .add(MI.getOperand(2)) // Rn
9263 .add(MI.getOperand(3)) // PredImm
9264 .add(MI.getOperand(4)) // PredReg
9265 .add(MI.getOperand(0)); // Rt
9266 MI.eraseFromParent();
9270 // The Thumb2 pre-indexed stores have the same MI operands, they just
9271 // define them differently in the .td files from the isel patterns, so
9272 // they need pseudos.
9273 case ARM::t2STR_preidx:
9274 MI.setDesc(TII->get(ARM::t2STR_PRE));
9276 case ARM::t2STRB_preidx:
9277 MI.setDesc(TII->get(ARM::t2STRB_PRE));
9279 case ARM::t2STRH_preidx:
9280 MI.setDesc(TII->get(ARM::t2STRH_PRE));
9283 case ARM::STRi_preidx:
9284 case ARM::STRBi_preidx: {
9285 unsigned NewOpc = MI.getOpcode() == ARM::STRi_preidx ? ARM::STR_PRE_IMM
9286 : ARM::STRB_PRE_IMM;
9287 // Decode the offset.
9288 unsigned Offset = MI.getOperand(4).getImm();
9289 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
9290 Offset = ARM_AM::getAM2Offset(Offset);
9294 MachineMemOperand *MMO = *MI.memoperands_begin();
9295 BuildMI(*BB, MI, dl, TII->get(NewOpc))
9296 .add(MI.getOperand(0)) // Rn_wb
9297 .add(MI.getOperand(1)) // Rt
9298 .add(MI.getOperand(2)) // Rn
9299 .addImm(Offset) // offset (skip GPR==zero_reg)
9300 .add(MI.getOperand(5)) // pred
9301 .add(MI.getOperand(6))
9302 .addMemOperand(MMO);
9303 MI.eraseFromParent();
9306 case ARM::STRr_preidx:
9307 case ARM::STRBr_preidx:
9308 case ARM::STRH_preidx: {
9310 switch (MI.getOpcode()) {
9311 default: llvm_unreachable("unexpected opcode!");
9312 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
9313 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
9314 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
9316 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
9317 for (unsigned i = 0; i < MI.getNumOperands(); ++i)
9318 MIB.add(MI.getOperand(i));
9319 MI.eraseFromParent();
9323 case ARM::tMOVCCr_pseudo: {
9324 // To "insert" a SELECT_CC instruction, we actually have to insert the
9325 // diamond control-flow pattern. The incoming instruction knows the
9326 // destination vreg to set, the condition code register to branch on, the
9327 // true/false values to select between, and a branch opcode to use.
9328 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9329 MachineFunction::iterator It = ++BB->getIterator();
9334 // cmpTY ccX, r1, r2
9336 // fallthrough --> copy0MBB
9337 MachineBasicBlock *thisMBB = BB;
9338 MachineFunction *F = BB->getParent();
9339 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9340 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9341 F->insert(It, copy0MBB);
9342 F->insert(It, sinkMBB);
9344 // Check whether CPSR is live past the tMOVCCr_pseudo.
9345 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
9346 if (!MI.killsRegister(ARM::CPSR) &&
9347 !checkAndUpdateCPSRKill(MI, thisMBB, TRI)) {
9348 copy0MBB->addLiveIn(ARM::CPSR);
9349 sinkMBB->addLiveIn(ARM::CPSR);
9352 // Transfer the remainder of BB and its successor edges to sinkMBB.
9353 sinkMBB->splice(sinkMBB->begin(), BB,
9354 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9355 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9357 BB->addSuccessor(copy0MBB);
9358 BB->addSuccessor(sinkMBB);
9360 BuildMI(BB, dl, TII->get(ARM::tBcc))
9362 .addImm(MI.getOperand(3).getImm())
9363 .addReg(MI.getOperand(4).getReg());
9366 // %FalseValue = ...
9367 // # fallthrough to sinkMBB
9370 // Update machine-CFG edges
9371 BB->addSuccessor(sinkMBB);
9374 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9377 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg())
9378 .addReg(MI.getOperand(1).getReg())
9380 .addReg(MI.getOperand(2).getReg())
9383 MI.eraseFromParent(); // The pseudo instruction is gone now.
9388 case ARM::BCCZi64: {
9389 // If there is an unconditional branch to the other successor, remove it.
9390 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
9392 // Compare both parts that make up the double comparison separately for
9394 bool RHSisZero = MI.getOpcode() == ARM::BCCZi64;
9396 unsigned LHS1 = MI.getOperand(1).getReg();
9397 unsigned LHS2 = MI.getOperand(2).getReg();
9399 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
9402 .add(predOps(ARMCC::AL));
9403 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
9404 .addReg(LHS2).addImm(0)
9405 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
9407 unsigned RHS1 = MI.getOperand(3).getReg();
9408 unsigned RHS2 = MI.getOperand(4).getReg();
9409 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
9412 .add(predOps(ARMCC::AL));
9413 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
9414 .addReg(LHS2).addReg(RHS2)
9415 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
9418 MachineBasicBlock *destMBB = MI.getOperand(RHSisZero ? 3 : 5).getMBB();
9419 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
9420 if (MI.getOperand(0).getImm() == ARMCC::NE)
9421 std::swap(destMBB, exitMBB);
9423 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
9424 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
9426 BuildMI(BB, dl, TII->get(ARM::t2B))
9428 .add(predOps(ARMCC::AL));
9430 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
9432 MI.eraseFromParent(); // The pseudo instruction is gone now.
9436 case ARM::Int_eh_sjlj_setjmp:
9437 case ARM::Int_eh_sjlj_setjmp_nofp:
9438 case ARM::tInt_eh_sjlj_setjmp:
9439 case ARM::t2Int_eh_sjlj_setjmp:
9440 case ARM::t2Int_eh_sjlj_setjmp_nofp:
9443 case ARM::Int_eh_sjlj_setup_dispatch:
9444 EmitSjLjDispatchBlock(MI, BB);
9449 // To insert an ABS instruction, we have to insert the
9450 // diamond control-flow pattern. The incoming instruction knows the
9451 // source vreg to test against 0, the destination vreg to set,
9452 // the condition code register to branch on, the
9453 // true/false values to select between, and a branch opcode to use.
9458 // BCC (branch to SinkBB if V0 >= 0)
9459 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
9460 // SinkBB: V1 = PHI(V2, V3)
9461 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9462 MachineFunction::iterator BBI = ++BB->getIterator();
9463 MachineFunction *Fn = BB->getParent();
9464 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
9465 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
9466 Fn->insert(BBI, RSBBB);
9467 Fn->insert(BBI, SinkBB);
9469 unsigned int ABSSrcReg = MI.getOperand(1).getReg();
9470 unsigned int ABSDstReg = MI.getOperand(0).getReg();
9471 bool ABSSrcKIll = MI.getOperand(1).isKill();
9472 bool isThumb2 = Subtarget->isThumb2();
9473 MachineRegisterInfo &MRI = Fn->getRegInfo();
9474 // In Thumb mode S must not be specified if source register is the SP or
9475 // PC and if destination register is the SP, so restrict register class
9476 unsigned NewRsbDstReg =
9477 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
9479 // Transfer the remainder of BB and its successor edges to sinkMBB.
9480 SinkBB->splice(SinkBB->begin(), BB,
9481 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9482 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
9484 BB->addSuccessor(RSBBB);
9485 BB->addSuccessor(SinkBB);
9487 // fall through to SinkMBB
9488 RSBBB->addSuccessor(SinkBB);
9490 // insert a cmp at the end of BB
9491 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
9494 .add(predOps(ARMCC::AL));
9496 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
9498 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
9499 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
9501 // insert rsbri in RSBBB
9502 // Note: BCC and rsbri will be converted into predicated rsbmi
9503 // by if-conversion pass
9504 BuildMI(*RSBBB, RSBBB->begin(), dl,
9505 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
9506 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
9508 .add(predOps(ARMCC::AL))
9511 // insert PHI in SinkBB,
9512 // reuse ABSDstReg to not change uses of ABS instruction
9513 BuildMI(*SinkBB, SinkBB->begin(), dl,
9514 TII->get(ARM::PHI), ABSDstReg)
9515 .addReg(NewRsbDstReg).addMBB(RSBBB)
9516 .addReg(ABSSrcReg).addMBB(BB);
9518 // remove ABS instruction
9519 MI.eraseFromParent();
9521 // return last added BB
9524 case ARM::COPY_STRUCT_BYVAL_I32:
9526 return EmitStructByval(MI, BB);
9527 case ARM::WIN__CHKSTK:
9528 return EmitLowered__chkstk(MI, BB);
9529 case ARM::WIN__DBZCHK:
9530 return EmitLowered__dbzchk(MI, BB);
9534 /// Attaches vregs to MEMCPY that it will use as scratch registers
9535 /// when it is expanded into LDM/STM. This is done as a post-isel lowering
9536 /// instead of as a custom inserter because we need the use list from the SDNode.
9537 static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget,
9538 MachineInstr &MI, const SDNode *Node) {
9539 bool isThumb1 = Subtarget->isThumb1Only();
9541 DebugLoc DL = MI.getDebugLoc();
9542 MachineFunction *MF = MI.getParent()->getParent();
9543 MachineRegisterInfo &MRI = MF->getRegInfo();
9544 MachineInstrBuilder MIB(*MF, MI);
9546 // If the new dst/src is unused mark it as dead.
9547 if (!Node->hasAnyUseOfValue(0)) {
9548 MI.getOperand(0).setIsDead(true);
9550 if (!Node->hasAnyUseOfValue(1)) {
9551 MI.getOperand(1).setIsDead(true);
9554 // The MEMCPY both defines and kills the scratch registers.
9555 for (unsigned I = 0; I != MI.getOperand(4).getImm(); ++I) {
9556 unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass
9557 : &ARM::GPRRegClass);
9558 MIB.addReg(TmpReg, RegState::Define|RegState::Dead);
9562 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
9563 SDNode *Node) const {
9564 if (MI.getOpcode() == ARM::MEMCPY) {
9565 attachMEMCPYScratchRegs(Subtarget, MI, Node);
9569 const MCInstrDesc *MCID = &MI.getDesc();
9570 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
9571 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
9572 // operand is still set to noreg. If needed, set the optional operand's
9573 // register to CPSR, and remove the redundant implicit def.
9575 // e.g. ADCS (..., implicit-def CPSR) -> ADC (... opt:def CPSR).
9577 // Rename pseudo opcodes.
9578 unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode());
9581 const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
9582 MCID = &TII->get(NewOpc);
9584 assert(MCID->getNumOperands() ==
9585 MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize()
9586 && "converted opcode should be the same except for cc_out"
9587 " (and, on Thumb1, pred)");
9591 // Add the optional cc_out operand
9592 MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
9594 // On Thumb1, move all input operands to the end, then add the predicate
9595 if (Subtarget->isThumb1Only()) {
9596 for (unsigned c = MCID->getNumOperands() - 4; c--;) {
9597 MI.addOperand(MI.getOperand(1));
9598 MI.RemoveOperand(1);
9602 for (unsigned i = MI.getNumOperands(); i--;) {
9603 const MachineOperand& op = MI.getOperand(i);
9604 if (op.isReg() && op.isUse()) {
9605 int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO);
9607 MI.tieOperands(DefIdx, i);
9611 MI.addOperand(MachineOperand::CreateImm(ARMCC::AL));
9612 MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/false));
9615 ccOutIdx = MCID->getNumOperands() - 1;
9617 ccOutIdx = MCID->getNumOperands() - 1;
9619 // Any ARM instruction that sets the 's' bit should specify an optional
9620 // "cc_out" operand in the last operand position.
9621 if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
9622 assert(!NewOpc && "Optional cc_out operand required");
9625 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
9626 // since we already have an optional CPSR def.
9627 bool definesCPSR = false;
9628 bool deadCPSR = false;
9629 for (unsigned i = MCID->getNumOperands(), e = MI.getNumOperands(); i != e;
9631 const MachineOperand &MO = MI.getOperand(i);
9632 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
9636 MI.RemoveOperand(i);
9641 assert(!NewOpc && "Optional cc_out operand required");
9644 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
9646 assert(!MI.getOperand(ccOutIdx).getReg() &&
9647 "expect uninitialized optional cc_out operand");
9648 // Thumb1 instructions must have the S bit even if the CPSR is dead.
9649 if (!Subtarget->isThumb1Only())
9653 // If this instruction was defined with an optional CPSR def and its dag node
9654 // had a live implicit CPSR def, then activate the optional CPSR def.
9655 MachineOperand &MO = MI.getOperand(ccOutIdx);
9656 MO.setReg(ARM::CPSR);
9660 //===----------------------------------------------------------------------===//
9661 // ARM Optimization Hooks
9662 //===----------------------------------------------------------------------===//
9664 // Helper function that checks if N is a null or all ones constant.
9665 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
9666 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
9669 // Return true if N is conditionally 0 or all ones.
9670 // Detects these expressions where cc is an i1 value:
9672 // (select cc 0, y) [AllOnes=0]
9673 // (select cc y, 0) [AllOnes=0]
9674 // (zext cc) [AllOnes=0]
9675 // (sext cc) [AllOnes=0/1]
9676 // (select cc -1, y) [AllOnes=1]
9677 // (select cc y, -1) [AllOnes=1]
9679 // Invert is set when N is the null/all ones constant when CC is false.
9680 // OtherOp is set to the alternative value of N.
9681 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
9682 SDValue &CC, bool &Invert,
9684 SelectionDAG &DAG) {
9685 switch (N->getOpcode()) {
9686 default: return false;
9688 CC = N->getOperand(0);
9689 SDValue N1 = N->getOperand(1);
9690 SDValue N2 = N->getOperand(2);
9691 if (isZeroOrAllOnes(N1, AllOnes)) {
9696 if (isZeroOrAllOnes(N2, AllOnes)) {
9703 case ISD::ZERO_EXTEND:
9704 // (zext cc) can never be the all ones value.
9708 case ISD::SIGN_EXTEND: {
9710 EVT VT = N->getValueType(0);
9711 CC = N->getOperand(0);
9712 if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC)
9716 // When looking for an AllOnes constant, N is an sext, and the 'other'
9718 OtherOp = DAG.getConstant(0, dl, VT);
9719 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9720 // When looking for a 0 constant, N can be zext or sext.
9721 OtherOp = DAG.getConstant(1, dl, VT);
9723 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
9730 // Combine a constant select operand into its use:
9732 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
9733 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
9734 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
9735 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
9736 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
9738 // The transform is rejected if the select doesn't have a constant operand that
9739 // is null, or all ones when AllOnes is set.
9741 // Also recognize sext/zext from i1:
9743 // (add (zext cc), x) -> (select cc (add x, 1), x)
9744 // (add (sext cc), x) -> (select cc (add x, -1), x)
9746 // These transformations eventually create predicated instructions.
9748 // @param N The node to transform.
9749 // @param Slct The N operand that is a select.
9750 // @param OtherOp The other N operand (x above).
9751 // @param DCI Context.
9752 // @param AllOnes Require the select constant to be all ones instead of null.
9753 // @returns The new node, or SDValue() on failure.
9755 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
9756 TargetLowering::DAGCombinerInfo &DCI,
9757 bool AllOnes = false) {
9758 SelectionDAG &DAG = DCI.DAG;
9759 EVT VT = N->getValueType(0);
9760 SDValue NonConstantVal;
9763 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
9764 NonConstantVal, DAG))
9767 // Slct is now know to be the desired identity constant when CC is true.
9768 SDValue TrueVal = OtherOp;
9769 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
9770 OtherOp, NonConstantVal);
9771 // Unless SwapSelectOps says CC should be false.
9773 std::swap(TrueVal, FalseVal);
9775 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
9776 CCOp, TrueVal, FalseVal);
9779 // Attempt combineSelectAndUse on each operand of a commutative operator N.
9781 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
9782 TargetLowering::DAGCombinerInfo &DCI) {
9783 SDValue N0 = N->getOperand(0);
9784 SDValue N1 = N->getOperand(1);
9785 if (N0.getNode()->hasOneUse())
9786 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
9788 if (N1.getNode()->hasOneUse())
9789 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
9794 static bool IsVUZPShuffleNode(SDNode *N) {
9795 // VUZP shuffle node.
9796 if (N->getOpcode() == ARMISD::VUZP)
9799 // "VUZP" on i32 is an alias for VTRN.
9800 if (N->getOpcode() == ARMISD::VTRN && N->getValueType(0) == MVT::v2i32)
9806 static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1,
9807 TargetLowering::DAGCombinerInfo &DCI,
9808 const ARMSubtarget *Subtarget) {
9809 // Look for ADD(VUZP.0, VUZP.1).
9810 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() ||
9814 // Make sure the ADD is a 64-bit add; there is no 128-bit VPADD.
9815 if (!N->getValueType(0).is64BitVector())
9819 SelectionDAG &DAG = DCI.DAG;
9820 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9822 SDNode *Unzip = N0.getNode();
9823 EVT VT = N->getValueType(0);
9825 SmallVector<SDValue, 8> Ops;
9826 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpadd, dl,
9827 TLI.getPointerTy(DAG.getDataLayout())));
9828 Ops.push_back(Unzip->getOperand(0));
9829 Ops.push_back(Unzip->getOperand(1));
9831 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);
9834 static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1,
9835 TargetLowering::DAGCombinerInfo &DCI,
9836 const ARMSubtarget *Subtarget) {
9837 // Check for two extended operands.
9838 if (!(N0.getOpcode() == ISD::SIGN_EXTEND &&
9839 N1.getOpcode() == ISD::SIGN_EXTEND) &&
9840 !(N0.getOpcode() == ISD::ZERO_EXTEND &&
9841 N1.getOpcode() == ISD::ZERO_EXTEND))
9844 SDValue N00 = N0.getOperand(0);
9845 SDValue N10 = N1.getOperand(0);
9847 // Look for ADD(SEXT(VUZP.0), SEXT(VUZP.1))
9848 if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() ||
9852 // We only recognize Q register paddl here; this can't be reached until
9853 // after type legalization.
9854 if (!N00.getValueType().is64BitVector() ||
9855 !N0.getValueType().is128BitVector())
9859 SelectionDAG &DAG = DCI.DAG;
9860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9862 EVT VT = N->getValueType(0);
9864 SmallVector<SDValue, 8> Ops;
9865 // Form vpaddl.sN or vpaddl.uN depending on the kind of extension.
9867 if (N0.getOpcode() == ISD::SIGN_EXTEND)
9868 Opcode = Intrinsic::arm_neon_vpaddls;
9870 Opcode = Intrinsic::arm_neon_vpaddlu;
9871 Ops.push_back(DAG.getConstant(Opcode, dl,
9872 TLI.getPointerTy(DAG.getDataLayout())));
9873 EVT ElemTy = N00.getValueType().getVectorElementType();
9874 unsigned NumElts = VT.getVectorNumElements();
9875 EVT ConcatVT = EVT::getVectorVT(*DAG.getContext(), ElemTy, NumElts * 2);
9876 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT,
9877 N00.getOperand(0), N00.getOperand(1));
9878 Ops.push_back(Concat);
9880 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);
9883 // FIXME: This function shouldn't be necessary; if we lower BUILD_VECTOR in
9884 // an appropriate manner, we end up with ADD(VUZP(ZEXT(N))), which is
9885 // much easier to match.
9887 AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
9888 TargetLowering::DAGCombinerInfo &DCI,
9889 const ARMSubtarget *Subtarget) {
9890 // Only perform optimization if after legalize, and if NEON is available. We
9891 // also expected both operands to be BUILD_VECTORs.
9892 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
9893 || N0.getOpcode() != ISD::BUILD_VECTOR
9894 || N1.getOpcode() != ISD::BUILD_VECTOR)
9897 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
9898 EVT VT = N->getValueType(0);
9899 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
9902 // Check that the vector operands are of the right form.
9903 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
9904 // operands, where N is the size of the formed vector.
9905 // Each EXTRACT_VECTOR should have the same input vector and odd or even
9906 // index such that we have a pair wise add pattern.
9908 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
9909 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9911 SDValue Vec = N0->getOperand(0)->getOperand(0);
9912 SDNode *V = Vec.getNode();
9913 unsigned nextIndex = 0;
9915 // For each operands to the ADD which are BUILD_VECTORs,
9916 // check to see if each of their operands are an EXTRACT_VECTOR with
9917 // the same vector and appropriate index.
9918 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
9919 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
9920 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9922 SDValue ExtVec0 = N0->getOperand(i);
9923 SDValue ExtVec1 = N1->getOperand(i);
9925 // First operand is the vector, verify its the same.
9926 if (V != ExtVec0->getOperand(0).getNode() ||
9927 V != ExtVec1->getOperand(0).getNode())
9930 // Second is the constant, verify its correct.
9931 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
9932 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
9934 // For the constant, we want to see all the even or all the odd.
9935 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
9936 || C1->getZExtValue() != nextIndex+1)
9945 // Don't generate vpaddl+vmovn; we'll match it to vpadd later. Also make sure
9946 // we're using the entire input vector, otherwise there's a size/legality
9947 // mismatch somewhere.
9948 if (nextIndex != Vec.getValueType().getVectorNumElements() ||
9949 Vec.getValueType().getVectorElementType() == VT.getVectorElementType())
9952 // Create VPADDL node.
9953 SelectionDAG &DAG = DCI.DAG;
9954 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9958 // Build operand list.
9959 SmallVector<SDValue, 8> Ops;
9960 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl,
9961 TLI.getPointerTy(DAG.getDataLayout())));
9963 // Input is the vector.
9966 // Get widened type and narrowed type.
9968 unsigned numElem = VT.getVectorNumElements();
9970 EVT inputLaneType = Vec.getValueType().getVectorElementType();
9971 switch (inputLaneType.getSimpleVT().SimpleTy) {
9972 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
9973 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
9974 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
9976 llvm_unreachable("Invalid vector element type for padd optimization.");
9979 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops);
9980 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
9981 return DAG.getNode(ExtOp, dl, VT, tmp);
9984 static SDValue findMUL_LOHI(SDValue V) {
9985 if (V->getOpcode() == ISD::UMUL_LOHI ||
9986 V->getOpcode() == ISD::SMUL_LOHI)
9991 static SDValue AddCombineTo64BitSMLAL16(SDNode *AddcNode, SDNode *AddeNode,
9992 TargetLowering::DAGCombinerInfo &DCI,
9993 const ARMSubtarget *Subtarget) {
9994 if (Subtarget->isThumb()) {
9995 if (!Subtarget->hasDSP())
9997 } else if (!Subtarget->hasV5TEOps())
10000 // SMLALBB, SMLALBT, SMLALTB, SMLALTT multiply two 16-bit values and
10001 // accumulates the product into a 64-bit value. The 16-bit values will
10002 // be sign extended somehow or SRA'd into 32-bit values
10003 // (addc (adde (mul 16bit, 16bit), lo), hi)
10004 SDValue Mul = AddcNode->getOperand(0);
10005 SDValue Lo = AddcNode->getOperand(1);
10006 if (Mul.getOpcode() != ISD::MUL) {
10007 Lo = AddcNode->getOperand(0);
10008 Mul = AddcNode->getOperand(1);
10009 if (Mul.getOpcode() != ISD::MUL)
10013 SDValue SRA = AddeNode->getOperand(0);
10014 SDValue Hi = AddeNode->getOperand(1);
10015 if (SRA.getOpcode() != ISD::SRA) {
10016 SRA = AddeNode->getOperand(1);
10017 Hi = AddeNode->getOperand(0);
10018 if (SRA.getOpcode() != ISD::SRA)
10021 if (auto Const = dyn_cast<ConstantSDNode>(SRA.getOperand(1))) {
10022 if (Const->getZExtValue() != 31)
10027 if (SRA.getOperand(0) != Mul)
10030 SelectionDAG &DAG = DCI.DAG;
10031 SDLoc dl(AddcNode);
10032 unsigned Opcode = 0;
10036 if (isS16(Mul.getOperand(0), DAG) && isS16(Mul.getOperand(1), DAG)) {
10037 Opcode = ARMISD::SMLALBB;
10038 Op0 = Mul.getOperand(0);
10039 Op1 = Mul.getOperand(1);
10040 } else if (isS16(Mul.getOperand(0), DAG) && isSRA16(Mul.getOperand(1))) {
10041 Opcode = ARMISD::SMLALBT;
10042 Op0 = Mul.getOperand(0);
10043 Op1 = Mul.getOperand(1).getOperand(0);
10044 } else if (isSRA16(Mul.getOperand(0)) && isS16(Mul.getOperand(1), DAG)) {
10045 Opcode = ARMISD::SMLALTB;
10046 Op0 = Mul.getOperand(0).getOperand(0);
10047 Op1 = Mul.getOperand(1);
10048 } else if (isSRA16(Mul.getOperand(0)) && isSRA16(Mul.getOperand(1))) {
10049 Opcode = ARMISD::SMLALTT;
10050 Op0 = Mul->getOperand(0).getOperand(0);
10051 Op1 = Mul->getOperand(1).getOperand(0);
10057 SDValue SMLAL = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
10059 // Replace the ADDs' nodes uses by the MLA node's values.
10060 SDValue HiMLALResult(SMLAL.getNode(), 1);
10061 SDValue LoMLALResult(SMLAL.getNode(), 0);
10063 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
10064 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
10066 // Return original node to notify the driver to stop replacing.
10067 SDValue resNode(AddcNode, 0);
10071 static SDValue AddCombineTo64bitMLAL(SDNode *AddeSubeNode,
10072 TargetLowering::DAGCombinerInfo &DCI,
10073 const ARMSubtarget *Subtarget) {
10074 // Look for multiply add opportunities.
10075 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
10076 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
10077 // a glue link from the first add to the second add.
10078 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
10079 // a S/UMLAL instruction.
10082 // V \ [no multiline comment]
10088 // In the special case where only the higher part of a signed result is used
10089 // and the add to the low part of the result of ISD::UMUL_LOHI adds or subtracts
10090 // a constant with the exact value of 0x80000000, we recognize we are dealing
10091 // with a "rounded multiply and add" (or subtract) and transform it into
10092 // either a ARMISD::SMMLAR or ARMISD::SMMLSR respectively.
10094 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE ||
10095 AddeSubeNode->getOpcode() == ARMISD::SUBE) &&
10096 "Expect an ADDE or SUBE");
10098 assert(AddeSubeNode->getNumOperands() == 3 &&
10099 AddeSubeNode->getOperand(2).getValueType() == MVT::i32 &&
10100 "ADDE node has the wrong inputs");
10102 // Check that we are chained to the right ADDC or SUBC node.
10103 SDNode *AddcSubcNode = AddeSubeNode->getOperand(2).getNode();
10104 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE &&
10105 AddcSubcNode->getOpcode() != ARMISD::ADDC) ||
10106 (AddeSubeNode->getOpcode() == ARMISD::SUBE &&
10107 AddcSubcNode->getOpcode() != ARMISD::SUBC))
10110 SDValue AddcSubcOp0 = AddcSubcNode->getOperand(0);
10111 SDValue AddcSubcOp1 = AddcSubcNode->getOperand(1);
10113 // Check if the two operands are from the same mul_lohi node.
10114 if (AddcSubcOp0.getNode() == AddcSubcOp1.getNode())
10117 assert(AddcSubcNode->getNumValues() == 2 &&
10118 AddcSubcNode->getValueType(0) == MVT::i32 &&
10119 "Expect ADDC with two result values. First: i32");
10121 // Check that the ADDC adds the low result of the S/UMUL_LOHI. If not, it
10122 // maybe a SMLAL which multiplies two 16-bit values.
10123 if (AddeSubeNode->getOpcode() == ARMISD::ADDE &&
10124 AddcSubcOp0->getOpcode() != ISD::UMUL_LOHI &&
10125 AddcSubcOp0->getOpcode() != ISD::SMUL_LOHI &&
10126 AddcSubcOp1->getOpcode() != ISD::UMUL_LOHI &&
10127 AddcSubcOp1->getOpcode() != ISD::SMUL_LOHI)
10128 return AddCombineTo64BitSMLAL16(AddcSubcNode, AddeSubeNode, DCI, Subtarget);
10130 // Check for the triangle shape.
10131 SDValue AddeSubeOp0 = AddeSubeNode->getOperand(0);
10132 SDValue AddeSubeOp1 = AddeSubeNode->getOperand(1);
10134 // Make sure that the ADDE/SUBE operands are not coming from the same node.
10135 if (AddeSubeOp0.getNode() == AddeSubeOp1.getNode())
10138 // Find the MUL_LOHI node walking up ADDE/SUBE's operands.
10139 bool IsLeftOperandMUL = false;
10140 SDValue MULOp = findMUL_LOHI(AddeSubeOp0);
10141 if (MULOp == SDValue())
10142 MULOp = findMUL_LOHI(AddeSubeOp1);
10144 IsLeftOperandMUL = true;
10145 if (MULOp == SDValue())
10148 // Figure out the right opcode.
10149 unsigned Opc = MULOp->getOpcode();
10150 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
10152 // Figure out the high and low input values to the MLAL node.
10153 SDValue *HiAddSub = nullptr;
10154 SDValue *LoMul = nullptr;
10155 SDValue *LowAddSub = nullptr;
10157 // Ensure that ADDE/SUBE is from high result of ISD::xMUL_LOHI.
10158 if ((AddeSubeOp0 != MULOp.getValue(1)) && (AddeSubeOp1 != MULOp.getValue(1)))
10161 if (IsLeftOperandMUL)
10162 HiAddSub = &AddeSubeOp1;
10164 HiAddSub = &AddeSubeOp0;
10166 // Ensure that LoMul and LowAddSub are taken from correct ISD::SMUL_LOHI node
10167 // whose low result is fed to the ADDC/SUBC we are checking.
10169 if (AddcSubcOp0 == MULOp.getValue(0)) {
10170 LoMul = &AddcSubcOp0;
10171 LowAddSub = &AddcSubcOp1;
10173 if (AddcSubcOp1 == MULOp.getValue(0)) {
10174 LoMul = &AddcSubcOp1;
10175 LowAddSub = &AddcSubcOp0;
10181 // If HiAddSub is the same node as ADDC/SUBC or is a predecessor of ADDC/SUBC
10182 // the replacement below will create a cycle.
10183 if (AddcSubcNode == HiAddSub->getNode() ||
10184 AddcSubcNode->isPredecessorOf(HiAddSub->getNode()))
10187 // Create the merged node.
10188 SelectionDAG &DAG = DCI.DAG;
10190 // Start building operand list.
10191 SmallVector<SDValue, 8> Ops;
10192 Ops.push_back(LoMul->getOperand(0));
10193 Ops.push_back(LoMul->getOperand(1));
10195 // Check whether we can use SMMLAR, SMMLSR or SMMULR instead. For this to be
10196 // the case, we must be doing signed multiplication and only use the higher
10197 // part of the result of the MLAL, furthermore the LowAddSub must be a constant
10198 // addition or subtraction with the value of 0x800000.
10199 if (Subtarget->hasV6Ops() && Subtarget->hasDSP() && Subtarget->useMulOps() &&
10200 FinalOpc == ARMISD::SMLAL && !AddeSubeNode->hasAnyUseOfValue(1) &&
10201 LowAddSub->getNode()->getOpcode() == ISD::Constant &&
10202 static_cast<ConstantSDNode *>(LowAddSub->getNode())->getZExtValue() ==
10204 Ops.push_back(*HiAddSub);
10205 if (AddcSubcNode->getOpcode() == ARMISD::SUBC) {
10206 FinalOpc = ARMISD::SMMLSR;
10208 FinalOpc = ARMISD::SMMLAR;
10210 SDValue NewNode = DAG.getNode(FinalOpc, SDLoc(AddcSubcNode), MVT::i32, Ops);
10211 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeSubeNode, 0), NewNode);
10213 return SDValue(AddeSubeNode, 0);
10214 } else if (AddcSubcNode->getOpcode() == ARMISD::SUBC)
10215 // SMMLS is generated during instruction selection and the rest of this
10216 // function can not handle the case where AddcSubcNode is a SUBC.
10219 // Finish building the operand list for {U/S}MLAL
10220 Ops.push_back(*LowAddSub);
10221 Ops.push_back(*HiAddSub);
10223 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcSubcNode),
10224 DAG.getVTList(MVT::i32, MVT::i32), Ops);
10226 // Replace the ADDs' nodes uses by the MLA node's values.
10227 SDValue HiMLALResult(MLALNode.getNode(), 1);
10228 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeSubeNode, 0), HiMLALResult);
10230 SDValue LoMLALResult(MLALNode.getNode(), 0);
10231 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcSubcNode, 0), LoMLALResult);
10233 // Return original node to notify the driver to stop replacing.
10234 return SDValue(AddeSubeNode, 0);
10237 static SDValue AddCombineTo64bitUMAAL(SDNode *AddeNode,
10238 TargetLowering::DAGCombinerInfo &DCI,
10239 const ARMSubtarget *Subtarget) {
10240 // UMAAL is similar to UMLAL except that it adds two unsigned values.
10241 // While trying to combine for the other MLAL nodes, first search for the
10242 // chance to use UMAAL. Check if Addc uses a node which has already
10243 // been combined into a UMLAL. The other pattern is UMLAL using Addc/Adde
10244 // as the addend, and it's handled in PerformUMLALCombine.
10246 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
10247 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget);
10249 // Check that we have a glued ADDC node.
10250 SDNode* AddcNode = AddeNode->getOperand(2).getNode();
10251 if (AddcNode->getOpcode() != ARMISD::ADDC)
10254 // Find the converted UMAAL or quit if it doesn't exist.
10255 SDNode *UmlalNode = nullptr;
10257 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) {
10258 UmlalNode = AddcNode->getOperand(0).getNode();
10259 AddHi = AddcNode->getOperand(1);
10260 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) {
10261 UmlalNode = AddcNode->getOperand(1).getNode();
10262 AddHi = AddcNode->getOperand(0);
10264 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget);
10267 // The ADDC should be glued to an ADDE node, which uses the same UMLAL as
10268 // the ADDC as well as Zero.
10269 if (!isNullConstant(UmlalNode->getOperand(3)))
10272 if ((isNullConstant(AddeNode->getOperand(0)) &&
10273 AddeNode->getOperand(1).getNode() == UmlalNode) ||
10274 (AddeNode->getOperand(0).getNode() == UmlalNode &&
10275 isNullConstant(AddeNode->getOperand(1)))) {
10276 SelectionDAG &DAG = DCI.DAG;
10277 SDValue Ops[] = { UmlalNode->getOperand(0), UmlalNode->getOperand(1),
10278 UmlalNode->getOperand(2), AddHi };
10279 SDValue UMAAL = DAG.getNode(ARMISD::UMAAL, SDLoc(AddcNode),
10280 DAG.getVTList(MVT::i32, MVT::i32), Ops);
10282 // Replace the ADDs' nodes uses by the UMAAL node's values.
10283 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), SDValue(UMAAL.getNode(), 1));
10284 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), SDValue(UMAAL.getNode(), 0));
10286 // Return original node to notify the driver to stop replacing.
10287 return SDValue(AddeNode, 0);
10292 static SDValue PerformUMLALCombine(SDNode *N, SelectionDAG &DAG,
10293 const ARMSubtarget *Subtarget) {
10294 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
10297 // Check that we have a pair of ADDC and ADDE as operands.
10298 // Both addends of the ADDE must be zero.
10299 SDNode* AddcNode = N->getOperand(2).getNode();
10300 SDNode* AddeNode = N->getOperand(3).getNode();
10301 if ((AddcNode->getOpcode() == ARMISD::ADDC) &&
10302 (AddeNode->getOpcode() == ARMISD::ADDE) &&
10303 isNullConstant(AddeNode->getOperand(0)) &&
10304 isNullConstant(AddeNode->getOperand(1)) &&
10305 (AddeNode->getOperand(2).getNode() == AddcNode))
10306 return DAG.getNode(ARMISD::UMAAL, SDLoc(N),
10307 DAG.getVTList(MVT::i32, MVT::i32),
10308 {N->getOperand(0), N->getOperand(1),
10309 AddcNode->getOperand(0), AddcNode->getOperand(1)});
10314 static SDValue PerformAddcSubcCombine(SDNode *N,
10315 TargetLowering::DAGCombinerInfo &DCI,
10316 const ARMSubtarget *Subtarget) {
10317 SelectionDAG &DAG(DCI.DAG);
10319 if (N->getOpcode() == ARMISD::SUBC) {
10320 // (SUBC (ADDE 0, 0, C), 1) -> C
10321 SDValue LHS = N->getOperand(0);
10322 SDValue RHS = N->getOperand(1);
10323 if (LHS->getOpcode() == ARMISD::ADDE &&
10324 isNullConstant(LHS->getOperand(0)) &&
10325 isNullConstant(LHS->getOperand(1)) && isOneConstant(RHS)) {
10326 return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
10330 if (Subtarget->isThumb1Only()) {
10331 SDValue RHS = N->getOperand(1);
10332 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
10333 int32_t imm = C->getSExtValue();
10334 if (imm < 0 && imm > std::numeric_limits<int>::min()) {
10336 RHS = DAG.getConstant(-imm, DL, MVT::i32);
10337 unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
10339 return DAG.getNode(Opcode, DL, N->getVTList(), N->getOperand(0), RHS);
10347 static SDValue PerformAddeSubeCombine(SDNode *N,
10348 TargetLowering::DAGCombinerInfo &DCI,
10349 const ARMSubtarget *Subtarget) {
10350 if (Subtarget->isThumb1Only()) {
10351 SelectionDAG &DAG = DCI.DAG;
10352 SDValue RHS = N->getOperand(1);
10353 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
10354 int64_t imm = C->getSExtValue();
10358 // The with-carry-in form matches bitwise not instead of the negation.
10359 // Effectively, the inverse interpretation of the carry flag already
10360 // accounts for part of the negation.
10361 RHS = DAG.getConstant(~imm, DL, MVT::i32);
10363 unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE
10365 return DAG.getNode(Opcode, DL, N->getVTList(),
10366 N->getOperand(0), RHS, N->getOperand(2));
10369 } else if (N->getOperand(1)->getOpcode() == ISD::SMUL_LOHI) {
10370 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
10375 /// PerformADDECombine - Target-specific dag combine transform from
10376 /// ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or
10377 /// ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL
10378 static SDValue PerformADDECombine(SDNode *N,
10379 TargetLowering::DAGCombinerInfo &DCI,
10380 const ARMSubtarget *Subtarget) {
10381 // Only ARM and Thumb2 support UMLAL/SMLAL.
10382 if (Subtarget->isThumb1Only())
10383 return PerformAddeSubeCombine(N, DCI, Subtarget);
10385 // Only perform the checks after legalize when the pattern is available.
10386 if (DCI.isBeforeLegalize()) return SDValue();
10388 return AddCombineTo64bitUMAAL(N, DCI, Subtarget);
10391 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
10392 /// operands N0 and N1. This is a helper for PerformADDCombine that is
10393 /// called with the default operands, and if that fails, with commuted
10395 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
10396 TargetLowering::DAGCombinerInfo &DCI,
10397 const ARMSubtarget *Subtarget){
10398 // Attempt to create vpadd for this add.
10399 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget))
10402 // Attempt to create vpaddl for this add.
10403 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget))
10405 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI,
10409 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
10410 if (N0.getNode()->hasOneUse())
10411 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI))
10417 ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
10418 CombineLevel Level) const {
10419 if (Level == BeforeLegalizeTypes)
10422 if (Subtarget->isThumb() && Subtarget->isThumb1Only())
10425 if (N->getOpcode() != ISD::SHL)
10428 // Turn off commute-with-shift transform after legalization, so it doesn't
10429 // conflict with PerformSHLSimplify. (We could try to detect when
10430 // PerformSHLSimplify would trigger more precisely, but it isn't
10431 // really necessary.)
10436 ARMTargetLowering::shouldFoldShiftPairToMask(const SDNode *N,
10437 CombineLevel Level) const {
10438 if (!Subtarget->isThumb1Only())
10441 if (Level == BeforeLegalizeTypes)
10447 static SDValue PerformSHLSimplify(SDNode *N,
10448 TargetLowering::DAGCombinerInfo &DCI,
10449 const ARMSubtarget *ST) {
10450 // Allow the generic combiner to identify potential bswaps.
10451 if (DCI.isBeforeLegalize())
10454 // DAG combiner will fold:
10455 // (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
10456 // (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2
10457 // Other code patterns that can be also be modified have the following form:
10458 // b + ((a << 1) | 510)
10459 // b + ((a << 1) & 510)
10460 // b + ((a << 1) ^ 510)
10461 // b + ((a << 1) + 510)
10463 // Many instructions can perform the shift for free, but it requires both
10464 // the operands to be registers. If c1 << c2 is too large, a mov immediate
10465 // instruction will needed. So, unfold back to the original pattern if:
10466 // - if c1 and c2 are small enough that they don't require mov imms.
10467 // - the user(s) of the node can perform an shl
10469 // No shifted operands for 16-bit instructions.
10470 if (ST->isThumb() && ST->isThumb1Only())
10473 // Check that all the users could perform the shl themselves.
10474 for (auto U : N->uses()) {
10475 switch(U->getOpcode()) {
10485 // Check that the user isn't already using a constant because there
10486 // aren't any instructions that support an immediate operand and a
10487 // shifted operand.
10488 if (isa<ConstantSDNode>(U->getOperand(0)) ||
10489 isa<ConstantSDNode>(U->getOperand(1)))
10492 // Check that it's not already using a shift.
10493 if (U->getOperand(0).getOpcode() == ISD::SHL ||
10494 U->getOperand(1).getOpcode() == ISD::SHL)
10500 if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::OR &&
10501 N->getOpcode() != ISD::XOR && N->getOpcode() != ISD::AND)
10504 if (N->getOperand(0).getOpcode() != ISD::SHL)
10507 SDValue SHL = N->getOperand(0);
10509 auto *C1ShlC2 = dyn_cast<ConstantSDNode>(N->getOperand(1));
10510 auto *C2 = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
10511 if (!C1ShlC2 || !C2)
10514 APInt C2Int = C2->getAPIntValue();
10515 APInt C1Int = C1ShlC2->getAPIntValue();
10517 // Check that performing a lshr will not lose any information.
10518 APInt Mask = APInt::getHighBitsSet(C2Int.getBitWidth(),
10519 C2Int.getBitWidth() - C2->getZExtValue());
10520 if ((C1Int & Mask) != C1Int)
10523 // Shift the first constant.
10524 C1Int.lshrInPlace(C2Int);
10526 // The immediates are encoded as an 8-bit value that can be rotated.
10527 auto LargeImm = [](const APInt &Imm) {
10528 unsigned Zeros = Imm.countLeadingZeros() + Imm.countTrailingZeros();
10529 return Imm.getBitWidth() - Zeros > 8;
10532 if (LargeImm(C1Int) || LargeImm(C2Int))
10535 SelectionDAG &DAG = DCI.DAG;
10537 SDValue X = SHL.getOperand(0);
10538 SDValue BinOp = DAG.getNode(N->getOpcode(), dl, MVT::i32, X,
10539 DAG.getConstant(C1Int, dl, MVT::i32));
10540 // Shift left to compensate for the lshr of C1Int.
10541 SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1));
10543 LLVM_DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump();
10544 SHL.dump(); N->dump());
10545 LLVM_DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump());
10550 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
10552 static SDValue PerformADDCombine(SDNode *N,
10553 TargetLowering::DAGCombinerInfo &DCI,
10554 const ARMSubtarget *Subtarget) {
10555 SDValue N0 = N->getOperand(0);
10556 SDValue N1 = N->getOperand(1);
10558 // Only works one way, because it needs an immediate operand.
10559 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
10562 // First try with the default operand order.
10563 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget))
10566 // If that didn't work, try again with the operands commuted.
10567 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
10570 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
10572 static SDValue PerformSUBCombine(SDNode *N,
10573 TargetLowering::DAGCombinerInfo &DCI) {
10574 SDValue N0 = N->getOperand(0);
10575 SDValue N1 = N->getOperand(1);
10577 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
10578 if (N1.getNode()->hasOneUse())
10579 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI))
10585 /// PerformVMULCombine
10586 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
10587 /// special multiplier accumulator forwarding.
10588 /// vmul d3, d0, d2
10589 /// vmla d3, d1, d2
10591 /// vadd d3, d0, d1
10592 /// vmul d3, d3, d2
10593 // However, for (A + B) * (A + B),
10600 static SDValue PerformVMULCombine(SDNode *N,
10601 TargetLowering::DAGCombinerInfo &DCI,
10602 const ARMSubtarget *Subtarget) {
10603 if (!Subtarget->hasVMLxForwarding())
10606 SelectionDAG &DAG = DCI.DAG;
10607 SDValue N0 = N->getOperand(0);
10608 SDValue N1 = N->getOperand(1);
10609 unsigned Opcode = N0.getOpcode();
10610 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
10611 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
10612 Opcode = N1.getOpcode();
10613 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
10614 Opcode != ISD::FADD && Opcode != ISD::FSUB)
10622 EVT VT = N->getValueType(0);
10624 SDValue N00 = N0->getOperand(0);
10625 SDValue N01 = N0->getOperand(1);
10626 return DAG.getNode(Opcode, DL, VT,
10627 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
10628 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
10631 static SDValue PerformMULCombine(SDNode *N,
10632 TargetLowering::DAGCombinerInfo &DCI,
10633 const ARMSubtarget *Subtarget) {
10634 SelectionDAG &DAG = DCI.DAG;
10636 if (Subtarget->isThumb1Only())
10639 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10642 EVT VT = N->getValueType(0);
10643 if (VT.is64BitVector() || VT.is128BitVector())
10644 return PerformVMULCombine(N, DCI, Subtarget);
10645 if (VT != MVT::i32)
10648 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10652 int64_t MulAmt = C->getSExtValue();
10653 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
10655 ShiftAmt = ShiftAmt & (32 - 1);
10656 SDValue V = N->getOperand(0);
10660 MulAmt >>= ShiftAmt;
10663 if (isPowerOf2_32(MulAmt - 1)) {
10664 // (mul x, 2^N + 1) => (add (shl x, N), x)
10665 Res = DAG.getNode(ISD::ADD, DL, VT,
10667 DAG.getNode(ISD::SHL, DL, VT,
10669 DAG.getConstant(Log2_32(MulAmt - 1), DL,
10671 } else if (isPowerOf2_32(MulAmt + 1)) {
10672 // (mul x, 2^N - 1) => (sub (shl x, N), x)
10673 Res = DAG.getNode(ISD::SUB, DL, VT,
10674 DAG.getNode(ISD::SHL, DL, VT,
10676 DAG.getConstant(Log2_32(MulAmt + 1), DL,
10682 uint64_t MulAmtAbs = -MulAmt;
10683 if (isPowerOf2_32(MulAmtAbs + 1)) {
10684 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
10685 Res = DAG.getNode(ISD::SUB, DL, VT,
10687 DAG.getNode(ISD::SHL, DL, VT,
10689 DAG.getConstant(Log2_32(MulAmtAbs + 1), DL,
10691 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
10692 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
10693 Res = DAG.getNode(ISD::ADD, DL, VT,
10695 DAG.getNode(ISD::SHL, DL, VT,
10697 DAG.getConstant(Log2_32(MulAmtAbs - 1), DL,
10699 Res = DAG.getNode(ISD::SUB, DL, VT,
10700 DAG.getConstant(0, DL, MVT::i32), Res);
10706 Res = DAG.getNode(ISD::SHL, DL, VT,
10707 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32));
10709 // Do not add new nodes to DAG combiner worklist.
10710 DCI.CombineTo(N, Res, false);
10714 static SDValue CombineANDShift(SDNode *N,
10715 TargetLowering::DAGCombinerInfo &DCI,
10716 const ARMSubtarget *Subtarget) {
10717 // Allow DAGCombine to pattern-match before we touch the canonical form.
10718 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10721 if (N->getValueType(0) != MVT::i32)
10724 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10728 uint32_t C1 = (uint32_t)N1C->getZExtValue();
10729 // Don't transform uxtb/uxth.
10730 if (C1 == 255 || C1 == 65535)
10733 SDNode *N0 = N->getOperand(0).getNode();
10734 if (!N0->hasOneUse())
10737 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
10740 bool LeftShift = N0->getOpcode() == ISD::SHL;
10742 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0->getOperand(1));
10746 uint32_t C2 = (uint32_t)N01C->getZExtValue();
10747 if (!C2 || C2 >= 32)
10750 // Clear irrelevant bits in the mask.
10756 SelectionDAG &DAG = DCI.DAG;
10759 // We have a pattern of the form "(and (shl x, c2) c1)" or
10760 // "(and (srl x, c2) c1)", where c1 is a shifted mask. Try to
10761 // transform to a pair of shifts, to save materializing c1.
10763 // First pattern: right shift, then mask off leading bits.
10764 // FIXME: Use demanded bits?
10765 if (!LeftShift && isMask_32(C1)) {
10766 uint32_t C3 = countLeadingZeros(C1);
10768 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
10769 DAG.getConstant(C3 - C2, DL, MVT::i32));
10770 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
10771 DAG.getConstant(C3, DL, MVT::i32));
10775 // First pattern, reversed: left shift, then mask off trailing bits.
10776 if (LeftShift && isMask_32(~C1)) {
10777 uint32_t C3 = countTrailingZeros(C1);
10779 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
10780 DAG.getConstant(C3 - C2, DL, MVT::i32));
10781 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
10782 DAG.getConstant(C3, DL, MVT::i32));
10786 // Second pattern: left shift, then mask off leading bits.
10787 // FIXME: Use demanded bits?
10788 if (LeftShift && isShiftedMask_32(C1)) {
10789 uint32_t Trailing = countTrailingZeros(C1);
10790 uint32_t C3 = countLeadingZeros(C1);
10791 if (Trailing == C2 && C2 + C3 < 32) {
10792 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
10793 DAG.getConstant(C2 + C3, DL, MVT::i32));
10794 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
10795 DAG.getConstant(C3, DL, MVT::i32));
10799 // Second pattern, reversed: right shift, then mask off trailing bits.
10800 // FIXME: Handle other patterns of known/demanded bits.
10801 if (!LeftShift && isShiftedMask_32(C1)) {
10802 uint32_t Leading = countLeadingZeros(C1);
10803 uint32_t C3 = countTrailingZeros(C1);
10804 if (Leading == C2 && C2 + C3 < 32) {
10805 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
10806 DAG.getConstant(C2 + C3, DL, MVT::i32));
10807 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
10808 DAG.getConstant(C3, DL, MVT::i32));
10812 // FIXME: Transform "(and (shl x, c2) c1)" ->
10813 // "(shl (and x, c1>>c2), c2)" if "c1 >> c2" is a cheaper immediate than
10818 static SDValue PerformANDCombine(SDNode *N,
10819 TargetLowering::DAGCombinerInfo &DCI,
10820 const ARMSubtarget *Subtarget) {
10821 // Attempt to use immediate-form VBIC
10822 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
10824 EVT VT = N->getValueType(0);
10825 SelectionDAG &DAG = DCI.DAG;
10827 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10830 APInt SplatBits, SplatUndef;
10831 unsigned SplatBitSize;
10834 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
10835 if (SplatBitSize <= 64) {
10837 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
10838 SplatUndef.getZExtValue(), SplatBitSize,
10839 DAG, dl, VbicVT, VT.is128BitVector(),
10841 if (Val.getNode()) {
10843 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
10844 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
10845 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
10850 if (!Subtarget->isThumb1Only()) {
10851 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
10852 if (SDValue Result = combineSelectAndUseCommutative(N, true, DCI))
10855 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
10859 if (Subtarget->isThumb1Only())
10860 if (SDValue Result = CombineANDShift(N, DCI, Subtarget))
10866 // Try combining OR nodes to SMULWB, SMULWT.
10867 static SDValue PerformORCombineToSMULWBT(SDNode *OR,
10868 TargetLowering::DAGCombinerInfo &DCI,
10869 const ARMSubtarget *Subtarget) {
10870 if (!Subtarget->hasV6Ops() ||
10871 (Subtarget->isThumb() &&
10872 (!Subtarget->hasThumb2() || !Subtarget->hasDSP())))
10875 SDValue SRL = OR->getOperand(0);
10876 SDValue SHL = OR->getOperand(1);
10878 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
10879 SRL = OR->getOperand(1);
10880 SHL = OR->getOperand(0);
10882 if (!isSRL16(SRL) || !isSHL16(SHL))
10885 // The first operands to the shifts need to be the two results from the
10886 // same smul_lohi node.
10887 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) ||
10888 SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI)
10891 SDNode *SMULLOHI = SRL.getOperand(0).getNode();
10892 if (SRL.getOperand(0) != SDValue(SMULLOHI, 0) ||
10893 SHL.getOperand(0) != SDValue(SMULLOHI, 1))
10897 // (or (srl (smul_lohi ?, ?), 16), (shl (smul_lohi ?, ?), 16)))
10898 // For SMUL[B|T] smul_lohi will take a 32-bit and a 16-bit arguments.
10899 // For SMUWB the 16-bit value will signed extended somehow.
10900 // For SMULWT only the SRA is required.
10901 // Check both sides of SMUL_LOHI
10902 SDValue OpS16 = SMULLOHI->getOperand(0);
10903 SDValue OpS32 = SMULLOHI->getOperand(1);
10905 SelectionDAG &DAG = DCI.DAG;
10906 if (!isS16(OpS16, DAG) && !isSRA16(OpS16)) {
10908 OpS32 = SMULLOHI->getOperand(0);
10912 unsigned Opcode = 0;
10913 if (isS16(OpS16, DAG))
10914 Opcode = ARMISD::SMULWB;
10915 else if (isSRA16(OpS16)) {
10916 Opcode = ARMISD::SMULWT;
10917 OpS16 = OpS16->getOperand(0);
10922 SDValue Res = DAG.getNode(Opcode, dl, MVT::i32, OpS32, OpS16);
10923 DAG.ReplaceAllUsesOfValueWith(SDValue(OR, 0), Res);
10924 return SDValue(OR, 0);
10927 static SDValue PerformORCombineToBFI(SDNode *N,
10928 TargetLowering::DAGCombinerInfo &DCI,
10929 const ARMSubtarget *Subtarget) {
10930 // BFI is only available on V6T2+
10931 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
10934 EVT VT = N->getValueType(0);
10935 SDValue N0 = N->getOperand(0);
10936 SDValue N1 = N->getOperand(1);
10937 SelectionDAG &DAG = DCI.DAG;
10939 // 1) or (and A, mask), val => ARMbfi A, val, mask
10940 // iff (val & mask) == val
10942 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
10943 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
10944 // && mask == ~mask2
10945 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
10946 // && ~mask == mask2
10947 // (i.e., copy a bitfield value into another bitfield of the same width)
10949 if (VT != MVT::i32)
10952 SDValue N00 = N0.getOperand(0);
10954 // The value and the mask need to be constants so we can verify this is
10955 // actually a bitfield set. If the mask is 0xffff, we can do better
10956 // via a movt instruction, so don't use BFI in that case.
10957 SDValue MaskOp = N0.getOperand(1);
10958 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
10961 unsigned Mask = MaskC->getZExtValue();
10962 if (Mask == 0xffff)
10965 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
10966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10968 unsigned Val = N1C->getZExtValue();
10969 if ((Val & ~Mask) != Val)
10972 if (ARM::isBitFieldInvertedMask(Mask)) {
10973 Val >>= countTrailingZeros(~Mask);
10975 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
10976 DAG.getConstant(Val, DL, MVT::i32),
10977 DAG.getConstant(Mask, DL, MVT::i32));
10979 DCI.CombineTo(N, Res, false);
10980 // Return value from the original node to inform the combiner than N is
10982 return SDValue(N, 0);
10984 } else if (N1.getOpcode() == ISD::AND) {
10985 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
10986 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
10989 unsigned Mask2 = N11C->getZExtValue();
10991 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
10993 if (ARM::isBitFieldInvertedMask(Mask) &&
10994 (Mask == ~Mask2)) {
10995 // The pack halfword instruction works better for masks that fit it,
10996 // so use that when it's available.
10997 if (Subtarget->hasDSP() &&
10998 (Mask == 0xffff || Mask == 0xffff0000))
11001 unsigned amt = countTrailingZeros(Mask2);
11002 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
11003 DAG.getConstant(amt, DL, MVT::i32));
11004 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
11005 DAG.getConstant(Mask, DL, MVT::i32));
11006 DCI.CombineTo(N, Res, false);
11007 // Return value from the original node to inform the combiner than N is
11009 return SDValue(N, 0);
11010 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
11011 (~Mask == Mask2)) {
11012 // The pack halfword instruction works better for masks that fit it,
11013 // so use that when it's available.
11014 if (Subtarget->hasDSP() &&
11015 (Mask2 == 0xffff || Mask2 == 0xffff0000))
11018 unsigned lsb = countTrailingZeros(Mask);
11019 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
11020 DAG.getConstant(lsb, DL, MVT::i32));
11021 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
11022 DAG.getConstant(Mask2, DL, MVT::i32));
11023 DCI.CombineTo(N, Res, false);
11024 // Return value from the original node to inform the combiner than N is
11026 return SDValue(N, 0);
11030 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
11031 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
11032 ARM::isBitFieldInvertedMask(~Mask)) {
11033 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
11034 // where lsb(mask) == #shamt and masked bits of B are known zero.
11035 SDValue ShAmt = N00.getOperand(1);
11036 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
11037 unsigned LSB = countTrailingZeros(Mask);
11041 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
11042 DAG.getConstant(~Mask, DL, MVT::i32));
11044 DCI.CombineTo(N, Res, false);
11045 // Return value from the original node to inform the combiner than N is
11047 return SDValue(N, 0);
11053 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
11054 static SDValue PerformORCombine(SDNode *N,
11055 TargetLowering::DAGCombinerInfo &DCI,
11056 const ARMSubtarget *Subtarget) {
11057 // Attempt to use immediate-form VORR
11058 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
11060 EVT VT = N->getValueType(0);
11061 SelectionDAG &DAG = DCI.DAG;
11063 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11066 APInt SplatBits, SplatUndef;
11067 unsigned SplatBitSize;
11069 if (BVN && Subtarget->hasNEON() &&
11070 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
11071 if (SplatBitSize <= 64) {
11073 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
11074 SplatUndef.getZExtValue(), SplatBitSize,
11075 DAG, dl, VorrVT, VT.is128BitVector(),
11077 if (Val.getNode()) {
11079 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
11080 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
11081 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
11086 if (!Subtarget->isThumb1Only()) {
11087 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
11088 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI))
11090 if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget))
11094 SDValue N0 = N->getOperand(0);
11095 SDValue N1 = N->getOperand(1);
11097 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
11098 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
11099 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11101 // The code below optimizes (or (and X, Y), Z).
11102 // The AND operand needs to have a single user to make these optimizations
11104 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
11108 unsigned SplatBitSize;
11111 APInt SplatBits0, SplatBits1;
11112 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
11113 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
11114 // Ensure that the second operand of both ands are constants
11115 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
11116 HasAnyUndefs) && !HasAnyUndefs) {
11117 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
11118 HasAnyUndefs) && !HasAnyUndefs) {
11119 // Ensure that the bit width of the constants are the same and that
11120 // the splat arguments are logical inverses as per the pattern we
11121 // are trying to simplify.
11122 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
11123 SplatBits0 == ~SplatBits1) {
11124 // Canonicalize the vector type to make instruction selection
11126 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
11127 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
11130 N1->getOperand(0));
11131 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
11137 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
11139 if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
11140 if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget))
11144 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
11150 static SDValue PerformXORCombine(SDNode *N,
11151 TargetLowering::DAGCombinerInfo &DCI,
11152 const ARMSubtarget *Subtarget) {
11153 EVT VT = N->getValueType(0);
11154 SelectionDAG &DAG = DCI.DAG;
11156 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11159 if (!Subtarget->isThumb1Only()) {
11160 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
11161 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI))
11164 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
11171 // ParseBFI - given a BFI instruction in N, extract the "from" value (Rn) and return it,
11172 // and fill in FromMask and ToMask with (consecutive) bits in "from" to be extracted and
11173 // their position in "to" (Rd).
11174 static SDValue ParseBFI(SDNode *N, APInt &ToMask, APInt &FromMask) {
11175 assert(N->getOpcode() == ARMISD::BFI);
11177 SDValue From = N->getOperand(1);
11178 ToMask = ~cast<ConstantSDNode>(N->getOperand(2))->getAPIntValue();
11179 FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.countPopulation());
11181 // If the Base came from a SHR #C, we can deduce that it is really testing bit
11182 // #C in the base of the SHR.
11183 if (From->getOpcode() == ISD::SRL &&
11184 isa<ConstantSDNode>(From->getOperand(1))) {
11185 APInt Shift = cast<ConstantSDNode>(From->getOperand(1))->getAPIntValue();
11186 assert(Shift.getLimitedValue() < 32 && "Shift too large!");
11187 FromMask <<= Shift.getLimitedValue(31);
11188 From = From->getOperand(0);
11194 // If A and B contain one contiguous set of bits, does A | B == A . B?
11196 // Neither A nor B must be zero.
11197 static bool BitsProperlyConcatenate(const APInt &A, const APInt &B) {
11198 unsigned LastActiveBitInA = A.countTrailingZeros();
11199 unsigned FirstActiveBitInB = B.getBitWidth() - B.countLeadingZeros() - 1;
11200 return LastActiveBitInA - 1 == FirstActiveBitInB;
11203 static SDValue FindBFIToCombineWith(SDNode *N) {
11204 // We have a BFI in N. Follow a possible chain of BFIs and find a BFI it can combine with,
11206 APInt ToMask, FromMask;
11207 SDValue From = ParseBFI(N, ToMask, FromMask);
11208 SDValue To = N->getOperand(0);
11210 // Now check for a compatible BFI to merge with. We can pass through BFIs that
11211 // aren't compatible, but not if they set the same bit in their destination as
11212 // we do (or that of any BFI we're going to combine with).
11214 APInt CombinedToMask = ToMask;
11215 while (V.getOpcode() == ARMISD::BFI) {
11216 APInt NewToMask, NewFromMask;
11217 SDValue NewFrom = ParseBFI(V.getNode(), NewToMask, NewFromMask);
11218 if (NewFrom != From) {
11219 // This BFI has a different base. Keep going.
11220 CombinedToMask |= NewToMask;
11221 V = V.getOperand(0);
11225 // Do the written bits conflict with any we've seen so far?
11226 if ((NewToMask & CombinedToMask).getBoolValue())
11227 // Conflicting bits - bail out because going further is unsafe.
11230 // Are the new bits contiguous when combined with the old bits?
11231 if (BitsProperlyConcatenate(ToMask, NewToMask) &&
11232 BitsProperlyConcatenate(FromMask, NewFromMask))
11234 if (BitsProperlyConcatenate(NewToMask, ToMask) &&
11235 BitsProperlyConcatenate(NewFromMask, FromMask))
11238 // We've seen a write to some bits, so track it.
11239 CombinedToMask |= NewToMask;
11241 V = V.getOperand(0);
11247 static SDValue PerformBFICombine(SDNode *N,
11248 TargetLowering::DAGCombinerInfo &DCI) {
11249 SDValue N1 = N->getOperand(1);
11250 if (N1.getOpcode() == ISD::AND) {
11251 // (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
11252 // the bits being cleared by the AND are not demanded by the BFI.
11253 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
11256 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
11257 unsigned LSB = countTrailingZeros(~InvMask);
11258 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
11260 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
11261 "undefined behavior");
11262 unsigned Mask = (1u << Width) - 1;
11263 unsigned Mask2 = N11C->getZExtValue();
11264 if ((Mask & (~Mask2)) == 0)
11265 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
11266 N->getOperand(0), N1.getOperand(0),
11268 } else if (N->getOperand(0).getOpcode() == ARMISD::BFI) {
11269 // We have a BFI of a BFI. Walk up the BFI chain to see how long it goes.
11270 // Keep track of any consecutive bits set that all come from the same base
11271 // value. We can combine these together into a single BFI.
11272 SDValue CombineBFI = FindBFIToCombineWith(N);
11273 if (CombineBFI == SDValue())
11276 // We've found a BFI.
11277 APInt ToMask1, FromMask1;
11278 SDValue From1 = ParseBFI(N, ToMask1, FromMask1);
11280 APInt ToMask2, FromMask2;
11281 SDValue From2 = ParseBFI(CombineBFI.getNode(), ToMask2, FromMask2);
11282 assert(From1 == From2);
11285 // First, unlink CombineBFI.
11286 DCI.DAG.ReplaceAllUsesWith(CombineBFI, CombineBFI.getOperand(0));
11287 // Then create a new BFI, combining the two together.
11288 APInt NewFromMask = FromMask1 | FromMask2;
11289 APInt NewToMask = ToMask1 | ToMask2;
11291 EVT VT = N->getValueType(0);
11294 if (NewFromMask[0] == 0)
11295 From1 = DCI.DAG.getNode(
11296 ISD::SRL, dl, VT, From1,
11297 DCI.DAG.getConstant(NewFromMask.countTrailingZeros(), dl, VT));
11298 return DCI.DAG.getNode(ARMISD::BFI, dl, VT, N->getOperand(0), From1,
11299 DCI.DAG.getConstant(~NewToMask, dl, VT));
11304 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
11305 /// ARMISD::VMOVRRD.
11306 static SDValue PerformVMOVRRDCombine(SDNode *N,
11307 TargetLowering::DAGCombinerInfo &DCI,
11308 const ARMSubtarget *Subtarget) {
11309 // vmovrrd(vmovdrr x, y) -> x,y
11310 SDValue InDouble = N->getOperand(0);
11311 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
11312 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
11314 // vmovrrd(load f64) -> (load i32), (load i32)
11315 SDNode *InNode = InDouble.getNode();
11316 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
11317 InNode->getValueType(0) == MVT::f64 &&
11318 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
11319 !cast<LoadSDNode>(InNode)->isVolatile()) {
11320 // TODO: Should this be done for non-FrameIndex operands?
11321 LoadSDNode *LD = cast<LoadSDNode>(InNode);
11323 SelectionDAG &DAG = DCI.DAG;
11325 SDValue BasePtr = LD->getBasePtr();
11327 DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, LD->getPointerInfo(),
11328 LD->getAlignment(), LD->getMemOperand()->getFlags());
11330 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
11331 DAG.getConstant(4, DL, MVT::i32));
11332 SDValue NewLD2 = DAG.getLoad(
11333 MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, LD->getPointerInfo(),
11334 std::min(4U, LD->getAlignment() / 2), LD->getMemOperand()->getFlags());
11336 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
11337 if (DCI.DAG.getDataLayout().isBigEndian())
11338 std::swap (NewLD1, NewLD2);
11339 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
11346 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
11347 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
11348 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
11349 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
11350 SDValue Op0 = N->getOperand(0);
11351 SDValue Op1 = N->getOperand(1);
11352 if (Op0.getOpcode() == ISD::BITCAST)
11353 Op0 = Op0.getOperand(0);
11354 if (Op1.getOpcode() == ISD::BITCAST)
11355 Op1 = Op1.getOperand(0);
11356 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
11357 Op0.getNode() == Op1.getNode() &&
11358 Op0.getResNo() == 0 && Op1.getResNo() == 1)
11359 return DAG.getNode(ISD::BITCAST, SDLoc(N),
11360 N->getValueType(0), Op0.getOperand(0));
11364 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
11365 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
11366 /// i64 vector to have f64 elements, since the value can then be loaded
11367 /// directly into a VFP register.
11368 static bool hasNormalLoadOperand(SDNode *N) {
11369 unsigned NumElts = N->getValueType(0).getVectorNumElements();
11370 for (unsigned i = 0; i < NumElts; ++i) {
11371 SDNode *Elt = N->getOperand(i).getNode();
11372 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
11378 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
11379 /// ISD::BUILD_VECTOR.
11380 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
11381 TargetLowering::DAGCombinerInfo &DCI,
11382 const ARMSubtarget *Subtarget) {
11383 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
11384 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
11385 // into a pair of GPRs, which is fine when the value is used as a scalar,
11386 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
11387 SelectionDAG &DAG = DCI.DAG;
11388 if (N->getNumOperands() == 2)
11389 if (SDValue RV = PerformVMOVDRRCombine(N, DAG))
11392 // Load i64 elements as f64 values so that type legalization does not split
11393 // them up into i32 values.
11394 EVT VT = N->getValueType(0);
11395 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
11398 SmallVector<SDValue, 8> Ops;
11399 unsigned NumElts = VT.getVectorNumElements();
11400 for (unsigned i = 0; i < NumElts; ++i) {
11401 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
11403 // Make the DAGCombiner fold the bitcast.
11404 DCI.AddToWorklist(V.getNode());
11406 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
11407 SDValue BV = DAG.getBuildVector(FloatVT, dl, Ops);
11408 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
11411 /// Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
11413 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
11414 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
11415 // At that time, we may have inserted bitcasts from integer to float.
11416 // If these bitcasts have survived DAGCombine, change the lowering of this
11417 // BUILD_VECTOR in something more vector friendly, i.e., that does not
11418 // force to use floating point types.
11420 // Make sure we can change the type of the vector.
11421 // This is possible iff:
11422 // 1. The vector is only used in a bitcast to a integer type. I.e.,
11423 // 1.1. Vector is used only once.
11424 // 1.2. Use is a bit convert to an integer type.
11425 // 2. The size of its operands are 32-bits (64-bits are not legal).
11426 EVT VT = N->getValueType(0);
11427 EVT EltVT = VT.getVectorElementType();
11429 // Check 1.1. and 2.
11430 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
11433 // By construction, the input type must be float.
11434 assert(EltVT == MVT::f32 && "Unexpected type!");
11437 SDNode *Use = *N->use_begin();
11438 if (Use->getOpcode() != ISD::BITCAST ||
11439 Use->getValueType(0).isFloatingPoint())
11442 // Check profitability.
11443 // Model is, if more than half of the relevant operands are bitcast from
11444 // i32, turn the build_vector into a sequence of insert_vector_elt.
11445 // Relevant operands are everything that is not statically
11446 // (i.e., at compile time) bitcasted.
11447 unsigned NumOfBitCastedElts = 0;
11448 unsigned NumElts = VT.getVectorNumElements();
11449 unsigned NumOfRelevantElts = NumElts;
11450 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
11451 SDValue Elt = N->getOperand(Idx);
11452 if (Elt->getOpcode() == ISD::BITCAST) {
11453 // Assume only bit cast to i32 will go away.
11454 if (Elt->getOperand(0).getValueType() == MVT::i32)
11455 ++NumOfBitCastedElts;
11456 } else if (Elt.isUndef() || isa<ConstantSDNode>(Elt))
11457 // Constants are statically casted, thus do not count them as
11458 // relevant operands.
11459 --NumOfRelevantElts;
11462 // Check if more than half of the elements require a non-free bitcast.
11463 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
11466 SelectionDAG &DAG = DCI.DAG;
11467 // Create the new vector type.
11468 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
11469 // Check if the type is legal.
11470 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11471 if (!TLI.isTypeLegal(VecVT))
11475 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
11476 // => BITCAST INSERT_VECTOR_ELT
11477 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
11478 // (BITCAST EN), N.
11479 SDValue Vec = DAG.getUNDEF(VecVT);
11481 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
11482 SDValue V = N->getOperand(Idx);
11485 if (V.getOpcode() == ISD::BITCAST &&
11486 V->getOperand(0).getValueType() == MVT::i32)
11487 // Fold obvious case.
11488 V = V.getOperand(0);
11490 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
11491 // Make the DAGCombiner fold the bitcasts.
11492 DCI.AddToWorklist(V.getNode());
11494 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32);
11495 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
11497 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
11498 // Make the DAGCombiner fold the bitcasts.
11499 DCI.AddToWorklist(Vec.getNode());
11503 /// PerformInsertEltCombine - Target-specific dag combine xforms for
11504 /// ISD::INSERT_VECTOR_ELT.
11505 static SDValue PerformInsertEltCombine(SDNode *N,
11506 TargetLowering::DAGCombinerInfo &DCI) {
11507 // Bitcast an i64 load inserted into a vector to f64.
11508 // Otherwise, the i64 value will be legalized to a pair of i32 values.
11509 EVT VT = N->getValueType(0);
11510 SDNode *Elt = N->getOperand(1).getNode();
11511 if (VT.getVectorElementType() != MVT::i64 ||
11512 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
11515 SelectionDAG &DAG = DCI.DAG;
11517 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
11518 VT.getVectorNumElements());
11519 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
11520 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
11521 // Make the DAGCombiner fold the bitcasts.
11522 DCI.AddToWorklist(Vec.getNode());
11523 DCI.AddToWorklist(V.getNode());
11524 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
11525 Vec, V, N->getOperand(2));
11526 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
11529 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
11530 /// ISD::VECTOR_SHUFFLE.
11531 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
11532 // The LLVM shufflevector instruction does not require the shuffle mask
11533 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
11534 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
11535 // operands do not match the mask length, they are extended by concatenating
11536 // them with undef vectors. That is probably the right thing for other
11537 // targets, but for NEON it is better to concatenate two double-register
11538 // size vector operands into a single quad-register size vector. Do that
11539 // transformation here:
11540 // shuffle(concat(v1, undef), concat(v2, undef)) ->
11541 // shuffle(concat(v1, v2), undef)
11542 SDValue Op0 = N->getOperand(0);
11543 SDValue Op1 = N->getOperand(1);
11544 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
11545 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
11546 Op0.getNumOperands() != 2 ||
11547 Op1.getNumOperands() != 2)
11549 SDValue Concat0Op1 = Op0.getOperand(1);
11550 SDValue Concat1Op1 = Op1.getOperand(1);
11551 if (!Concat0Op1.isUndef() || !Concat1Op1.isUndef())
11553 // Skip the transformation if any of the types are illegal.
11554 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11555 EVT VT = N->getValueType(0);
11556 if (!TLI.isTypeLegal(VT) ||
11557 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
11558 !TLI.isTypeLegal(Concat1Op1.getValueType()))
11561 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11562 Op0.getOperand(0), Op1.getOperand(0));
11563 // Translate the shuffle mask.
11564 SmallVector<int, 16> NewMask;
11565 unsigned NumElts = VT.getVectorNumElements();
11566 unsigned HalfElts = NumElts/2;
11567 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
11568 for (unsigned n = 0; n < NumElts; ++n) {
11569 int MaskElt = SVN->getMaskElt(n);
11571 if (MaskElt < (int)HalfElts)
11573 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
11574 NewElt = HalfElts + MaskElt - NumElts;
11575 NewMask.push_back(NewElt);
11577 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
11578 DAG.getUNDEF(VT), NewMask);
11581 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
11582 /// NEON load/store intrinsics, and generic vector load/stores, to merge
11583 /// base address updates.
11584 /// For generic load/stores, the memory type is assumed to be a vector.
11585 /// The caller is assumed to have checked legality.
11586 static SDValue CombineBaseUpdate(SDNode *N,
11587 TargetLowering::DAGCombinerInfo &DCI) {
11588 SelectionDAG &DAG = DCI.DAG;
11589 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
11590 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
11591 const bool isStore = N->getOpcode() == ISD::STORE;
11592 const unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
11593 SDValue Addr = N->getOperand(AddrOpIdx);
11594 MemSDNode *MemN = cast<MemSDNode>(N);
11597 // Search for a use of the address operand that is an increment.
11598 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
11599 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
11600 SDNode *User = *UI;
11601 if (User->getOpcode() != ISD::ADD ||
11602 UI.getUse().getResNo() != Addr.getResNo())
11605 // Check that the add is independent of the load/store. Otherwise, folding
11606 // it would create a cycle. We can avoid searching through Addr as it's a
11607 // predecessor to both.
11608 SmallPtrSet<const SDNode *, 32> Visited;
11609 SmallVector<const SDNode *, 16> Worklist;
11610 Visited.insert(Addr.getNode());
11611 Worklist.push_back(N);
11612 Worklist.push_back(User);
11613 if (SDNode::hasPredecessorHelper(N, Visited, Worklist) ||
11614 SDNode::hasPredecessorHelper(User, Visited, Worklist))
11617 // Find the new opcode for the updating load/store.
11618 bool isLoadOp = true;
11619 bool isLaneOp = false;
11620 unsigned NewOpc = 0;
11621 unsigned NumVecs = 0;
11623 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
11625 default: llvm_unreachable("unexpected intrinsic for Neon base update");
11626 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
11627 NumVecs = 1; break;
11628 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
11629 NumVecs = 2; break;
11630 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
11631 NumVecs = 3; break;
11632 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
11633 NumVecs = 4; break;
11634 case Intrinsic::arm_neon_vld2dup:
11635 case Intrinsic::arm_neon_vld3dup:
11636 case Intrinsic::arm_neon_vld4dup:
11637 // TODO: Support updating VLDxDUP nodes. For now, we just skip
11638 // combining base updates for such intrinsics.
11640 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
11641 NumVecs = 2; isLaneOp = true; break;
11642 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
11643 NumVecs = 3; isLaneOp = true; break;
11644 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
11645 NumVecs = 4; isLaneOp = true; break;
11646 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
11647 NumVecs = 1; isLoadOp = false; break;
11648 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
11649 NumVecs = 2; isLoadOp = false; break;
11650 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
11651 NumVecs = 3; isLoadOp = false; break;
11652 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
11653 NumVecs = 4; isLoadOp = false; break;
11654 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
11655 NumVecs = 2; isLoadOp = false; isLaneOp = true; break;
11656 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
11657 NumVecs = 3; isLoadOp = false; isLaneOp = true; break;
11658 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
11659 NumVecs = 4; isLoadOp = false; isLaneOp = true; break;
11663 switch (N->getOpcode()) {
11664 default: llvm_unreachable("unexpected opcode for Neon base update");
11665 case ARMISD::VLD1DUP: NewOpc = ARMISD::VLD1DUP_UPD; NumVecs = 1; break;
11666 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
11667 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
11668 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
11669 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
11670 NumVecs = 1; isLaneOp = false; break;
11671 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
11672 NumVecs = 1; isLaneOp = false; isLoadOp = false; break;
11676 // Find the size of memory referenced by the load/store.
11679 VecTy = N->getValueType(0);
11680 } else if (isIntrinsic) {
11681 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
11683 assert(isStore && "Node has to be a load, a store, or an intrinsic!");
11684 VecTy = N->getOperand(1).getValueType();
11687 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
11689 NumBytes /= VecTy.getVectorNumElements();
11691 // If the increment is a constant, it must match the memory ref size.
11692 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
11693 ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode());
11694 if (NumBytes >= 3 * 16 && (!CInc || CInc->getZExtValue() != NumBytes)) {
11695 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
11696 // separate instructions that make it harder to use a non-constant update.
11700 // OK, we found an ADD we can fold into the base update.
11701 // Now, create a _UPD node, taking care of not breaking alignment.
11703 EVT AlignedVecTy = VecTy;
11704 unsigned Alignment = MemN->getAlignment();
11706 // If this is a less-than-standard-aligned load/store, change the type to
11707 // match the standard alignment.
11708 // The alignment is overlooked when selecting _UPD variants; and it's
11709 // easier to introduce bitcasts here than fix that.
11710 // There are 3 ways to get to this base-update combine:
11711 // - intrinsics: they are assumed to be properly aligned (to the standard
11712 // alignment of the memory type), so we don't need to do anything.
11713 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
11714 // intrinsics, so, likewise, there's nothing to do.
11715 // - generic load/store instructions: the alignment is specified as an
11716 // explicit operand, rather than implicitly as the standard alignment
11717 // of the memory type (like the intrisics). We need to change the
11718 // memory type to match the explicit alignment. That way, we don't
11719 // generate non-standard-aligned ARMISD::VLDx nodes.
11720 if (isa<LSBaseSDNode>(N)) {
11721 if (Alignment == 0)
11723 if (Alignment < VecTy.getScalarSizeInBits() / 8) {
11724 MVT EltTy = MVT::getIntegerVT(Alignment * 8);
11725 assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
11726 assert(!isLaneOp && "Unexpected generic load/store lane.");
11727 unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
11728 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
11730 // Don't set an explicit alignment on regular load/stores that we want
11731 // to transform to VLD/VST 1_UPD nodes.
11732 // This matches the behavior of regular load/stores, which only get an
11733 // explicit alignment if the MMO alignment is larger than the standard
11734 // alignment of the memory type.
11735 // Intrinsics, however, always get an explicit alignment, set to the
11736 // alignment of the MMO.
11740 // Create the new updating load/store node.
11741 // First, create an SDVTList for the new updating node's results.
11743 unsigned NumResultVecs = (isLoadOp ? NumVecs : 0);
11745 for (n = 0; n < NumResultVecs; ++n)
11746 Tys[n] = AlignedVecTy;
11747 Tys[n++] = MVT::i32;
11748 Tys[n] = MVT::Other;
11749 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
11751 // Then, gather the new node's operands.
11752 SmallVector<SDValue, 8> Ops;
11753 Ops.push_back(N->getOperand(0)); // incoming chain
11754 Ops.push_back(N->getOperand(AddrOpIdx));
11755 Ops.push_back(Inc);
11757 if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
11758 // Try to match the intrinsic's signature
11759 Ops.push_back(StN->getValue());
11761 // Loads (and of course intrinsics) match the intrinsics' signature,
11762 // so just add all but the alignment operand.
11763 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands() - 1; ++i)
11764 Ops.push_back(N->getOperand(i));
11767 // For all node types, the alignment operand is always the last one.
11768 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32));
11770 // If this is a non-standard-aligned STORE, the penultimate operand is the
11771 // stored value. Bitcast it to the aligned type.
11772 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
11773 SDValue &StVal = Ops[Ops.size()-2];
11774 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal);
11777 EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy;
11778 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT,
11779 MemN->getMemOperand());
11781 // Update the uses.
11782 SmallVector<SDValue, 5> NewResults;
11783 for (unsigned i = 0; i < NumResultVecs; ++i)
11784 NewResults.push_back(SDValue(UpdN.getNode(), i));
11786 // If this is an non-standard-aligned LOAD, the first result is the loaded
11787 // value. Bitcast it to the expected result type.
11788 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
11789 SDValue &LdVal = NewResults[0];
11790 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal);
11793 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
11794 DCI.CombineTo(N, NewResults);
11795 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
11802 static SDValue PerformVLDCombine(SDNode *N,
11803 TargetLowering::DAGCombinerInfo &DCI) {
11804 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
11807 return CombineBaseUpdate(N, DCI);
11810 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
11811 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
11812 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
11814 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
11815 SelectionDAG &DAG = DCI.DAG;
11816 EVT VT = N->getValueType(0);
11817 // vldN-dup instructions only support 64-bit vectors for N > 1.
11818 if (!VT.is64BitVector())
11821 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
11822 SDNode *VLD = N->getOperand(0).getNode();
11823 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
11825 unsigned NumVecs = 0;
11826 unsigned NewOpc = 0;
11827 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
11828 if (IntNo == Intrinsic::arm_neon_vld2lane) {
11830 NewOpc = ARMISD::VLD2DUP;
11831 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
11833 NewOpc = ARMISD::VLD3DUP;
11834 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
11836 NewOpc = ARMISD::VLD4DUP;
11841 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
11842 // numbers match the load.
11843 unsigned VLDLaneNo =
11844 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
11845 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
11847 // Ignore uses of the chain result.
11848 if (UI.getUse().getResNo() == NumVecs)
11850 SDNode *User = *UI;
11851 if (User->getOpcode() != ARMISD::VDUPLANE ||
11852 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
11856 // Create the vldN-dup node.
11859 for (n = 0; n < NumVecs; ++n)
11861 Tys[n] = MVT::Other;
11862 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
11863 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
11864 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
11865 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
11866 Ops, VLDMemInt->getMemoryVT(),
11867 VLDMemInt->getMemOperand());
11869 // Update the uses.
11870 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
11872 unsigned ResNo = UI.getUse().getResNo();
11873 // Ignore uses of the chain result.
11874 if (ResNo == NumVecs)
11876 SDNode *User = *UI;
11877 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
11880 // Now the vldN-lane intrinsic is dead except for its chain result.
11881 // Update uses of the chain.
11882 std::vector<SDValue> VLDDupResults;
11883 for (unsigned n = 0; n < NumVecs; ++n)
11884 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
11885 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
11886 DCI.CombineTo(VLD, VLDDupResults);
11891 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
11892 /// ARMISD::VDUPLANE.
11893 static SDValue PerformVDUPLANECombine(SDNode *N,
11894 TargetLowering::DAGCombinerInfo &DCI) {
11895 SDValue Op = N->getOperand(0);
11897 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
11898 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
11899 if (CombineVLDDUP(N, DCI))
11900 return SDValue(N, 0);
11902 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
11903 // redundant. Ignore bit_converts for now; element sizes are checked below.
11904 while (Op.getOpcode() == ISD::BITCAST)
11905 Op = Op.getOperand(0);
11906 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
11909 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
11910 unsigned EltSize = Op.getScalarValueSizeInBits();
11911 // The canonical VMOV for a zero vector uses a 32-bit element size.
11912 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11914 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
11916 EVT VT = N->getValueType(0);
11917 if (EltSize > VT.getScalarSizeInBits())
11920 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
11923 /// PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.
11924 static SDValue PerformVDUPCombine(SDNode *N,
11925 TargetLowering::DAGCombinerInfo &DCI) {
11926 SelectionDAG &DAG = DCI.DAG;
11927 SDValue Op = N->getOperand(0);
11929 // Match VDUP(LOAD) -> VLD1DUP.
11930 // We match this pattern here rather than waiting for isel because the
11931 // transform is only legal for unindexed loads.
11932 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode());
11933 if (LD && Op.hasOneUse() && LD->isUnindexed() &&
11934 LD->getMemoryVT() == N->getValueType(0).getVectorElementType()) {
11935 SDValue Ops[] = { LD->getOperand(0), LD->getOperand(1),
11936 DAG.getConstant(LD->getAlignment(), SDLoc(N), MVT::i32) };
11937 SDVTList SDTys = DAG.getVTList(N->getValueType(0), MVT::Other);
11938 SDValue VLDDup = DAG.getMemIntrinsicNode(ARMISD::VLD1DUP, SDLoc(N), SDTys,
11939 Ops, LD->getMemoryVT(),
11940 LD->getMemOperand());
11941 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), VLDDup.getValue(1));
11948 static SDValue PerformLOADCombine(SDNode *N,
11949 TargetLowering::DAGCombinerInfo &DCI) {
11950 EVT VT = N->getValueType(0);
11952 // If this is a legal vector load, try to combine it into a VLD1_UPD.
11953 if (ISD::isNormalLoad(N) && VT.isVector() &&
11954 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
11955 return CombineBaseUpdate(N, DCI);
11960 /// PerformSTORECombine - Target-specific dag combine xforms for
11962 static SDValue PerformSTORECombine(SDNode *N,
11963 TargetLowering::DAGCombinerInfo &DCI) {
11964 StoreSDNode *St = cast<StoreSDNode>(N);
11965 if (St->isVolatile())
11968 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
11969 // pack all of the elements in one place. Next, store to memory in fewer
11971 SDValue StVal = St->getValue();
11972 EVT VT = StVal.getValueType();
11973 if (St->isTruncatingStore() && VT.isVector()) {
11974 SelectionDAG &DAG = DCI.DAG;
11975 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11976 EVT StVT = St->getMemoryVT();
11977 unsigned NumElems = VT.getVectorNumElements();
11978 assert(StVT != VT && "Cannot truncate to the same type");
11979 unsigned FromEltSz = VT.getScalarSizeInBits();
11980 unsigned ToEltSz = StVT.getScalarSizeInBits();
11982 // From, To sizes and ElemCount must be pow of two
11983 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
11985 // We are going to use the original vector elt for storing.
11986 // Accumulated smaller vector elements must be a multiple of the store size.
11987 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
11989 unsigned SizeRatio = FromEltSz / ToEltSz;
11990 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
11992 // Create a type on which we perform the shuffle.
11993 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
11994 NumElems*SizeRatio);
11995 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
11998 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
11999 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
12000 for (unsigned i = 0; i < NumElems; ++i)
12001 ShuffleVec[i] = DAG.getDataLayout().isBigEndian()
12002 ? (i + 1) * SizeRatio - 1
12005 // Can't shuffle using an illegal type.
12006 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
12008 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
12009 DAG.getUNDEF(WideVec.getValueType()),
12011 // At this point all of the data is stored at the bottom of the
12012 // register. We now need to save it to mem.
12014 // Find the largest store unit
12015 MVT StoreType = MVT::i8;
12016 for (MVT Tp : MVT::integer_valuetypes()) {
12017 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
12020 // Didn't find a legal store type.
12021 if (!TLI.isTypeLegal(StoreType))
12024 // Bitcast the original vector into a vector of store-size units
12025 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
12026 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
12027 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
12028 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
12029 SmallVector<SDValue, 8> Chains;
12030 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, DL,
12031 TLI.getPointerTy(DAG.getDataLayout()));
12032 SDValue BasePtr = St->getBasePtr();
12034 // Perform one or more big stores into memory.
12035 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
12036 for (unsigned I = 0; I < E; I++) {
12037 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
12038 StoreType, ShuffWide,
12039 DAG.getIntPtrConstant(I, DL));
12040 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
12041 St->getPointerInfo(), St->getAlignment(),
12042 St->getMemOperand()->getFlags());
12043 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
12045 Chains.push_back(Ch);
12047 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
12050 if (!ISD::isNormalStore(St))
12053 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
12054 // ARM stores of arguments in the same cache line.
12055 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
12056 StVal.getNode()->hasOneUse()) {
12057 SelectionDAG &DAG = DCI.DAG;
12058 bool isBigEndian = DAG.getDataLayout().isBigEndian();
12060 SDValue BasePtr = St->getBasePtr();
12061 SDValue NewST1 = DAG.getStore(
12062 St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0),
12063 BasePtr, St->getPointerInfo(), St->getAlignment(),
12064 St->getMemOperand()->getFlags());
12066 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
12067 DAG.getConstant(4, DL, MVT::i32));
12068 return DAG.getStore(NewST1.getValue(0), DL,
12069 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
12070 OffsetPtr, St->getPointerInfo(),
12071 std::min(4U, St->getAlignment() / 2),
12072 St->getMemOperand()->getFlags());
12075 if (StVal.getValueType() == MVT::i64 &&
12076 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
12078 // Bitcast an i64 store extracted from a vector to f64.
12079 // Otherwise, the i64 value will be legalized to a pair of i32 values.
12080 SelectionDAG &DAG = DCI.DAG;
12082 SDValue IntVec = StVal.getOperand(0);
12083 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
12084 IntVec.getValueType().getVectorNumElements());
12085 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
12086 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12087 Vec, StVal.getOperand(1));
12089 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
12090 // Make the DAGCombiner fold the bitcasts.
12091 DCI.AddToWorklist(Vec.getNode());
12092 DCI.AddToWorklist(ExtElt.getNode());
12093 DCI.AddToWorklist(V.getNode());
12094 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
12095 St->getPointerInfo(), St->getAlignment(),
12096 St->getMemOperand()->getFlags(), St->getAAInfo());
12099 // If this is a legal vector store, try to combine it into a VST1_UPD.
12100 if (ISD::isNormalStore(N) && VT.isVector() &&
12101 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
12102 return CombineBaseUpdate(N, DCI);
12107 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
12108 /// can replace combinations of VMUL and VCVT (floating-point to integer)
12109 /// when the VMUL has a constant operand that is a power of 2.
12111 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
12112 /// vmul.f32 d16, d17, d16
12113 /// vcvt.s32.f32 d16, d16
12115 /// vcvt.s32.f32 d16, d16, #3
12116 static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
12117 const ARMSubtarget *Subtarget) {
12118 if (!Subtarget->hasNEON())
12121 SDValue Op = N->getOperand(0);
12122 if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
12123 Op.getOpcode() != ISD::FMUL)
12126 SDValue ConstVec = Op->getOperand(1);
12127 if (!isa<BuildVectorSDNode>(ConstVec))
12130 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
12131 uint32_t FloatBits = FloatTy.getSizeInBits();
12132 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
12133 uint32_t IntBits = IntTy.getSizeInBits();
12134 unsigned NumLanes = Op.getValueType().getVectorNumElements();
12135 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
12136 // These instructions only exist converting from f32 to i32. We can handle
12137 // smaller integers by generating an extra truncate, but larger ones would
12138 // be lossy. We also can't handle more then 4 lanes, since these intructions
12139 // only support v2i32/v4i32 types.
12143 BitVector UndefElements;
12144 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
12145 int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, 33);
12146 if (C == -1 || C == 0 || C > 32)
12150 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
12151 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
12152 Intrinsic::arm_neon_vcvtfp2fxu;
12153 SDValue FixConv = DAG.getNode(
12154 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
12155 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), Op->getOperand(0),
12156 DAG.getConstant(C, dl, MVT::i32));
12158 if (IntBits < FloatBits)
12159 FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv);
12164 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
12165 /// can replace combinations of VCVT (integer to floating-point) and VDIV
12166 /// when the VDIV has a constant operand that is a power of 2.
12168 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
12169 /// vcvt.f32.s32 d16, d16
12170 /// vdiv.f32 d16, d17, d16
12172 /// vcvt.f32.s32 d16, d16, #3
12173 static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
12174 const ARMSubtarget *Subtarget) {
12175 if (!Subtarget->hasNEON())
12178 SDValue Op = N->getOperand(0);
12179 unsigned OpOpcode = Op.getNode()->getOpcode();
12180 if (!N->getValueType(0).isVector() || !N->getValueType(0).isSimple() ||
12181 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
12184 SDValue ConstVec = N->getOperand(1);
12185 if (!isa<BuildVectorSDNode>(ConstVec))
12188 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
12189 uint32_t FloatBits = FloatTy.getSizeInBits();
12190 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
12191 uint32_t IntBits = IntTy.getSizeInBits();
12192 unsigned NumLanes = Op.getValueType().getVectorNumElements();
12193 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
12194 // These instructions only exist converting from i32 to f32. We can handle
12195 // smaller integers by generating an extra extend, but larger ones would
12196 // be lossy. We also can't handle more then 4 lanes, since these intructions
12197 // only support v2i32/v4i32 types.
12201 BitVector UndefElements;
12202 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
12203 int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, 33);
12204 if (C == -1 || C == 0 || C > 32)
12208 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
12209 SDValue ConvInput = Op.getOperand(0);
12210 if (IntBits < FloatBits)
12211 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
12212 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
12215 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
12216 Intrinsic::arm_neon_vcvtfxu2fp;
12217 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
12219 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
12220 ConvInput, DAG.getConstant(C, dl, MVT::i32));
12223 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
12224 /// operand of a vector shift operation, where all the elements of the
12225 /// build_vector must have the same constant integer value.
12226 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
12227 // Ignore bit_converts.
12228 while (Op.getOpcode() == ISD::BITCAST)
12229 Op = Op.getOperand(0);
12230 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
12231 APInt SplatBits, SplatUndef;
12232 unsigned SplatBitSize;
12234 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
12235 HasAnyUndefs, ElementBits) ||
12236 SplatBitSize > ElementBits)
12238 Cnt = SplatBits.getSExtValue();
12242 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
12243 /// operand of a vector shift left operation. That value must be in the range:
12244 /// 0 <= Value < ElementBits for a left shift; or
12245 /// 0 <= Value <= ElementBits for a long left shift.
12246 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
12247 assert(VT.isVector() && "vector shift count is not a vector type");
12248 int64_t ElementBits = VT.getScalarSizeInBits();
12249 if (! getVShiftImm(Op, ElementBits, Cnt))
12251 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
12254 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
12255 /// operand of a vector shift right operation. For a shift opcode, the value
12256 /// is positive, but for an intrinsic the value count must be negative. The
12257 /// absolute value must be in the range:
12258 /// 1 <= |Value| <= ElementBits for a right shift; or
12259 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
12260 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
12262 assert(VT.isVector() && "vector shift count is not a vector type");
12263 int64_t ElementBits = VT.getScalarSizeInBits();
12264 if (! getVShiftImm(Op, ElementBits, Cnt))
12267 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
12268 if (Cnt >= -(isNarrow ? ElementBits/2 : ElementBits) && Cnt <= -1) {
12275 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
12276 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
12277 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
12280 // Don't do anything for most intrinsics.
12283 // Vector shifts: check for immediate versions and lower them.
12284 // Note: This is done during DAG combining instead of DAG legalizing because
12285 // the build_vectors for 64-bit vector element shift counts are generally
12286 // not legal, and it is hard to see their values after they get legalized to
12287 // loads from a constant pool.
12288 case Intrinsic::arm_neon_vshifts:
12289 case Intrinsic::arm_neon_vshiftu:
12290 case Intrinsic::arm_neon_vrshifts:
12291 case Intrinsic::arm_neon_vrshiftu:
12292 case Intrinsic::arm_neon_vrshiftn:
12293 case Intrinsic::arm_neon_vqshifts:
12294 case Intrinsic::arm_neon_vqshiftu:
12295 case Intrinsic::arm_neon_vqshiftsu:
12296 case Intrinsic::arm_neon_vqshiftns:
12297 case Intrinsic::arm_neon_vqshiftnu:
12298 case Intrinsic::arm_neon_vqshiftnsu:
12299 case Intrinsic::arm_neon_vqrshiftns:
12300 case Intrinsic::arm_neon_vqrshiftnu:
12301 case Intrinsic::arm_neon_vqrshiftnsu: {
12302 EVT VT = N->getOperand(1).getValueType();
12304 unsigned VShiftOpc = 0;
12307 case Intrinsic::arm_neon_vshifts:
12308 case Intrinsic::arm_neon_vshiftu:
12309 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
12310 VShiftOpc = ARMISD::VSHL;
12313 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
12314 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
12315 ARMISD::VSHRs : ARMISD::VSHRu);
12320 case Intrinsic::arm_neon_vrshifts:
12321 case Intrinsic::arm_neon_vrshiftu:
12322 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
12326 case Intrinsic::arm_neon_vqshifts:
12327 case Intrinsic::arm_neon_vqshiftu:
12328 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
12332 case Intrinsic::arm_neon_vqshiftsu:
12333 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
12335 llvm_unreachable("invalid shift count for vqshlu intrinsic");
12337 case Intrinsic::arm_neon_vrshiftn:
12338 case Intrinsic::arm_neon_vqshiftns:
12339 case Intrinsic::arm_neon_vqshiftnu:
12340 case Intrinsic::arm_neon_vqshiftnsu:
12341 case Intrinsic::arm_neon_vqrshiftns:
12342 case Intrinsic::arm_neon_vqrshiftnu:
12343 case Intrinsic::arm_neon_vqrshiftnsu:
12344 // Narrowing shifts require an immediate right shift.
12345 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
12347 llvm_unreachable("invalid shift count for narrowing vector shift "
12351 llvm_unreachable("unhandled vector shift");
12355 case Intrinsic::arm_neon_vshifts:
12356 case Intrinsic::arm_neon_vshiftu:
12357 // Opcode already set above.
12359 case Intrinsic::arm_neon_vrshifts:
12360 VShiftOpc = ARMISD::VRSHRs; break;
12361 case Intrinsic::arm_neon_vrshiftu:
12362 VShiftOpc = ARMISD::VRSHRu; break;
12363 case Intrinsic::arm_neon_vrshiftn:
12364 VShiftOpc = ARMISD::VRSHRN; break;
12365 case Intrinsic::arm_neon_vqshifts:
12366 VShiftOpc = ARMISD::VQSHLs; break;
12367 case Intrinsic::arm_neon_vqshiftu:
12368 VShiftOpc = ARMISD::VQSHLu; break;
12369 case Intrinsic::arm_neon_vqshiftsu:
12370 VShiftOpc = ARMISD::VQSHLsu; break;
12371 case Intrinsic::arm_neon_vqshiftns:
12372 VShiftOpc = ARMISD::VQSHRNs; break;
12373 case Intrinsic::arm_neon_vqshiftnu:
12374 VShiftOpc = ARMISD::VQSHRNu; break;
12375 case Intrinsic::arm_neon_vqshiftnsu:
12376 VShiftOpc = ARMISD::VQSHRNsu; break;
12377 case Intrinsic::arm_neon_vqrshiftns:
12378 VShiftOpc = ARMISD::VQRSHRNs; break;
12379 case Intrinsic::arm_neon_vqrshiftnu:
12380 VShiftOpc = ARMISD::VQRSHRNu; break;
12381 case Intrinsic::arm_neon_vqrshiftnsu:
12382 VShiftOpc = ARMISD::VQRSHRNsu; break;
12386 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
12387 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32));
12390 case Intrinsic::arm_neon_vshiftins: {
12391 EVT VT = N->getOperand(1).getValueType();
12393 unsigned VShiftOpc = 0;
12395 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
12396 VShiftOpc = ARMISD::VSLI;
12397 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
12398 VShiftOpc = ARMISD::VSRI;
12400 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
12404 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
12405 N->getOperand(1), N->getOperand(2),
12406 DAG.getConstant(Cnt, dl, MVT::i32));
12409 case Intrinsic::arm_neon_vqrshifts:
12410 case Intrinsic::arm_neon_vqrshiftu:
12411 // No immediate versions of these to check for.
12418 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
12419 /// lowers them. As with the vector shift intrinsics, this is done during DAG
12420 /// combining instead of DAG legalizing because the build_vectors for 64-bit
12421 /// vector element shift counts are generally not legal, and it is hard to see
12422 /// their values after they get legalized to loads from a constant pool.
12423 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
12424 const ARMSubtarget *ST) {
12425 EVT VT = N->getValueType(0);
12426 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
12427 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
12428 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
12429 SDValue N1 = N->getOperand(1);
12430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
12431 SDValue N0 = N->getOperand(0);
12432 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
12433 DAG.MaskedValueIsZero(N0.getOperand(0),
12434 APInt::getHighBitsSet(32, 16)))
12435 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
12439 // Nothing to be done for scalar shifts.
12440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12441 if (!VT.isVector() || !TLI.isTypeLegal(VT))
12444 assert(ST->hasNEON() && "unexpected vector shift");
12447 switch (N->getOpcode()) {
12448 default: llvm_unreachable("unexpected shift opcode");
12451 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) {
12453 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
12454 DAG.getConstant(Cnt, dl, MVT::i32));
12460 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
12461 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
12462 ARMISD::VSHRs : ARMISD::VSHRu);
12464 return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),
12465 DAG.getConstant(Cnt, dl, MVT::i32));
12471 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
12472 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
12473 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
12474 const ARMSubtarget *ST) {
12475 SDValue N0 = N->getOperand(0);
12477 // Check for sign- and zero-extensions of vector extract operations of 8-
12478 // and 16-bit vector elements. NEON supports these directly. They are
12479 // handled during DAG combining because type legalization will promote them
12480 // to 32-bit types and it is messy to recognize the operations after that.
12481 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
12482 SDValue Vec = N0.getOperand(0);
12483 SDValue Lane = N0.getOperand(1);
12484 EVT VT = N->getValueType(0);
12485 EVT EltVT = N0.getValueType();
12486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12488 if (VT == MVT::i32 &&
12489 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
12490 TLI.isTypeLegal(Vec.getValueType()) &&
12491 isa<ConstantSDNode>(Lane)) {
12494 switch (N->getOpcode()) {
12495 default: llvm_unreachable("unexpected opcode");
12496 case ISD::SIGN_EXTEND:
12497 Opc = ARMISD::VGETLANEs;
12499 case ISD::ZERO_EXTEND:
12500 case ISD::ANY_EXTEND:
12501 Opc = ARMISD::VGETLANEu;
12504 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
12511 static const APInt *isPowerOf2Constant(SDValue V) {
12512 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12515 const APInt *CV = &C->getAPIntValue();
12516 return CV->isPowerOf2() ? CV : nullptr;
12519 SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {
12520 // If we have a CMOV, OR and AND combination such as:
12525 // * CN is a single bit;
12526 // * All bits covered by CM are known zero in y
12528 // Then we can convert this into a sequence of BFI instructions. This will
12529 // always be a win if CM is a single bit, will always be no worse than the
12530 // TST&OR sequence if CM is two bits, and for thumb will be no worse if CM is
12531 // three bits (due to the extra IT instruction).
12533 SDValue Op0 = CMOV->getOperand(0);
12534 SDValue Op1 = CMOV->getOperand(1);
12535 auto CCNode = cast<ConstantSDNode>(CMOV->getOperand(2));
12536 auto CC = CCNode->getAPIntValue().getLimitedValue();
12537 SDValue CmpZ = CMOV->getOperand(4);
12539 // The compare must be against zero.
12540 if (!isNullConstant(CmpZ->getOperand(1)))
12543 assert(CmpZ->getOpcode() == ARMISD::CMPZ);
12544 SDValue And = CmpZ->getOperand(0);
12545 if (And->getOpcode() != ISD::AND)
12547 const APInt *AndC = isPowerOf2Constant(And->getOperand(1));
12550 SDValue X = And->getOperand(0);
12552 if (CC == ARMCC::EQ) {
12553 // We're performing an "equal to zero" compare. Swap the operands so we
12554 // canonicalize on a "not equal to zero" compare.
12555 std::swap(Op0, Op1);
12557 assert(CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?");
12560 if (Op1->getOpcode() != ISD::OR)
12563 ConstantSDNode *OrC = dyn_cast<ConstantSDNode>(Op1->getOperand(1));
12566 SDValue Y = Op1->getOperand(0);
12571 // Now, is it profitable to continue?
12572 APInt OrCI = OrC->getAPIntValue();
12573 unsigned Heuristic = Subtarget->isThumb() ? 3 : 2;
12574 if (OrCI.countPopulation() > Heuristic)
12577 // Lastly, can we determine that the bits defined by OrCI
12579 KnownBits Known = DAG.computeKnownBits(Y);
12580 if ((OrCI & Known.Zero) != OrCI)
12583 // OK, we can do the combine.
12586 EVT VT = X.getValueType();
12587 unsigned BitInX = AndC->logBase2();
12590 // We must shift X first.
12591 X = DAG.getNode(ISD::SRL, dl, VT, X,
12592 DAG.getConstant(BitInX, dl, VT));
12595 for (unsigned BitInY = 0, NumActiveBits = OrCI.getActiveBits();
12596 BitInY < NumActiveBits; ++BitInY) {
12597 if (OrCI[BitInY] == 0)
12599 APInt Mask(VT.getSizeInBits(), 0);
12600 Mask.setBit(BitInY);
12601 V = DAG.getNode(ARMISD::BFI, dl, VT, V, X,
12602 // Confusingly, the operand is an *inverted* mask.
12603 DAG.getConstant(~Mask, dl, VT));
12609 /// PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
12611 ARMTargetLowering::PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const {
12612 SDValue Cmp = N->getOperand(4);
12613 if (Cmp.getOpcode() != ARMISD::CMPZ)
12614 // Only looking at NE cases.
12617 EVT VT = N->getValueType(0);
12619 SDValue LHS = Cmp.getOperand(0);
12620 SDValue RHS = Cmp.getOperand(1);
12621 SDValue Chain = N->getOperand(0);
12622 SDValue BB = N->getOperand(1);
12623 SDValue ARMcc = N->getOperand(2);
12624 ARMCC::CondCodes CC =
12625 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
12627 // (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0))
12628 // -> (brcond Chain BB CC CPSR Cmp)
12629 if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
12630 LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
12631 LHS->getOperand(0)->hasOneUse()) {
12632 auto *LHS00C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(0));
12633 auto *LHS01C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(1));
12634 auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
12635 auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
12636 if ((LHS00C && LHS00C->getZExtValue() == 0) &&
12637 (LHS01C && LHS01C->getZExtValue() == 1) &&
12638 (LHS1C && LHS1C->getZExtValue() == 1) &&
12639 (RHSC && RHSC->getZExtValue() == 0)) {
12640 return DAG.getNode(
12641 ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2),
12642 LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4));
12649 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
12651 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
12652 SDValue Cmp = N->getOperand(4);
12653 if (Cmp.getOpcode() != ARMISD::CMPZ)
12654 // Only looking at EQ and NE cases.
12657 EVT VT = N->getValueType(0);
12659 SDValue LHS = Cmp.getOperand(0);
12660 SDValue RHS = Cmp.getOperand(1);
12661 SDValue FalseVal = N->getOperand(0);
12662 SDValue TrueVal = N->getOperand(1);
12663 SDValue ARMcc = N->getOperand(2);
12664 ARMCC::CondCodes CC =
12665 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
12667 // BFI is only available on V6T2+.
12668 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) {
12669 SDValue R = PerformCMOVToBFICombine(N, DAG);
12690 /// FIXME: Turn this into a target neutral optimization?
12692 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
12693 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
12694 N->getOperand(3), Cmp);
12695 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
12697 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
12698 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
12699 N->getOperand(3), NewCmp);
12702 // (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0))
12703 // -> (cmov F T CC CPSR Cmp)
12704 if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
12705 auto *LHS0C = dyn_cast<ConstantSDNode>(LHS->getOperand(0));
12706 auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
12707 auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
12708 if ((LHS0C && LHS0C->getZExtValue() == 0) &&
12709 (LHS1C && LHS1C->getZExtValue() == 1) &&
12710 (RHSC && RHSC->getZExtValue() == 0)) {
12711 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
12712 LHS->getOperand(2), LHS->getOperand(3),
12713 LHS->getOperand(4));
12717 if (!VT.isInteger())
12720 // Materialize a boolean comparison for integers so we can avoid branching.
12721 if (isNullConstant(FalseVal)) {
12722 if (CC == ARMCC::EQ && isOneConstant(TrueVal)) {
12723 if (!Subtarget->isThumb1Only() && Subtarget->hasV5TOps()) {
12724 // If x == y then x - y == 0 and ARM's CLZ will return 32, shifting it
12725 // right 5 bits will make that 32 be 1, otherwise it will be 0.
12726 // CMOV 0, 1, ==, (CMPZ x, y) -> SRL (CTLZ (SUB x, y)), 5
12727 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
12728 Res = DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::CTLZ, dl, VT, Sub),
12729 DAG.getConstant(5, dl, MVT::i32));
12731 // CMOV 0, 1, ==, (CMPZ x, y) ->
12732 // (ADDCARRY (SUB x, y), t:0, t:1)
12733 // where t = (SUBCARRY 0, (SUB x, y), 0)
12735 // The SUBCARRY computes 0 - (x - y) and this will give a borrow when
12736 // x != y. In other words, a carry C == 1 when x == y, C == 0
12738 // The final ADDCARRY computes
12739 // x - y + (0 - (x - y)) + C == C
12740 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
12741 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12742 SDValue Neg = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, Sub);
12743 // ISD::SUBCARRY returns a borrow but we want the carry here
12746 DAG.getNode(ISD::SUB, dl, MVT::i32,
12747 DAG.getConstant(1, dl, MVT::i32), Neg.getValue(1));
12748 Res = DAG.getNode(ISD::ADDCARRY, dl, VTs, Sub, Neg, Carry);
12750 } else if (CC == ARMCC::NE && !isNullConstant(RHS) &&
12751 (!Subtarget->isThumb1Only() || isPowerOf2Constant(TrueVal))) {
12752 // This seems pointless but will allow us to combine it further below.
12753 // CMOV 0, z, !=, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1
12755 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
12756 SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
12757 Sub.getValue(1), SDValue());
12758 Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, TrueVal, ARMcc,
12759 N->getOperand(3), CPSRGlue.getValue(1));
12762 } else if (isNullConstant(TrueVal)) {
12763 if (CC == ARMCC::EQ && !isNullConstant(RHS) &&
12764 (!Subtarget->isThumb1Only() || isPowerOf2Constant(FalseVal))) {
12765 // This seems pointless but will allow us to combine it further below
12766 // Note that we change == for != as this is the dual for the case above.
12767 // CMOV z, 0, ==, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1
12769 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
12770 SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
12771 Sub.getValue(1), SDValue());
12772 Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, FalseVal,
12773 DAG.getConstant(ARMCC::NE, dl, MVT::i32),
12774 N->getOperand(3), CPSRGlue.getValue(1));
12779 // On Thumb1, the DAG above may be further combined if z is a power of 2
12781 // CMOV (SUBS x, y), z, !=, (SUBS x, y):1 ->
12783 // where t1 = (SUBCARRY (SUB x, y), z, 0)
12784 // t2 = (SUBCARRY (SUB x, y), t1:0, t1:1)
12785 // t3 = if K != 0 then (SHL t2:0, K) else t2:0
12786 // t4 = (SUB 1, t2:1) [ we want a carry, not a borrow ]
12787 const APInt *TrueConst;
12788 if (Subtarget->isThumb1Only() && CC == ARMCC::NE &&
12789 (FalseVal.getOpcode() == ARMISD::SUBS) &&
12790 (FalseVal.getOperand(0) == LHS) && (FalseVal.getOperand(1) == RHS) &&
12791 (TrueConst = isPowerOf2Constant(TrueVal))) {
12792 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12793 unsigned ShiftAmount = TrueConst->logBase2();
12795 TrueVal = DAG.getConstant(1, dl, VT);
12796 SDValue Subc = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, TrueVal);
12797 Res = DAG.getNode(ISD::SUBCARRY, dl, VTs, FalseVal, Subc, Subc.getValue(1));
12798 // Make it a carry, not a borrow.
12799 SDValue Carry = DAG.getNode(
12800 ISD::SUB, dl, VT, DAG.getConstant(1, dl, MVT::i32), Res.getValue(1));
12801 Res = DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Res, Carry);
12804 Res = DAG.getNode(ISD::SHL, dl, VT, Res,
12805 DAG.getConstant(ShiftAmount, dl, MVT::i32));
12808 if (Res.getNode()) {
12809 KnownBits Known = DAG.computeKnownBits(SDValue(N,0));
12810 // Capture demanded bits information that would be otherwise lost.
12811 if (Known.Zero == 0xfffffffe)
12812 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
12813 DAG.getValueType(MVT::i1));
12814 else if (Known.Zero == 0xffffff00)
12815 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
12816 DAG.getValueType(MVT::i8));
12817 else if (Known.Zero == 0xffff0000)
12818 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
12819 DAG.getValueType(MVT::i16));
12825 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
12826 DAGCombinerInfo &DCI) const {
12827 switch (N->getOpcode()) {
12829 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget);
12830 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget);
12831 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
12832 case ISD::SUB: return PerformSUBCombine(N, DCI);
12833 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
12834 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
12835 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
12836 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
12838 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget);
12839 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget);
12840 case ARMISD::BFI: return PerformBFICombine(N, DCI);
12841 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
12842 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
12843 case ISD::STORE: return PerformSTORECombine(N, DCI);
12844 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
12845 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
12846 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
12847 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
12848 case ARMISD::VDUP: return PerformVDUPCombine(N, DCI);
12849 case ISD::FP_TO_SINT:
12850 case ISD::FP_TO_UINT:
12851 return PerformVCVTCombine(N, DCI.DAG, Subtarget);
12853 return PerformVDIVCombine(N, DCI.DAG, Subtarget);
12854 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
12857 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
12858 case ISD::SIGN_EXTEND:
12859 case ISD::ZERO_EXTEND:
12860 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
12861 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
12862 case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG);
12863 case ISD::LOAD: return PerformLOADCombine(N, DCI);
12864 case ARMISD::VLD1DUP:
12865 case ARMISD::VLD2DUP:
12866 case ARMISD::VLD3DUP:
12867 case ARMISD::VLD4DUP:
12868 return PerformVLDCombine(N, DCI);
12869 case ARMISD::BUILD_VECTOR:
12870 return PerformARMBUILD_VECTORCombine(N, DCI);
12871 case ARMISD::SMULWB: {
12872 unsigned BitWidth = N->getValueType(0).getSizeInBits();
12873 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
12874 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
12878 case ARMISD::SMULWT: {
12879 unsigned BitWidth = N->getValueType(0).getSizeInBits();
12880 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 16);
12881 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
12885 case ARMISD::SMLALBB: {
12886 unsigned BitWidth = N->getValueType(0).getSizeInBits();
12887 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
12888 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
12889 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
12893 case ARMISD::SMLALBT: {
12894 unsigned LowWidth = N->getOperand(0).getValueType().getSizeInBits();
12895 APInt LowMask = APInt::getLowBitsSet(LowWidth, 16);
12896 unsigned HighWidth = N->getOperand(1).getValueType().getSizeInBits();
12897 APInt HighMask = APInt::getHighBitsSet(HighWidth, 16);
12898 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) ||
12899 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI)))
12903 case ARMISD::SMLALTB: {
12904 unsigned HighWidth = N->getOperand(0).getValueType().getSizeInBits();
12905 APInt HighMask = APInt::getHighBitsSet(HighWidth, 16);
12906 unsigned LowWidth = N->getOperand(1).getValueType().getSizeInBits();
12907 APInt LowMask = APInt::getLowBitsSet(LowWidth, 16);
12908 if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) ||
12909 (SimplifyDemandedBits(N->getOperand(1), LowMask, DCI)))
12913 case ARMISD::SMLALTT: {
12914 unsigned BitWidth = N->getValueType(0).getSizeInBits();
12915 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 16);
12916 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
12917 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
12921 case ISD::INTRINSIC_VOID:
12922 case ISD::INTRINSIC_W_CHAIN:
12923 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
12924 case Intrinsic::arm_neon_vld1:
12925 case Intrinsic::arm_neon_vld1x2:
12926 case Intrinsic::arm_neon_vld1x3:
12927 case Intrinsic::arm_neon_vld1x4:
12928 case Intrinsic::arm_neon_vld2:
12929 case Intrinsic::arm_neon_vld3:
12930 case Intrinsic::arm_neon_vld4:
12931 case Intrinsic::arm_neon_vld2lane:
12932 case Intrinsic::arm_neon_vld3lane:
12933 case Intrinsic::arm_neon_vld4lane:
12934 case Intrinsic::arm_neon_vld2dup:
12935 case Intrinsic::arm_neon_vld3dup:
12936 case Intrinsic::arm_neon_vld4dup:
12937 case Intrinsic::arm_neon_vst1:
12938 case Intrinsic::arm_neon_vst1x2:
12939 case Intrinsic::arm_neon_vst1x3:
12940 case Intrinsic::arm_neon_vst1x4:
12941 case Intrinsic::arm_neon_vst2:
12942 case Intrinsic::arm_neon_vst3:
12943 case Intrinsic::arm_neon_vst4:
12944 case Intrinsic::arm_neon_vst2lane:
12945 case Intrinsic::arm_neon_vst3lane:
12946 case Intrinsic::arm_neon_vst4lane:
12947 return PerformVLDCombine(N, DCI);
12955 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
12957 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
12960 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
12963 bool *Fast) const {
12964 // Depends what it gets converted into if the type is weird.
12965 if (!VT.isSimple())
12968 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
12969 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
12971 switch (VT.getSimpleVT().SimpleTy) {
12977 // Unaligned access can use (for example) LRDB, LRDH, LDR
12978 if (AllowsUnaligned) {
12980 *Fast = Subtarget->hasV7Ops();
12987 // For any little-endian targets with neon, we can support unaligned ld/st
12988 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
12989 // A big-endian target may also explicitly support unaligned accesses
12990 if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) {
13000 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
13001 unsigned AlignCheck) {
13002 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
13003 (DstAlign == 0 || DstAlign % AlignCheck == 0));
13006 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
13007 unsigned DstAlign, unsigned SrcAlign,
13008 bool IsMemset, bool ZeroMemset,
13010 MachineFunction &MF) const {
13011 const Function &F = MF.getFunction();
13013 // See if we can use NEON instructions for this...
13014 if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() &&
13015 !F.hasFnAttribute(Attribute::NoImplicitFloat)) {
13018 (memOpAlign(SrcAlign, DstAlign, 16) ||
13019 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
13021 } else if (Size >= 8 &&
13022 (memOpAlign(SrcAlign, DstAlign, 8) ||
13023 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
13029 // Let the target-independent logic figure it out.
13033 // 64-bit integers are split into their high and low parts and held in two
13034 // different registers, so the trunc is free since the low register can just
13036 bool ARMTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
13037 if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
13039 unsigned SrcBits = SrcTy->getPrimitiveSizeInBits();
13040 unsigned DestBits = DstTy->getPrimitiveSizeInBits();
13041 return (SrcBits == 64 && DestBits == 32);
13044 bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
13045 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() ||
13046 !DstVT.isInteger())
13048 unsigned SrcBits = SrcVT.getSizeInBits();
13049 unsigned DestBits = DstVT.getSizeInBits();
13050 return (SrcBits == 64 && DestBits == 32);
13053 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13054 if (Val.getOpcode() != ISD::LOAD)
13057 EVT VT1 = Val.getValueType();
13058 if (!VT1.isSimple() || !VT1.isInteger() ||
13059 !VT2.isSimple() || !VT2.isInteger())
13062 switch (VT1.getSimpleVT().SimpleTy) {
13067 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
13074 bool ARMTargetLowering::isFNegFree(EVT VT) const {
13075 if (!VT.isSimple())
13078 // There are quite a few FP16 instructions (e.g. VNMLA, VNMLS, etc.) that
13079 // negate values directly (fneg is free). So, we don't want to let the DAG
13080 // combiner rewrite fneg into xors and some other instructions. For f16 and
13081 // FullFP16 argument passing, some bitcast nodes may be introduced,
13082 // triggering this DAG combine rewrite, so we are avoiding that with this.
13083 switch (VT.getSimpleVT().SimpleTy) {
13086 return Subtarget->hasFullFP16();
13092 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
13093 EVT VT = ExtVal.getValueType();
13095 if (!isTypeLegal(VT))
13098 // Don't create a loadext if we can fold the extension into a wide/long
13100 // If there's more than one user instruction, the loadext is desirable no
13101 // matter what. There can be two uses by the same instruction.
13102 if (ExtVal->use_empty() ||
13103 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
13106 SDNode *U = *ExtVal->use_begin();
13107 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
13108 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
13114 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13115 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13118 if (!isTypeLegal(EVT::getEVT(Ty1)))
13121 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13123 // Assuming the caller doesn't have a zeroext or signext return parameter,
13124 // truncation all the way down to i1 is valid.
13128 int ARMTargetLowering::getScalingFactorCost(const DataLayout &DL,
13129 const AddrMode &AM, Type *Ty,
13130 unsigned AS) const {
13131 if (isLegalAddressingMode(DL, AM, Ty, AS)) {
13132 if (Subtarget->hasFPAO())
13133 return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster
13139 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
13143 unsigned Scale = 1;
13144 switch (VT.getSimpleVT().SimpleTy) {
13145 default: return false;
13160 if ((V & (Scale - 1)) != 0)
13163 return V == (V & ((1LL << 5) - 1));
13166 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
13167 const ARMSubtarget *Subtarget) {
13168 bool isNeg = false;
13174 switch (VT.getSimpleVT().SimpleTy) {
13175 default: return false;
13180 // + imm12 or - imm8
13182 return V == (V & ((1LL << 8) - 1));
13183 return V == (V & ((1LL << 12) - 1));
13186 // Same as ARM mode. FIXME: NEON?
13187 if (!Subtarget->hasVFP2())
13192 return V == (V & ((1LL << 8) - 1));
13196 /// isLegalAddressImmediate - Return true if the integer value can be used
13197 /// as the offset of the target addressing mode for load / store of the
13199 static bool isLegalAddressImmediate(int64_t V, EVT VT,
13200 const ARMSubtarget *Subtarget) {
13204 if (!VT.isSimple())
13207 if (Subtarget->isThumb1Only())
13208 return isLegalT1AddressImmediate(V, VT);
13209 else if (Subtarget->isThumb2())
13210 return isLegalT2AddressImmediate(V, VT, Subtarget);
13215 switch (VT.getSimpleVT().SimpleTy) {
13216 default: return false;
13221 return V == (V & ((1LL << 12) - 1));
13224 return V == (V & ((1LL << 8) - 1));
13227 if (!Subtarget->hasVFP2()) // FIXME: NEON?
13232 return V == (V & ((1LL << 8) - 1));
13236 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
13238 int Scale = AM.Scale;
13242 switch (VT.getSimpleVT().SimpleTy) {
13243 default: return false;
13251 Scale = Scale & ~1;
13252 return Scale == 2 || Scale == 4 || Scale == 8;
13254 // FIXME: What are we trying to model here? ldrd doesn't have an r + r
13255 // version in Thumb mode.
13259 // r * 2 (this can be lowered to r + r).
13260 if (!AM.HasBaseReg && Scale == 2)
13264 // Note, we allow "void" uses (basically, uses that aren't loads or
13265 // stores), because arm allows folding a scale into many arithmetic
13266 // operations. This should be made more precise and revisited later.
13268 // Allow r << imm, but the imm has to be a multiple of two.
13269 if (Scale & 1) return false;
13270 return isPowerOf2_32(Scale);
13274 bool ARMTargetLowering::isLegalT1ScaledAddressingMode(const AddrMode &AM,
13276 const int Scale = AM.Scale;
13278 // Negative scales are not supported in Thumb1.
13282 // Thumb1 addressing modes do not support register scaling excepting the
13283 // following cases:
13284 // 1. Scale == 1 means no scaling.
13285 // 2. Scale == 2 this can be lowered to r + r if there is no base register.
13286 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2);
13289 /// isLegalAddressingMode - Return true if the addressing mode represented
13290 /// by AM is legal for this target, for a load/store of the specified type.
13291 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
13292 const AddrMode &AM, Type *Ty,
13293 unsigned AS, Instruction *I) const {
13294 EVT VT = getValueType(DL, Ty, true);
13295 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
13298 // Can never fold addr of global into load/store.
13302 switch (AM.Scale) {
13303 case 0: // no scale reg, must be "r+i" or "r", or "i".
13306 // ARM doesn't support any R+R*scale+imm addr modes.
13310 if (!VT.isSimple())
13313 if (Subtarget->isThumb1Only())
13314 return isLegalT1ScaledAddressingMode(AM, VT);
13316 if (Subtarget->isThumb2())
13317 return isLegalT2ScaledAddressingMode(AM, VT);
13319 int Scale = AM.Scale;
13320 switch (VT.getSimpleVT().SimpleTy) {
13321 default: return false;
13325 if (Scale < 0) Scale = -Scale;
13329 return isPowerOf2_32(Scale & ~1);
13333 if (Scale == 1 || (AM.HasBaseReg && Scale == -1))
13335 // r * 2 (this can be lowered to r + r).
13336 if (!AM.HasBaseReg && Scale == 2)
13341 // Note, we allow "void" uses (basically, uses that aren't loads or
13342 // stores), because arm allows folding a scale into many arithmetic
13343 // operations. This should be made more precise and revisited later.
13345 // Allow r << imm, but the imm has to be a multiple of two.
13346 if (Scale & 1) return false;
13347 return isPowerOf2_32(Scale);
13353 /// isLegalICmpImmediate - Return true if the specified immediate is legal
13354 /// icmp immediate, that is the target has icmp instructions which can compare
13355 /// a register against the immediate without having to materialize the
13356 /// immediate into a register.
13357 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13358 // Thumb2 and ARM modes can use cmn for negative immediates.
13359 if (!Subtarget->isThumb())
13360 return ARM_AM::getSOImmVal((uint32_t)Imm) != -1 ||
13361 ARM_AM::getSOImmVal(-(uint32_t)Imm) != -1;
13362 if (Subtarget->isThumb2())
13363 return ARM_AM::getT2SOImmVal((uint32_t)Imm) != -1 ||
13364 ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
13365 // Thumb1 doesn't have cmn, and only 8-bit immediates.
13366 return Imm >= 0 && Imm <= 255;
13369 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
13370 /// *or sub* immediate, that is the target has add or sub instructions which can
13371 /// add a register with the immediate without having to materialize the
13372 /// immediate into a register.
13373 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
13374 // Same encoding for add/sub, just flip the sign.
13375 int64_t AbsImm = std::abs(Imm);
13376 if (!Subtarget->isThumb())
13377 return ARM_AM::getSOImmVal(AbsImm) != -1;
13378 if (Subtarget->isThumb2())
13379 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
13380 // Thumb1 only has 8-bit unsigned immediate.
13381 return AbsImm >= 0 && AbsImm <= 255;
13384 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
13385 bool isSEXTLoad, SDValue &Base,
13386 SDValue &Offset, bool &isInc,
13387 SelectionDAG &DAG) {
13388 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
13391 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
13392 // AddressingMode 3
13393 Base = Ptr->getOperand(0);
13394 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
13395 int RHSC = (int)RHS->getZExtValue();
13396 if (RHSC < 0 && RHSC > -256) {
13397 assert(Ptr->getOpcode() == ISD::ADD);
13399 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
13403 isInc = (Ptr->getOpcode() == ISD::ADD);
13404 Offset = Ptr->getOperand(1);
13406 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
13407 // AddressingMode 2
13408 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
13409 int RHSC = (int)RHS->getZExtValue();
13410 if (RHSC < 0 && RHSC > -0x1000) {
13411 assert(Ptr->getOpcode() == ISD::ADD);
13413 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
13414 Base = Ptr->getOperand(0);
13419 if (Ptr->getOpcode() == ISD::ADD) {
13421 ARM_AM::ShiftOpc ShOpcVal=
13422 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
13423 if (ShOpcVal != ARM_AM::no_shift) {
13424 Base = Ptr->getOperand(1);
13425 Offset = Ptr->getOperand(0);
13427 Base = Ptr->getOperand(0);
13428 Offset = Ptr->getOperand(1);
13433 isInc = (Ptr->getOpcode() == ISD::ADD);
13434 Base = Ptr->getOperand(0);
13435 Offset = Ptr->getOperand(1);
13439 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
13443 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
13444 bool isSEXTLoad, SDValue &Base,
13445 SDValue &Offset, bool &isInc,
13446 SelectionDAG &DAG) {
13447 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
13450 Base = Ptr->getOperand(0);
13451 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
13452 int RHSC = (int)RHS->getZExtValue();
13453 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
13454 assert(Ptr->getOpcode() == ISD::ADD);
13456 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
13458 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
13459 isInc = Ptr->getOpcode() == ISD::ADD;
13460 Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0));
13468 /// getPreIndexedAddressParts - returns true by value, base pointer and
13469 /// offset pointer and addressing mode by reference if the node's address
13470 /// can be legally represented as pre-indexed load / store address.
13472 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
13474 ISD::MemIndexedMode &AM,
13475 SelectionDAG &DAG) const {
13476 if (Subtarget->isThumb1Only())
13481 bool isSEXTLoad = false;
13482 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
13483 Ptr = LD->getBasePtr();
13484 VT = LD->getMemoryVT();
13485 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
13486 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
13487 Ptr = ST->getBasePtr();
13488 VT = ST->getMemoryVT();
13493 bool isLegal = false;
13494 if (Subtarget->isThumb2())
13495 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
13496 Offset, isInc, DAG);
13498 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
13499 Offset, isInc, DAG);
13503 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
13507 /// getPostIndexedAddressParts - returns true by value, base pointer and
13508 /// offset pointer and addressing mode by reference if this node can be
13509 /// combined with a load / store to form a post-indexed load / store.
13510 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
13513 ISD::MemIndexedMode &AM,
13514 SelectionDAG &DAG) const {
13517 bool isSEXTLoad = false, isNonExt;
13518 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
13519 VT = LD->getMemoryVT();
13520 Ptr = LD->getBasePtr();
13521 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
13522 isNonExt = LD->getExtensionType() == ISD::NON_EXTLOAD;
13523 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
13524 VT = ST->getMemoryVT();
13525 Ptr = ST->getBasePtr();
13526 isNonExt = !ST->isTruncatingStore();
13530 if (Subtarget->isThumb1Only()) {
13531 // Thumb-1 can do a limited post-inc load or store as an updating LDM. It
13532 // must be non-extending/truncating, i32, with an offset of 4.
13533 assert(Op->getValueType(0) == MVT::i32 && "Non-i32 post-inc op?!");
13534 if (Op->getOpcode() != ISD::ADD || !isNonExt)
13536 auto *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1));
13537 if (!RHS || RHS->getZExtValue() != 4)
13540 Offset = Op->getOperand(1);
13541 Base = Op->getOperand(0);
13542 AM = ISD::POST_INC;
13547 bool isLegal = false;
13548 if (Subtarget->isThumb2())
13549 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
13552 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
13558 // Swap base ptr and offset to catch more post-index load / store when
13559 // it's legal. In Thumb2 mode, offset must be an immediate.
13560 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
13561 !Subtarget->isThumb2())
13562 std::swap(Base, Offset);
13564 // Post-indexed load / store update the base pointer.
13569 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
13573 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
13575 const APInt &DemandedElts,
13576 const SelectionDAG &DAG,
13577 unsigned Depth) const {
13578 unsigned BitWidth = Known.getBitWidth();
13580 switch (Op.getOpcode()) {
13586 // Special cases when we convert a carry to a boolean.
13587 if (Op.getResNo() == 0) {
13588 SDValue LHS = Op.getOperand(0);
13589 SDValue RHS = Op.getOperand(1);
13590 // (ADDE 0, 0, C) will give us a single bit.
13591 if (Op->getOpcode() == ARMISD::ADDE && isNullConstant(LHS) &&
13592 isNullConstant(RHS)) {
13593 Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
13598 case ARMISD::CMOV: {
13599 // Bits are known zero/one if known on the LHS and RHS.
13600 Known = DAG.computeKnownBits(Op.getOperand(0), Depth+1);
13601 if (Known.isUnknown())
13604 KnownBits KnownRHS = DAG.computeKnownBits(Op.getOperand(1), Depth+1);
13605 Known.Zero &= KnownRHS.Zero;
13606 Known.One &= KnownRHS.One;
13609 case ISD::INTRINSIC_W_CHAIN: {
13610 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
13611 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
13614 case Intrinsic::arm_ldaex:
13615 case Intrinsic::arm_ldrex: {
13616 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
13617 unsigned MemBits = VT.getScalarSizeInBits();
13618 Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
13623 case ARMISD::BFI: {
13624 // Conservatively, we can recurse down the first operand
13625 // and just mask out all affected bits.
13626 Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
13628 // The operand to BFI is already a mask suitable for removing the bits it
13630 ConstantSDNode *CI = cast<ConstantSDNode>(Op.getOperand(2));
13631 const APInt &Mask = CI->getAPIntValue();
13632 Known.Zero &= Mask;
13636 case ARMISD::VGETLANEs:
13637 case ARMISD::VGETLANEu: {
13638 const SDValue &SrcSV = Op.getOperand(0);
13639 EVT VecVT = SrcSV.getValueType();
13640 assert(VecVT.isVector() && "VGETLANE expected a vector type");
13641 const unsigned NumSrcElts = VecVT.getVectorNumElements();
13642 ConstantSDNode *Pos = cast<ConstantSDNode>(Op.getOperand(1).getNode());
13643 assert(Pos->getAPIntValue().ult(NumSrcElts) &&
13644 "VGETLANE index out of bounds");
13645 unsigned Idx = Pos->getZExtValue();
13646 APInt DemandedElt = APInt::getOneBitSet(NumSrcElts, Idx);
13647 Known = DAG.computeKnownBits(SrcSV, DemandedElt, Depth + 1);
13649 EVT VT = Op.getValueType();
13650 const unsigned DstSz = VT.getScalarSizeInBits();
13651 const unsigned SrcSz = VecVT.getVectorElementType().getSizeInBits();
13652 assert(SrcSz == Known.getBitWidth());
13653 assert(DstSz > SrcSz);
13654 if (Op.getOpcode() == ARMISD::VGETLANEs)
13655 Known = Known.sext(DstSz);
13657 Known = Known.zext(DstSz);
13658 Known.Zero.setBitsFrom(SrcSz);
13660 assert(DstSz == Known.getBitWidth());
13667 ARMTargetLowering::targetShrinkDemandedConstant(SDValue Op,
13668 const APInt &DemandedAPInt,
13669 TargetLoweringOpt &TLO) const {
13670 // Delay optimization, so we don't have to deal with illegal types, or block
13675 // Only optimize AND for now.
13676 if (Op.getOpcode() != ISD::AND)
13679 EVT VT = Op.getValueType();
13685 assert(VT == MVT::i32 && "Unexpected integer type");
13687 // Make sure the RHS really is a constant.
13688 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13692 unsigned Mask = C->getZExtValue();
13694 unsigned Demanded = DemandedAPInt.getZExtValue();
13695 unsigned ShrunkMask = Mask & Demanded;
13696 unsigned ExpandedMask = Mask | ~Demanded;
13698 // If the mask is all zeros, let the target-independent code replace the
13699 // result with zero.
13700 if (ShrunkMask == 0)
13703 // If the mask is all ones, erase the AND. (Currently, the target-independent
13704 // code won't do this, so we have to do it explicitly to avoid an infinite
13705 // loop in obscure cases.)
13706 if (ExpandedMask == ~0U)
13707 return TLO.CombineTo(Op, Op.getOperand(0));
13709 auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
13710 return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0;
13712 auto UseMask = [Mask, Op, VT, &TLO](unsigned NewMask) -> bool {
13713 if (NewMask == Mask)
13716 SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT);
13717 SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);
13718 return TLO.CombineTo(Op, NewOp);
13721 // Prefer uxtb mask.
13722 if (IsLegalMask(0xFF))
13723 return UseMask(0xFF);
13725 // Prefer uxth mask.
13726 if (IsLegalMask(0xFFFF))
13727 return UseMask(0xFFFF);
13729 // [1, 255] is Thumb1 movs+ands, legal immediate for ARM/Thumb2.
13730 // FIXME: Prefer a contiguous sequence of bits for other optimizations.
13731 if (ShrunkMask < 256)
13732 return UseMask(ShrunkMask);
13734 // [-256, -2] is Thumb1 movs+bics, legal immediate for ARM/Thumb2.
13735 // FIXME: Prefer a contiguous sequence of bits for other optimizations.
13736 if ((int)ExpandedMask <= -2 && (int)ExpandedMask >= -256)
13737 return UseMask(ExpandedMask);
13739 // Potential improvements:
13741 // We could try to recognize lsls+lsrs or lsrs+lsls pairs here.
13742 // We could try to prefer Thumb1 immediates which can be lowered to a
13743 // two-instruction sequence.
13744 // We could try to recognize more legal ARM/Thumb2 immediates here.
13750 //===----------------------------------------------------------------------===//
13751 // ARM Inline Assembly Support
13752 //===----------------------------------------------------------------------===//
13754 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
13755 // Looking for "rev" which is V6+.
13756 if (!Subtarget->hasV6Ops())
13759 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13760 std::string AsmStr = IA->getAsmString();
13761 SmallVector<StringRef, 4> AsmPieces;
13762 SplitString(AsmStr, AsmPieces, ";\n");
13764 switch (AsmPieces.size()) {
13765 default: return false;
13767 AsmStr = AsmPieces[0];
13769 SplitString(AsmStr, AsmPieces, " \t,");
13772 if (AsmPieces.size() == 3 &&
13773 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
13774 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
13775 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13776 if (Ty && Ty->getBitWidth() == 32)
13777 return IntrinsicLowering::LowerToByteSwap(CI);
13785 const char *ARMTargetLowering::LowerXConstraint(EVT ConstraintVT) const {
13786 // At this point, we have to lower this constraint to something else, so we
13787 // lower it to an "r" or "w". However, by doing this we will force the result
13788 // to be in register, while the X constraint is much more permissive.
13790 // Although we are correct (we are free to emit anything, without
13791 // constraints), we might break use cases that would expect us to be more
13792 // efficient and emit something else.
13793 if (!Subtarget->hasVFP2())
13795 if (ConstraintVT.isFloatingPoint())
13797 if (ConstraintVT.isVector() && Subtarget->hasNEON() &&
13798 (ConstraintVT.getSizeInBits() == 64 ||
13799 ConstraintVT.getSizeInBits() == 128))
13805 /// getConstraintType - Given a constraint letter, return the type of
13806 /// constraint it is for this target.
13807 ARMTargetLowering::ConstraintType
13808 ARMTargetLowering::getConstraintType(StringRef Constraint) const {
13809 if (Constraint.size() == 1) {
13810 switch (Constraint[0]) {
13812 case 'l': return C_RegisterClass;
13813 case 'w': return C_RegisterClass;
13814 case 'h': return C_RegisterClass;
13815 case 'x': return C_RegisterClass;
13816 case 't': return C_RegisterClass;
13817 case 'j': return C_Other; // Constant for movw.
13818 // An address with a single base register. Due to the way we
13819 // currently handle addresses it is the same as an 'r' memory constraint.
13820 case 'Q': return C_Memory;
13822 } else if (Constraint.size() == 2) {
13823 switch (Constraint[0]) {
13825 // All 'U+' constraints are addresses.
13826 case 'U': return C_Memory;
13829 return TargetLowering::getConstraintType(Constraint);
13832 /// Examine constraint type and operand type and determine a weight value.
13833 /// This object must already have been set up with the operand type
13834 /// and the current alternative constraint selected.
13835 TargetLowering::ConstraintWeight
13836 ARMTargetLowering::getSingleConstraintMatchWeight(
13837 AsmOperandInfo &info, const char *constraint) const {
13838 ConstraintWeight weight = CW_Invalid;
13839 Value *CallOperandVal = info.CallOperandVal;
13840 // If we don't have a value, we can't do a match,
13841 // but allow it at the lowest weight.
13842 if (!CallOperandVal)
13844 Type *type = CallOperandVal->getType();
13845 // Look at the constraint type.
13846 switch (*constraint) {
13848 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
13851 if (type->isIntegerTy()) {
13852 if (Subtarget->isThumb())
13853 weight = CW_SpecificReg;
13855 weight = CW_Register;
13859 if (type->isFloatingPointTy())
13860 weight = CW_Register;
13866 using RCPair = std::pair<unsigned, const TargetRegisterClass *>;
13868 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
13869 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
13870 if (Constraint.size() == 1) {
13871 // GCC ARM Constraint Letters
13872 switch (Constraint[0]) {
13873 case 'l': // Low regs or general regs.
13874 if (Subtarget->isThumb())
13875 return RCPair(0U, &ARM::tGPRRegClass);
13876 return RCPair(0U, &ARM::GPRRegClass);
13877 case 'h': // High regs or no regs.
13878 if (Subtarget->isThumb())
13879 return RCPair(0U, &ARM::hGPRRegClass);
13882 if (Subtarget->isThumb1Only())
13883 return RCPair(0U, &ARM::tGPRRegClass);
13884 return RCPair(0U, &ARM::GPRRegClass);
13886 if (VT == MVT::Other)
13888 if (VT == MVT::f32)
13889 return RCPair(0U, &ARM::SPRRegClass);
13890 if (VT.getSizeInBits() == 64)
13891 return RCPair(0U, &ARM::DPRRegClass);
13892 if (VT.getSizeInBits() == 128)
13893 return RCPair(0U, &ARM::QPRRegClass);
13896 if (VT == MVT::Other)
13898 if (VT == MVT::f32)
13899 return RCPair(0U, &ARM::SPR_8RegClass);
13900 if (VT.getSizeInBits() == 64)
13901 return RCPair(0U, &ARM::DPR_8RegClass);
13902 if (VT.getSizeInBits() == 128)
13903 return RCPair(0U, &ARM::QPR_8RegClass);
13906 if (VT == MVT::Other)
13908 if (VT == MVT::f32 || VT == MVT::i32)
13909 return RCPair(0U, &ARM::SPRRegClass);
13910 if (VT.getSizeInBits() == 64)
13911 return RCPair(0U, &ARM::DPR_VFP2RegClass);
13912 if (VT.getSizeInBits() == 128)
13913 return RCPair(0U, &ARM::QPR_VFP2RegClass);
13917 if (StringRef("{cc}").equals_lower(Constraint))
13918 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
13920 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
13923 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
13924 /// vector. If it is invalid, don't add anything to Ops.
13925 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
13926 std::string &Constraint,
13927 std::vector<SDValue>&Ops,
13928 SelectionDAG &DAG) const {
13931 // Currently only support length 1 constraints.
13932 if (Constraint.length() != 1) return;
13934 char ConstraintLetter = Constraint[0];
13935 switch (ConstraintLetter) {
13938 case 'I': case 'J': case 'K': case 'L':
13939 case 'M': case 'N': case 'O':
13940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
13944 int64_t CVal64 = C->getSExtValue();
13945 int CVal = (int) CVal64;
13946 // None of these constraints allow values larger than 32 bits. Check
13947 // that the value fits in an int.
13948 if (CVal != CVal64)
13951 switch (ConstraintLetter) {
13953 // Constant suitable for movw, must be between 0 and
13955 if (Subtarget->hasV6T2Ops())
13956 if (CVal >= 0 && CVal <= 65535)
13960 if (Subtarget->isThumb1Only()) {
13961 // This must be a constant between 0 and 255, for ADD
13963 if (CVal >= 0 && CVal <= 255)
13965 } else if (Subtarget->isThumb2()) {
13966 // A constant that can be used as an immediate value in a
13967 // data-processing instruction.
13968 if (ARM_AM::getT2SOImmVal(CVal) != -1)
13971 // A constant that can be used as an immediate value in a
13972 // data-processing instruction.
13973 if (ARM_AM::getSOImmVal(CVal) != -1)
13979 if (Subtarget->isThumb1Only()) {
13980 // This must be a constant between -255 and -1, for negated ADD
13981 // immediates. This can be used in GCC with an "n" modifier that
13982 // prints the negated value, for use with SUB instructions. It is
13983 // not useful otherwise but is implemented for compatibility.
13984 if (CVal >= -255 && CVal <= -1)
13987 // This must be a constant between -4095 and 4095. It is not clear
13988 // what this constraint is intended for. Implemented for
13989 // compatibility with GCC.
13990 if (CVal >= -4095 && CVal <= 4095)
13996 if (Subtarget->isThumb1Only()) {
13997 // A 32-bit value where only one byte has a nonzero value. Exclude
13998 // zero to match GCC. This constraint is used by GCC internally for
13999 // constants that can be loaded with a move/shift combination.
14000 // It is not useful otherwise but is implemented for compatibility.
14001 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
14003 } else if (Subtarget->isThumb2()) {
14004 // A constant whose bitwise inverse can be used as an immediate
14005 // value in a data-processing instruction. This can be used in GCC
14006 // with a "B" modifier that prints the inverted value, for use with
14007 // BIC and MVN instructions. It is not useful otherwise but is
14008 // implemented for compatibility.
14009 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
14012 // A constant whose bitwise inverse can be used as an immediate
14013 // value in a data-processing instruction. This can be used in GCC
14014 // with a "B" modifier that prints the inverted value, for use with
14015 // BIC and MVN instructions. It is not useful otherwise but is
14016 // implemented for compatibility.
14017 if (ARM_AM::getSOImmVal(~CVal) != -1)
14023 if (Subtarget->isThumb1Only()) {
14024 // This must be a constant between -7 and 7,
14025 // for 3-operand ADD/SUB immediate instructions.
14026 if (CVal >= -7 && CVal < 7)
14028 } else if (Subtarget->isThumb2()) {
14029 // A constant whose negation can be used as an immediate value in a
14030 // data-processing instruction. This can be used in GCC with an "n"
14031 // modifier that prints the negated value, for use with SUB
14032 // instructions. It is not useful otherwise but is implemented for
14034 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
14037 // A constant whose negation can be used as an immediate value in a
14038 // data-processing instruction. This can be used in GCC with an "n"
14039 // modifier that prints the negated value, for use with SUB
14040 // instructions. It is not useful otherwise but is implemented for
14042 if (ARM_AM::getSOImmVal(-CVal) != -1)
14048 if (Subtarget->isThumb1Only()) {
14049 // This must be a multiple of 4 between 0 and 1020, for
14050 // ADD sp + immediate.
14051 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
14054 // A power of two or a constant between 0 and 32. This is used in
14055 // GCC for the shift amount on shifted register operands, but it is
14056 // useful in general for any shift amounts.
14057 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
14063 if (Subtarget->isThumb()) { // FIXME thumb2
14064 // This must be a constant between 0 and 31, for shift amounts.
14065 if (CVal >= 0 && CVal <= 31)
14071 if (Subtarget->isThumb()) { // FIXME thumb2
14072 // This must be a multiple of 4 between -508 and 508, for
14073 // ADD/SUB sp = sp + immediate.
14074 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
14079 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType());
14083 if (Result.getNode()) {
14084 Ops.push_back(Result);
14087 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14090 static RTLIB::Libcall getDivRemLibcall(
14091 const SDNode *N, MVT::SimpleValueType SVT) {
14092 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
14093 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
14094 "Unhandled Opcode in getDivRemLibcall");
14095 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
14096 N->getOpcode() == ISD::SREM;
14099 default: llvm_unreachable("Unexpected request for libcall!");
14100 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
14101 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
14102 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
14103 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
14108 static TargetLowering::ArgListTy getDivRemArgList(
14109 const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget) {
14110 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
14111 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
14112 "Unhandled Opcode in getDivRemArgList");
14113 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
14114 N->getOpcode() == ISD::SREM;
14115 TargetLowering::ArgListTy Args;
14116 TargetLowering::ArgListEntry Entry;
14117 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
14118 EVT ArgVT = N->getOperand(i).getValueType();
14119 Type *ArgTy = ArgVT.getTypeForEVT(*Context);
14120 Entry.Node = N->getOperand(i);
14122 Entry.IsSExt = isSigned;
14123 Entry.IsZExt = !isSigned;
14124 Args.push_back(Entry);
14126 if (Subtarget->isTargetWindows() && Args.size() >= 2)
14127 std::swap(Args[0], Args[1]);
14131 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
14132 assert((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
14133 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
14134 Subtarget->isTargetWindows()) &&
14135 "Register-based DivRem lowering only");
14136 unsigned Opcode = Op->getOpcode();
14137 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
14138 "Invalid opcode for Div/Rem lowering");
14139 bool isSigned = (Opcode == ISD::SDIVREM);
14140 EVT VT = Op->getValueType(0);
14141 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
14144 // If the target has hardware divide, use divide + multiply + subtract:
14146 // rem = a - b * div
14147 // return {div, rem}
14148 // This should be lowered into UDIV/SDIV + MLS later on.
14149 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
14150 : Subtarget->hasDivideInARMMode();
14151 if (hasDivide && Op->getValueType(0).isSimple() &&
14152 Op->getSimpleValueType(0) == MVT::i32) {
14153 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
14154 const SDValue Dividend = Op->getOperand(0);
14155 const SDValue Divisor = Op->getOperand(1);
14156 SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor);
14157 SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor);
14158 SDValue Rem = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul);
14160 SDValue Values[2] = {Div, Rem};
14161 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values);
14164 RTLIB::Libcall LC = getDivRemLibcall(Op.getNode(),
14165 VT.getSimpleVT().SimpleTy);
14166 SDValue InChain = DAG.getEntryNode();
14168 TargetLowering::ArgListTy Args = getDivRemArgList(Op.getNode(),
14172 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
14173 getPointerTy(DAG.getDataLayout()));
14175 Type *RetTy = StructType::get(Ty, Ty);
14177 if (Subtarget->isTargetWindows())
14178 InChain = WinDBZCheckDenominator(DAG, Op.getNode(), InChain);
14180 TargetLowering::CallLoweringInfo CLI(DAG);
14181 CLI.setDebugLoc(dl).setChain(InChain)
14182 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
14183 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
14185 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
14186 return CallInfo.first;
14189 // Lowers REM using divmod helpers
14190 // see RTABI section 4.2/4.3
14191 SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {
14192 // Build return types (div and rem)
14193 std::vector<Type*> RetTyParams;
14194 Type *RetTyElement;
14196 switch (N->getValueType(0).getSimpleVT().SimpleTy) {
14197 default: llvm_unreachable("Unexpected request for libcall!");
14198 case MVT::i8: RetTyElement = Type::getInt8Ty(*DAG.getContext()); break;
14199 case MVT::i16: RetTyElement = Type::getInt16Ty(*DAG.getContext()); break;
14200 case MVT::i32: RetTyElement = Type::getInt32Ty(*DAG.getContext()); break;
14201 case MVT::i64: RetTyElement = Type::getInt64Ty(*DAG.getContext()); break;
14204 RetTyParams.push_back(RetTyElement);
14205 RetTyParams.push_back(RetTyElement);
14206 ArrayRef<Type*> ret = ArrayRef<Type*>(RetTyParams);
14207 Type *RetTy = StructType::get(*DAG.getContext(), ret);
14209 RTLIB::Libcall LC = getDivRemLibcall(N, N->getValueType(0).getSimpleVT().
14211 SDValue InChain = DAG.getEntryNode();
14212 TargetLowering::ArgListTy Args = getDivRemArgList(N, DAG.getContext(),
14214 bool isSigned = N->getOpcode() == ISD::SREM;
14215 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
14216 getPointerTy(DAG.getDataLayout()));
14218 if (Subtarget->isTargetWindows())
14219 InChain = WinDBZCheckDenominator(DAG, N, InChain);
14222 CallLoweringInfo CLI(DAG);
14223 CLI.setChain(InChain)
14224 .setCallee(CallingConv::ARM_AAPCS, RetTy, Callee, std::move(Args))
14225 .setSExtResult(isSigned).setZExtResult(!isSigned).setDebugLoc(SDLoc(N));
14226 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
14228 // Return second (rem) result operand (first contains div)
14229 SDNode *ResNode = CallResult.first.getNode();
14230 assert(ResNode->getNumOperands() == 2 && "divmod should return two operands");
14231 return ResNode->getOperand(1);
14235 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
14236 assert(Subtarget->isTargetWindows() && "unsupported target platform");
14240 SDValue Chain = Op.getOperand(0);
14241 SDValue Size = Op.getOperand(1);
14243 if (DAG.getMachineFunction().getFunction().hasFnAttribute(
14244 "no-stack-arg-probe")) {
14245 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14246 SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
14247 Chain = SP.getValue(1);
14248 SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);
14250 SP = DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0),
14251 DAG.getConstant(-(uint64_t)Align, DL, MVT::i32));
14252 Chain = DAG.getCopyToReg(Chain, DL, ARM::SP, SP);
14253 SDValue Ops[2] = { SP, Chain };
14254 return DAG.getMergeValues(Ops, DL);
14257 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
14258 DAG.getConstant(2, DL, MVT::i32));
14261 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
14262 Flag = Chain.getValue(1);
14264 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14265 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
14267 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
14268 Chain = NewSP.getValue(1);
14270 SDValue Ops[2] = { NewSP, Chain };
14271 return DAG.getMergeValues(Ops, DL);
14274 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
14275 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
14276 "Unexpected type for custom-lowering FP_EXTEND");
14279 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
14281 SDValue SrcVal = Op.getOperand(0);
14282 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
14286 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
14287 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
14288 Subtarget->isFPOnlySP() &&
14289 "Unexpected type for custom-lowering FP_ROUND");
14292 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
14294 SDValue SrcVal = Op.getOperand(0);
14295 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
14300 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
14301 // The ARM target isn't yet aware of offsets.
14305 bool ARM::isBitFieldInvertedMask(unsigned v) {
14306 if (v == 0xffffffff)
14309 // there can be 1's on either or both "outsides", all the "inside"
14310 // bits must be 0's
14311 return isShiftedMask_32(~v);
14314 /// isFPImmLegal - Returns true if the target can instruction select the
14315 /// specified FP immediate natively. If false, the legalizer will
14316 /// materialize the FP immediate as a load from a constant pool.
14317 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
14318 if (!Subtarget->hasVFP3())
14320 if (VT == MVT::f16 && Subtarget->hasFullFP16())
14321 return ARM_AM::getFP16Imm(Imm) != -1;
14322 if (VT == MVT::f32)
14323 return ARM_AM::getFP32Imm(Imm) != -1;
14324 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
14325 return ARM_AM::getFP64Imm(Imm) != -1;
14329 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
14330 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
14331 /// specified in the intrinsic calls.
14332 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
14334 MachineFunction &MF,
14335 unsigned Intrinsic) const {
14336 switch (Intrinsic) {
14337 case Intrinsic::arm_neon_vld1:
14338 case Intrinsic::arm_neon_vld2:
14339 case Intrinsic::arm_neon_vld3:
14340 case Intrinsic::arm_neon_vld4:
14341 case Intrinsic::arm_neon_vld2lane:
14342 case Intrinsic::arm_neon_vld3lane:
14343 case Intrinsic::arm_neon_vld4lane:
14344 case Intrinsic::arm_neon_vld2dup:
14345 case Intrinsic::arm_neon_vld3dup:
14346 case Intrinsic::arm_neon_vld4dup: {
14347 Info.opc = ISD::INTRINSIC_W_CHAIN;
14348 // Conservatively set memVT to the entire set of vectors loaded.
14349 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
14350 uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
14351 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
14352 Info.ptrVal = I.getArgOperand(0);
14354 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
14355 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
14356 // volatile loads with NEON intrinsics not supported
14357 Info.flags = MachineMemOperand::MOLoad;
14360 case Intrinsic::arm_neon_vld1x2:
14361 case Intrinsic::arm_neon_vld1x3:
14362 case Intrinsic::arm_neon_vld1x4: {
14363 Info.opc = ISD::INTRINSIC_W_CHAIN;
14364 // Conservatively set memVT to the entire set of vectors loaded.
14365 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
14366 uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
14367 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
14368 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
14371 // volatile loads with NEON intrinsics not supported
14372 Info.flags = MachineMemOperand::MOLoad;
14375 case Intrinsic::arm_neon_vst1:
14376 case Intrinsic::arm_neon_vst2:
14377 case Intrinsic::arm_neon_vst3:
14378 case Intrinsic::arm_neon_vst4:
14379 case Intrinsic::arm_neon_vst2lane:
14380 case Intrinsic::arm_neon_vst3lane:
14381 case Intrinsic::arm_neon_vst4lane: {
14382 Info.opc = ISD::INTRINSIC_VOID;
14383 // Conservatively set memVT to the entire set of vectors stored.
14384 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
14385 unsigned NumElts = 0;
14386 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
14387 Type *ArgTy = I.getArgOperand(ArgI)->getType();
14388 if (!ArgTy->isVectorTy())
14390 NumElts += DL.getTypeSizeInBits(ArgTy) / 64;
14392 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
14393 Info.ptrVal = I.getArgOperand(0);
14395 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
14396 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
14397 // volatile stores with NEON intrinsics not supported
14398 Info.flags = MachineMemOperand::MOStore;
14401 case Intrinsic::arm_neon_vst1x2:
14402 case Intrinsic::arm_neon_vst1x3:
14403 case Intrinsic::arm_neon_vst1x4: {
14404 Info.opc = ISD::INTRINSIC_VOID;
14405 // Conservatively set memVT to the entire set of vectors stored.
14406 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
14407 unsigned NumElts = 0;
14408 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
14409 Type *ArgTy = I.getArgOperand(ArgI)->getType();
14410 if (!ArgTy->isVectorTy())
14412 NumElts += DL.getTypeSizeInBits(ArgTy) / 64;
14414 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
14415 Info.ptrVal = I.getArgOperand(0);
14418 // volatile stores with NEON intrinsics not supported
14419 Info.flags = MachineMemOperand::MOStore;
14422 case Intrinsic::arm_ldaex:
14423 case Intrinsic::arm_ldrex: {
14424 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
14425 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
14426 Info.opc = ISD::INTRINSIC_W_CHAIN;
14427 Info.memVT = MVT::getVT(PtrTy->getElementType());
14428 Info.ptrVal = I.getArgOperand(0);
14430 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
14431 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
14434 case Intrinsic::arm_stlex:
14435 case Intrinsic::arm_strex: {
14436 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
14437 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
14438 Info.opc = ISD::INTRINSIC_W_CHAIN;
14439 Info.memVT = MVT::getVT(PtrTy->getElementType());
14440 Info.ptrVal = I.getArgOperand(1);
14442 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
14443 Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
14446 case Intrinsic::arm_stlexd:
14447 case Intrinsic::arm_strexd:
14448 Info.opc = ISD::INTRINSIC_W_CHAIN;
14449 Info.memVT = MVT::i64;
14450 Info.ptrVal = I.getArgOperand(2);
14453 Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
14456 case Intrinsic::arm_ldaexd:
14457 case Intrinsic::arm_ldrexd:
14458 Info.opc = ISD::INTRINSIC_W_CHAIN;
14459 Info.memVT = MVT::i64;
14460 Info.ptrVal = I.getArgOperand(0);
14463 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
14473 /// Returns true if it is beneficial to convert a load of a constant
14474 /// to just the constant itself.
14475 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
14477 assert(Ty->isIntegerTy());
14479 unsigned Bits = Ty->getPrimitiveSizeInBits();
14480 if (Bits == 0 || Bits > 32)
14485 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
14486 unsigned Index) const {
14487 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
14490 return (Index == 0 || Index == ResVT.getVectorNumElements());
14493 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
14494 ARM_MB::MemBOpt Domain) const {
14495 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
14497 // First, if the target has no DMB, see what fallback we can use.
14498 if (!Subtarget->hasDataBarrier()) {
14499 // Some ARMv6 cpus can support data barriers with an mcr instruction.
14500 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
14502 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
14503 Function *MCR = Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
14504 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
14505 Builder.getInt32(0), Builder.getInt32(7),
14506 Builder.getInt32(10), Builder.getInt32(5)};
14507 return Builder.CreateCall(MCR, args);
14509 // Instead of using barriers, atomic accesses on these subtargets use
14511 llvm_unreachable("makeDMB on a target so old that it has no barriers");
14514 Function *DMB = Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
14515 // Only a full system barrier exists in the M-class architectures.
14516 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
14517 Constant *CDomain = Builder.getInt32(Domain);
14518 return Builder.CreateCall(DMB, CDomain);
14522 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
14523 Instruction *ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
14525 AtomicOrdering Ord) const {
14527 case AtomicOrdering::NotAtomic:
14528 case AtomicOrdering::Unordered:
14529 llvm_unreachable("Invalid fence: unordered/non-atomic");
14530 case AtomicOrdering::Monotonic:
14531 case AtomicOrdering::Acquire:
14532 return nullptr; // Nothing to do
14533 case AtomicOrdering::SequentiallyConsistent:
14534 if (!Inst->hasAtomicStore())
14535 return nullptr; // Nothing to do
14537 case AtomicOrdering::Release:
14538 case AtomicOrdering::AcquireRelease:
14539 if (Subtarget->preferISHSTBarriers())
14540 return makeDMB(Builder, ARM_MB::ISHST);
14541 // FIXME: add a comment with a link to documentation justifying this.
14543 return makeDMB(Builder, ARM_MB::ISH);
14545 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
14548 Instruction *ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
14550 AtomicOrdering Ord) const {
14552 case AtomicOrdering::NotAtomic:
14553 case AtomicOrdering::Unordered:
14554 llvm_unreachable("Invalid fence: unordered/not-atomic");
14555 case AtomicOrdering::Monotonic:
14556 case AtomicOrdering::Release:
14557 return nullptr; // Nothing to do
14558 case AtomicOrdering::Acquire:
14559 case AtomicOrdering::AcquireRelease:
14560 case AtomicOrdering::SequentiallyConsistent:
14561 return makeDMB(Builder, ARM_MB::ISH);
14563 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
14566 // Loads and stores less than 64-bits are already atomic; ones above that
14567 // are doomed anyway, so defer to the default libcall and blame the OS when
14568 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
14569 // anything for those.
14570 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
14571 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
14572 return (Size == 64) && !Subtarget->isMClass();
14575 // Loads and stores less than 64-bits are already atomic; ones above that
14576 // are doomed anyway, so defer to the default libcall and blame the OS when
14577 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
14578 // anything for those.
14579 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
14580 // guarantee, see DDI0406C ARM architecture reference manual,
14581 // sections A8.8.72-74 LDRD)
14582 TargetLowering::AtomicExpansionKind
14583 ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
14584 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
14585 return ((Size == 64) && !Subtarget->isMClass()) ? AtomicExpansionKind::LLOnly
14586 : AtomicExpansionKind::None;
14589 // For the real atomic operations, we have ldrex/strex up to 32 bits,
14590 // and up to 64 bits on the non-M profiles
14591 TargetLowering::AtomicExpansionKind
14592 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
14593 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
14594 bool hasAtomicRMW = !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps();
14595 return (Size <= (Subtarget->isMClass() ? 32U : 64U) && hasAtomicRMW)
14596 ? AtomicExpansionKind::LLSC
14597 : AtomicExpansionKind::None;
14600 TargetLowering::AtomicExpansionKind
14601 ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
14602 // At -O0, fast-regalloc cannot cope with the live vregs necessary to
14603 // implement cmpxchg without spilling. If the address being exchanged is also
14604 // on the stack and close enough to the spill slot, this can lead to a
14605 // situation where the monitor always gets cleared and the atomic operation
14606 // can never succeed. So at -O0 we need a late-expanded pseudo-inst instead.
14607 bool HasAtomicCmpXchg =
14608 !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps();
14609 if (getTargetMachine().getOptLevel() != 0 && HasAtomicCmpXchg)
14610 return AtomicExpansionKind::LLSC;
14611 return AtomicExpansionKind::None;
14614 bool ARMTargetLowering::shouldInsertFencesForAtomic(
14615 const Instruction *I) const {
14616 return InsertFencesForAtomic;
14619 // This has so far only been implemented for MachO.
14620 bool ARMTargetLowering::useLoadStackGuardNode() const {
14621 return Subtarget->isTargetMachO();
14624 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
14625 unsigned &Cost) const {
14626 // If we do not have NEON, vector types are not natively supported.
14627 if (!Subtarget->hasNEON())
14630 // Floating point values and vector values map to the same register file.
14631 // Therefore, although we could do a store extract of a vector type, this is
14632 // better to leave at float as we have more freedom in the addressing mode for
14634 if (VectorTy->isFPOrFPVectorTy())
14637 // If the index is unknown at compile time, this is very expensive to lower
14638 // and it is not possible to combine the store with the extract.
14639 if (!isa<ConstantInt>(Idx))
14642 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
14643 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
14644 // We can do a store + vector extract on any vector that fits perfectly in a D
14646 if (BitWidth == 64 || BitWidth == 128) {
14653 bool ARMTargetLowering::isCheapToSpeculateCttz() const {
14654 return Subtarget->hasV6T2Ops();
14657 bool ARMTargetLowering::isCheapToSpeculateCtlz() const {
14658 return Subtarget->hasV6T2Ops();
14661 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
14662 AtomicOrdering Ord) const {
14663 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
14664 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
14665 bool IsAcquire = isAcquireOrStronger(Ord);
14667 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
14668 // intrinsic must return {i32, i32} and we have to recombine them into a
14669 // single i64 here.
14670 if (ValTy->getPrimitiveSizeInBits() == 64) {
14671 Intrinsic::ID Int =
14672 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
14673 Function *Ldrex = Intrinsic::getDeclaration(M, Int);
14675 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
14676 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
14678 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
14679 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
14680 if (!Subtarget->isLittle())
14681 std::swap (Lo, Hi);
14682 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
14683 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
14684 return Builder.CreateOr(
14685 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
14688 Type *Tys[] = { Addr->getType() };
14689 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
14690 Function *Ldrex = Intrinsic::getDeclaration(M, Int, Tys);
14692 return Builder.CreateTruncOrBitCast(
14693 Builder.CreateCall(Ldrex, Addr),
14694 cast<PointerType>(Addr->getType())->getElementType());
14697 void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
14698 IRBuilder<> &Builder) const {
14699 if (!Subtarget->hasV7Ops())
14701 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
14702 Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
14705 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
14707 AtomicOrdering Ord) const {
14708 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
14709 bool IsRelease = isReleaseOrStronger(Ord);
14711 // Since the intrinsics must have legal type, the i64 intrinsics take two
14712 // parameters: "i32, i32". We must marshal Val into the appropriate form
14713 // before the call.
14714 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
14715 Intrinsic::ID Int =
14716 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
14717 Function *Strex = Intrinsic::getDeclaration(M, Int);
14718 Type *Int32Ty = Type::getInt32Ty(M->getContext());
14720 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
14721 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
14722 if (!Subtarget->isLittle())
14724 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
14725 return Builder.CreateCall(Strex, {Lo, Hi, Addr});
14728 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
14729 Type *Tys[] = { Addr->getType() };
14730 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
14732 return Builder.CreateCall(
14733 Strex, {Builder.CreateZExtOrBitCast(
14734 Val, Strex->getFunctionType()->getParamType(0)),
14739 bool ARMTargetLowering::alignLoopsWithOptSize() const {
14740 return Subtarget->isMClass();
14743 /// A helper function for determining the number of interleaved accesses we
14744 /// will generate when lowering accesses of the given type.
14746 ARMTargetLowering::getNumInterleavedAccesses(VectorType *VecTy,
14747 const DataLayout &DL) const {
14748 return (DL.getTypeSizeInBits(VecTy) + 127) / 128;
14751 bool ARMTargetLowering::isLegalInterleavedAccessType(
14752 VectorType *VecTy, const DataLayout &DL) const {
14754 unsigned VecSize = DL.getTypeSizeInBits(VecTy);
14755 unsigned ElSize = DL.getTypeSizeInBits(VecTy->getElementType());
14757 // Ensure the vector doesn't have f16 elements. Even though we could do an
14758 // i16 vldN, we can't hold the f16 vectors and will end up converting via
14760 if (VecTy->getElementType()->isHalfTy())
14763 // Ensure the number of vector elements is greater than 1.
14764 if (VecTy->getNumElements() < 2)
14767 // Ensure the element type is legal.
14768 if (ElSize != 8 && ElSize != 16 && ElSize != 32)
14771 // Ensure the total vector size is 64 or a multiple of 128. Types larger than
14772 // 128 will be split into multiple interleaved accesses.
14773 return VecSize == 64 || VecSize % 128 == 0;
14776 /// Lower an interleaved load into a vldN intrinsic.
14778 /// E.g. Lower an interleaved load (Factor = 2):
14779 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
14780 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
14781 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
14784 /// %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
14785 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
14786 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1
14787 bool ARMTargetLowering::lowerInterleavedLoad(
14788 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
14789 ArrayRef<unsigned> Indices, unsigned Factor) const {
14790 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
14791 "Invalid interleave factor");
14792 assert(!Shuffles.empty() && "Empty shufflevector input");
14793 assert(Shuffles.size() == Indices.size() &&
14794 "Unmatched number of shufflevectors and indices");
14796 VectorType *VecTy = Shuffles[0]->getType();
14797 Type *EltTy = VecTy->getVectorElementType();
14799 const DataLayout &DL = LI->getModule()->getDataLayout();
14801 // Skip if we do not have NEON and skip illegal vector types. We can
14802 // "legalize" wide vector types into multiple interleaved accesses as long as
14803 // the vector types are divisible by 128.
14804 if (!Subtarget->hasNEON() || !isLegalInterleavedAccessType(VecTy, DL))
14807 unsigned NumLoads = getNumInterleavedAccesses(VecTy, DL);
14809 // A pointer vector can not be the return type of the ldN intrinsics. Need to
14810 // load integer vectors first and then convert to pointer vectors.
14811 if (EltTy->isPointerTy())
14813 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
14815 IRBuilder<> Builder(LI);
14817 // The base address of the load.
14818 Value *BaseAddr = LI->getPointerOperand();
14820 if (NumLoads > 1) {
14821 // If we're going to generate more than one load, reset the sub-vector type
14822 // to something legal.
14823 VecTy = VectorType::get(VecTy->getVectorElementType(),
14824 VecTy->getVectorNumElements() / NumLoads);
14826 // We will compute the pointer operand of each load from the original base
14827 // address using GEPs. Cast the base address to a pointer to the scalar
14829 BaseAddr = Builder.CreateBitCast(
14830 BaseAddr, VecTy->getVectorElementType()->getPointerTo(
14831 LI->getPointerAddressSpace()));
14834 assert(isTypeLegal(EVT::getEVT(VecTy)) && "Illegal vldN vector type!");
14836 Type *Int8Ptr = Builder.getInt8PtrTy(LI->getPointerAddressSpace());
14837 Type *Tys[] = {VecTy, Int8Ptr};
14838 static const Intrinsic::ID LoadInts[3] = {Intrinsic::arm_neon_vld2,
14839 Intrinsic::arm_neon_vld3,
14840 Intrinsic::arm_neon_vld4};
14841 Function *VldnFunc =
14842 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
14844 // Holds sub-vectors extracted from the load intrinsic return values. The
14845 // sub-vectors are associated with the shufflevector instructions they will
14847 DenseMap<ShuffleVectorInst *, SmallVector<Value *, 4>> SubVecs;
14849 for (unsigned LoadCount = 0; LoadCount < NumLoads; ++LoadCount) {
14850 // If we're generating more than one load, compute the base address of
14851 // subsequent loads as an offset from the previous.
14853 BaseAddr = Builder.CreateConstGEP1_32(
14854 BaseAddr, VecTy->getVectorNumElements() * Factor);
14856 SmallVector<Value *, 2> Ops;
14857 Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
14858 Ops.push_back(Builder.getInt32(LI->getAlignment()));
14860 CallInst *VldN = Builder.CreateCall(VldnFunc, Ops, "vldN");
14862 // Replace uses of each shufflevector with the corresponding vector loaded
14864 for (unsigned i = 0; i < Shuffles.size(); i++) {
14865 ShuffleVectorInst *SV = Shuffles[i];
14866 unsigned Index = Indices[i];
14868 Value *SubVec = Builder.CreateExtractValue(VldN, Index);
14870 // Convert the integer vector to pointer vector if the element is pointer.
14871 if (EltTy->isPointerTy())
14872 SubVec = Builder.CreateIntToPtr(
14873 SubVec, VectorType::get(SV->getType()->getVectorElementType(),
14874 VecTy->getVectorNumElements()));
14876 SubVecs[SV].push_back(SubVec);
14880 // Replace uses of the shufflevector instructions with the sub-vectors
14881 // returned by the load intrinsic. If a shufflevector instruction is
14882 // associated with more than one sub-vector, those sub-vectors will be
14883 // concatenated into a single wide vector.
14884 for (ShuffleVectorInst *SVI : Shuffles) {
14885 auto &SubVec = SubVecs[SVI];
14887 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0];
14888 SVI->replaceAllUsesWith(WideVec);
14894 /// Lower an interleaved store into a vstN intrinsic.
14896 /// E.g. Lower an interleaved store (Factor = 3):
14897 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
14898 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
14899 /// store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
14902 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
14903 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
14904 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
14905 /// call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)
14907 /// Note that the new shufflevectors will be removed and we'll only generate one
14908 /// vst3 instruction in CodeGen.
14910 /// Example for a more general valid mask (Factor 3). Lower:
14911 /// %i.vec = shuffle <32 x i32> %v0, <32 x i32> %v1,
14912 /// <4, 32, 16, 5, 33, 17, 6, 34, 18, 7, 35, 19>
14913 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
14916 /// %sub.v0 = shuffle <32 x i32> %v0, <32 x i32> v1, <4, 5, 6, 7>
14917 /// %sub.v1 = shuffle <32 x i32> %v0, <32 x i32> v1, <32, 33, 34, 35>
14918 /// %sub.v2 = shuffle <32 x i32> %v0, <32 x i32> v1, <16, 17, 18, 19>
14919 /// call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)
14920 bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
14921 ShuffleVectorInst *SVI,
14922 unsigned Factor) const {
14923 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
14924 "Invalid interleave factor");
14926 VectorType *VecTy = SVI->getType();
14927 assert(VecTy->getVectorNumElements() % Factor == 0 &&
14928 "Invalid interleaved store");
14930 unsigned LaneLen = VecTy->getVectorNumElements() / Factor;
14931 Type *EltTy = VecTy->getVectorElementType();
14932 VectorType *SubVecTy = VectorType::get(EltTy, LaneLen);
14934 const DataLayout &DL = SI->getModule()->getDataLayout();
14936 // Skip if we do not have NEON and skip illegal vector types. We can
14937 // "legalize" wide vector types into multiple interleaved accesses as long as
14938 // the vector types are divisible by 128.
14939 if (!Subtarget->hasNEON() || !isLegalInterleavedAccessType(SubVecTy, DL))
14942 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL);
14944 Value *Op0 = SVI->getOperand(0);
14945 Value *Op1 = SVI->getOperand(1);
14946 IRBuilder<> Builder(SI);
14948 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
14949 // vectors to integer vectors.
14950 if (EltTy->isPointerTy()) {
14951 Type *IntTy = DL.getIntPtrType(EltTy);
14953 // Convert to the corresponding integer vector.
14955 VectorType::get(IntTy, Op0->getType()->getVectorNumElements());
14956 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
14957 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
14959 SubVecTy = VectorType::get(IntTy, LaneLen);
14962 // The base address of the store.
14963 Value *BaseAddr = SI->getPointerOperand();
14965 if (NumStores > 1) {
14966 // If we're going to generate more than one store, reset the lane length
14967 // and sub-vector type to something legal.
14968 LaneLen /= NumStores;
14969 SubVecTy = VectorType::get(SubVecTy->getVectorElementType(), LaneLen);
14971 // We will compute the pointer operand of each store from the original base
14972 // address using GEPs. Cast the base address to a pointer to the scalar
14974 BaseAddr = Builder.CreateBitCast(
14975 BaseAddr, SubVecTy->getVectorElementType()->getPointerTo(
14976 SI->getPointerAddressSpace()));
14979 assert(isTypeLegal(EVT::getEVT(SubVecTy)) && "Illegal vstN vector type!");
14981 auto Mask = SVI->getShuffleMask();
14983 Type *Int8Ptr = Builder.getInt8PtrTy(SI->getPointerAddressSpace());
14984 Type *Tys[] = {Int8Ptr, SubVecTy};
14985 static const Intrinsic::ID StoreInts[3] = {Intrinsic::arm_neon_vst2,
14986 Intrinsic::arm_neon_vst3,
14987 Intrinsic::arm_neon_vst4};
14989 for (unsigned StoreCount = 0; StoreCount < NumStores; ++StoreCount) {
14990 // If we generating more than one store, we compute the base address of
14991 // subsequent stores as an offset from the previous.
14992 if (StoreCount > 0)
14993 BaseAddr = Builder.CreateConstGEP1_32(BaseAddr, LaneLen * Factor);
14995 SmallVector<Value *, 6> Ops;
14996 Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
14998 Function *VstNFunc =
14999 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
15001 // Split the shufflevector operands into sub vectors for the new vstN call.
15002 for (unsigned i = 0; i < Factor; i++) {
15003 unsigned IdxI = StoreCount * LaneLen * Factor + i;
15004 if (Mask[IdxI] >= 0) {
15005 Ops.push_back(Builder.CreateShuffleVector(
15006 Op0, Op1, createSequentialMask(Builder, Mask[IdxI], LaneLen, 0)));
15008 unsigned StartMask = 0;
15009 for (unsigned j = 1; j < LaneLen; j++) {
15010 unsigned IdxJ = StoreCount * LaneLen * Factor + j;
15011 if (Mask[IdxJ * Factor + IdxI] >= 0) {
15012 StartMask = Mask[IdxJ * Factor + IdxI] - IdxJ;
15016 // Note: If all elements in a chunk are undefs, StartMask=0!
15017 // Note: Filling undef gaps with random elements is ok, since
15018 // those elements were being written anyway (with undefs).
15019 // In the case of all undefs we're defaulting to using elems from 0
15020 // Note: StartMask cannot be negative, it's checked in
15021 // isReInterleaveMask
15022 Ops.push_back(Builder.CreateShuffleVector(
15023 Op0, Op1, createSequentialMask(Builder, StartMask, LaneLen, 0)));
15027 Ops.push_back(Builder.getInt32(SI->getAlignment()));
15028 Builder.CreateCall(VstNFunc, Ops);
15041 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
15042 uint64_t &Members) {
15043 if (auto *ST = dyn_cast<StructType>(Ty)) {
15044 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
15045 uint64_t SubMembers = 0;
15046 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
15048 Members += SubMembers;
15050 } else if (auto *AT = dyn_cast<ArrayType>(Ty)) {
15051 uint64_t SubMembers = 0;
15052 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
15054 Members += SubMembers * AT->getNumElements();
15055 } else if (Ty->isFloatTy()) {
15056 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
15060 } else if (Ty->isDoubleTy()) {
15061 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
15065 } else if (auto *VT = dyn_cast<VectorType>(Ty)) {
15072 return VT->getBitWidth() == 64;
15074 return VT->getBitWidth() == 128;
15076 switch (VT->getBitWidth()) {
15089 return (Members > 0 && Members <= 4);
15092 /// Return the correct alignment for the current calling convention.
15094 ARMTargetLowering::getABIAlignmentForCallingConv(Type *ArgTy,
15095 DataLayout DL) const {
15096 if (!ArgTy->isVectorTy())
15097 return DL.getABITypeAlignment(ArgTy);
15099 // Avoid over-aligning vector parameters. It would require realigning the
15100 // stack and waste space for no real benefit.
15101 return std::min(DL.getABITypeAlignment(ArgTy), DL.getStackAlignment());
15104 /// Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
15105 /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when
15106 /// passing according to AAPCS rules.
15107 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
15108 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
15109 if (getEffectiveCallingConv(CallConv, isVarArg) !=
15110 CallingConv::ARM_AAPCS_VFP)
15113 HABaseType Base = HA_UNKNOWN;
15114 uint64_t Members = 0;
15115 bool IsHA = isHomogeneousAggregate(Ty, Base, Members);
15116 LLVM_DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump());
15118 bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy();
15119 return IsHA || IsIntArray;
15122 unsigned ARMTargetLowering::getExceptionPointerRegister(
15123 const Constant *PersonalityFn) const {
15124 // Platforms which do not use SjLj EH may return values in these registers
15125 // via the personality function.
15126 return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R0;
15129 unsigned ARMTargetLowering::getExceptionSelectorRegister(
15130 const Constant *PersonalityFn) const {
15131 // Platforms which do not use SjLj EH may return values in these registers
15132 // via the personality function.
15133 return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R1;
15136 void ARMTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
15137 // Update IsSplitCSR in ARMFunctionInfo.
15138 ARMFunctionInfo *AFI = Entry->getParent()->getInfo<ARMFunctionInfo>();
15139 AFI->setIsSplitCSR(true);
15142 void ARMTargetLowering::insertCopiesSplitCSR(
15143 MachineBasicBlock *Entry,
15144 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
15145 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
15146 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
15150 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
15151 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
15152 MachineBasicBlock::iterator MBBI = Entry->begin();
15153 for (const MCPhysReg *I = IStart; *I; ++I) {
15154 const TargetRegisterClass *RC = nullptr;
15155 if (ARM::GPRRegClass.contains(*I))
15156 RC = &ARM::GPRRegClass;
15157 else if (ARM::DPRRegClass.contains(*I))
15158 RC = &ARM::DPRRegClass;
15160 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
15162 unsigned NewVR = MRI->createVirtualRegister(RC);
15163 // Create copy from CSR to a virtual register.
15164 // FIXME: this currently does not emit CFI pseudo-instructions, it works
15165 // fine for CXX_FAST_TLS since the C++-style TLS access functions should be
15166 // nounwind. If we want to generalize this later, we may need to emit
15167 // CFI pseudo-instructions.
15168 assert(Entry->getParent()->getFunction().hasFnAttribute(
15169 Attribute::NoUnwind) &&
15170 "Function should be nounwind in insertCopiesSplitCSR!");
15171 Entry->addLiveIn(*I);
15172 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
15175 // Insert the copy-back instructions right before the terminator.
15176 for (auto *Exit : Exits)
15177 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
15178 TII->get(TargetOpcode::COPY), *I)
15183 void ARMTargetLowering::finalizeLowering(MachineFunction &MF) const {
15184 MF.getFrameInfo().computeMaxCallFrameSize(MF);
15185 TargetLoweringBase::finalizeLowering(MF);