1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineValueType.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/IRBuilder.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/Support/CodeGen.h"
31 #include "llvm/Target/TargetLowering.h"
37 class InstrItineraryData;
41 // ARM Specific DAG Nodes
42 enum NodeType : unsigned {
43 // Start the numbering where the builtin ops and target ops leave off.
44 FIRST_NUMBER = ISD::BUILTIN_OP_END,
46 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
47 // TargetExternalSymbol, and TargetGlobalAddress.
48 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
50 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
52 // Add pseudo op to model memcpy for struct byval.
55 CALL, // Function call.
56 CALL_PRED, // Function call that's predicable.
57 CALL_NOLINK, // Function call with branch not branch-and-link.
58 BRCOND, // Conditional branch.
59 BR_JT, // Jumptable branch.
60 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
61 RET_FLAG, // Return with a flag operand.
62 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
64 PIC_ADD, // Add with a PC operand and a PIC label.
66 CMP, // ARM compare instructions.
67 CMN, // ARM CMN instructions.
68 CMPZ, // ARM compare that sets only Z flag.
69 CMPFP, // ARM VFP compare instruction, sets FPSCR.
70 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
71 FMSTAT, // ARM fmstat instruction.
73 CMOV, // ARM conditional move instructions.
75 SSAT, // Signed saturation
79 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
80 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
81 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
83 ADDC, // Add with carry
84 ADDE, // Add using carry
85 SUBC, // Sub with carry
86 SUBE, // Sub using carry
88 VMOVRRD, // double to two gprs.
89 VMOVDRR, // Two gprs to double.
91 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
92 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
93 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
95 TC_RETURN, // Tail call return pseudo.
99 DYN_ALLOC, // Dynamic allocation on the stack.
101 MEMBARRIER_MCR, // Memory barrier (MCR)
105 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
106 WIN__DBZCHK, // Windows' divide by zero check
108 VCEQ, // Vector compare equal.
109 VCEQZ, // Vector compare equal to zero.
110 VCGE, // Vector compare greater than or equal.
111 VCGEZ, // Vector compare greater than or equal to zero.
112 VCLEZ, // Vector compare less than or equal to zero.
113 VCGEU, // Vector compare unsigned greater than or equal.
114 VCGT, // Vector compare greater than.
115 VCGTZ, // Vector compare greater than zero.
116 VCLTZ, // Vector compare less than zero.
117 VCGTU, // Vector compare unsigned greater than.
118 VTST, // Vector test bits.
120 // Vector shift by immediate:
122 VSHRs, // ...right (signed)
123 VSHRu, // ...right (unsigned)
125 // Vector rounding shift by immediate:
126 VRSHRs, // ...right (signed)
127 VRSHRu, // ...right (unsigned)
128 VRSHRN, // ...right narrow
130 // Vector saturating shift by immediate:
131 VQSHLs, // ...left (signed)
132 VQSHLu, // ...left (unsigned)
133 VQSHLsu, // ...left (signed to unsigned)
134 VQSHRNs, // ...right narrow (signed)
135 VQSHRNu, // ...right narrow (unsigned)
136 VQSHRNsu, // ...right narrow (signed to unsigned)
138 // Vector saturating rounding shift by immediate:
139 VQRSHRNs, // ...right narrow (signed)
140 VQRSHRNu, // ...right narrow (unsigned)
141 VQRSHRNsu, // ...right narrow (signed to unsigned)
143 // Vector shift and insert:
147 // Vector get lane (VMOV scalar to ARM core register)
148 // (These are used for 8- and 16-bit element types only.)
149 VGETLANEu, // zero-extend vector extract element
150 VGETLANEs, // sign-extend vector extract element
152 // Vector move immediate and move negated immediate:
156 // Vector move f32 immediate:
165 VREV64, // reverse elements within 64-bit doublewords
166 VREV32, // reverse elements within 32-bit words
167 VREV16, // reverse elements within 16-bit halfwords
168 VZIP, // zip (interleave)
169 VUZP, // unzip (deinterleave)
171 VTBL1, // 1-register shuffle with mask
172 VTBL2, // 2-register shuffle with mask
174 // Vector multiply long:
176 VMULLu, // ...unsigned
178 SMULWB, // Signed multiply word by half word, bottom
179 SMULWT, // Signed multiply word by half word, top
180 UMLAL, // 64bit Unsigned Accumulate Multiply
181 SMLAL, // 64bit Signed Accumulate Multiply
182 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
183 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
184 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
185 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
186 SMLALTT, // 64-bit signed accumulate multiply top, top 16
188 // Operands of the standard BUILD_VECTOR node are not legalized, which
189 // is fine if BUILD_VECTORs are always lowered to shuffles or other
190 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
191 // operands need to be legalized. Define an ARM-specific version of
192 // BUILD_VECTOR for this purpose.
198 // Vector OR with immediate
200 // Vector AND with NOT of immediate
203 // Vector bitwise select
206 // Pseudo-instruction representing a memory copy using ldm/stm
210 // Vector load N-element structure to all lanes:
211 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
216 // NEON loads with post-increment base updates:
229 // NEON stores with post-increment base updates:
239 } // end namespace ARMISD
241 /// Define some predicates that are used for node matching.
244 bool isBitFieldInvertedMask(unsigned v);
246 } // end namespace ARM
248 //===--------------------------------------------------------------------===//
249 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
251 class ARMTargetLowering : public TargetLowering {
253 explicit ARMTargetLowering(const TargetMachine &TM,
254 const ARMSubtarget &STI);
256 unsigned getJumpTableEncoding() const override;
257 bool useSoftFloat() const override;
259 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
261 /// ReplaceNodeResults - Replace the results of node with an illegal result
262 /// type with new values built out of custom code.
264 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
265 SelectionDAG &DAG) const override;
267 const char *getTargetNodeName(unsigned Opcode) const override;
269 bool isSelectSupported(SelectSupportKind Kind) const override {
270 // ARM does not support scalar condition selects on vectors.
271 return (Kind != ScalarCondVectorVal);
274 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
275 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
276 EVT VT) const override;
279 EmitInstrWithCustomInserter(MachineInstr &MI,
280 MachineBasicBlock *MBB) const override;
282 void AdjustInstrPostInstrSelection(MachineInstr &MI,
283 SDNode *Node) const override;
285 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
286 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
287 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
288 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
290 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
292 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
293 /// unaligned memory accesses of the specified type. Returns whether it
294 /// is "fast" by reference in the second argument.
295 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
297 bool *Fast) const override;
299 EVT getOptimalMemOpType(uint64_t Size,
300 unsigned DstAlign, unsigned SrcAlign,
301 bool IsMemset, bool ZeroMemset,
303 MachineFunction &MF) const override;
305 using TargetLowering::isZExtFree;
306 bool isZExtFree(SDValue Val, EVT VT2) const override;
308 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
310 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
313 /// isLegalAddressingMode - Return true if the addressing mode represented
314 /// by AM is legal for this target, for a load/store of the specified type.
315 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
316 Type *Ty, unsigned AS) const override;
318 /// getScalingFactorCost - Return the cost of the scaling used in
319 /// addressing mode represented by AM.
320 /// If the AM is supported, the return value must be >= 0.
321 /// If the AM is not supported, the return value must be negative.
322 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
323 unsigned AS) const override;
325 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
327 /// isLegalICmpImmediate - Return true if the specified immediate is legal
328 /// icmp immediate, that is the target has icmp instructions which can
329 /// compare a register against the immediate without having to materialize
330 /// the immediate into a register.
331 bool isLegalICmpImmediate(int64_t Imm) const override;
333 /// isLegalAddImmediate - Return true if the specified immediate is legal
334 /// add immediate, that is the target has add instructions which can
335 /// add a register and the immediate without having to materialize
336 /// the immediate into a register.
337 bool isLegalAddImmediate(int64_t Imm) const override;
339 /// getPreIndexedAddressParts - returns true by value, base pointer and
340 /// offset pointer and addressing mode by reference if the node's address
341 /// can be legally represented as pre-indexed load / store address.
342 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
343 ISD::MemIndexedMode &AM,
344 SelectionDAG &DAG) const override;
346 /// getPostIndexedAddressParts - returns true by value, base pointer and
347 /// offset pointer and addressing mode by reference if this node can be
348 /// combined with a load / store to form a post-indexed load / store.
349 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
350 SDValue &Offset, ISD::MemIndexedMode &AM,
351 SelectionDAG &DAG) const override;
353 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
354 const APInt &DemandedElts,
355 const SelectionDAG &DAG,
356 unsigned Depth) const override;
359 bool ExpandInlineAsm(CallInst *CI) const override;
361 ConstraintType getConstraintType(StringRef Constraint) const override;
363 /// Examine constraint string and operand type and determine a weight value.
364 /// The operand object must already have been set up with the operand type.
365 ConstraintWeight getSingleConstraintMatchWeight(
366 AsmOperandInfo &info, const char *constraint) const override;
368 std::pair<unsigned, const TargetRegisterClass *>
369 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
370 StringRef Constraint, MVT VT) const override;
372 const char *LowerXConstraint(EVT ConstraintVT) const override;
374 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
375 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
376 /// true it means one of the asm constraint of the inline asm instruction
377 /// being processed is 'm'.
378 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
379 std::vector<SDValue> &Ops,
380 SelectionDAG &DAG) const override;
383 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
384 if (ConstraintCode == "Q")
385 return InlineAsm::Constraint_Q;
386 else if (ConstraintCode == "o")
387 return InlineAsm::Constraint_o;
388 else if (ConstraintCode.size() == 2) {
389 if (ConstraintCode[0] == 'U') {
390 switch(ConstraintCode[1]) {
394 return InlineAsm::Constraint_Um;
396 return InlineAsm::Constraint_Un;
398 return InlineAsm::Constraint_Uq;
400 return InlineAsm::Constraint_Us;
402 return InlineAsm::Constraint_Ut;
404 return InlineAsm::Constraint_Uv;
406 return InlineAsm::Constraint_Uy;
410 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
413 const ARMSubtarget* getSubtarget() const {
417 /// getRegClassFor - Return the register class that should be used for the
418 /// specified value type.
419 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
421 /// Returns true if a cast between SrcAS and DestAS is a noop.
422 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
423 // Addrspacecasts are always noops.
427 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
428 unsigned &PrefAlign) const override;
430 /// createFastISel - This method returns a target specific FastISel object,
431 /// or null if the target does not support "fast" ISel.
432 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
433 const TargetLibraryInfo *libInfo) const override;
435 Sched::Preference getSchedulingPreference(SDNode *N) const override;
438 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
439 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
441 /// isFPImmLegal - Returns true if the target can instruction select the
442 /// specified FP immediate natively. If false, the legalizer will
443 /// materialize the FP immediate as a load from a constant pool.
444 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
446 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
448 unsigned Intrinsic) const override;
450 /// \brief Returns true if it is beneficial to convert a load of a constant
451 /// to just the constant itself.
452 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
453 Type *Ty) const override;
455 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
457 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
459 /// \brief Returns true if an argument of type Ty needs to be passed in a
460 /// contiguous block of registers in calling convention CallConv.
461 bool functionArgumentNeedsConsecutiveRegisters(
462 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
464 /// If a physical register, this returns the register that receives the
465 /// exception address on entry to an EH pad.
467 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
469 /// If a physical register, this returns the register that receives the
470 /// exception typeid on entry to a landing pad.
472 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
474 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
475 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
476 AtomicOrdering Ord) const override;
477 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
478 Value *Addr, AtomicOrdering Ord) const override;
480 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
482 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
483 bool IsStore, bool IsLoad) const override;
484 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
485 bool IsStore, bool IsLoad) const override;
487 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
489 bool lowerInterleavedLoad(LoadInst *LI,
490 ArrayRef<ShuffleVectorInst *> Shuffles,
491 ArrayRef<unsigned> Indices,
492 unsigned Factor) const override;
493 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
494 unsigned Factor) const override;
496 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
497 TargetLoweringBase::AtomicExpansionKind
498 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
499 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
500 TargetLoweringBase::AtomicExpansionKind
501 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
502 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
504 bool useLoadStackGuardNode() const override;
506 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
507 unsigned &Cost) const override;
509 bool canMergeStoresTo(EVT MemVT) const override {
510 // Do not merge to larger than i32.
511 return (MemVT.getSizeInBits() <= 32);
514 bool isCheapToSpeculateCttz() const override;
515 bool isCheapToSpeculateCtlz() const override;
517 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
518 return VT.isScalarInteger();
521 bool supportSwiftError() const override {
525 bool hasStandaloneRem(EVT VT) const override {
526 return HasStandaloneRem;
529 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
530 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
532 /// Returns true if \p VecTy is a legal interleaved access type. This
533 /// function checks the vector element type and the overall width of the
535 bool isLegalInterleavedAccessType(VectorType *VecTy,
536 const DataLayout &DL) const;
538 /// Returns the number of interleaved accesses that will be generated when
539 /// lowering accesses of the given type.
540 unsigned getNumInterleavedAccesses(VectorType *VecTy,
541 const DataLayout &DL) const;
544 std::pair<const TargetRegisterClass *, uint8_t>
545 findRepresentativeClass(const TargetRegisterInfo *TRI,
546 MVT VT) const override;
549 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
550 /// make the right decision when generating code for different targets.
551 const ARMSubtarget *Subtarget;
553 const TargetRegisterInfo *RegInfo;
555 const InstrItineraryData *Itins;
557 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
559 unsigned ARMPCLabelIndex;
561 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
563 bool InsertFencesForAtomic;
565 bool HasStandaloneRem = true;
567 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
568 void addDRTypeForNEON(MVT VT);
569 void addQRTypeForNEON(MVT VT);
570 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
572 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
574 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
575 SDValue &Arg, RegsToPassVector &RegsToPass,
576 CCValAssign &VA, CCValAssign &NextVA,
578 SmallVectorImpl<SDValue> &MemOpChains,
579 ISD::ArgFlagsTy Flags) const;
580 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
581 SDValue &Root, SelectionDAG &DAG,
582 const SDLoc &dl) const;
584 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
585 bool isVarArg) const;
586 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
587 bool isVarArg) const;
588 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
589 const SDLoc &dl, SelectionDAG &DAG,
590 const CCValAssign &VA,
591 ISD::ArgFlagsTy Flags) const;
592 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
593 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
594 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
595 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
596 const ARMSubtarget *Subtarget) const;
597 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
598 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
599 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
600 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
601 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
602 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
603 SelectionDAG &DAG) const;
604 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
606 TLSModel::Model model) const;
607 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
608 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
609 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
610 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
611 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
612 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
613 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
614 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
615 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
616 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
617 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
618 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
619 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
620 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
621 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
622 const ARMSubtarget *ST) const;
623 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
624 const ARMSubtarget *ST) const;
625 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
626 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
627 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
628 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
629 SmallVectorImpl<SDValue> &Results) const;
630 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
631 SDValue &Chain) const;
632 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
633 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
634 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
635 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
636 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
637 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
639 unsigned getRegisterByName(const char* RegName, EVT VT,
640 SelectionDAG &DAG) const override;
642 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
643 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
644 /// expanded to FMAs when this method returns true, otherwise fmuladd is
645 /// expanded to fmul + fadd.
647 /// ARM supports both fused and unfused multiply-add operations; we already
648 /// lower a pair of fmul and fadd to the latter so it's not clear that there
649 /// would be a gain or that the gain would be worthwhile enough to risk
650 /// correctness bugs.
651 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
653 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
655 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
656 CallingConv::ID CallConv, bool isVarArg,
657 const SmallVectorImpl<ISD::InputArg> &Ins,
658 const SDLoc &dl, SelectionDAG &DAG,
659 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
660 SDValue ThisVal) const;
662 bool supportSplitCSR(MachineFunction *MF) const override {
663 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
664 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
667 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
668 void insertCopiesSplitCSR(
669 MachineBasicBlock *Entry,
670 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
673 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
674 const SmallVectorImpl<ISD::InputArg> &Ins,
675 const SDLoc &dl, SelectionDAG &DAG,
676 SmallVectorImpl<SDValue> &InVals) const override;
678 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
679 SDValue &Chain, const Value *OrigArg,
680 unsigned InRegsParamRecordIdx, int ArgOffset,
681 unsigned ArgSize) const;
683 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
684 const SDLoc &dl, SDValue &Chain,
685 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
686 bool ForceMutable = false) const;
688 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
689 SmallVectorImpl<SDValue> &InVals) const override;
691 /// HandleByVal - Target-specific cleanup for ByVal support.
692 void HandleByVal(CCState *, unsigned &, unsigned) const override;
694 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
695 /// for tail call optimization. Targets which want to do tail call
696 /// optimization should implement this function.
697 bool IsEligibleForTailCallOptimization(SDValue Callee,
698 CallingConv::ID CalleeCC,
700 bool isCalleeStructRet,
701 bool isCallerStructRet,
702 const SmallVectorImpl<ISD::OutputArg> &Outs,
703 const SmallVectorImpl<SDValue> &OutVals,
704 const SmallVectorImpl<ISD::InputArg> &Ins,
705 SelectionDAG& DAG) const;
707 bool CanLowerReturn(CallingConv::ID CallConv,
708 MachineFunction &MF, bool isVarArg,
709 const SmallVectorImpl<ISD::OutputArg> &Outs,
710 LLVMContext &Context) const override;
712 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
713 const SmallVectorImpl<ISD::OutputArg> &Outs,
714 const SmallVectorImpl<SDValue> &OutVals,
715 const SDLoc &dl, SelectionDAG &DAG) const override;
717 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
719 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
721 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
722 SDValue ARMcc, SDValue CCR, SDValue Cmp,
723 SelectionDAG &DAG) const;
724 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
725 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
726 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
727 const SDLoc &dl, bool InvalidOnQNaN) const;
728 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
730 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
732 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
733 MachineBasicBlock *DispatchBB, int FI) const;
735 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
737 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
739 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
740 MachineBasicBlock *MBB) const;
742 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
743 MachineBasicBlock *MBB) const;
744 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
745 MachineBasicBlock *MBB) const;
748 enum NEONModImmType {
756 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
757 const TargetLibraryInfo *libInfo);
759 } // end namespace ARM
761 } // end namespace llvm
763 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H