1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineValueType.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/IRBuilder.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/Support/CodeGen.h"
31 #include "llvm/Target/TargetLowering.h"
37 class InstrItineraryData;
41 // ARM Specific DAG Nodes
42 enum NodeType : unsigned {
43 // Start the numbering where the builtin ops and target ops leave off.
44 FIRST_NUMBER = ISD::BUILTIN_OP_END,
46 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
47 // TargetExternalSymbol, and TargetGlobalAddress.
48 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
50 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
52 // Add pseudo op to model memcpy for struct byval.
55 CALL, // Function call.
56 CALL_PRED, // Function call that's predicable.
57 CALL_NOLINK, // Function call with branch not branch-and-link.
58 BRCOND, // Conditional branch.
59 BR_JT, // Jumptable branch.
60 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
61 RET_FLAG, // Return with a flag operand.
62 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
64 PIC_ADD, // Add with a PC operand and a PIC label.
66 CMP, // ARM compare instructions.
67 CMN, // ARM CMN instructions.
68 CMPZ, // ARM compare that sets only Z flag.
69 CMPFP, // ARM VFP compare instruction, sets FPSCR.
70 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
71 FMSTAT, // ARM fmstat instruction.
73 CMOV, // ARM conditional move instructions.
75 SSAT, // Signed saturation
79 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
80 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
81 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
83 ADDC, // Add with carry
84 ADDE, // Add using carry
85 SUBC, // Sub with carry
86 SUBE, // Sub using carry
88 VMOVRRD, // double to two gprs.
89 VMOVDRR, // Two gprs to double.
91 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
92 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
93 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
95 TC_RETURN, // Tail call return pseudo.
99 DYN_ALLOC, // Dynamic allocation on the stack.
101 MEMBARRIER_MCR, // Memory barrier (MCR)
105 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
106 WIN__DBZCHK, // Windows' divide by zero check
108 VCEQ, // Vector compare equal.
109 VCEQZ, // Vector compare equal to zero.
110 VCGE, // Vector compare greater than or equal.
111 VCGEZ, // Vector compare greater than or equal to zero.
112 VCLEZ, // Vector compare less than or equal to zero.
113 VCGEU, // Vector compare unsigned greater than or equal.
114 VCGT, // Vector compare greater than.
115 VCGTZ, // Vector compare greater than zero.
116 VCLTZ, // Vector compare less than zero.
117 VCGTU, // Vector compare unsigned greater than.
118 VTST, // Vector test bits.
120 // Vector shift by immediate:
122 VSHRs, // ...right (signed)
123 VSHRu, // ...right (unsigned)
125 // Vector rounding shift by immediate:
126 VRSHRs, // ...right (signed)
127 VRSHRu, // ...right (unsigned)
128 VRSHRN, // ...right narrow
130 // Vector saturating shift by immediate:
131 VQSHLs, // ...left (signed)
132 VQSHLu, // ...left (unsigned)
133 VQSHLsu, // ...left (signed to unsigned)
134 VQSHRNs, // ...right narrow (signed)
135 VQSHRNu, // ...right narrow (unsigned)
136 VQSHRNsu, // ...right narrow (signed to unsigned)
138 // Vector saturating rounding shift by immediate:
139 VQRSHRNs, // ...right narrow (signed)
140 VQRSHRNu, // ...right narrow (unsigned)
141 VQRSHRNsu, // ...right narrow (signed to unsigned)
143 // Vector shift and insert:
147 // Vector get lane (VMOV scalar to ARM core register)
148 // (These are used for 8- and 16-bit element types only.)
149 VGETLANEu, // zero-extend vector extract element
150 VGETLANEs, // sign-extend vector extract element
152 // Vector move immediate and move negated immediate:
156 // Vector move f32 immediate:
165 VREV64, // reverse elements within 64-bit doublewords
166 VREV32, // reverse elements within 32-bit words
167 VREV16, // reverse elements within 16-bit halfwords
168 VZIP, // zip (interleave)
169 VUZP, // unzip (deinterleave)
171 VTBL1, // 1-register shuffle with mask
172 VTBL2, // 2-register shuffle with mask
174 // Vector multiply long:
176 VMULLu, // ...unsigned
178 UMLAL, // 64bit Unsigned Accumulate Multiply
179 SMLAL, // 64bit Signed Accumulate Multiply
180 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
182 // Operands of the standard BUILD_VECTOR node are not legalized, which
183 // is fine if BUILD_VECTORs are always lowered to shuffles or other
184 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
185 // operands need to be legalized. Define an ARM-specific version of
186 // BUILD_VECTOR for this purpose.
192 // Vector OR with immediate
194 // Vector AND with NOT of immediate
197 // Vector bitwise select
200 // Pseudo-instruction representing a memory copy using ldm/stm
204 // Vector load N-element structure to all lanes:
205 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
210 // NEON loads with post-increment base updates:
223 // NEON stores with post-increment base updates:
233 } // end namespace ARMISD
235 /// Define some predicates that are used for node matching.
238 bool isBitFieldInvertedMask(unsigned v);
240 } // end namespace ARM
242 //===--------------------------------------------------------------------===//
243 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
245 class ARMTargetLowering : public TargetLowering {
247 explicit ARMTargetLowering(const TargetMachine &TM,
248 const ARMSubtarget &STI);
250 unsigned getJumpTableEncoding() const override;
251 bool useSoftFloat() const override;
253 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
255 /// ReplaceNodeResults - Replace the results of node with an illegal result
256 /// type with new values built out of custom code.
258 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
259 SelectionDAG &DAG) const override;
261 const char *getTargetNodeName(unsigned Opcode) const override;
263 bool isSelectSupported(SelectSupportKind Kind) const override {
264 // ARM does not support scalar condition selects on vectors.
265 return (Kind != ScalarCondVectorVal);
268 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
269 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
270 EVT VT) const override;
273 EmitInstrWithCustomInserter(MachineInstr &MI,
274 MachineBasicBlock *MBB) const override;
276 void AdjustInstrPostInstrSelection(MachineInstr &MI,
277 SDNode *Node) const override;
279 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
280 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
281 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
282 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
284 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
286 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
287 /// unaligned memory accesses of the specified type. Returns whether it
288 /// is "fast" by reference in the second argument.
289 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
291 bool *Fast) const override;
293 EVT getOptimalMemOpType(uint64_t Size,
294 unsigned DstAlign, unsigned SrcAlign,
295 bool IsMemset, bool ZeroMemset,
297 MachineFunction &MF) const override;
299 using TargetLowering::isZExtFree;
300 bool isZExtFree(SDValue Val, EVT VT2) const override;
302 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
304 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
307 /// isLegalAddressingMode - Return true if the addressing mode represented
308 /// by AM is legal for this target, for a load/store of the specified type.
309 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
310 Type *Ty, unsigned AS) const override;
312 /// getScalingFactorCost - Return the cost of the scaling used in
313 /// addressing mode represented by AM.
314 /// If the AM is supported, the return value must be >= 0.
315 /// If the AM is not supported, the return value must be negative.
316 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
317 unsigned AS) const override;
319 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
321 /// isLegalICmpImmediate - Return true if the specified immediate is legal
322 /// icmp immediate, that is the target has icmp instructions which can
323 /// compare a register against the immediate without having to materialize
324 /// the immediate into a register.
325 bool isLegalICmpImmediate(int64_t Imm) const override;
327 /// isLegalAddImmediate - Return true if the specified immediate is legal
328 /// add immediate, that is the target has add instructions which can
329 /// add a register and the immediate without having to materialize
330 /// the immediate into a register.
331 bool isLegalAddImmediate(int64_t Imm) const override;
333 /// getPreIndexedAddressParts - returns true by value, base pointer and
334 /// offset pointer and addressing mode by reference if the node's address
335 /// can be legally represented as pre-indexed load / store address.
336 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
337 ISD::MemIndexedMode &AM,
338 SelectionDAG &DAG) const override;
340 /// getPostIndexedAddressParts - returns true by value, base pointer and
341 /// offset pointer and addressing mode by reference if this node can be
342 /// combined with a load / store to form a post-indexed load / store.
343 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
344 SDValue &Offset, ISD::MemIndexedMode &AM,
345 SelectionDAG &DAG) const override;
347 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
349 const SelectionDAG &DAG,
350 unsigned Depth) const override;
353 bool ExpandInlineAsm(CallInst *CI) const override;
355 ConstraintType getConstraintType(StringRef Constraint) const override;
357 /// Examine constraint string and operand type and determine a weight value.
358 /// The operand object must already have been set up with the operand type.
359 ConstraintWeight getSingleConstraintMatchWeight(
360 AsmOperandInfo &info, const char *constraint) const override;
362 std::pair<unsigned, const TargetRegisterClass *>
363 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
364 StringRef Constraint, MVT VT) const override;
366 const char *LowerXConstraint(EVT ConstraintVT) const override;
368 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
369 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
370 /// true it means one of the asm constraint of the inline asm instruction
371 /// being processed is 'm'.
372 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
373 std::vector<SDValue> &Ops,
374 SelectionDAG &DAG) const override;
377 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
378 if (ConstraintCode == "Q")
379 return InlineAsm::Constraint_Q;
380 else if (ConstraintCode == "o")
381 return InlineAsm::Constraint_o;
382 else if (ConstraintCode.size() == 2) {
383 if (ConstraintCode[0] == 'U') {
384 switch(ConstraintCode[1]) {
388 return InlineAsm::Constraint_Um;
390 return InlineAsm::Constraint_Un;
392 return InlineAsm::Constraint_Uq;
394 return InlineAsm::Constraint_Us;
396 return InlineAsm::Constraint_Ut;
398 return InlineAsm::Constraint_Uv;
400 return InlineAsm::Constraint_Uy;
404 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
407 const ARMSubtarget* getSubtarget() const {
411 /// getRegClassFor - Return the register class that should be used for the
412 /// specified value type.
413 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
415 /// Returns true if a cast between SrcAS and DestAS is a noop.
416 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
417 // Addrspacecasts are always noops.
421 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
422 unsigned &PrefAlign) const override;
424 /// createFastISel - This method returns a target specific FastISel object,
425 /// or null if the target does not support "fast" ISel.
426 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
427 const TargetLibraryInfo *libInfo) const override;
429 Sched::Preference getSchedulingPreference(SDNode *N) const override;
432 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
433 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
435 /// isFPImmLegal - Returns true if the target can instruction select the
436 /// specified FP immediate natively. If false, the legalizer will
437 /// materialize the FP immediate as a load from a constant pool.
438 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
440 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
442 unsigned Intrinsic) const override;
444 /// \brief Returns true if it is beneficial to convert a load of a constant
445 /// to just the constant itself.
446 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
447 Type *Ty) const override;
449 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
451 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
453 /// \brief Returns true if an argument of type Ty needs to be passed in a
454 /// contiguous block of registers in calling convention CallConv.
455 bool functionArgumentNeedsConsecutiveRegisters(
456 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
458 /// If a physical register, this returns the register that receives the
459 /// exception address on entry to an EH pad.
461 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
463 /// If a physical register, this returns the register that receives the
464 /// exception typeid on entry to a landing pad.
466 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
468 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
469 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
470 AtomicOrdering Ord) const override;
471 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
472 Value *Addr, AtomicOrdering Ord) const override;
474 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
476 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
477 bool IsStore, bool IsLoad) const override;
478 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
479 bool IsStore, bool IsLoad) const override;
481 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
483 bool lowerInterleavedLoad(LoadInst *LI,
484 ArrayRef<ShuffleVectorInst *> Shuffles,
485 ArrayRef<unsigned> Indices,
486 unsigned Factor) const override;
487 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
488 unsigned Factor) const override;
490 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
491 TargetLoweringBase::AtomicExpansionKind
492 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
493 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
494 TargetLoweringBase::AtomicExpansionKind
495 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
496 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
498 bool useLoadStackGuardNode() const override;
500 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
501 unsigned &Cost) const override;
503 bool isCheapToSpeculateCttz() const override;
504 bool isCheapToSpeculateCtlz() const override;
506 bool supportSwiftError() const override {
510 bool hasStandaloneRem(EVT VT) const override {
511 return HasStandaloneRem;
514 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
515 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
518 std::pair<const TargetRegisterClass *, uint8_t>
519 findRepresentativeClass(const TargetRegisterInfo *TRI,
520 MVT VT) const override;
523 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
524 /// make the right decision when generating code for different targets.
525 const ARMSubtarget *Subtarget;
527 const TargetRegisterInfo *RegInfo;
529 const InstrItineraryData *Itins;
531 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
533 unsigned ARMPCLabelIndex;
535 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
537 bool InsertFencesForAtomic;
539 bool HasStandaloneRem = true;
541 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
542 void addDRTypeForNEON(MVT VT);
543 void addQRTypeForNEON(MVT VT);
544 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
546 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
548 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
549 SDValue &Arg, RegsToPassVector &RegsToPass,
550 CCValAssign &VA, CCValAssign &NextVA,
552 SmallVectorImpl<SDValue> &MemOpChains,
553 ISD::ArgFlagsTy Flags) const;
554 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
555 SDValue &Root, SelectionDAG &DAG,
556 const SDLoc &dl) const;
558 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
559 bool isVarArg) const;
560 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
561 bool isVarArg) const;
562 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
563 const SDLoc &dl, SelectionDAG &DAG,
564 const CCValAssign &VA,
565 ISD::ArgFlagsTy Flags) const;
566 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
567 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
568 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
569 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
570 const ARMSubtarget *Subtarget) const;
571 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
572 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
573 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
574 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
575 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
576 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
577 SelectionDAG &DAG) const;
578 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
580 TLSModel::Model model) const;
581 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
582 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
583 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
584 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
585 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
586 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
587 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
588 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
589 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
590 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
591 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
592 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
593 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
594 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
595 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
596 const ARMSubtarget *ST) const;
597 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
598 const ARMSubtarget *ST) const;
599 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
600 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
601 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
602 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
603 SmallVectorImpl<SDValue> &Results) const;
604 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
605 SDValue &Chain) const;
606 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
607 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
608 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
609 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
610 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
611 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
613 unsigned getRegisterByName(const char* RegName, EVT VT,
614 SelectionDAG &DAG) const override;
616 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
617 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
618 /// expanded to FMAs when this method returns true, otherwise fmuladd is
619 /// expanded to fmul + fadd.
621 /// ARM supports both fused and unfused multiply-add operations; we already
622 /// lower a pair of fmul and fadd to the latter so it's not clear that there
623 /// would be a gain or that the gain would be worthwhile enough to risk
624 /// correctness bugs.
625 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
627 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
629 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
630 CallingConv::ID CallConv, bool isVarArg,
631 const SmallVectorImpl<ISD::InputArg> &Ins,
632 const SDLoc &dl, SelectionDAG &DAG,
633 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
634 SDValue ThisVal) const;
636 bool supportSplitCSR(MachineFunction *MF) const override {
637 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
638 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
641 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
642 void insertCopiesSplitCSR(
643 MachineBasicBlock *Entry,
644 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
647 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
648 const SmallVectorImpl<ISD::InputArg> &Ins,
649 const SDLoc &dl, SelectionDAG &DAG,
650 SmallVectorImpl<SDValue> &InVals) const override;
652 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
653 SDValue &Chain, const Value *OrigArg,
654 unsigned InRegsParamRecordIdx, int ArgOffset,
655 unsigned ArgSize) const;
657 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
658 const SDLoc &dl, SDValue &Chain,
659 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
660 bool ForceMutable = false) const;
662 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
663 SmallVectorImpl<SDValue> &InVals) const override;
665 /// HandleByVal - Target-specific cleanup for ByVal support.
666 void HandleByVal(CCState *, unsigned &, unsigned) const override;
668 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
669 /// for tail call optimization. Targets which want to do tail call
670 /// optimization should implement this function.
671 bool IsEligibleForTailCallOptimization(SDValue Callee,
672 CallingConv::ID CalleeCC,
674 bool isCalleeStructRet,
675 bool isCallerStructRet,
676 const SmallVectorImpl<ISD::OutputArg> &Outs,
677 const SmallVectorImpl<SDValue> &OutVals,
678 const SmallVectorImpl<ISD::InputArg> &Ins,
679 SelectionDAG& DAG) const;
681 bool CanLowerReturn(CallingConv::ID CallConv,
682 MachineFunction &MF, bool isVarArg,
683 const SmallVectorImpl<ISD::OutputArg> &Outs,
684 LLVMContext &Context) const override;
686 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
687 const SmallVectorImpl<ISD::OutputArg> &Outs,
688 const SmallVectorImpl<SDValue> &OutVals,
689 const SDLoc &dl, SelectionDAG &DAG) const override;
691 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
693 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
695 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
696 SDValue ARMcc, SDValue CCR, SDValue Cmp,
697 SelectionDAG &DAG) const;
698 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
699 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
700 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
701 const SDLoc &dl) const;
702 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
704 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
706 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
707 MachineBasicBlock *DispatchBB, int FI) const;
709 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
711 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
713 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
714 MachineBasicBlock *MBB) const;
716 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
717 MachineBasicBlock *MBB) const;
718 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
719 MachineBasicBlock *MBB) const;
722 enum NEONModImmType {
730 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
731 const TargetLibraryInfo *libInfo);
733 } // end namespace ARM
735 } // end namespace llvm
737 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H