1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 BRCOND, // Conditional branch.
47 BR_JT, // Jumptable branch.
48 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
49 RET_FLAG, // Return with a flag operand.
50 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
52 PIC_ADD, // Add with a PC operand and a PIC label.
54 CMP, // ARM compare instructions.
55 CMN, // ARM CMN instructions.
56 CMPZ, // ARM compare that sets only Z flag.
57 CMPFP, // ARM VFP compare instruction, sets FPSCR.
58 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
59 FMSTAT, // ARM fmstat instruction.
61 CMOV, // ARM conditional move instructions.
63 SSAT, // Signed saturation
67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
71 ADDC, // Add with carry
72 ADDE, // Add using carry
73 SUBC, // Sub with carry
74 SUBE, // Sub using carry
76 VMOVRRD, // double to two gprs.
77 VMOVDRR, // Two gprs to double.
79 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
80 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
81 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
83 TC_RETURN, // Tail call return pseudo.
87 DYN_ALLOC, // Dynamic allocation on the stack.
89 MEMBARRIER_MCR, // Memory barrier (MCR)
93 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
94 WIN__DBZCHK, // Windows' divide by zero check
96 VCEQ, // Vector compare equal.
97 VCEQZ, // Vector compare equal to zero.
98 VCGE, // Vector compare greater than or equal.
99 VCGEZ, // Vector compare greater than or equal to zero.
100 VCLEZ, // Vector compare less than or equal to zero.
101 VCGEU, // Vector compare unsigned greater than or equal.
102 VCGT, // Vector compare greater than.
103 VCGTZ, // Vector compare greater than zero.
104 VCLTZ, // Vector compare less than zero.
105 VCGTU, // Vector compare unsigned greater than.
106 VTST, // Vector test bits.
108 // Vector shift by immediate:
110 VSHRs, // ...right (signed)
111 VSHRu, // ...right (unsigned)
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
131 // Vector shift and insert:
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
140 // Vector move immediate and move negated immediate:
144 // Vector move f32 immediate:
153 VREV64, // reverse elements within 64-bit doublewords
154 VREV32, // reverse elements within 32-bit words
155 VREV16, // reverse elements within 16-bit halfwords
156 VZIP, // zip (interleave)
157 VUZP, // unzip (deinterleave)
159 VTBL1, // 1-register shuffle with mask
160 VTBL2, // 2-register shuffle with mask
162 // Vector multiply long:
164 VMULLu, // ...unsigned
166 UMLAL, // 64bit Unsigned Accumulate Multiply
167 SMLAL, // 64bit Signed Accumulate Multiply
168 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
170 // Operands of the standard BUILD_VECTOR node are not legalized, which
171 // is fine if BUILD_VECTORs are always lowered to shuffles or other
172 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
173 // operands need to be legalized. Define an ARM-specific version of
174 // BUILD_VECTOR for this purpose.
180 // Vector OR with immediate
182 // Vector AND with NOT of immediate
185 // Vector bitwise select
188 // Pseudo-instruction representing a memory copy using ldm/stm
192 // Vector load N-element structure to all lanes:
193 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
198 // NEON loads with post-increment base updates:
211 // NEON stores with post-increment base updates:
222 /// Define some predicates that are used for node matching.
224 bool isBitFieldInvertedMask(unsigned v);
227 //===--------------------------------------------------------------------===//
228 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
230 class ARMTargetLowering : public TargetLowering {
232 explicit ARMTargetLowering(const TargetMachine &TM,
233 const ARMSubtarget &STI);
235 unsigned getJumpTableEncoding() const override;
236 bool useSoftFloat() const override;
238 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
240 /// ReplaceNodeResults - Replace the results of node with an illegal result
241 /// type with new values built out of custom code.
243 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
244 SelectionDAG &DAG) const override;
246 const char *getTargetNodeName(unsigned Opcode) const override;
248 bool isSelectSupported(SelectSupportKind Kind) const override {
249 // ARM does not support scalar condition selects on vectors.
250 return (Kind != ScalarCondVectorVal);
253 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
254 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
255 EVT VT) const override;
258 EmitInstrWithCustomInserter(MachineInstr &MI,
259 MachineBasicBlock *MBB) const override;
261 void AdjustInstrPostInstrSelection(MachineInstr &MI,
262 SDNode *Node) const override;
264 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
265 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
266 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
267 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
269 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
271 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
272 /// unaligned memory accesses of the specified type. Returns whether it
273 /// is "fast" by reference in the second argument.
274 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
276 bool *Fast) const override;
278 EVT getOptimalMemOpType(uint64_t Size,
279 unsigned DstAlign, unsigned SrcAlign,
280 bool IsMemset, bool ZeroMemset,
282 MachineFunction &MF) const override;
284 using TargetLowering::isZExtFree;
285 bool isZExtFree(SDValue Val, EVT VT2) const override;
287 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
289 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
292 /// isLegalAddressingMode - Return true if the addressing mode represented
293 /// by AM is legal for this target, for a load/store of the specified type.
294 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
295 Type *Ty, unsigned AS) const override;
297 /// getScalingFactorCost - Return the cost of the scaling used in
298 /// addressing mode represented by AM.
299 /// If the AM is supported, the return value must be >= 0.
300 /// If the AM is not supported, the return value must be negative.
301 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
302 unsigned AS) const override;
304 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
306 /// isLegalICmpImmediate - Return true if the specified immediate is legal
307 /// icmp immediate, that is the target has icmp instructions which can
308 /// compare a register against the immediate without having to materialize
309 /// the immediate into a register.
310 bool isLegalICmpImmediate(int64_t Imm) const override;
312 /// isLegalAddImmediate - Return true if the specified immediate is legal
313 /// add immediate, that is the target has add instructions which can
314 /// add a register and the immediate without having to materialize
315 /// the immediate into a register.
316 bool isLegalAddImmediate(int64_t Imm) const override;
318 /// getPreIndexedAddressParts - returns true by value, base pointer and
319 /// offset pointer and addressing mode by reference if the node's address
320 /// can be legally represented as pre-indexed load / store address.
321 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
322 ISD::MemIndexedMode &AM,
323 SelectionDAG &DAG) const override;
325 /// getPostIndexedAddressParts - returns true by value, base pointer and
326 /// offset pointer and addressing mode by reference if this node can be
327 /// combined with a load / store to form a post-indexed load / store.
328 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
329 SDValue &Offset, ISD::MemIndexedMode &AM,
330 SelectionDAG &DAG) const override;
332 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
334 const SelectionDAG &DAG,
335 unsigned Depth) const override;
338 bool ExpandInlineAsm(CallInst *CI) const override;
340 ConstraintType getConstraintType(StringRef Constraint) const override;
342 /// Examine constraint string and operand type and determine a weight value.
343 /// The operand object must already have been set up with the operand type.
344 ConstraintWeight getSingleConstraintMatchWeight(
345 AsmOperandInfo &info, const char *constraint) const override;
347 std::pair<unsigned, const TargetRegisterClass *>
348 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
349 StringRef Constraint, MVT VT) const override;
351 const char *LowerXConstraint(EVT ConstraintVT) const override;
353 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
354 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
355 /// true it means one of the asm constraint of the inline asm instruction
356 /// being processed is 'm'.
357 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
358 std::vector<SDValue> &Ops,
359 SelectionDAG &DAG) const override;
362 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
363 if (ConstraintCode == "Q")
364 return InlineAsm::Constraint_Q;
365 else if (ConstraintCode == "o")
366 return InlineAsm::Constraint_o;
367 else if (ConstraintCode.size() == 2) {
368 if (ConstraintCode[0] == 'U') {
369 switch(ConstraintCode[1]) {
373 return InlineAsm::Constraint_Um;
375 return InlineAsm::Constraint_Un;
377 return InlineAsm::Constraint_Uq;
379 return InlineAsm::Constraint_Us;
381 return InlineAsm::Constraint_Ut;
383 return InlineAsm::Constraint_Uv;
385 return InlineAsm::Constraint_Uy;
389 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
392 const ARMSubtarget* getSubtarget() const {
396 /// getRegClassFor - Return the register class that should be used for the
397 /// specified value type.
398 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
400 /// Returns true if a cast between SrcAS and DestAS is a noop.
401 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
402 // Addrspacecasts are always noops.
406 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
407 unsigned &PrefAlign) const override;
409 /// createFastISel - This method returns a target specific FastISel object,
410 /// or null if the target does not support "fast" ISel.
411 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
412 const TargetLibraryInfo *libInfo) const override;
414 Sched::Preference getSchedulingPreference(SDNode *N) const override;
417 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
418 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
420 /// isFPImmLegal - Returns true if the target can instruction select the
421 /// specified FP immediate natively. If false, the legalizer will
422 /// materialize the FP immediate as a load from a constant pool.
423 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
425 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
427 unsigned Intrinsic) const override;
429 /// \brief Returns true if it is beneficial to convert a load of a constant
430 /// to just the constant itself.
431 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
432 Type *Ty) const override;
434 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
436 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
438 /// \brief Returns true if an argument of type Ty needs to be passed in a
439 /// contiguous block of registers in calling convention CallConv.
440 bool functionArgumentNeedsConsecutiveRegisters(
441 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
443 /// If a physical register, this returns the register that receives the
444 /// exception address on entry to an EH pad.
446 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
448 /// If a physical register, this returns the register that receives the
449 /// exception typeid on entry to a landing pad.
451 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
453 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
454 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
455 AtomicOrdering Ord) const override;
456 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
457 Value *Addr, AtomicOrdering Ord) const override;
459 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
461 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
462 bool IsStore, bool IsLoad) const override;
463 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
464 bool IsStore, bool IsLoad) const override;
466 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
468 bool lowerInterleavedLoad(LoadInst *LI,
469 ArrayRef<ShuffleVectorInst *> Shuffles,
470 ArrayRef<unsigned> Indices,
471 unsigned Factor) const override;
472 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
473 unsigned Factor) const override;
475 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
476 TargetLoweringBase::AtomicExpansionKind
477 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
478 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
479 TargetLoweringBase::AtomicExpansionKind
480 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
481 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
483 bool useLoadStackGuardNode() const override;
485 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
486 unsigned &Cost) const override;
488 bool isCheapToSpeculateCttz() const override;
489 bool isCheapToSpeculateCtlz() const override;
491 bool supportSwiftError() const override {
495 bool hasStandaloneRem(EVT VT) const override {
496 return HasStandaloneRem;
499 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
500 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
503 std::pair<const TargetRegisterClass *, uint8_t>
504 findRepresentativeClass(const TargetRegisterInfo *TRI,
505 MVT VT) const override;
508 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
509 /// make the right decision when generating code for different targets.
510 const ARMSubtarget *Subtarget;
512 const TargetRegisterInfo *RegInfo;
514 const InstrItineraryData *Itins;
516 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
518 unsigned ARMPCLabelIndex;
520 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
522 bool InsertFencesForAtomic;
524 bool HasStandaloneRem = true;
526 void InitLibcallCallingConvs();
528 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
529 void addDRTypeForNEON(MVT VT);
530 void addQRTypeForNEON(MVT VT);
531 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
533 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
534 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
535 SDValue &Arg, RegsToPassVector &RegsToPass,
536 CCValAssign &VA, CCValAssign &NextVA,
538 SmallVectorImpl<SDValue> &MemOpChains,
539 ISD::ArgFlagsTy Flags) const;
540 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
541 SDValue &Root, SelectionDAG &DAG,
542 const SDLoc &dl) const;
544 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
545 bool isVarArg) const;
546 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
547 bool isVarArg) const;
548 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
549 const SDLoc &dl, SelectionDAG &DAG,
550 const CCValAssign &VA,
551 ISD::ArgFlagsTy Flags) const;
552 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
553 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
554 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
556 const ARMSubtarget *Subtarget) const;
557 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
558 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
559 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
560 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
561 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
562 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
563 SelectionDAG &DAG) const;
564 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
566 TLSModel::Model model) const;
567 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
568 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
569 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
570 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
571 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
572 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
573 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
574 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
575 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
576 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
577 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
578 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
579 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
580 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
581 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
582 const ARMSubtarget *ST) const;
583 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
584 const ARMSubtarget *ST) const;
585 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
586 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
587 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
588 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
589 SmallVectorImpl<SDValue> &Results) const;
590 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
591 SDValue &Chain) const;
592 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
593 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
594 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
595 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
596 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
597 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
599 unsigned getRegisterByName(const char* RegName, EVT VT,
600 SelectionDAG &DAG) const override;
602 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
603 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
604 /// expanded to FMAs when this method returns true, otherwise fmuladd is
605 /// expanded to fmul + fadd.
607 /// ARM supports both fused and unfused multiply-add operations; we already
608 /// lower a pair of fmul and fadd to the latter so it's not clear that there
609 /// would be a gain or that the gain would be worthwhile enough to risk
610 /// correctness bugs.
611 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
613 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
615 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
616 CallingConv::ID CallConv, bool isVarArg,
617 const SmallVectorImpl<ISD::InputArg> &Ins,
618 const SDLoc &dl, SelectionDAG &DAG,
619 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
620 SDValue ThisVal) const;
622 bool supportSplitCSR(MachineFunction *MF) const override {
623 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
624 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
626 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
627 void insertCopiesSplitCSR(
628 MachineBasicBlock *Entry,
629 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
632 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
633 const SmallVectorImpl<ISD::InputArg> &Ins,
634 const SDLoc &dl, SelectionDAG &DAG,
635 SmallVectorImpl<SDValue> &InVals) const override;
637 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
638 SDValue &Chain, const Value *OrigArg,
639 unsigned InRegsParamRecordIdx, int ArgOffset,
640 unsigned ArgSize) const;
642 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
643 const SDLoc &dl, SDValue &Chain,
644 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
645 bool ForceMutable = false) const;
648 LowerCall(TargetLowering::CallLoweringInfo &CLI,
649 SmallVectorImpl<SDValue> &InVals) const override;
651 /// HandleByVal - Target-specific cleanup for ByVal support.
652 void HandleByVal(CCState *, unsigned &, unsigned) const override;
654 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
655 /// for tail call optimization. Targets which want to do tail call
656 /// optimization should implement this function.
657 bool IsEligibleForTailCallOptimization(SDValue Callee,
658 CallingConv::ID CalleeCC,
660 bool isCalleeStructRet,
661 bool isCallerStructRet,
662 const SmallVectorImpl<ISD::OutputArg> &Outs,
663 const SmallVectorImpl<SDValue> &OutVals,
664 const SmallVectorImpl<ISD::InputArg> &Ins,
665 SelectionDAG& DAG) const;
667 bool CanLowerReturn(CallingConv::ID CallConv,
668 MachineFunction &MF, bool isVarArg,
669 const SmallVectorImpl<ISD::OutputArg> &Outs,
670 LLVMContext &Context) const override;
672 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
673 const SmallVectorImpl<ISD::OutputArg> &Outs,
674 const SmallVectorImpl<SDValue> &OutVals,
675 const SDLoc &dl, SelectionDAG &DAG) const override;
677 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
679 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
681 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
682 SDValue ARMcc, SDValue CCR, SDValue Cmp,
683 SelectionDAG &DAG) const;
684 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
685 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
686 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
687 const SDLoc &dl) const;
688 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
690 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
692 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
693 MachineBasicBlock *DispatchBB, int FI) const;
695 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
697 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
699 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
700 MachineBasicBlock *MBB) const;
702 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
703 MachineBasicBlock *MBB) const;
704 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
705 MachineBasicBlock *MBB) const;
708 enum NEONModImmType {
715 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
716 const TargetLibraryInfo *libInfo);
720 #endif // ARMISELLOWERING_H