1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 BRCOND, // Conditional branch.
47 BR_JT, // Jumptable branch.
48 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
49 RET_FLAG, // Return with a flag operand.
50 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
52 PIC_ADD, // Add with a PC operand and a PIC label.
54 CMP, // ARM compare instructions.
55 CMN, // ARM CMN instructions.
56 CMPZ, // ARM compare that sets only Z flag.
57 CMPFP, // ARM VFP compare instruction, sets FPSCR.
58 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
59 FMSTAT, // ARM fmstat instruction.
61 CMOV, // ARM conditional move instructions.
63 SSAT, // Signed saturation
67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
71 ADDC, // Add with carry
72 ADDE, // Add using carry
73 SUBC, // Sub with carry
74 SUBE, // Sub using carry
76 VMOVRRD, // double to two gprs.
77 VMOVDRR, // Two gprs to double.
79 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
80 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
81 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
83 TC_RETURN, // Tail call return pseudo.
87 DYN_ALLOC, // Dynamic allocation on the stack.
89 MEMBARRIER_MCR, // Memory barrier (MCR)
93 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
94 WIN__DBZCHK, // Windows' divide by zero check
96 VCEQ, // Vector compare equal.
97 VCEQZ, // Vector compare equal to zero.
98 VCGE, // Vector compare greater than or equal.
99 VCGEZ, // Vector compare greater than or equal to zero.
100 VCLEZ, // Vector compare less than or equal to zero.
101 VCGEU, // Vector compare unsigned greater than or equal.
102 VCGT, // Vector compare greater than.
103 VCGTZ, // Vector compare greater than zero.
104 VCLTZ, // Vector compare less than zero.
105 VCGTU, // Vector compare unsigned greater than.
106 VTST, // Vector test bits.
108 // Vector shift by immediate:
110 VSHRs, // ...right (signed)
111 VSHRu, // ...right (unsigned)
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
131 // Vector shift and insert:
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
140 // Vector move immediate and move negated immediate:
144 // Vector move f32 immediate:
153 VREV64, // reverse elements within 64-bit doublewords
154 VREV32, // reverse elements within 32-bit words
155 VREV16, // reverse elements within 16-bit halfwords
156 VZIP, // zip (interleave)
157 VUZP, // unzip (deinterleave)
159 VTBL1, // 1-register shuffle with mask
160 VTBL2, // 2-register shuffle with mask
162 // Vector multiply long:
164 VMULLu, // ...unsigned
166 UMLAL, // 64bit Unsigned Accumulate Multiply
167 SMLAL, // 64bit Signed Accumulate Multiply
168 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
170 // Operands of the standard BUILD_VECTOR node are not legalized, which
171 // is fine if BUILD_VECTORs are always lowered to shuffles or other
172 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
173 // operands need to be legalized. Define an ARM-specific version of
174 // BUILD_VECTOR for this purpose.
180 // Vector OR with immediate
182 // Vector AND with NOT of immediate
185 // Vector bitwise select
188 // Pseudo-instruction representing a memory copy using ldm/stm
192 // Vector load N-element structure to all lanes:
193 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
197 // NEON loads with post-increment base updates:
209 // NEON stores with post-increment base updates:
220 /// Define some predicates that are used for node matching.
222 bool isBitFieldInvertedMask(unsigned v);
225 //===--------------------------------------------------------------------===//
226 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
228 class ARMTargetLowering : public TargetLowering {
230 explicit ARMTargetLowering(const TargetMachine &TM,
231 const ARMSubtarget &STI);
233 unsigned getJumpTableEncoding() const override;
234 bool useSoftFloat() const override;
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 /// ReplaceNodeResults - Replace the results of node with an illegal result
239 /// type with new values built out of custom code.
241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
242 SelectionDAG &DAG) const override;
244 const char *getTargetNodeName(unsigned Opcode) const override;
246 bool isSelectSupported(SelectSupportKind Kind) const override {
247 // ARM does not support scalar condition selects on vectors.
248 return (Kind != ScalarCondVectorVal);
251 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
252 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
253 EVT VT) const override;
256 EmitInstrWithCustomInserter(MachineInstr &MI,
257 MachineBasicBlock *MBB) const override;
259 void AdjustInstrPostInstrSelection(MachineInstr &MI,
260 SDNode *Node) const override;
262 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
263 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
264 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
265 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
267 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
269 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
270 /// unaligned memory accesses of the specified type. Returns whether it
271 /// is "fast" by reference in the second argument.
272 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
274 bool *Fast) const override;
276 EVT getOptimalMemOpType(uint64_t Size,
277 unsigned DstAlign, unsigned SrcAlign,
278 bool IsMemset, bool ZeroMemset,
280 MachineFunction &MF) const override;
282 using TargetLowering::isZExtFree;
283 bool isZExtFree(SDValue Val, EVT VT2) const override;
285 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
287 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
290 /// isLegalAddressingMode - Return true if the addressing mode represented
291 /// by AM is legal for this target, for a load/store of the specified type.
292 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
293 Type *Ty, unsigned AS) const override;
294 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
296 /// isLegalICmpImmediate - Return true if the specified immediate is legal
297 /// icmp immediate, that is the target has icmp instructions which can
298 /// compare a register against the immediate without having to materialize
299 /// the immediate into a register.
300 bool isLegalICmpImmediate(int64_t Imm) const override;
302 /// isLegalAddImmediate - Return true if the specified immediate is legal
303 /// add immediate, that is the target has add instructions which can
304 /// add a register and the immediate without having to materialize
305 /// the immediate into a register.
306 bool isLegalAddImmediate(int64_t Imm) const override;
308 /// getPreIndexedAddressParts - returns true by value, base pointer and
309 /// offset pointer and addressing mode by reference if the node's address
310 /// can be legally represented as pre-indexed load / store address.
311 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
312 ISD::MemIndexedMode &AM,
313 SelectionDAG &DAG) const override;
315 /// getPostIndexedAddressParts - returns true by value, base pointer and
316 /// offset pointer and addressing mode by reference if this node can be
317 /// combined with a load / store to form a post-indexed load / store.
318 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
319 SDValue &Offset, ISD::MemIndexedMode &AM,
320 SelectionDAG &DAG) const override;
322 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
324 const SelectionDAG &DAG,
325 unsigned Depth) const override;
328 bool ExpandInlineAsm(CallInst *CI) const override;
330 ConstraintType getConstraintType(StringRef Constraint) const override;
332 /// Examine constraint string and operand type and determine a weight value.
333 /// The operand object must already have been set up with the operand type.
334 ConstraintWeight getSingleConstraintMatchWeight(
335 AsmOperandInfo &info, const char *constraint) const override;
337 std::pair<unsigned, const TargetRegisterClass *>
338 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
339 StringRef Constraint, MVT VT) const override;
341 const char *LowerXConstraint(EVT ConstraintVT) const override;
343 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
344 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
345 /// true it means one of the asm constraint of the inline asm instruction
346 /// being processed is 'm'.
347 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
348 std::vector<SDValue> &Ops,
349 SelectionDAG &DAG) const override;
352 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
353 if (ConstraintCode == "Q")
354 return InlineAsm::Constraint_Q;
355 else if (ConstraintCode == "o")
356 return InlineAsm::Constraint_o;
357 else if (ConstraintCode.size() == 2) {
358 if (ConstraintCode[0] == 'U') {
359 switch(ConstraintCode[1]) {
363 return InlineAsm::Constraint_Um;
365 return InlineAsm::Constraint_Un;
367 return InlineAsm::Constraint_Uq;
369 return InlineAsm::Constraint_Us;
371 return InlineAsm::Constraint_Ut;
373 return InlineAsm::Constraint_Uv;
375 return InlineAsm::Constraint_Uy;
379 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
382 const ARMSubtarget* getSubtarget() const {
386 /// getRegClassFor - Return the register class that should be used for the
387 /// specified value type.
388 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
390 /// Returns true if a cast between SrcAS and DestAS is a noop.
391 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
392 // Addrspacecasts are always noops.
396 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
397 unsigned &PrefAlign) const override;
399 /// createFastISel - This method returns a target specific FastISel object,
400 /// or null if the target does not support "fast" ISel.
401 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
402 const TargetLibraryInfo *libInfo) const override;
404 Sched::Preference getSchedulingPreference(SDNode *N) const override;
407 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
408 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
410 /// isFPImmLegal - Returns true if the target can instruction select the
411 /// specified FP immediate natively. If false, the legalizer will
412 /// materialize the FP immediate as a load from a constant pool.
413 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
415 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
417 unsigned Intrinsic) const override;
419 /// \brief Returns true if it is beneficial to convert a load of a constant
420 /// to just the constant itself.
421 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
422 Type *Ty) const override;
424 /// \brief Returns true if an argument of type Ty needs to be passed in a
425 /// contiguous block of registers in calling convention CallConv.
426 bool functionArgumentNeedsConsecutiveRegisters(
427 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
429 /// If a physical register, this returns the register that receives the
430 /// exception address on entry to an EH pad.
432 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
434 /// If a physical register, this returns the register that receives the
435 /// exception typeid on entry to a landing pad.
437 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
439 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
440 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
441 AtomicOrdering Ord) const override;
442 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
443 Value *Addr, AtomicOrdering Ord) const override;
445 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
447 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
448 bool IsStore, bool IsLoad) const override;
449 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
450 bool IsStore, bool IsLoad) const override;
452 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
454 bool lowerInterleavedLoad(LoadInst *LI,
455 ArrayRef<ShuffleVectorInst *> Shuffles,
456 ArrayRef<unsigned> Indices,
457 unsigned Factor) const override;
458 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
459 unsigned Factor) const override;
461 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
462 TargetLoweringBase::AtomicExpansionKind
463 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
464 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
465 TargetLoweringBase::AtomicExpansionKind
466 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
467 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
469 bool useLoadStackGuardNode() const override;
471 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
472 unsigned &Cost) const override;
474 bool isCheapToSpeculateCttz() const override;
475 bool isCheapToSpeculateCtlz() const override;
477 bool supportSwiftError() const override {
481 bool hasStandaloneRem(EVT VT) const override {
482 return HasStandaloneRem;
486 std::pair<const TargetRegisterClass *, uint8_t>
487 findRepresentativeClass(const TargetRegisterInfo *TRI,
488 MVT VT) const override;
491 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
492 /// make the right decision when generating code for different targets.
493 const ARMSubtarget *Subtarget;
495 const TargetRegisterInfo *RegInfo;
497 const InstrItineraryData *Itins;
499 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
501 unsigned ARMPCLabelIndex;
503 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
505 bool InsertFencesForAtomic;
507 bool HasStandaloneRem = true;
509 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
510 void addDRTypeForNEON(MVT VT);
511 void addQRTypeForNEON(MVT VT);
512 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
514 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
515 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
516 SDValue &Arg, RegsToPassVector &RegsToPass,
517 CCValAssign &VA, CCValAssign &NextVA,
519 SmallVectorImpl<SDValue> &MemOpChains,
520 ISD::ArgFlagsTy Flags) const;
521 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
522 SDValue &Root, SelectionDAG &DAG,
523 const SDLoc &dl) const;
525 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
526 bool isVarArg) const;
527 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
528 bool isVarArg) const;
529 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
530 const SDLoc &dl, SelectionDAG &DAG,
531 const CCValAssign &VA,
532 ISD::ArgFlagsTy Flags) const;
533 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
534 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
535 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
536 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
537 const ARMSubtarget *Subtarget) const;
538 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
539 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
540 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
541 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
542 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
543 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
544 SelectionDAG &DAG) const;
545 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
547 TLSModel::Model model) const;
548 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
549 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
550 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
551 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
552 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
553 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
554 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
556 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
557 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
558 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
559 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
560 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
561 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
562 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
563 const ARMSubtarget *ST) const;
564 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
565 const ARMSubtarget *ST) const;
566 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
567 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
568 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
569 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
570 SmallVectorImpl<SDValue> &Results) const;
571 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
572 SDValue &Chain) const;
573 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
574 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
575 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
576 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
577 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
578 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
580 unsigned getRegisterByName(const char* RegName, EVT VT,
581 SelectionDAG &DAG) const override;
583 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
584 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
585 /// expanded to FMAs when this method returns true, otherwise fmuladd is
586 /// expanded to fmul + fadd.
588 /// ARM supports both fused and unfused multiply-add operations; we already
589 /// lower a pair of fmul and fadd to the latter so it's not clear that there
590 /// would be a gain or that the gain would be worthwhile enough to risk
591 /// correctness bugs.
592 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
594 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
596 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
597 CallingConv::ID CallConv, bool isVarArg,
598 const SmallVectorImpl<ISD::InputArg> &Ins,
599 const SDLoc &dl, SelectionDAG &DAG,
600 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
601 SDValue ThisVal) const;
603 bool supportSplitCSR(MachineFunction *MF) const override {
604 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
605 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
607 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
608 void insertCopiesSplitCSR(
609 MachineBasicBlock *Entry,
610 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
613 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
614 const SmallVectorImpl<ISD::InputArg> &Ins,
615 const SDLoc &dl, SelectionDAG &DAG,
616 SmallVectorImpl<SDValue> &InVals) const override;
618 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
619 SDValue &Chain, const Value *OrigArg,
620 unsigned InRegsParamRecordIdx, int ArgOffset,
621 unsigned ArgSize) const;
623 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
624 const SDLoc &dl, SDValue &Chain,
625 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
626 bool ForceMutable = false) const;
629 LowerCall(TargetLowering::CallLoweringInfo &CLI,
630 SmallVectorImpl<SDValue> &InVals) const override;
632 /// HandleByVal - Target-specific cleanup for ByVal support.
633 void HandleByVal(CCState *, unsigned &, unsigned) const override;
635 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
636 /// for tail call optimization. Targets which want to do tail call
637 /// optimization should implement this function.
638 bool IsEligibleForTailCallOptimization(SDValue Callee,
639 CallingConv::ID CalleeCC,
641 bool isCalleeStructRet,
642 bool isCallerStructRet,
643 const SmallVectorImpl<ISD::OutputArg> &Outs,
644 const SmallVectorImpl<SDValue> &OutVals,
645 const SmallVectorImpl<ISD::InputArg> &Ins,
646 SelectionDAG& DAG) const;
648 bool CanLowerReturn(CallingConv::ID CallConv,
649 MachineFunction &MF, bool isVarArg,
650 const SmallVectorImpl<ISD::OutputArg> &Outs,
651 LLVMContext &Context) const override;
653 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
654 const SmallVectorImpl<ISD::OutputArg> &Outs,
655 const SmallVectorImpl<SDValue> &OutVals,
656 const SDLoc &dl, SelectionDAG &DAG) const override;
658 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
660 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
662 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
663 SDValue ARMcc, SDValue CCR, SDValue Cmp,
664 SelectionDAG &DAG) const;
665 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
666 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
667 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
668 const SDLoc &dl) const;
669 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
671 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
673 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
674 MachineBasicBlock *DispatchBB, int FI) const;
676 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
678 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
680 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
681 MachineBasicBlock *MBB) const;
683 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
684 MachineBasicBlock *MBB) const;
685 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
686 MachineBasicBlock *MBB) const;
689 enum NEONModImmType {
696 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
697 const TargetLibraryInfo *libInfo);
701 #endif // ARMISELLOWERING_H