1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Selectable predicate operand for CMOV instructions. We can't use a normal
159 // predicate because the default values interfere with instruction selection. In
160 // all other respects it is identical though: pseudo-instruction expansion
161 // relies on the MachineOperands being compatible.
162 def cmovpred : Operand<i32>, PredicateOp,
163 ComplexPattern<i32, 2, "SelectCMOVPred"> {
164 let MIOperandInfo = (ops i32imm, i32imm);
165 let PrintMethod = "printPredicateOperand";
168 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
169 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
170 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
171 let EncoderMethod = "getCCOutOpValue";
172 let PrintMethod = "printSBitModifierOperand";
173 let ParserMatchClass = CCOutOperand;
174 let DecoderMethod = "DecodeCCOutOperand";
177 // Same as cc_out except it defaults to setting CPSR.
178 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
179 let EncoderMethod = "getCCOutOpValue";
180 let PrintMethod = "printSBitModifierOperand";
181 let ParserMatchClass = CCOutOperand;
182 let DecoderMethod = "DecodeCCOutOperand";
185 // ARM special operands for disassembly only.
187 def SetEndAsmOperand : ImmAsmOperand {
188 let Name = "SetEndImm";
189 let ParserMethod = "parseSetEndImm";
191 def setend_op : Operand<i32> {
192 let PrintMethod = "printSetendOperand";
193 let ParserMatchClass = SetEndAsmOperand;
196 def MSRMaskOperand : AsmOperandClass {
197 let Name = "MSRMask";
198 let ParserMethod = "parseMSRMaskOperand";
200 def msr_mask : Operand<i32> {
201 let PrintMethod = "printMSRMaskOperand";
202 let DecoderMethod = "DecodeMSRMask";
203 let ParserMatchClass = MSRMaskOperand;
206 def BankedRegOperand : AsmOperandClass {
207 let Name = "BankedReg";
208 let ParserMethod = "parseBankedRegOperand";
210 def banked_reg : Operand<i32> {
211 let PrintMethod = "printBankedRegOperand";
212 let DecoderMethod = "DecodeBankedReg";
213 let ParserMatchClass = BankedRegOperand;
216 // Shift Right Immediate - A shift right immediate is encoded differently from
217 // other shift immediates. The imm6 field is encoded like so:
220 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
221 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
222 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
223 // 64 64 - <imm> is encoded in imm6<5:0>
224 def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
225 def shr_imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 8; }]> {
226 let EncoderMethod = "getShiftRight8Imm";
227 let DecoderMethod = "DecodeShiftRight8Imm";
228 let ParserMatchClass = shr_imm8_asm_operand;
230 def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
231 def shr_imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }]> {
232 let EncoderMethod = "getShiftRight16Imm";
233 let DecoderMethod = "DecodeShiftRight16Imm";
234 let ParserMatchClass = shr_imm16_asm_operand;
236 def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
237 def shr_imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> {
238 let EncoderMethod = "getShiftRight32Imm";
239 let DecoderMethod = "DecodeShiftRight32Imm";
240 let ParserMatchClass = shr_imm32_asm_operand;
242 def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
243 def shr_imm64 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 64; }]> {
244 let EncoderMethod = "getShiftRight64Imm";
245 let DecoderMethod = "DecodeShiftRight64Imm";
246 let ParserMatchClass = shr_imm64_asm_operand;
250 // ARM Assembler operand for ldr Rd, =expression which generates an offset
251 // to a constant pool entry or a MOV depending on the value of expression
252 def const_pool_asm_operand : AsmOperandClass { let Name = "ConstPoolAsmImm"; }
253 def const_pool_asm_imm : Operand<i32> {
254 let ParserMatchClass = const_pool_asm_operand;
258 //===----------------------------------------------------------------------===//
259 // ARM Assembler alias templates.
261 // Note: When EmitPriority == 1, the alias will be used for printing
262 class ARMInstAlias<string Asm, dag Result, bit EmitPriority = 0>
263 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsARM]>;
264 class tInstAlias<string Asm, dag Result, bit EmitPriority = 0>
265 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb]>;
266 class t2InstAlias<string Asm, dag Result, bit EmitPriority = 0>
267 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb2]>;
268 class VFP2InstAlias<string Asm, dag Result, bit EmitPriority = 0>
269 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2]>;
270 class VFP2DPInstAlias<string Asm, dag Result, bit EmitPriority = 0>
271 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2,HasDPVFP]>;
272 class VFP3InstAlias<string Asm, dag Result, bit EmitPriority = 0>
273 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>;
274 class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0>
275 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>;
278 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
280 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
283 //===----------------------------------------------------------------------===//
284 // ARM Instruction templates.
288 class InstTemplate<AddrMode am, int sz, IndexMode im,
289 Format f, Domain d, string cstr, InstrItinClass itin>
291 let Namespace = "ARM";
296 bits<2> IndexModeBits = IM.Value;
298 bits<6> Form = F.Value;
300 bit isUnaryDataProc = 0;
301 bit canXformTo16Bit = 0;
302 // The instruction is a 16-bit flag setting Thumb instruction. Used
303 // by the parser to determine whether to require the 'S' suffix on the
304 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
305 bit thumbArithFlagSetting = 0;
307 // If this is a pseudo instruction, mark it isCodeGenOnly.
308 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
310 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
311 let TSFlags{4-0} = AM.Value;
312 let TSFlags{6-5} = IndexModeBits;
313 let TSFlags{12-7} = Form;
314 let TSFlags{13} = isUnaryDataProc;
315 let TSFlags{14} = canXformTo16Bit;
316 let TSFlags{17-15} = D.Value;
317 let TSFlags{18} = thumbArithFlagSetting;
319 let Constraints = cstr;
320 let Itinerary = itin;
325 // Mask of bits that cause an encoding to be UNPREDICTABLE.
326 // If a bit is set, then if the corresponding bit in the
327 // target encoding differs from its value in the "Inst" field,
328 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
329 field bits<32> Unpredictable = 0;
330 // SoftFail is the generic name for this field, but we alias it so
331 // as to make it more obvious what it means in ARM-land.
332 field bits<32> SoftFail = Unpredictable;
335 class InstARM<AddrMode am, int sz, IndexMode im,
336 Format f, Domain d, string cstr, InstrItinClass itin>
337 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
338 let DecoderNamespace = "ARM";
341 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
342 // on by adding flavors to specific instructions.
343 class InstThumb<AddrMode am, int sz, IndexMode im,
344 Format f, Domain d, string cstr, InstrItinClass itin>
345 : InstTemplate<am, sz, im, f, d, cstr, itin> {
346 let DecoderNamespace = "Thumb";
349 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
350 // These are aliases that require C++ handling to convert to the target
351 // instruction, while InstAliases can be handled directly by tblgen.
352 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
353 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
355 let OutOperandList = oops;
356 let InOperandList = iops;
358 let isCodeGenOnly = 0; // So we get asm matcher for it.
363 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
364 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
365 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
366 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
367 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
368 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
369 class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
370 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
371 class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)>
372 : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>;
374 // Pseudo instructions for the code generator.
375 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
376 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
377 GenericDomain, "", itin> {
378 let OutOperandList = oops;
379 let InOperandList = iops;
380 let Pattern = pattern;
381 let isCodeGenOnly = 1;
385 // PseudoInst that's ARM-mode only.
386 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
388 : PseudoInst<oops, iops, itin, pattern> {
390 list<Predicate> Predicates = [IsARM];
393 // PseudoInst that's Thumb-mode only.
394 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
396 : PseudoInst<oops, iops, itin, pattern> {
398 list<Predicate> Predicates = [IsThumb];
401 // PseudoInst that's in ARMv8-M baseline (Somewhere between Thumb and Thumb2)
402 class t2basePseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
404 : PseudoInst<oops, iops, itin, pattern> {
406 list<Predicate> Predicates = [IsThumb,HasV8MBaseline];
409 // PseudoInst that's Thumb2-mode only.
410 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
412 : PseudoInst<oops, iops, itin, pattern> {
414 list<Predicate> Predicates = [IsThumb2];
417 class ARMPseudoExpand<dag oops, dag iops, int sz,
418 InstrItinClass itin, list<dag> pattern,
420 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
421 PseudoInstExpansion<Result>;
423 class tPseudoExpand<dag oops, dag iops, int sz,
424 InstrItinClass itin, list<dag> pattern,
426 : tPseudoInst<oops, iops, sz, itin, pattern>,
427 PseudoInstExpansion<Result>;
429 class t2PseudoExpand<dag oops, dag iops, int sz,
430 InstrItinClass itin, list<dag> pattern,
432 : t2PseudoInst<oops, iops, sz, itin, pattern>,
433 PseudoInstExpansion<Result>;
435 // Almost all ARM instructions are predicable.
436 class I<dag oops, dag iops, AddrMode am, int sz,
437 IndexMode im, Format f, InstrItinClass itin,
438 string opc, string asm, string cstr,
440 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
443 let OutOperandList = oops;
444 let InOperandList = !con(iops, (ins pred:$p));
445 let AsmString = !strconcat(opc, "${p}", asm);
446 let Pattern = pattern;
447 list<Predicate> Predicates = [IsARM];
450 // A few are not predicable
451 class InoP<dag oops, dag iops, AddrMode am, int sz,
452 IndexMode im, Format f, InstrItinClass itin,
453 string opc, string asm, string cstr,
455 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
456 let OutOperandList = oops;
457 let InOperandList = iops;
458 let AsmString = !strconcat(opc, asm);
459 let Pattern = pattern;
460 let isPredicable = 0;
461 list<Predicate> Predicates = [IsARM];
464 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
465 // operand since by default it's a zero register. It will become an implicit def
466 // once it's "flipped".
467 class sI<dag oops, dag iops, AddrMode am, int sz,
468 IndexMode im, Format f, InstrItinClass itin,
469 string opc, string asm, string cstr,
471 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
472 bits<4> p; // Predicate operand
473 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
477 let OutOperandList = oops;
478 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
479 let AsmString = !strconcat(opc, "${s}${p}", asm);
480 let Pattern = pattern;
481 list<Predicate> Predicates = [IsARM];
485 class XI<dag oops, dag iops, AddrMode am, int sz,
486 IndexMode im, Format f, InstrItinClass itin,
487 string asm, string cstr, list<dag> pattern>
488 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
489 let OutOperandList = oops;
490 let InOperandList = iops;
492 let Pattern = pattern;
493 list<Predicate> Predicates = [IsARM];
496 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
497 string opc, string asm, list<dag> pattern>
498 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
499 opc, asm, "", pattern>;
500 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
501 string opc, string asm, list<dag> pattern>
502 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
503 opc, asm, "", pattern>;
504 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
505 string asm, list<dag> pattern>
506 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
508 class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin,
509 string asm, list<dag> pattern>
510 : XI<oops, iops, am, 4, IndexModeNone, f, itin,
512 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
513 string opc, string asm, list<dag> pattern>
514 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
515 opc, asm, "", pattern>;
517 // Ctrl flow instructions
518 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
519 string opc, string asm, list<dag> pattern>
520 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
521 opc, asm, "", pattern> {
522 let Inst{27-24} = opcod;
524 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
525 string asm, list<dag> pattern>
526 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
528 let Inst{27-24} = opcod;
531 // BR_JT instructions
532 class JTI<dag oops, dag iops, InstrItinClass itin,
533 string asm, list<dag> pattern>
534 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
537 class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
538 string opc, string asm, list<dag> pattern>
539 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
540 opc, asm, "", pattern> {
543 let Inst{27-23} = 0b00011;
544 let Inst{22-21} = opcod;
546 let Inst{19-16} = addr;
547 let Inst{15-12} = Rt;
548 let Inst{11-10} = 0b11;
549 let Inst{9-8} = opcod2;
550 let Inst{7-0} = 0b10011111;
552 class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
553 string opc, string asm, list<dag> pattern>
554 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
555 opc, asm, "", pattern> {
558 let Inst{27-23} = 0b00011;
559 let Inst{22-21} = opcod;
561 let Inst{19-16} = addr;
562 let Inst{11-10} = 0b11;
563 let Inst{9-8} = opcod2;
564 let Inst{7-4} = 0b1001;
567 // Atomic load/store instructions
568 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
569 string opc, string asm, list<dag> pattern>
570 : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>;
572 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
573 string opc, string asm, list<dag> pattern>
574 : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> {
576 let Inst{15-12} = Rd;
579 // Exclusive load/store instructions
581 class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
582 string opc, string asm, list<dag> pattern>
583 : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
584 Requires<[IsARM, HasAcquireRelease, HasV7Clrex]>;
586 class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
587 string opc, string asm, list<dag> pattern>
588 : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
589 Requires<[IsARM, HasAcquireRelease, HasV7Clrex]> {
591 let Inst{15-12} = Rd;
594 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
595 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
599 let Inst{27-23} = 0b00010;
601 let Inst{21-20} = 0b00;
602 let Inst{19-16} = addr;
603 let Inst{15-12} = Rt;
604 let Inst{11-4} = 0b00001001;
607 let Unpredictable{11-8} = 0b1111;
608 let DecoderMethod = "DecodeSwap";
610 // Acquire/Release load/store instructions
611 class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
612 string opc, string asm, list<dag> pattern>
613 : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
614 Requires<[IsARM, HasAcquireRelease]>;
616 class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
617 string opc, string asm, list<dag> pattern>
618 : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
619 Requires<[IsARM, HasAcquireRelease]> {
620 let Inst{15-12} = 0b1111;
623 // addrmode1 instructions
624 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
625 string opc, string asm, list<dag> pattern>
626 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
627 opc, asm, "", pattern> {
628 let Inst{24-21} = opcod;
629 let Inst{27-26} = 0b00;
631 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
632 string opc, string asm, list<dag> pattern>
633 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
634 opc, asm, "", pattern> {
635 let Inst{24-21} = opcod;
636 let Inst{27-26} = 0b00;
638 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
639 string asm, list<dag> pattern>
640 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
642 let Inst{24-21} = opcod;
643 let Inst{27-26} = 0b00;
648 // LDR/LDRB/STR/STRB/...
649 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
650 Format f, InstrItinClass itin, string opc, string asm,
652 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
654 let Inst{27-25} = op;
655 let Inst{24} = 1; // 24 == P
657 let Inst{22} = isByte;
658 let Inst{21} = 0; // 21 == W
661 // Indexed load/stores
662 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
663 IndexMode im, Format f, InstrItinClass itin, string opc,
664 string asm, string cstr, list<dag> pattern>
665 : I<oops, iops, AddrMode2, 4, im, f, itin,
666 opc, asm, cstr, pattern> {
668 let Inst{27-26} = 0b01;
669 let Inst{24} = isPre; // P bit
670 let Inst{22} = isByte; // B bit
671 let Inst{21} = isPre; // W bit
672 let Inst{20} = isLd; // L bit
673 let Inst{15-12} = Rt;
675 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
676 IndexMode im, Format f, InstrItinClass itin, string opc,
677 string asm, string cstr, list<dag> pattern>
678 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
680 // AM2 store w/ two operands: (GPR, am2offset)
686 let Inst{23} = offset{12};
687 let Inst{19-16} = Rn;
688 let Inst{11-5} = offset{11-5};
690 let Inst{3-0} = offset{3-0};
693 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
694 IndexMode im, Format f, InstrItinClass itin, string opc,
695 string asm, string cstr, list<dag> pattern>
696 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
698 // AM2 store w/ two operands: (GPR, am2offset)
704 let Inst{23} = offset{12};
705 let Inst{19-16} = Rn;
706 let Inst{11-0} = offset{11-0};
710 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
711 // but for now use this class for STRT and STRBT.
712 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
713 IndexMode im, Format f, InstrItinClass itin, string opc,
714 string asm, string cstr, list<dag> pattern>
715 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
717 // AM2 store w/ two operands: (GPR, am2offset)
719 // {13} 1 == Rm, 0 == imm12
723 let Inst{25} = addr{13};
724 let Inst{23} = addr{12};
725 let Inst{19-16} = addr{17-14};
726 let Inst{11-0} = addr{11-0};
729 // addrmode3 instructions
730 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
731 InstrItinClass itin, string opc, string asm, list<dag> pattern>
732 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
733 opc, asm, "", pattern> {
736 let Inst{27-25} = 0b000;
737 let Inst{24} = 1; // P bit
738 let Inst{23} = addr{8}; // U bit
739 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
740 let Inst{21} = 0; // W bit
741 let Inst{20} = op20; // L bit
742 let Inst{19-16} = addr{12-9}; // Rn
743 let Inst{15-12} = Rt; // Rt
744 let Inst{11-8} = addr{7-4}; // imm7_4/zero
746 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
748 let DecoderMethod = "DecodeAddrMode3Instruction";
751 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
752 IndexMode im, Format f, InstrItinClass itin, string opc,
753 string asm, string cstr, list<dag> pattern>
754 : I<oops, iops, AddrMode3, 4, im, f, itin,
755 opc, asm, cstr, pattern> {
757 let Inst{27-25} = 0b000;
758 let Inst{24} = isPre; // P bit
759 let Inst{21} = isPre; // W bit
760 let Inst{20} = op20; // L bit
761 let Inst{15-12} = Rt; // Rt
765 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
766 // but for now use this class for LDRSBT, LDRHT, LDSHT.
767 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
768 IndexMode im, Format f, InstrItinClass itin, string opc,
769 string asm, string cstr, list<dag> pattern>
770 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
771 // {13} 1 == imm8, 0 == Rm
778 let Inst{27-25} = 0b000;
779 let Inst{24} = 0; // P bit
781 let Inst{20} = isLoad; // L bit
782 let Inst{19-16} = addr; // Rn
783 let Inst{15-12} = Rt; // Rt
788 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
789 string opc, string asm, list<dag> pattern>
790 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
791 opc, asm, "", pattern> {
794 let Inst{27-25} = 0b000;
795 let Inst{24} = 1; // P bit
796 let Inst{23} = addr{8}; // U bit
797 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
798 let Inst{21} = 0; // W bit
799 let Inst{20} = 0; // L bit
800 let Inst{19-16} = addr{12-9}; // Rn
801 let Inst{15-12} = Rt; // Rt
802 let Inst{11-8} = addr{7-4}; // imm7_4/zero
804 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
805 let DecoderMethod = "DecodeAddrMode3Instruction";
808 // addrmode4 instructions
809 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
810 string asm, string cstr, list<dag> pattern>
811 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
816 let Inst{27-25} = 0b100;
817 let Inst{22} = 0; // S bit
818 let Inst{19-16} = Rn;
819 let Inst{15-0} = regs;
822 // Unsigned multiply, multiply-accumulate instructions.
823 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
824 string opc, string asm, list<dag> pattern>
825 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
826 opc, asm, "", pattern> {
827 let Inst{7-4} = 0b1001;
828 let Inst{20} = 0; // S bit
829 let Inst{27-21} = opcod;
831 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
832 string opc, string asm, list<dag> pattern>
833 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
834 opc, asm, "", pattern> {
835 let Inst{7-4} = 0b1001;
836 let Inst{27-21} = opcod;
839 // Most significant word multiply
840 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
841 InstrItinClass itin, string opc, string asm, list<dag> pattern>
842 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
843 opc, asm, "", pattern> {
847 let Inst{7-4} = opc7_4;
849 let Inst{27-21} = opcod;
850 let Inst{19-16} = Rd;
854 // MSW multiple w/ Ra operand
855 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
856 InstrItinClass itin, string opc, string asm, list<dag> pattern>
857 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
859 let Inst{15-12} = Ra;
862 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
863 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
864 InstrItinClass itin, string opc, string asm, list<dag> pattern>
865 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
866 opc, asm, "", pattern> {
872 let Inst{27-21} = opcod;
873 let Inst{6-5} = bit6_5;
877 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
878 InstrItinClass itin, string opc, string asm, list<dag> pattern>
879 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
881 let Inst{19-16} = Rd;
884 // AMulxyI with Ra operand
885 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
886 InstrItinClass itin, string opc, string asm, list<dag> pattern>
887 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
889 let Inst{15-12} = Ra;
892 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
893 InstrItinClass itin, string opc, string asm, list<dag> pattern>
894 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
897 let Inst{19-16} = RdHi;
898 let Inst{15-12} = RdLo;
901 // Extend instructions.
902 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
903 string opc, string asm, list<dag> pattern>
904 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
905 opc, asm, "", pattern> {
906 // All AExtI instructions have Rd and Rm register operands.
909 let Inst{15-12} = Rd;
911 let Inst{7-4} = 0b0111;
912 let Inst{9-8} = 0b00;
913 let Inst{27-20} = opcod;
915 let Unpredictable{9-8} = 0b11;
918 // Misc Arithmetic instructions.
919 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
920 InstrItinClass itin, string opc, string asm, list<dag> pattern>
921 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
922 opc, asm, "", pattern> {
925 let Inst{27-20} = opcod;
926 let Inst{19-16} = 0b1111;
927 let Inst{15-12} = Rd;
928 let Inst{11-8} = 0b1111;
929 let Inst{7-4} = opc7_4;
933 // Division instructions.
934 class ADivA1I<bits<3> opcod, dag oops, dag iops,
935 InstrItinClass itin, string opc, string asm, list<dag> pattern>
936 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
937 opc, asm, "", pattern> {
941 let Inst{27-23} = 0b01110;
942 let Inst{22-20} = opcod;
943 let Inst{19-16} = Rd;
944 let Inst{15-12} = 0b1111;
946 let Inst{7-4} = 0b0001;
951 def PKHLSLAsmOperand : ImmAsmOperand {
952 let Name = "PKHLSLImm";
953 let ParserMethod = "parsePKHLSLImm";
955 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
956 let PrintMethod = "printPKHLSLShiftImm";
957 let ParserMatchClass = PKHLSLAsmOperand;
959 def PKHASRAsmOperand : AsmOperandClass {
960 let Name = "PKHASRImm";
961 let ParserMethod = "parsePKHASRImm";
963 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
964 let PrintMethod = "printPKHASRShiftImm";
965 let ParserMatchClass = PKHASRAsmOperand;
968 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
969 string opc, string asm, list<dag> pattern>
970 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
971 opc, asm, "", pattern> {
976 let Inst{27-20} = opcod;
977 let Inst{19-16} = Rn;
978 let Inst{15-12} = Rd;
981 let Inst{5-4} = 0b01;
985 //===----------------------------------------------------------------------===//
987 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
988 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
989 list<Predicate> Predicates = [IsARM];
991 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
992 list<Predicate> Predicates = [IsARM, HasV5T];
994 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
995 list<Predicate> Predicates = [IsARM, HasV5TE];
997 // ARMV5MOPat - Same as ARMV5TEPat with UseMulOps.
998 class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> {
999 list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
1001 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
1002 list<Predicate> Predicates = [IsARM, HasV6];
1004 class VFPPat<dag pattern, dag result> : Pat<pattern, result> {
1005 list<Predicate> Predicates = [HasVFP2];
1007 class VFPNoNEONPat<dag pattern, dag result> : Pat<pattern, result> {
1008 list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
1010 class Thumb2DSPPat<dag pattern, dag result> : Pat<pattern, result> {
1011 list<Predicate> Predicates = [IsThumb2, HasDSP];
1013 class Thumb2DSPMulPat<dag pattern, dag result> : Pat<pattern, result> {
1014 list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
1016 class Thumb2ExtractPat<dag pattern, dag result> : Pat<pattern, result> {
1017 list<Predicate> Predicates = [IsThumb2, HasT2ExtractPack];
1019 //===----------------------------------------------------------------------===//
1020 // Thumb Instruction Format Definitions.
1023 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
1024 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1025 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1026 let OutOperandList = oops;
1027 let InOperandList = iops;
1028 let AsmString = asm;
1029 let Pattern = pattern;
1030 list<Predicate> Predicates = [IsThumb];
1033 // TI - Thumb instruction.
1034 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
1035 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
1037 // Two-address instructions
1038 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1040 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
1043 // tBL, tBX 32-bit instructions
1044 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1045 dag oops, dag iops, InstrItinClass itin, string asm,
1047 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
1049 let Inst{31-27} = opcod1;
1050 let Inst{15-14} = opcod2;
1051 let Inst{12} = opcod3;
1054 // BR_JT instructions
1055 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1057 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1060 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
1061 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1062 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1063 let OutOperandList = oops;
1064 let InOperandList = iops;
1065 let AsmString = asm;
1066 let Pattern = pattern;
1067 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1070 class T1I<dag oops, dag iops, InstrItinClass itin,
1071 string asm, list<dag> pattern>
1072 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
1073 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1074 string asm, list<dag> pattern>
1075 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1077 // Two-address instructions
1078 class T1It<dag oops, dag iops, InstrItinClass itin,
1079 string asm, string cstr, list<dag> pattern>
1080 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
1081 asm, cstr, pattern>;
1083 // Thumb1 instruction that can either be predicated or set CPSR.
1084 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
1085 InstrItinClass itin,
1086 string opc, string asm, string cstr, list<dag> pattern>
1087 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1088 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1089 let InOperandList = !con(iops, (ins pred:$p));
1090 let AsmString = !strconcat(opc, "${s}${p}", asm);
1091 let Pattern = pattern;
1092 let thumbArithFlagSetting = 1;
1093 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1094 let DecoderNamespace = "ThumbSBit";
1097 class T1sI<dag oops, dag iops, InstrItinClass itin,
1098 string opc, string asm, list<dag> pattern>
1099 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1101 // Two-address instructions
1102 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1103 string opc, string asm, list<dag> pattern>
1104 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1105 "$Rn = $Rdn", pattern>;
1107 // Thumb1 instruction that can be predicated.
1108 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
1109 InstrItinClass itin,
1110 string opc, string asm, string cstr, list<dag> pattern>
1111 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1112 let OutOperandList = oops;
1113 let InOperandList = !con(iops, (ins pred:$p));
1114 let AsmString = !strconcat(opc, "${p}", asm);
1115 let Pattern = pattern;
1116 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1119 class T1pI<dag oops, dag iops, InstrItinClass itin,
1120 string opc, string asm, list<dag> pattern>
1121 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1123 // Two-address instructions
1124 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1125 string opc, string asm, list<dag> pattern>
1126 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1127 "$Rn = $Rdn", pattern>;
1129 class T1pIs<dag oops, dag iops,
1130 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1131 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1133 class Encoding16 : Encoding {
1134 let Inst{31-16} = 0x0000;
1137 // A6.2 16-bit Thumb instruction encoding
1138 class T1Encoding<bits<6> opcode> : Encoding16 {
1139 let Inst{15-10} = opcode;
1142 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1143 class T1General<bits<5> opcode> : Encoding16 {
1144 let Inst{15-14} = 0b00;
1145 let Inst{13-9} = opcode;
1148 // A6.2.2 Data-processing encoding.
1149 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1150 let Inst{15-10} = 0b010000;
1151 let Inst{9-6} = opcode;
1154 // A6.2.3 Special data instructions and branch and exchange encoding.
1155 class T1Special<bits<4> opcode> : Encoding16 {
1156 let Inst{15-10} = 0b010001;
1157 let Inst{9-6} = opcode;
1160 // A6.2.4 Load/store single data item encoding.
1161 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1162 let Inst{15-12} = opA;
1163 let Inst{11-9} = opB;
1165 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1167 class T1BranchCond<bits<4> opcode> : Encoding16 {
1168 let Inst{15-12} = opcode;
1171 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1172 // following bits are used for "opA" (see A6.2.4):
1174 // 0b0110 => Immediate, 4 bytes
1175 // 0b1000 => Immediate, 2 bytes
1176 // 0b0111 => Immediate, 1 byte
1177 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1178 InstrItinClass itin, string opc, string asm,
1180 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1181 T1LoadStore<0b0101, opcode> {
1184 let Inst{8-6} = addr{5-3}; // Rm
1185 let Inst{5-3} = addr{2-0}; // Rn
1188 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1189 InstrItinClass itin, string opc, string asm,
1191 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1192 T1LoadStore<opA, {opB,?,?}> {
1195 let Inst{10-6} = addr{7-3}; // imm5
1196 let Inst{5-3} = addr{2-0}; // Rn
1200 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1201 class T1Misc<bits<7> opcode> : Encoding16 {
1202 let Inst{15-12} = 0b1011;
1203 let Inst{11-5} = opcode;
1206 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1207 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1208 InstrItinClass itin,
1209 string opc, string asm, string cstr, list<dag> pattern>
1210 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1211 let OutOperandList = oops;
1212 let InOperandList = !con(iops, (ins pred:$p));
1213 let AsmString = !strconcat(opc, "${p}", asm);
1214 let Pattern = pattern;
1215 list<Predicate> Predicates = [IsThumb2];
1216 let DecoderNamespace = "Thumb2";
1219 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1220 // input operand since by default it's a zero register. It will become an
1221 // implicit def once it's "flipped".
1223 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1225 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1226 InstrItinClass itin,
1227 string opc, string asm, string cstr, list<dag> pattern>
1228 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1229 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1232 let OutOperandList = oops;
1233 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1234 let AsmString = !strconcat(opc, "${s}${p}", asm);
1235 let Pattern = pattern;
1236 list<Predicate> Predicates = [IsThumb2];
1237 let DecoderNamespace = "Thumb2";
1241 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1242 InstrItinClass itin,
1243 string asm, string cstr, list<dag> pattern>
1244 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1245 let OutOperandList = oops;
1246 let InOperandList = iops;
1247 let AsmString = asm;
1248 let Pattern = pattern;
1249 list<Predicate> Predicates = [IsThumb2];
1250 let DecoderNamespace = "Thumb2";
1253 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1254 InstrItinClass itin,
1255 string asm, string cstr, list<dag> pattern>
1256 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1257 let OutOperandList = oops;
1258 let InOperandList = iops;
1259 let AsmString = asm;
1260 let Pattern = pattern;
1261 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1262 let DecoderNamespace = "Thumb";
1265 class T2I<dag oops, dag iops, InstrItinClass itin,
1266 string opc, string asm, list<dag> pattern>
1267 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1268 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1269 string opc, string asm, list<dag> pattern>
1270 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1271 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1272 string opc, string asm, list<dag> pattern>
1273 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1274 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1275 string opc, string asm, list<dag> pattern>
1276 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1277 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1278 string opc, string asm, list<dag> pattern>
1279 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1280 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1281 string opc, string asm, string cstr, list<dag> pattern>
1282 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1287 let Inst{31-25} = 0b1110100;
1289 let Inst{23} = addr{8};
1292 let Inst{20} = isLoad;
1293 let Inst{19-16} = addr{12-9};
1294 let Inst{15-12} = Rt{3-0};
1295 let Inst{11-8} = Rt2{3-0};
1296 let Inst{7-0} = addr{7-0};
1298 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1299 InstrItinClass itin, string opc, string asm, string cstr,
1301 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1307 let Inst{31-25} = 0b1110100;
1309 let Inst{23} = imm{8};
1312 let Inst{20} = isLoad;
1313 let Inst{19-16} = addr;
1314 let Inst{15-12} = Rt{3-0};
1315 let Inst{11-8} = Rt2{3-0};
1316 let Inst{7-0} = imm{7-0};
1319 class T2sI<dag oops, dag iops, InstrItinClass itin,
1320 string opc, string asm, list<dag> pattern>
1321 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1323 class T2XI<dag oops, dag iops, InstrItinClass itin,
1324 string asm, list<dag> pattern>
1325 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1326 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1327 string asm, list<dag> pattern>
1328 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1330 // Move to/from coprocessor instructions
1331 class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
1333 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
1334 let Inst{31-28} = opc;
1337 // Two-address instructions
1338 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1339 string asm, string cstr, list<dag> pattern>
1340 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1342 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1343 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1345 AddrMode am, IndexMode im, InstrItinClass itin,
1346 string opc, string asm, string cstr, list<dag> pattern>
1347 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1348 let OutOperandList = oops;
1349 let InOperandList = !con(iops, (ins pred:$p));
1350 let AsmString = !strconcat(opc, "${p}", asm);
1351 let Pattern = pattern;
1352 list<Predicate> Predicates = [IsThumb2];
1353 let DecoderNamespace = "Thumb2";
1357 let Inst{31-27} = 0b11111;
1358 let Inst{26-25} = 0b00;
1359 let Inst{24} = signed;
1361 let Inst{22-21} = opcod;
1362 let Inst{20} = load;
1363 let Inst{19-16} = addr{12-9};
1364 let Inst{15-12} = Rt{3-0};
1366 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1367 let Inst{10} = pre; // The P bit.
1368 let Inst{9} = addr{8}; // Sign bit
1369 let Inst{8} = 1; // The W bit.
1370 let Inst{7-0} = addr{7-0};
1372 let DecoderMethod = "DecodeT2LdStPre";
1375 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1376 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1378 AddrMode am, IndexMode im, InstrItinClass itin,
1379 string opc, string asm, string cstr, list<dag> pattern>
1380 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1381 let OutOperandList = oops;
1382 let InOperandList = !con(iops, (ins pred:$p));
1383 let AsmString = !strconcat(opc, "${p}", asm);
1384 let Pattern = pattern;
1385 list<Predicate> Predicates = [IsThumb2];
1386 let DecoderNamespace = "Thumb2";
1391 let Inst{31-27} = 0b11111;
1392 let Inst{26-25} = 0b00;
1393 let Inst{24} = signed;
1395 let Inst{22-21} = opcod;
1396 let Inst{20} = load;
1397 let Inst{19-16} = Rn;
1398 let Inst{15-12} = Rt{3-0};
1400 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1401 let Inst{10} = pre; // The P bit.
1402 let Inst{9} = offset{8}; // Sign bit
1403 let Inst{8} = 1; // The W bit.
1404 let Inst{7-0} = offset{7-0};
1406 let DecoderMethod = "DecodeT2LdStPre";
1409 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1410 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1411 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1414 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1415 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1416 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1419 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1420 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1421 list<Predicate> Predicates = [IsThumb2];
1424 //===----------------------------------------------------------------------===//
1426 //===----------------------------------------------------------------------===//
1427 // ARM VFP Instruction templates.
1430 // Almost all VFP instructions are predicable.
1431 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1432 IndexMode im, Format f, InstrItinClass itin,
1433 string opc, string asm, string cstr, list<dag> pattern>
1434 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1436 let Inst{31-28} = p;
1437 let OutOperandList = oops;
1438 let InOperandList = !con(iops, (ins pred:$p));
1439 let AsmString = !strconcat(opc, "${p}", asm);
1440 let Pattern = pattern;
1441 let PostEncoderMethod = "VFPThumb2PostEncoder";
1442 let DecoderNamespace = "VFP";
1443 list<Predicate> Predicates = [HasVFP2];
1447 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1448 IndexMode im, Format f, InstrItinClass itin,
1449 string asm, string cstr, list<dag> pattern>
1450 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1452 let Inst{31-28} = p;
1453 let OutOperandList = oops;
1454 let InOperandList = iops;
1455 let AsmString = asm;
1456 let Pattern = pattern;
1457 let PostEncoderMethod = "VFPThumb2PostEncoder";
1458 let DecoderNamespace = "VFP";
1459 list<Predicate> Predicates = [HasVFP2];
1462 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1463 string opc, string asm, list<dag> pattern>
1464 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1465 opc, asm, "", pattern> {
1466 let PostEncoderMethod = "VFPThumb2PostEncoder";
1469 // ARM VFP addrmode5 loads and stores
1470 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1471 InstrItinClass itin,
1472 string opc, string asm, list<dag> pattern>
1473 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1474 VFPLdStFrm, itin, opc, asm, "", pattern> {
1475 // Instruction operands.
1479 // Encode instruction operands.
1480 let Inst{23} = addr{8}; // U (add = (U == '1'))
1481 let Inst{22} = Dd{4};
1482 let Inst{19-16} = addr{12-9}; // Rn
1483 let Inst{15-12} = Dd{3-0};
1484 let Inst{7-0} = addr{7-0}; // imm8
1486 let Inst{27-24} = opcod1;
1487 let Inst{21-20} = opcod2;
1488 let Inst{11-9} = 0b101;
1489 let Inst{8} = 1; // Double precision
1491 // Loads & stores operate on both NEON and VFP pipelines.
1492 let D = VFPNeonDomain;
1495 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1496 InstrItinClass itin,
1497 string opc, string asm, list<dag> pattern>
1498 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1499 VFPLdStFrm, itin, opc, asm, "", pattern> {
1500 // Instruction operands.
1504 // Encode instruction operands.
1505 let Inst{23} = addr{8}; // U (add = (U == '1'))
1506 let Inst{22} = Sd{0};
1507 let Inst{19-16} = addr{12-9}; // Rn
1508 let Inst{15-12} = Sd{4-1};
1509 let Inst{7-0} = addr{7-0}; // imm8
1511 let Inst{27-24} = opcod1;
1512 let Inst{21-20} = opcod2;
1513 let Inst{11-9} = 0b101;
1514 let Inst{8} = 0; // Single precision
1516 // Loads & stores operate on both NEON and VFP pipelines.
1517 let D = VFPNeonDomain;
1520 class AHI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1521 InstrItinClass itin,
1522 string opc, string asm, list<dag> pattern>
1523 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1524 VFPLdStFrm, itin, opc, asm, "", pattern> {
1525 list<Predicate> Predicates = [HasFullFP16];
1527 // Instruction operands.
1531 // Encode instruction operands.
1532 let Inst{23} = addr{8}; // U (add = (U == '1'))
1533 let Inst{22} = Sd{0};
1534 let Inst{19-16} = addr{12-9}; // Rn
1535 let Inst{15-12} = Sd{4-1};
1536 let Inst{7-0} = addr{7-0}; // imm8
1538 let Inst{27-24} = opcod1;
1539 let Inst{21-20} = opcod2;
1540 let Inst{11-8} = 0b1001; // Half precision
1542 // Loads & stores operate on both NEON and VFP pipelines.
1543 let D = VFPNeonDomain;
1546 // VFP Load / store multiple pseudo instructions.
1547 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1549 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1551 let OutOperandList = oops;
1552 let InOperandList = !con(iops, (ins pred:$p));
1553 let Pattern = pattern;
1554 list<Predicate> Predicates = [HasVFP2];
1557 // Load / store multiple
1559 // Unknown precision
1560 class AXXI4<dag oops, dag iops, IndexMode im,
1561 string asm, string cstr, list<dag> pattern>
1562 : VFPXI<oops, iops, AddrMode4, 4, im,
1563 VFPLdStFrm, NoItinerary, asm, cstr, pattern> {
1564 // Instruction operands.
1568 // Encode instruction operands.
1569 let Inst{19-16} = Rn;
1571 let Inst{15-12} = regs{11-8};
1572 let Inst{7-1} = regs{7-1};
1574 let Inst{27-25} = 0b110;
1575 let Inst{11-8} = 0b1011;
1580 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1581 string asm, string cstr, list<dag> pattern>
1582 : VFPXI<oops, iops, AddrMode4, 4, im,
1583 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1584 // Instruction operands.
1588 // Encode instruction operands.
1589 let Inst{19-16} = Rn;
1590 let Inst{22} = regs{12};
1591 let Inst{15-12} = regs{11-8};
1592 let Inst{7-1} = regs{7-1};
1594 let Inst{27-25} = 0b110;
1595 let Inst{11-9} = 0b101;
1596 let Inst{8} = 1; // Double precision
1601 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1602 string asm, string cstr, list<dag> pattern>
1603 : VFPXI<oops, iops, AddrMode4, 4, im,
1604 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1605 // Instruction operands.
1609 // Encode instruction operands.
1610 let Inst{19-16} = Rn;
1611 let Inst{22} = regs{8};
1612 let Inst{15-12} = regs{12-9};
1613 let Inst{7-0} = regs{7-0};
1615 let Inst{27-25} = 0b110;
1616 let Inst{11-9} = 0b101;
1617 let Inst{8} = 0; // Single precision
1620 // Double precision, unary
1621 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1622 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1623 string asm, list<dag> pattern>
1624 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1625 // Instruction operands.
1629 // Encode instruction operands.
1630 let Inst{3-0} = Dm{3-0};
1631 let Inst{5} = Dm{4};
1632 let Inst{15-12} = Dd{3-0};
1633 let Inst{22} = Dd{4};
1635 let Inst{27-23} = opcod1;
1636 let Inst{21-20} = opcod2;
1637 let Inst{19-16} = opcod3;
1638 let Inst{11-9} = 0b101;
1639 let Inst{8} = 1; // Double precision
1640 let Inst{7-6} = opcod4;
1641 let Inst{4} = opcod5;
1643 let Predicates = [HasVFP2, HasDPVFP];
1646 // Double precision, unary, not-predicated
1647 class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1648 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1649 string asm, list<dag> pattern>
1650 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> {
1651 // Instruction operands.
1655 let Inst{31-28} = 0b1111;
1657 // Encode instruction operands.
1658 let Inst{3-0} = Dm{3-0};
1659 let Inst{5} = Dm{4};
1660 let Inst{15-12} = Dd{3-0};
1661 let Inst{22} = Dd{4};
1663 let Inst{27-23} = opcod1;
1664 let Inst{21-20} = opcod2;
1665 let Inst{19-16} = opcod3;
1666 let Inst{11-9} = 0b101;
1667 let Inst{8} = 1; // Double precision
1668 let Inst{7-6} = opcod4;
1669 let Inst{4} = opcod5;
1672 // Double precision, binary
1673 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1674 dag iops, InstrItinClass itin, string opc, string asm,
1676 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1677 // Instruction operands.
1682 // Encode instruction operands.
1683 let Inst{3-0} = Dm{3-0};
1684 let Inst{5} = Dm{4};
1685 let Inst{19-16} = Dn{3-0};
1686 let Inst{7} = Dn{4};
1687 let Inst{15-12} = Dd{3-0};
1688 let Inst{22} = Dd{4};
1690 let Inst{27-23} = opcod1;
1691 let Inst{21-20} = opcod2;
1692 let Inst{11-9} = 0b101;
1693 let Inst{8} = 1; // Double precision
1697 let Predicates = [HasVFP2, HasDPVFP];
1700 // FP, binary, not predicated
1701 class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1702 InstrItinClass itin, string asm, list<dag> pattern>
1703 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin,
1706 // Instruction operands.
1711 let Inst{31-28} = 0b1111;
1713 // Encode instruction operands.
1714 let Inst{3-0} = Dm{3-0};
1715 let Inst{5} = Dm{4};
1716 let Inst{19-16} = Dn{3-0};
1717 let Inst{7} = Dn{4};
1718 let Inst{15-12} = Dd{3-0};
1719 let Inst{22} = Dd{4};
1721 let Inst{27-23} = opcod1;
1722 let Inst{21-20} = opcod2;
1723 let Inst{11-9} = 0b101;
1724 let Inst{8} = 1; // double precision
1725 let Inst{6} = opcod3;
1728 let Predicates = [HasVFP2, HasDPVFP];
1731 // Single precision, unary, predicated
1732 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1733 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1734 string asm, list<dag> pattern>
1735 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1736 // Instruction operands.
1740 // Encode instruction operands.
1741 let Inst{3-0} = Sm{4-1};
1742 let Inst{5} = Sm{0};
1743 let Inst{15-12} = Sd{4-1};
1744 let Inst{22} = Sd{0};
1746 let Inst{27-23} = opcod1;
1747 let Inst{21-20} = opcod2;
1748 let Inst{19-16} = opcod3;
1749 let Inst{11-9} = 0b101;
1750 let Inst{8} = 0; // Single precision
1751 let Inst{7-6} = opcod4;
1752 let Inst{4} = opcod5;
1755 // Single precision, unary, non-predicated
1756 class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1757 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1758 string asm, list<dag> pattern>
1759 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1760 VFPUnaryFrm, itin, asm, "", pattern> {
1761 // Instruction operands.
1765 let Inst{31-28} = 0b1111;
1767 // Encode instruction operands.
1768 let Inst{3-0} = Sm{4-1};
1769 let Inst{5} = Sm{0};
1770 let Inst{15-12} = Sd{4-1};
1771 let Inst{22} = Sd{0};
1773 let Inst{27-23} = opcod1;
1774 let Inst{21-20} = opcod2;
1775 let Inst{19-16} = opcod3;
1776 let Inst{11-9} = 0b101;
1777 let Inst{8} = 0; // Single precision
1778 let Inst{7-6} = opcod4;
1779 let Inst{4} = opcod5;
1782 // Single precision unary, if no NEON. Same as ASuI except not available if
1784 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1785 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1786 string asm, list<dag> pattern>
1787 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1789 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1792 // Single precision, binary
1793 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1794 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1795 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1796 // Instruction operands.
1801 // Encode instruction operands.
1802 let Inst{3-0} = Sm{4-1};
1803 let Inst{5} = Sm{0};
1804 let Inst{19-16} = Sn{4-1};
1805 let Inst{7} = Sn{0};
1806 let Inst{15-12} = Sd{4-1};
1807 let Inst{22} = Sd{0};
1809 let Inst{27-23} = opcod1;
1810 let Inst{21-20} = opcod2;
1811 let Inst{11-9} = 0b101;
1812 let Inst{8} = 0; // Single precision
1817 // Single precision, binary, not predicated
1818 class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1819 InstrItinClass itin, string asm, list<dag> pattern>
1820 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1821 VFPBinaryFrm, itin, asm, "", pattern>
1823 // Instruction operands.
1828 let Inst{31-28} = 0b1111;
1830 // Encode instruction operands.
1831 let Inst{3-0} = Sm{4-1};
1832 let Inst{5} = Sm{0};
1833 let Inst{19-16} = Sn{4-1};
1834 let Inst{7} = Sn{0};
1835 let Inst{15-12} = Sd{4-1};
1836 let Inst{22} = Sd{0};
1838 let Inst{27-23} = opcod1;
1839 let Inst{21-20} = opcod2;
1840 let Inst{11-9} = 0b101;
1841 let Inst{8} = 0; // Single precision
1842 let Inst{6} = opcod3;
1846 // Single precision binary, if no NEON. Same as ASbI except not available if
1848 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1849 dag iops, InstrItinClass itin, string opc, string asm,
1851 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1852 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1854 // Instruction operands.
1859 // Encode instruction operands.
1860 let Inst{3-0} = Sm{4-1};
1861 let Inst{5} = Sm{0};
1862 let Inst{19-16} = Sn{4-1};
1863 let Inst{7} = Sn{0};
1864 let Inst{15-12} = Sd{4-1};
1865 let Inst{22} = Sd{0};
1868 // Half precision, unary, predicated
1869 class AHuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1870 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1871 string asm, list<dag> pattern>
1872 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1873 list<Predicate> Predicates = [HasFullFP16];
1875 // Instruction operands.
1879 // Encode instruction operands.
1880 let Inst{3-0} = Sm{4-1};
1881 let Inst{5} = Sm{0};
1882 let Inst{15-12} = Sd{4-1};
1883 let Inst{22} = Sd{0};
1885 let Inst{27-23} = opcod1;
1886 let Inst{21-20} = opcod2;
1887 let Inst{19-16} = opcod3;
1888 let Inst{11-8} = 0b1001; // Half precision
1889 let Inst{7-6} = opcod4;
1890 let Inst{4} = opcod5;
1893 // Half precision, unary, non-predicated
1894 class AHuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1895 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1896 string asm, list<dag> pattern>
1897 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1898 VFPUnaryFrm, itin, asm, "", pattern> {
1899 list<Predicate> Predicates = [HasFullFP16];
1901 // Instruction operands.
1905 let Inst{31-28} = 0b1111;
1907 // Encode instruction operands.
1908 let Inst{3-0} = Sm{4-1};
1909 let Inst{5} = Sm{0};
1910 let Inst{15-12} = Sd{4-1};
1911 let Inst{22} = Sd{0};
1913 let Inst{27-23} = opcod1;
1914 let Inst{21-20} = opcod2;
1915 let Inst{19-16} = opcod3;
1916 let Inst{11-8} = 0b1001; // Half precision
1917 let Inst{7-6} = opcod4;
1918 let Inst{4} = opcod5;
1921 // Half precision, binary
1922 class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1923 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1924 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1925 list<Predicate> Predicates = [HasFullFP16];
1927 // Instruction operands.
1932 // Encode instruction operands.
1933 let Inst{3-0} = Sm{4-1};
1934 let Inst{5} = Sm{0};
1935 let Inst{19-16} = Sn{4-1};
1936 let Inst{7} = Sn{0};
1937 let Inst{15-12} = Sd{4-1};
1938 let Inst{22} = Sd{0};
1940 let Inst{27-23} = opcod1;
1941 let Inst{21-20} = opcod2;
1942 let Inst{11-8} = 0b1001; // Half precision
1947 // Half precision, binary, not predicated
1948 class AHbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1949 InstrItinClass itin, string asm, list<dag> pattern>
1950 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1951 VFPBinaryFrm, itin, asm, "", pattern> {
1952 list<Predicate> Predicates = [HasFullFP16];
1954 // Instruction operands.
1959 let Inst{31-28} = 0b1111;
1961 // Encode instruction operands.
1962 let Inst{3-0} = Sm{4-1};
1963 let Inst{5} = Sm{0};
1964 let Inst{19-16} = Sn{4-1};
1965 let Inst{7} = Sn{0};
1966 let Inst{15-12} = Sd{4-1};
1967 let Inst{22} = Sd{0};
1969 let Inst{27-23} = opcod1;
1970 let Inst{21-20} = opcod2;
1971 let Inst{11-8} = 0b1001; // Half precision
1972 let Inst{6} = opcod3;
1976 // VFP conversion instructions
1977 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1978 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1980 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1981 let Inst{27-23} = opcod1;
1982 let Inst{21-20} = opcod2;
1983 let Inst{19-16} = opcod3;
1984 let Inst{11-8} = opcod4;
1989 // VFP conversion between floating-point and fixed-point
1990 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1991 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1993 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1995 // size (fixed-point number): sx == 0 ? 16 : 32
1996 let Inst{7} = op5; // sx
1997 let Inst{5} = fbits{0};
1998 let Inst{3-0} = fbits{4-1};
2001 // VFP conversion instructions, if no NEON
2002 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
2003 dag oops, dag iops, InstrItinClass itin,
2004 string opc, string asm, list<dag> pattern>
2005 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
2007 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
2010 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
2011 InstrItinClass itin,
2012 string opc, string asm, list<dag> pattern>
2013 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
2014 let Inst{27-20} = opcod1;
2015 let Inst{11-8} = opcod2;
2019 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2020 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2021 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
2023 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2024 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2025 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
2027 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2028 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2029 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
2031 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2032 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2033 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
2035 //===----------------------------------------------------------------------===//
2037 //===----------------------------------------------------------------------===//
2038 // ARM NEON Instruction templates.
2041 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2042 InstrItinClass itin, string opc, string dt, string asm, string cstr,
2044 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2045 let OutOperandList = oops;
2046 let InOperandList = !con(iops, (ins pred:$p));
2047 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
2048 let Pattern = pattern;
2049 list<Predicate> Predicates = [HasNEON];
2050 let DecoderNamespace = "NEON";
2053 // Same as NeonI except it does not have a "data type" specifier.
2054 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2055 InstrItinClass itin, string opc, string asm, string cstr,
2057 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2058 let OutOperandList = oops;
2059 let InOperandList = !con(iops, (ins pred:$p));
2060 let AsmString = !strconcat(opc, "${p}", "\t", asm);
2061 let Pattern = pattern;
2062 list<Predicate> Predicates = [HasNEON];
2063 let DecoderNamespace = "NEON";
2066 // Same as NeonI except it is not predicated
2067 class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2068 InstrItinClass itin, string opc, string dt, string asm, string cstr,
2070 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2071 let OutOperandList = oops;
2072 let InOperandList = iops;
2073 let AsmString = !strconcat(opc, ".", dt, "\t", asm);
2074 let Pattern = pattern;
2075 list<Predicate> Predicates = [HasNEON];
2076 let DecoderNamespace = "NEON";
2078 let Inst{31-28} = 0b1111;
2081 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
2082 dag oops, dag iops, InstrItinClass itin,
2083 string opc, string dt, string asm, string cstr, list<dag> pattern>
2084 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
2086 let Inst{31-24} = 0b11110100;
2087 let Inst{23} = op23;
2088 let Inst{21-20} = op21_20;
2089 let Inst{11-8} = op11_8;
2090 let Inst{7-4} = op7_4;
2092 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
2093 let DecoderNamespace = "NEONLoadStore";
2099 let Inst{22} = Vd{4};
2100 let Inst{15-12} = Vd{3-0};
2101 let Inst{19-16} = Rn{3-0};
2102 let Inst{3-0} = Rm{3-0};
2105 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
2106 dag oops, dag iops, InstrItinClass itin,
2107 string opc, string dt, string asm, string cstr, list<dag> pattern>
2108 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
2109 dt, asm, cstr, pattern> {
2113 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
2114 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
2116 let OutOperandList = oops;
2117 let InOperandList = !con(iops, (ins pred:$p));
2118 list<Predicate> Predicates = [HasNEON];
2121 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
2123 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
2125 let OutOperandList = oops;
2126 let InOperandList = !con(iops, (ins pred:$p));
2127 let Pattern = pattern;
2128 list<Predicate> Predicates = [HasNEON];
2131 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
2132 string opc, string dt, string asm, string cstr, list<dag> pattern>
2133 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
2135 let Inst{31-25} = 0b1111001;
2136 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
2137 let DecoderNamespace = "NEONData";
2140 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
2141 string opc, string asm, string cstr, list<dag> pattern>
2142 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
2144 let Inst{31-25} = 0b1111001;
2145 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
2146 let DecoderNamespace = "NEONData";
2149 // NEON "one register and a modified immediate" format.
2150 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
2152 dag oops, dag iops, InstrItinClass itin,
2153 string opc, string dt, string asm, string cstr,
2155 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
2156 let Inst{23} = op23;
2157 let Inst{21-19} = op21_19;
2158 let Inst{11-8} = op11_8;
2164 // Instruction operands.
2168 let Inst{15-12} = Vd{3-0};
2169 let Inst{22} = Vd{4};
2170 let Inst{24} = SIMM{7};
2171 let Inst{18-16} = SIMM{6-4};
2172 let Inst{3-0} = SIMM{3-0};
2173 let DecoderMethod = "DecodeNEONModImmInstruction";
2176 // NEON 2 vector register format.
2177 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2178 bits<5> op11_7, bit op6, bit op4,
2179 dag oops, dag iops, InstrItinClass itin,
2180 string opc, string dt, string asm, string cstr, list<dag> pattern>
2181 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
2182 let Inst{24-23} = op24_23;
2183 let Inst{21-20} = op21_20;
2184 let Inst{19-18} = op19_18;
2185 let Inst{17-16} = op17_16;
2186 let Inst{11-7} = op11_7;
2190 // Instruction operands.
2194 let Inst{15-12} = Vd{3-0};
2195 let Inst{22} = Vd{4};
2196 let Inst{3-0} = Vm{3-0};
2197 let Inst{5} = Vm{4};
2200 // Same as N2V but not predicated.
2201 class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
2202 dag oops, dag iops, InstrItinClass itin, string OpcodeStr,
2203 string Dt, list<dag> pattern>
2204 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin,
2205 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
2209 // Encode instruction operands
2210 let Inst{22} = Vd{4};
2211 let Inst{15-12} = Vd{3-0};
2212 let Inst{5} = Vm{4};
2213 let Inst{3-0} = Vm{3-0};
2215 // Encode constant bits
2216 let Inst{27-23} = 0b00111;
2217 let Inst{21-20} = 0b11;
2218 let Inst{19-18} = op19_18;
2219 let Inst{17-16} = op17_16;
2221 let Inst{10-8} = op10_8;
2226 let DecoderNamespace = "NEON";
2229 // Same as N2V except it doesn't have a datatype suffix.
2230 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2231 bits<5> op11_7, bit op6, bit op4,
2232 dag oops, dag iops, InstrItinClass itin,
2233 string opc, string asm, string cstr, list<dag> pattern>
2234 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
2235 let Inst{24-23} = op24_23;
2236 let Inst{21-20} = op21_20;
2237 let Inst{19-18} = op19_18;
2238 let Inst{17-16} = op17_16;
2239 let Inst{11-7} = op11_7;
2243 // Instruction operands.
2247 let Inst{15-12} = Vd{3-0};
2248 let Inst{22} = Vd{4};
2249 let Inst{3-0} = Vm{3-0};
2250 let Inst{5} = Vm{4};
2253 // NEON 2 vector register with immediate.
2254 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2255 dag oops, dag iops, Format f, InstrItinClass itin,
2256 string opc, string dt, string asm, string cstr, list<dag> pattern>
2257 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2258 let Inst{24} = op24;
2259 let Inst{23} = op23;
2260 let Inst{11-8} = op11_8;
2265 // Instruction operands.
2270 let Inst{15-12} = Vd{3-0};
2271 let Inst{22} = Vd{4};
2272 let Inst{3-0} = Vm{3-0};
2273 let Inst{5} = Vm{4};
2274 let Inst{21-16} = SIMM{5-0};
2277 // NEON 3 vector register format.
2279 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2280 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2281 string opc, string dt, string asm, string cstr,
2283 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2284 let Inst{24} = op24;
2285 let Inst{23} = op23;
2286 let Inst{21-20} = op21_20;
2287 let Inst{11-8} = op11_8;
2292 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
2293 dag oops, dag iops, Format f, InstrItinClass itin,
2294 string opc, string dt, string asm, string cstr, list<dag> pattern>
2295 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2296 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2297 // Instruction operands.
2302 let Inst{15-12} = Vd{3-0};
2303 let Inst{22} = Vd{4};
2304 let Inst{19-16} = Vn{3-0};
2305 let Inst{7} = Vn{4};
2306 let Inst{3-0} = Vm{3-0};
2307 let Inst{5} = Vm{4};
2310 class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2311 bit op4, dag oops, dag iops,Format f, InstrItinClass itin,
2312 string OpcodeStr, string Dt, list<dag> pattern>
2313 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr,
2314 Dt, "$Vd, $Vn, $Vm", "", pattern> {
2319 // Encode instruction operands
2320 let Inst{22} = Vd{4};
2321 let Inst{15-12} = Vd{3-0};
2322 let Inst{19-16} = Vn{3-0};
2323 let Inst{7} = Vn{4};
2324 let Inst{5} = Vm{4};
2325 let Inst{3-0} = Vm{3-0};
2327 // Encode constant bits
2328 let Inst{27-23} = op27_23;
2329 let Inst{21-20} = op21_20;
2330 let Inst{11-8} = op11_8;
2335 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2336 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2337 string opc, string dt, string asm, string cstr,
2339 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2340 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2342 // Instruction operands.
2348 let Inst{15-12} = Vd{3-0};
2349 let Inst{22} = Vd{4};
2350 let Inst{19-16} = Vn{3-0};
2351 let Inst{7} = Vn{4};
2352 let Inst{3-0} = Vm{3-0};
2356 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2357 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2358 string opc, string dt, string asm, string cstr,
2360 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2361 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2363 // Instruction operands.
2369 let Inst{15-12} = Vd{3-0};
2370 let Inst{22} = Vd{4};
2371 let Inst{19-16} = Vn{3-0};
2372 let Inst{7} = Vn{4};
2373 let Inst{2-0} = Vm{2-0};
2374 let Inst{5} = lane{1};
2375 let Inst{3} = lane{0};
2378 // Same as N3V except it doesn't have a data type suffix.
2379 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2381 dag oops, dag iops, Format f, InstrItinClass itin,
2382 string opc, string asm, string cstr, list<dag> pattern>
2383 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
2384 let Inst{24} = op24;
2385 let Inst{23} = op23;
2386 let Inst{21-20} = op21_20;
2387 let Inst{11-8} = op11_8;
2391 // Instruction operands.
2396 let Inst{15-12} = Vd{3-0};
2397 let Inst{22} = Vd{4};
2398 let Inst{19-16} = Vn{3-0};
2399 let Inst{7} = Vn{4};
2400 let Inst{3-0} = Vm{3-0};
2401 let Inst{5} = Vm{4};
2404 // NEON VMOVs between scalar and core registers.
2405 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2406 dag oops, dag iops, Format f, InstrItinClass itin,
2407 string opc, string dt, string asm, list<dag> pattern>
2408 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
2410 let Inst{27-20} = opcod1;
2411 let Inst{11-8} = opcod2;
2412 let Inst{6-5} = opcod3;
2414 // A8.6.303, A8.6.328, A8.6.329
2415 let Inst{3-0} = 0b0000;
2417 let OutOperandList = oops;
2418 let InOperandList = !con(iops, (ins pred:$p));
2419 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
2420 let Pattern = pattern;
2421 list<Predicate> Predicates = [HasNEON];
2423 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
2424 let DecoderNamespace = "NEONDup";
2431 let Inst{31-28} = p{3-0};
2433 let Inst{19-16} = V{3-0};
2434 let Inst{15-12} = R{3-0};
2436 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2437 dag oops, dag iops, InstrItinClass itin,
2438 string opc, string dt, string asm, list<dag> pattern>
2439 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
2440 opc, dt, asm, pattern>;
2441 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2442 dag oops, dag iops, InstrItinClass itin,
2443 string opc, string dt, string asm, list<dag> pattern>
2444 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
2445 opc, dt, asm, pattern>;
2446 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2447 dag oops, dag iops, InstrItinClass itin,
2448 string opc, string dt, string asm, list<dag> pattern>
2449 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
2450 opc, dt, asm, pattern>;
2452 // Vector Duplicate Lane (from scalar to all elements)
2453 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2454 InstrItinClass itin, string opc, string dt, string asm,
2456 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2457 let Inst{24-23} = 0b11;
2458 let Inst{21-20} = 0b11;
2459 let Inst{19-16} = op19_16;
2460 let Inst{11-7} = 0b11000;
2467 let Inst{22} = Vd{4};
2468 let Inst{15-12} = Vd{3-0};
2469 let Inst{5} = Vm{4};
2470 let Inst{3-0} = Vm{3-0};
2473 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2474 // for single-precision FP.
2475 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2476 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2479 // VFP/NEON Instruction aliases for type suffices.
2480 // Note: When EmitPriority == 1, the alias will be used for printing
2481 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> :
2482 InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>;
2484 // Note: When EmitPriority == 1, the alias will be used for printing
2485 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
2486 def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>;
2487 def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>;
2488 def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>;
2489 def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>;
2492 // Note: When EmitPriority == 1, the alias will be used for printing
2493 multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
2494 let Predicates = [HasNEON] in {
2495 def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>;
2496 def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>;
2497 def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>;
2498 def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>;
2502 // The same alias classes using AsmPseudo instead, for the more complex
2503 // stuff in NEON that InstAlias can't quite handle.
2504 // Note that we can't use anonymous defm references here like we can
2505 // above, as we care about the ultimate instruction enum names generated, unlike
2506 // for instalias defs.
2507 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2508 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2510 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2511 def : TokenAlias<".s8", ".i8">;
2512 def : TokenAlias<".u8", ".i8">;
2513 def : TokenAlias<".s16", ".i16">;
2514 def : TokenAlias<".u16", ".i16">;
2515 def : TokenAlias<".s32", ".i32">;
2516 def : TokenAlias<".u32", ".i32">;
2517 def : TokenAlias<".s64", ".i64">;
2518 def : TokenAlias<".u64", ".i64">;
2520 def : TokenAlias<".i8", ".8">;
2521 def : TokenAlias<".i16", ".16">;
2522 def : TokenAlias<".i32", ".32">;
2523 def : TokenAlias<".i64", ".64">;
2525 def : TokenAlias<".p8", ".8">;
2526 def : TokenAlias<".p16", ".16">;
2528 def : TokenAlias<".f32", ".32">;
2529 def : TokenAlias<".f64", ".64">;
2530 def : TokenAlias<".f", ".f32">;
2531 def : TokenAlias<".d", ".f64">;