1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
21 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
23 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
24 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
26 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
28 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
30 def SDT_ARMCMov : SDTypeProfile<1, 3,
31 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
34 def SDT_ARMBrcond : SDTypeProfile<0, 2,
35 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
37 def SDT_ARMBrJT : SDTypeProfile<0, 2,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
40 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>,
58 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
59 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
61 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
62 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
64 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
65 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
67 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
69 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
72 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
75 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
77 def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
79 def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
80 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
83 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
86 SDTCisInt<0>, SDTCisVT<1, i32>]>;
88 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
89 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
96 def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>,
101 SDTCisSameAs<0, 5>]>;
103 def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>;
104 def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>;
105 def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>;
106 def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>;
109 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
110 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
111 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
113 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
114 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
115 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
116 [SDNPHasChain, SDNPSideEffect,
117 SDNPOptInGlue, SDNPOutGlue]>;
118 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
120 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
121 SDNPMayStore, SDNPMayLoad]>;
123 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
126 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
129 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
133 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
134 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
135 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
137 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
140 def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;
142 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
143 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
145 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
147 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
150 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
153 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
156 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
159 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
160 [SDNPOutGlue, SDNPCommutative]>;
162 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
164 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
165 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
166 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
168 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
170 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
171 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
172 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
174 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
175 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
176 SDT_ARMEH_SJLJ_Setjmp,
177 [SDNPHasChain, SDNPSideEffect]>;
178 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
179 SDT_ARMEH_SJLJ_Longjmp,
180 [SDNPHasChain, SDNPSideEffect]>;
181 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
182 SDT_ARMEH_SJLJ_SetupDispatch,
183 [SDNPHasChain, SDNPSideEffect]>;
185 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
186 [SDNPHasChain, SDNPSideEffect]>;
187 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
190 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
191 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
193 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
195 def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY,
196 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
197 SDNPMayStore, SDNPMayLoad]>;
199 def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>;
200 def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>;
201 def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>;
202 def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>;
203 def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>;
204 def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>;
206 //===----------------------------------------------------------------------===//
207 // ARM Instruction Predicate Definitions.
209 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
210 AssemblerPredicate<"HasV4TOps", "armv4t">;
211 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
212 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
213 AssemblerPredicate<"HasV5TOps", "armv5t">;
214 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
215 AssemblerPredicate<"HasV5TEOps", "armv5te">;
216 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
217 AssemblerPredicate<"HasV6Ops", "armv6">;
218 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
219 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
220 AssemblerPredicate<"HasV6MOps",
221 "armv6m or armv6t2">;
222 def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
223 AssemblerPredicate<"HasV8MBaselineOps",
225 def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">,
226 AssemblerPredicate<"HasV8MMainlineOps",
228 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
229 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
230 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
231 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
232 AssemblerPredicate<"HasV6KOps", "armv6k">;
233 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
234 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
235 AssemblerPredicate<"HasV7Ops", "armv7">;
236 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
237 AssemblerPredicate<"HasV8Ops", "armv8">;
238 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
239 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
240 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
241 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
242 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
243 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
244 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
245 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
246 AssemblerPredicate<"FeatureVFP2", "VFP2">;
247 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
248 AssemblerPredicate<"FeatureVFP3", "VFP3">;
249 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
250 AssemblerPredicate<"FeatureVFP4", "VFP4">;
251 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
252 AssemblerPredicate<"!FeatureVFPOnlySP",
253 "double precision VFP">;
254 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
255 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
256 def HasNEON : Predicate<"Subtarget->hasNEON()">,
257 AssemblerPredicate<"FeatureNEON", "NEON">;
258 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
259 AssemblerPredicate<"FeatureCrypto", "crypto">;
260 def HasCRC : Predicate<"Subtarget->hasCRC()">,
261 AssemblerPredicate<"FeatureCRC", "crc">;
262 def HasRAS : Predicate<"Subtarget->hasRAS()">,
263 AssemblerPredicate<"FeatureRAS", "ras">;
264 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
265 AssemblerPredicate<"FeatureFP16","half-float conversions">;
266 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
267 AssemblerPredicate<"FeatureFullFP16","full half-float">;
268 def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">,
269 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">;
270 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
271 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
272 def HasDSP : Predicate<"Subtarget->hasDSP()">,
273 AssemblerPredicate<"FeatureDSP", "dsp">;
274 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
275 AssemblerPredicate<"FeatureDB",
277 def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">,
278 AssemblerPredicate<"FeatureV7Clrex",
280 def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">,
281 AssemblerPredicate<"FeatureAcquireRelease",
283 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
284 AssemblerPredicate<"FeatureMP",
286 def HasVirtualization: Predicate<"false">,
287 AssemblerPredicate<"FeatureVirtualization",
288 "virtualization-extensions">;
289 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
290 AssemblerPredicate<"FeatureTrustZone",
292 def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">,
293 AssemblerPredicate<"Feature8MSecExt",
294 "ARMv8-M Security Extensions">;
295 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
296 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
297 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
298 def IsThumb : Predicate<"Subtarget->isThumb()">,
299 AssemblerPredicate<"ModeThumb", "thumb">;
300 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
301 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
302 AssemblerPredicate<"ModeThumb,FeatureThumb2",
304 def IsMClass : Predicate<"Subtarget->isMClass()">,
305 AssemblerPredicate<"FeatureMClass", "armv*m">;
306 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
307 AssemblerPredicate<"!FeatureMClass",
309 def IsARM : Predicate<"!Subtarget->isThumb()">,
310 AssemblerPredicate<"!ModeThumb", "arm-mode">;
311 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
312 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
313 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
314 def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
315 def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">;
316 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
317 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
318 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
320 def UseNegativeImmediates :
322 AssemblerPredicate<"!FeatureNoNegativeImmediates",
323 "NegativeImmediates">;
325 // FIXME: Eventually this will be just "hasV6T2Ops".
326 let RecomputePerFunction = 1 in {
327 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
328 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
330 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
331 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
333 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
334 // But only select them if more precision in FP computation is allowed.
335 // Do not use them for Darwin platforms.
336 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
337 " FPOpFusion::Fast && "
338 " Subtarget->hasVFP4()) && "
339 "!Subtarget->isTargetDarwin()">;
340 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
341 " FPOpFusion::Fast &&"
342 " Subtarget->hasVFP4()) || "
343 "Subtarget->isTargetDarwin()">;
345 def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">;
346 def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">;
348 def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">;
349 def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">;
351 def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||"
352 "!Subtarget->useNEONForSinglePrecisionFP()">;
353 def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"
354 "Subtarget->useNEONForSinglePrecisionFP()">;
356 let RecomputePerFunction = 1 in {
357 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
358 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
361 def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
363 //===----------------------------------------------------------------------===//
364 // ARM Flag Definitions.
366 class RegConstraint<string C> {
367 string Constraints = C;
370 //===----------------------------------------------------------------------===//
371 // ARM specific transformation functions and pattern fragments.
374 // imm_neg_XFORM - Return the negation of an i32 immediate value.
375 def imm_neg_XFORM : SDNodeXForm<imm, [{
376 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
379 // imm_not_XFORM - Return the complement of a i32 immediate value.
380 def imm_not_XFORM : SDNodeXForm<imm, [{
381 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
384 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
385 def imm16_31 : ImmLeaf<i32, [{
386 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
389 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
390 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
391 if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17)
394 if (N->getOpcode() != ISD::SRA)
396 if (N->getOperand(0).getOpcode() != ISD::SHL)
399 auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1));
400 if (!ShiftVal || ShiftVal->getZExtValue() != 16)
403 ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1));
404 if (!ShiftVal || ShiftVal->getZExtValue() != 16)
410 /// Split a 32-bit immediate into two 16 bit parts.
411 def hi16 : SDNodeXForm<imm, [{
412 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
416 def lo16AllZero : PatLeaf<(i32 imm), [{
417 // Returns true if all low 16-bits are 0.
418 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
421 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
422 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
424 // An 'and' node with a single use.
425 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
426 return N->hasOneUse();
429 // An 'xor' node with a single use.
430 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
431 return N->hasOneUse();
434 // An 'fmul' node with a single use.
435 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
436 return N->hasOneUse();
439 // An 'fadd' node which checks for single non-hazardous use.
440 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
441 return hasNoVMLxHazardUse(N);
444 // An 'fsub' node which checks for single non-hazardous use.
445 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
446 return hasNoVMLxHazardUse(N);
449 //===----------------------------------------------------------------------===//
450 // Operand Definitions.
453 // Immediate operands with a shared generic asm render method.
454 class ImmAsmOperand<int Low, int High> : AsmOperandClass {
455 let RenderMethod = "addImmOperands";
456 let PredicateMethod = "isImmediate<" # Low # "," # High # ">";
457 let DiagnosticType = "ImmRange" # Low # "_" # High;
460 class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass {
461 let PredicateMethod = "isImmediate<" # Low # "," # High # ">";
462 let DiagnosticType = "ImmRange" # Low # "_" # High;
465 // Operands that are part of a memory addressing mode.
466 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
469 // FIXME: rename brtarget to t2_brtarget
470 def brtarget : Operand<OtherVT> {
471 let EncoderMethod = "getBranchTargetOpValue";
472 let OperandType = "OPERAND_PCREL";
473 let DecoderMethod = "DecodeT2BROperand";
476 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
478 def ARMBranchTarget : AsmOperandClass {
479 let Name = "ARMBranchTarget";
482 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
484 def ThumbBranchTarget : AsmOperandClass {
485 let Name = "ThumbBranchTarget";
488 def arm_br_target : Operand<OtherVT> {
489 let ParserMatchClass = ARMBranchTarget;
490 let EncoderMethod = "getARMBranchTargetOpValue";
491 let OperandType = "OPERAND_PCREL";
494 // Call target for ARM. Handles conditional/unconditional
495 // FIXME: rename bl_target to t2_bltarget?
496 def arm_bl_target : Operand<i32> {
497 let ParserMatchClass = ARMBranchTarget;
498 let EncoderMethod = "getARMBLTargetOpValue";
499 let OperandType = "OPERAND_PCREL";
502 // Target for BLX *from* ARM mode.
503 def arm_blx_target : Operand<i32> {
504 let ParserMatchClass = ThumbBranchTarget;
505 let EncoderMethod = "getARMBLXTargetOpValue";
506 let OperandType = "OPERAND_PCREL";
509 // A list of registers separated by comma. Used by load/store multiple.
510 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
511 def reglist : Operand<i32> {
512 let EncoderMethod = "getRegisterListOpValue";
513 let ParserMatchClass = RegListAsmOperand;
514 let PrintMethod = "printRegisterList";
515 let DecoderMethod = "DecodeRegListOperand";
518 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
520 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
521 def dpr_reglist : Operand<i32> {
522 let EncoderMethod = "getRegisterListOpValue";
523 let ParserMatchClass = DPRRegListAsmOperand;
524 let PrintMethod = "printRegisterList";
525 let DecoderMethod = "DecodeDPRRegListOperand";
528 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
529 def spr_reglist : Operand<i32> {
530 let EncoderMethod = "getRegisterListOpValue";
531 let ParserMatchClass = SPRRegListAsmOperand;
532 let PrintMethod = "printRegisterList";
533 let DecoderMethod = "DecodeSPRRegListOperand";
536 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
537 def cpinst_operand : Operand<i32> {
538 let PrintMethod = "printCPInstOperand";
542 def pclabel : Operand<i32> {
543 let PrintMethod = "printPCLabel";
546 // ADR instruction labels.
547 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
548 def adrlabel : Operand<i32> {
549 let EncoderMethod = "getAdrLabelOpValue";
550 let ParserMatchClass = AdrLabelAsmOperand;
551 let PrintMethod = "printAdrLabelOperand<0>";
554 def neon_vcvt_imm32 : Operand<i32> {
555 let EncoderMethod = "getNEONVcvtImm32OpValue";
556 let DecoderMethod = "DecodeVCVTImmOperand";
559 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
560 def rot_imm_XFORM: SDNodeXForm<imm, [{
561 switch (N->getZExtValue()){
562 default: llvm_unreachable(nullptr);
563 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
564 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
565 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
566 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
569 def RotImmAsmOperand : AsmOperandClass {
571 let ParserMethod = "parseRotImm";
573 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
574 int32_t v = N->getZExtValue();
575 return v == 8 || v == 16 || v == 24; }],
577 let PrintMethod = "printRotImmOperand";
578 let ParserMatchClass = RotImmAsmOperand;
581 // shift_imm: An integer that encodes a shift amount and the type of shift
582 // (asr or lsl). The 6-bit immediate encodes as:
585 // {4-0} imm5 shift amount.
586 // asr #32 encoded as imm5 == 0.
587 def ShifterImmAsmOperand : AsmOperandClass {
588 let Name = "ShifterImm";
589 let ParserMethod = "parseShifterImm";
591 def shift_imm : Operand<i32> {
592 let PrintMethod = "printShiftImmOperand";
593 let ParserMatchClass = ShifterImmAsmOperand;
596 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
597 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
598 def so_reg_reg : Operand<i32>, // reg reg imm
599 ComplexPattern<i32, 3, "SelectRegShifterOperand",
600 [shl, srl, sra, rotr]> {
601 let EncoderMethod = "getSORegRegOpValue";
602 let PrintMethod = "printSORegRegOperand";
603 let DecoderMethod = "DecodeSORegRegOperand";
604 let ParserMatchClass = ShiftedRegAsmOperand;
605 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
608 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
609 def so_reg_imm : Operand<i32>, // reg imm
610 ComplexPattern<i32, 2, "SelectImmShifterOperand",
611 [shl, srl, sra, rotr]> {
612 let EncoderMethod = "getSORegImmOpValue";
613 let PrintMethod = "printSORegImmOperand";
614 let DecoderMethod = "DecodeSORegImmOperand";
615 let ParserMatchClass = ShiftedImmAsmOperand;
616 let MIOperandInfo = (ops GPR, i32imm);
619 // FIXME: Does this need to be distinct from so_reg?
620 def shift_so_reg_reg : Operand<i32>, // reg reg imm
621 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
622 [shl,srl,sra,rotr]> {
623 let EncoderMethod = "getSORegRegOpValue";
624 let PrintMethod = "printSORegRegOperand";
625 let DecoderMethod = "DecodeSORegRegOperand";
626 let ParserMatchClass = ShiftedRegAsmOperand;
627 let MIOperandInfo = (ops GPR, GPR, i32imm);
630 // FIXME: Does this need to be distinct from so_reg?
631 def shift_so_reg_imm : Operand<i32>, // reg reg imm
632 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
633 [shl,srl,sra,rotr]> {
634 let EncoderMethod = "getSORegImmOpValue";
635 let PrintMethod = "printSORegImmOperand";
636 let DecoderMethod = "DecodeSORegImmOperand";
637 let ParserMatchClass = ShiftedImmAsmOperand;
638 let MIOperandInfo = (ops GPR, i32imm);
641 // mod_imm: match a 32-bit immediate operand, which can be encoded into
642 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
643 // - "Modified Immediate Constants"). Within the MC layer we keep this
644 // immediate in its encoded form.
645 def ModImmAsmOperand: AsmOperandClass {
647 let ParserMethod = "parseModImm";
649 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
650 return ARM_AM::getSOImmVal(Imm) != -1;
652 let EncoderMethod = "getModImmOpValue";
653 let PrintMethod = "printModImmOperand";
654 let ParserMatchClass = ModImmAsmOperand;
657 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
658 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
659 // The actual parsing, encoding, decoding are handled by the destination
660 // instructions, which use mod_imm.
662 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
663 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
664 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
666 let ParserMatchClass = ModImmNotAsmOperand;
669 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
670 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
671 unsigned Value = -(unsigned)N->getZExtValue();
672 return Value && ARM_AM::getSOImmVal(Value) != -1;
674 let ParserMatchClass = ModImmNegAsmOperand;
677 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
678 def arm_i32imm : PatLeaf<(imm), [{
679 if (Subtarget->useMovt(*MF))
681 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
684 /// imm0_1 predicate - Immediate in the range [0,1].
685 def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; }
686 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
688 /// imm0_3 predicate - Immediate in the range [0,3].
689 def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; }
690 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
692 /// imm0_7 predicate - Immediate in the range [0,7].
693 def Imm0_7AsmOperand: ImmAsmOperand<0,7> {
696 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
697 return Imm >= 0 && Imm < 8;
699 let ParserMatchClass = Imm0_7AsmOperand;
702 /// imm8_255 predicate - Immediate in the range [8,255].
703 def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; }
704 def imm8_255 : Operand<i32>, ImmLeaf<i32, [{
705 return Imm >= 8 && Imm < 256;
707 let ParserMatchClass = Imm8_255AsmOperand;
710 /// imm8 predicate - Immediate is exactly 8.
711 def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; }
712 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
713 let ParserMatchClass = Imm8AsmOperand;
716 /// imm16 predicate - Immediate is exactly 16.
717 def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; }
718 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
719 let ParserMatchClass = Imm16AsmOperand;
722 /// imm32 predicate - Immediate is exactly 32.
723 def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; }
724 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
725 let ParserMatchClass = Imm32AsmOperand;
728 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
730 /// imm1_7 predicate - Immediate in the range [1,7].
731 def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; }
732 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
733 let ParserMatchClass = Imm1_7AsmOperand;
736 /// imm1_15 predicate - Immediate in the range [1,15].
737 def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; }
738 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
739 let ParserMatchClass = Imm1_15AsmOperand;
742 /// imm1_31 predicate - Immediate in the range [1,31].
743 def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; }
744 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
745 let ParserMatchClass = Imm1_31AsmOperand;
748 /// imm0_15 predicate - Immediate in the range [0,15].
749 def Imm0_15AsmOperand: ImmAsmOperand<0,15> {
750 let Name = "Imm0_15";
751 let DiagnosticType = "ImmRange0_15";
753 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
754 return Imm >= 0 && Imm < 16;
756 let ParserMatchClass = Imm0_15AsmOperand;
759 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
760 def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; }
761 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
762 return Imm >= 0 && Imm < 32;
764 let ParserMatchClass = Imm0_31AsmOperand;
767 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
768 def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; }
769 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
770 return Imm >= 0 && Imm < 33;
772 let ParserMatchClass = Imm0_32AsmOperand;
775 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
776 def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; }
777 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
778 return Imm >= 0 && Imm < 64;
780 let ParserMatchClass = Imm0_63AsmOperand;
783 /// imm0_239 predicate - Immediate in the range [0,239].
784 def Imm0_239AsmOperand : ImmAsmOperand<0,239> {
785 let Name = "Imm0_239";
786 let DiagnosticType = "ImmRange0_239";
788 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
789 let ParserMatchClass = Imm0_239AsmOperand;
792 /// imm0_255 predicate - Immediate in the range [0,255].
793 def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; }
794 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
795 let ParserMatchClass = Imm0_255AsmOperand;
798 /// imm0_65535 - An immediate is in the range [0,65535].
799 def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; }
800 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
801 return Imm >= 0 && Imm < 65536;
803 let ParserMatchClass = Imm0_65535AsmOperand;
806 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
807 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
808 return -Imm >= 0 && -Imm < 65536;
811 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
812 // a relocatable expression.
814 // FIXME: This really needs a Thumb version separate from the ARM version.
815 // While the range is the same, and can thus use the same match class,
816 // the encoding is different so it should have a different encoder method.
817 def Imm0_65535ExprAsmOperand: AsmOperandClass {
818 let Name = "Imm0_65535Expr";
819 let RenderMethod = "addImmOperands";
822 def imm0_65535_expr : Operand<i32> {
823 let EncoderMethod = "getHiLo16ImmOpValue";
824 let ParserMatchClass = Imm0_65535ExprAsmOperand;
827 def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; }
828 def imm256_65535_expr : Operand<i32> {
829 let ParserMatchClass = Imm256_65535ExprAsmOperand;
832 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
833 def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { let Name = "Imm24bit"; }
834 def imm24b : Operand<i32>, ImmLeaf<i32, [{
835 return Imm >= 0 && Imm <= 0xffffff;
837 let ParserMatchClass = Imm24bitAsmOperand;
841 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
843 def BitfieldAsmOperand : AsmOperandClass {
844 let Name = "Bitfield";
845 let ParserMethod = "parseBitfield";
848 def bf_inv_mask_imm : Operand<i32>,
850 return ARM::isBitFieldInvertedMask(N->getZExtValue());
852 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
853 let PrintMethod = "printBitfieldInvMaskImmOperand";
854 let DecoderMethod = "DecodeBitfieldMaskOperand";
855 let ParserMatchClass = BitfieldAsmOperand;
858 def imm1_32_XFORM: SDNodeXForm<imm, [{
859 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
862 def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> {
863 let Name = "Imm1_32";
865 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
866 uint64_t Imm = N->getZExtValue();
867 return Imm > 0 && Imm <= 32;
870 let PrintMethod = "printImmPlusOneOperand";
871 let ParserMatchClass = Imm1_32AsmOperand;
874 def imm1_16_XFORM: SDNodeXForm<imm, [{
875 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
878 def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; }
879 def imm1_16 : Operand<i32>, ImmLeaf<i32, [{
880 return Imm > 0 && Imm <= 16;
883 let PrintMethod = "printImmPlusOneOperand";
884 let ParserMatchClass = Imm1_16AsmOperand;
887 // Define ARM specific addressing modes.
888 // addrmode_imm12 := reg +/- imm12
890 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
891 class AddrMode_Imm12 : MemOperand,
892 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
893 // 12-bit immediate operand. Note that instructions using this encode
894 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
895 // immediate values are as normal.
897 let EncoderMethod = "getAddrModeImm12OpValue";
898 let DecoderMethod = "DecodeAddrModeImm12Operand";
899 let ParserMatchClass = MemImm12OffsetAsmOperand;
900 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
903 def addrmode_imm12 : AddrMode_Imm12 {
904 let PrintMethod = "printAddrModeImm12Operand<false>";
907 def addrmode_imm12_pre : AddrMode_Imm12 {
908 let PrintMethod = "printAddrModeImm12Operand<true>";
911 // ldst_so_reg := reg +/- reg shop imm
913 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
914 def ldst_so_reg : MemOperand,
915 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
916 let EncoderMethod = "getLdStSORegOpValue";
917 // FIXME: Simplify the printer
918 let PrintMethod = "printAddrMode2Operand";
919 let DecoderMethod = "DecodeSORegMemOperand";
920 let ParserMatchClass = MemRegOffsetAsmOperand;
921 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
924 // postidx_imm8 := +/- [0,255]
927 // {8} 1 is imm8 is non-negative. 0 otherwise.
928 // {7-0} [0,255] imm8 value.
929 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
930 def postidx_imm8 : MemOperand {
931 let PrintMethod = "printPostIdxImm8Operand";
932 let ParserMatchClass = PostIdxImm8AsmOperand;
933 let MIOperandInfo = (ops i32imm);
936 // postidx_imm8s4 := +/- [0,1020]
939 // {8} 1 is imm8 is non-negative. 0 otherwise.
940 // {7-0} [0,255] imm8 value, scaled by 4.
941 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
942 def postidx_imm8s4 : MemOperand {
943 let PrintMethod = "printPostIdxImm8s4Operand";
944 let ParserMatchClass = PostIdxImm8s4AsmOperand;
945 let MIOperandInfo = (ops i32imm);
949 // postidx_reg := +/- reg
951 def PostIdxRegAsmOperand : AsmOperandClass {
952 let Name = "PostIdxReg";
953 let ParserMethod = "parsePostIdxReg";
955 def postidx_reg : MemOperand {
956 let EncoderMethod = "getPostIdxRegOpValue";
957 let DecoderMethod = "DecodePostIdxReg";
958 let PrintMethod = "printPostIdxRegOperand";
959 let ParserMatchClass = PostIdxRegAsmOperand;
960 let MIOperandInfo = (ops GPRnopc, i32imm);
964 // addrmode2 := reg +/- imm12
965 // := reg +/- reg shop imm
967 // FIXME: addrmode2 should be refactored the rest of the way to always
968 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
969 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
970 def addrmode2 : MemOperand,
971 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
972 let EncoderMethod = "getAddrMode2OpValue";
973 let PrintMethod = "printAddrMode2Operand";
974 let ParserMatchClass = AddrMode2AsmOperand;
975 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
978 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
979 let Name = "PostIdxRegShifted";
980 let ParserMethod = "parsePostIdxReg";
982 def am2offset_reg : MemOperand,
983 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
984 [], [SDNPWantRoot]> {
985 let EncoderMethod = "getAddrMode2OffsetOpValue";
986 let PrintMethod = "printAddrMode2OffsetOperand";
987 // When using this for assembly, it's always as a post-index offset.
988 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
989 let MIOperandInfo = (ops GPRnopc, i32imm);
992 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
993 // the GPR is purely vestigal at this point.
994 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
995 def am2offset_imm : MemOperand,
996 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
997 [], [SDNPWantRoot]> {
998 let EncoderMethod = "getAddrMode2OffsetOpValue";
999 let PrintMethod = "printAddrMode2OffsetOperand";
1000 let ParserMatchClass = AM2OffsetImmAsmOperand;
1001 let MIOperandInfo = (ops GPRnopc, i32imm);
1005 // addrmode3 := reg +/- reg
1006 // addrmode3 := reg +/- imm8
1008 // FIXME: split into imm vs. reg versions.
1009 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
1010 class AddrMode3 : MemOperand,
1011 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
1012 let EncoderMethod = "getAddrMode3OpValue";
1013 let ParserMatchClass = AddrMode3AsmOperand;
1014 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1017 def addrmode3 : AddrMode3
1019 let PrintMethod = "printAddrMode3Operand<false>";
1022 def addrmode3_pre : AddrMode3
1024 let PrintMethod = "printAddrMode3Operand<true>";
1027 // FIXME: split into imm vs. reg versions.
1028 // FIXME: parser method to handle +/- register.
1029 def AM3OffsetAsmOperand : AsmOperandClass {
1030 let Name = "AM3Offset";
1031 let ParserMethod = "parseAM3Offset";
1033 def am3offset : MemOperand,
1034 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
1035 [], [SDNPWantRoot]> {
1036 let EncoderMethod = "getAddrMode3OffsetOpValue";
1037 let PrintMethod = "printAddrMode3OffsetOperand";
1038 let ParserMatchClass = AM3OffsetAsmOperand;
1039 let MIOperandInfo = (ops GPR, i32imm);
1042 // ldstm_mode := {ia, ib, da, db}
1044 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
1045 let EncoderMethod = "getLdStmModeOpValue";
1046 let PrintMethod = "printLdStmModeOperand";
1049 // addrmode5 := reg +/- imm8*4
1051 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
1052 class AddrMode5 : MemOperand,
1053 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
1054 let EncoderMethod = "getAddrMode5OpValue";
1055 let DecoderMethod = "DecodeAddrMode5Operand";
1056 let ParserMatchClass = AddrMode5AsmOperand;
1057 let MIOperandInfo = (ops GPR:$base, i32imm);
1060 def addrmode5 : AddrMode5 {
1061 let PrintMethod = "printAddrMode5Operand<false>";
1064 def addrmode5_pre : AddrMode5 {
1065 let PrintMethod = "printAddrMode5Operand<true>";
1068 // addrmode5fp16 := reg +/- imm8*2
1070 def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; }
1071 class AddrMode5FP16 : Operand<i32>,
1072 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> {
1073 let EncoderMethod = "getAddrMode5FP16OpValue";
1074 let DecoderMethod = "DecodeAddrMode5FP16Operand";
1075 let ParserMatchClass = AddrMode5FP16AsmOperand;
1076 let MIOperandInfo = (ops GPR:$base, i32imm);
1079 def addrmode5fp16 : AddrMode5FP16 {
1080 let PrintMethod = "printAddrMode5FP16Operand<false>";
1083 // addrmode6 := reg with optional alignment
1085 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
1086 def addrmode6 : MemOperand,
1087 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1088 let PrintMethod = "printAddrMode6Operand";
1089 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1090 let EncoderMethod = "getAddrMode6AddressOpValue";
1091 let DecoderMethod = "DecodeAddrMode6Operand";
1092 let ParserMatchClass = AddrMode6AsmOperand;
1095 def am6offset : MemOperand,
1096 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
1097 [], [SDNPWantRoot]> {
1098 let PrintMethod = "printAddrMode6OffsetOperand";
1099 let MIOperandInfo = (ops GPR);
1100 let EncoderMethod = "getAddrMode6OffsetOpValue";
1101 let DecoderMethod = "DecodeGPRRegisterClass";
1104 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
1105 // (single element from one lane) for size 32.
1106 def addrmode6oneL32 : MemOperand,
1107 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1108 let PrintMethod = "printAddrMode6Operand";
1109 let MIOperandInfo = (ops GPR:$addr, i32imm);
1110 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1113 // Base class for addrmode6 with specific alignment restrictions.
1114 class AddrMode6Align : MemOperand,
1115 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1116 let PrintMethod = "printAddrMode6Operand";
1117 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1118 let EncoderMethod = "getAddrMode6AddressOpValue";
1119 let DecoderMethod = "DecodeAddrMode6Operand";
1122 // Special version of addrmode6 to handle no allowed alignment encoding for
1123 // VLD/VST instructions and checking the alignment is not specified.
1124 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1125 let Name = "AlignedMemoryNone";
1126 let DiagnosticType = "AlignedMemoryRequiresNone";
1128 def addrmode6alignNone : AddrMode6Align {
1129 // The alignment specifier can only be omitted.
1130 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1133 // Special version of addrmode6 to handle 16-bit alignment encoding for
1134 // VLD/VST instructions and checking the alignment value.
1135 def AddrMode6Align16AsmOperand : AsmOperandClass {
1136 let Name = "AlignedMemory16";
1137 let DiagnosticType = "AlignedMemoryRequires16";
1139 def addrmode6align16 : AddrMode6Align {
1140 // The alignment specifier can only be 16 or omitted.
1141 let ParserMatchClass = AddrMode6Align16AsmOperand;
1144 // Special version of addrmode6 to handle 32-bit alignment encoding for
1145 // VLD/VST instructions and checking the alignment value.
1146 def AddrMode6Align32AsmOperand : AsmOperandClass {
1147 let Name = "AlignedMemory32";
1148 let DiagnosticType = "AlignedMemoryRequires32";
1150 def addrmode6align32 : AddrMode6Align {
1151 // The alignment specifier can only be 32 or omitted.
1152 let ParserMatchClass = AddrMode6Align32AsmOperand;
1155 // Special version of addrmode6 to handle 64-bit alignment encoding for
1156 // VLD/VST instructions and checking the alignment value.
1157 def AddrMode6Align64AsmOperand : AsmOperandClass {
1158 let Name = "AlignedMemory64";
1159 let DiagnosticType = "AlignedMemoryRequires64";
1161 def addrmode6align64 : AddrMode6Align {
1162 // The alignment specifier can only be 64 or omitted.
1163 let ParserMatchClass = AddrMode6Align64AsmOperand;
1166 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1167 // for VLD/VST instructions and checking the alignment value.
1168 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1169 let Name = "AlignedMemory64or128";
1170 let DiagnosticType = "AlignedMemoryRequires64or128";
1172 def addrmode6align64or128 : AddrMode6Align {
1173 // The alignment specifier can only be 64, 128 or omitted.
1174 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1177 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1178 // encoding for VLD/VST instructions and checking the alignment value.
1179 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1180 let Name = "AlignedMemory64or128or256";
1181 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1183 def addrmode6align64or128or256 : AddrMode6Align {
1184 // The alignment specifier can only be 64, 128, 256 or omitted.
1185 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1188 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1189 // instructions, specifically VLD4-dup.
1190 def addrmode6dup : MemOperand,
1191 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1192 let PrintMethod = "printAddrMode6Operand";
1193 let MIOperandInfo = (ops GPR:$addr, i32imm);
1194 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1195 // FIXME: This is close, but not quite right. The alignment specifier is
1197 let ParserMatchClass = AddrMode6AsmOperand;
1200 // Base class for addrmode6dup with specific alignment restrictions.
1201 class AddrMode6DupAlign : MemOperand,
1202 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1203 let PrintMethod = "printAddrMode6Operand";
1204 let MIOperandInfo = (ops GPR:$addr, i32imm);
1205 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1208 // Special version of addrmode6 to handle no allowed alignment encoding for
1209 // VLD-dup instruction and checking the alignment is not specified.
1210 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1211 let Name = "DupAlignedMemoryNone";
1212 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1214 def addrmode6dupalignNone : AddrMode6DupAlign {
1215 // The alignment specifier can only be omitted.
1216 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1219 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1220 // instruction and checking the alignment value.
1221 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1222 let Name = "DupAlignedMemory16";
1223 let DiagnosticType = "DupAlignedMemoryRequires16";
1225 def addrmode6dupalign16 : AddrMode6DupAlign {
1226 // The alignment specifier can only be 16 or omitted.
1227 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1230 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1231 // instruction and checking the alignment value.
1232 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1233 let Name = "DupAlignedMemory32";
1234 let DiagnosticType = "DupAlignedMemoryRequires32";
1236 def addrmode6dupalign32 : AddrMode6DupAlign {
1237 // The alignment specifier can only be 32 or omitted.
1238 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1241 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1242 // instructions and checking the alignment value.
1243 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1244 let Name = "DupAlignedMemory64";
1245 let DiagnosticType = "DupAlignedMemoryRequires64";
1247 def addrmode6dupalign64 : AddrMode6DupAlign {
1248 // The alignment specifier can only be 64 or omitted.
1249 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1252 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1253 // for VLD instructions and checking the alignment value.
1254 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1255 let Name = "DupAlignedMemory64or128";
1256 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1258 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1259 // The alignment specifier can only be 64, 128 or omitted.
1260 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1263 // addrmodepc := pc + reg
1265 def addrmodepc : MemOperand,
1266 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1267 let PrintMethod = "printAddrModePCOperand";
1268 let MIOperandInfo = (ops GPR, i32imm);
1271 // addr_offset_none := reg
1273 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1274 def addr_offset_none : MemOperand,
1275 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1276 let PrintMethod = "printAddrMode7Operand";
1277 let DecoderMethod = "DecodeAddrMode7Operand";
1278 let ParserMatchClass = MemNoOffsetAsmOperand;
1279 let MIOperandInfo = (ops GPR:$base);
1282 def nohash_imm : Operand<i32> {
1283 let PrintMethod = "printNoHashImmediate";
1286 def CoprocNumAsmOperand : AsmOperandClass {
1287 let Name = "CoprocNum";
1288 let ParserMethod = "parseCoprocNumOperand";
1290 def p_imm : Operand<i32> {
1291 let PrintMethod = "printPImmediate";
1292 let ParserMatchClass = CoprocNumAsmOperand;
1293 let DecoderMethod = "DecodeCoprocessor";
1296 def CoprocRegAsmOperand : AsmOperandClass {
1297 let Name = "CoprocReg";
1298 let ParserMethod = "parseCoprocRegOperand";
1300 def c_imm : Operand<i32> {
1301 let PrintMethod = "printCImmediate";
1302 let ParserMatchClass = CoprocRegAsmOperand;
1304 def CoprocOptionAsmOperand : AsmOperandClass {
1305 let Name = "CoprocOption";
1306 let ParserMethod = "parseCoprocOptionOperand";
1308 def coproc_option_imm : Operand<i32> {
1309 let PrintMethod = "printCoprocOptionImm";
1310 let ParserMatchClass = CoprocOptionAsmOperand;
1313 //===----------------------------------------------------------------------===//
1315 include "ARMInstrFormats.td"
1317 //===----------------------------------------------------------------------===//
1318 // Multiclass helpers...
1321 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1322 /// binop that produces a value.
1323 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1324 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1325 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1326 SDPatternOperator opnode, bit Commutable = 0> {
1327 // The register-immediate version is re-materializable. This is useful
1328 // in particular for taking the address of a local.
1329 let isReMaterializable = 1 in {
1330 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1331 iii, opc, "\t$Rd, $Rn, $imm",
1332 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1333 Sched<[WriteALU, ReadALU]> {
1338 let Inst{19-16} = Rn;
1339 let Inst{15-12} = Rd;
1340 let Inst{11-0} = imm;
1343 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1344 iir, opc, "\t$Rd, $Rn, $Rm",
1345 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1346 Sched<[WriteALU, ReadALU, ReadALU]> {
1351 let isCommutable = Commutable;
1352 let Inst{19-16} = Rn;
1353 let Inst{15-12} = Rd;
1354 let Inst{11-4} = 0b00000000;
1358 def rsi : AsI1<opcod, (outs GPR:$Rd),
1359 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1360 iis, opc, "\t$Rd, $Rn, $shift",
1361 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1362 Sched<[WriteALUsi, ReadALU]> {
1367 let Inst{19-16} = Rn;
1368 let Inst{15-12} = Rd;
1369 let Inst{11-5} = shift{11-5};
1371 let Inst{3-0} = shift{3-0};
1374 def rsr : AsI1<opcod, (outs GPR:$Rd),
1375 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1376 iis, opc, "\t$Rd, $Rn, $shift",
1377 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1378 Sched<[WriteALUsr, ReadALUsr]> {
1383 let Inst{19-16} = Rn;
1384 let Inst{15-12} = Rd;
1385 let Inst{11-8} = shift{11-8};
1387 let Inst{6-5} = shift{6-5};
1389 let Inst{3-0} = shift{3-0};
1393 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1394 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1395 /// it is equivalent to the AsI1_bin_irs counterpart.
1396 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1397 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1398 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1399 SDNode opnode, bit Commutable = 0> {
1400 // The register-immediate version is re-materializable. This is useful
1401 // in particular for taking the address of a local.
1402 let isReMaterializable = 1 in {
1403 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1404 iii, opc, "\t$Rd, $Rn, $imm",
1405 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1406 Sched<[WriteALU, ReadALU]> {
1411 let Inst{19-16} = Rn;
1412 let Inst{15-12} = Rd;
1413 let Inst{11-0} = imm;
1416 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1417 iir, opc, "\t$Rd, $Rn, $Rm",
1418 [/* pattern left blank */]>,
1419 Sched<[WriteALU, ReadALU, ReadALU]> {
1423 let Inst{11-4} = 0b00000000;
1426 let Inst{15-12} = Rd;
1427 let Inst{19-16} = Rn;
1430 def rsi : AsI1<opcod, (outs GPR:$Rd),
1431 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1432 iis, opc, "\t$Rd, $Rn, $shift",
1433 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1434 Sched<[WriteALUsi, ReadALU]> {
1439 let Inst{19-16} = Rn;
1440 let Inst{15-12} = Rd;
1441 let Inst{11-5} = shift{11-5};
1443 let Inst{3-0} = shift{3-0};
1446 def rsr : AsI1<opcod, (outs GPR:$Rd),
1447 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1448 iis, opc, "\t$Rd, $Rn, $shift",
1449 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1450 Sched<[WriteALUsr, ReadALUsr]> {
1455 let Inst{19-16} = Rn;
1456 let Inst{15-12} = Rd;
1457 let Inst{11-8} = shift{11-8};
1459 let Inst{6-5} = shift{6-5};
1461 let Inst{3-0} = shift{3-0};
1465 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1467 /// These opcodes will be converted to the real non-S opcodes by
1468 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1469 let hasPostISelHook = 1, Defs = [CPSR] in {
1470 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1471 InstrItinClass iis, SDNode opnode,
1472 bit Commutable = 0> {
1473 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1475 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1476 Sched<[WriteALU, ReadALU]>;
1478 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1480 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1481 Sched<[WriteALU, ReadALU, ReadALU]> {
1482 let isCommutable = Commutable;
1484 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1485 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1487 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1488 so_reg_imm:$shift))]>,
1489 Sched<[WriteALUsi, ReadALU]>;
1491 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1492 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1494 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1495 so_reg_reg:$shift))]>,
1496 Sched<[WriteALUSsr, ReadALUsr]>;
1500 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1501 /// operands are reversed.
1502 let hasPostISelHook = 1, Defs = [CPSR] in {
1503 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1504 InstrItinClass iis, SDNode opnode,
1505 bit Commutable = 0> {
1506 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1508 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1509 Sched<[WriteALU, ReadALU]>;
1511 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1512 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1514 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1516 Sched<[WriteALUsi, ReadALU]>;
1518 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1519 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1521 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1523 Sched<[WriteALUSsr, ReadALUsr]>;
1527 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1528 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1529 /// a explicit result, only implicitly set CPSR.
1530 let isCompare = 1, Defs = [CPSR] in {
1531 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1532 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1533 SDPatternOperator opnode, bit Commutable = 0,
1534 string rrDecoderMethod = ""> {
1535 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1537 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1538 Sched<[WriteCMP, ReadALU]> {
1543 let Inst{19-16} = Rn;
1544 let Inst{15-12} = 0b0000;
1545 let Inst{11-0} = imm;
1547 let Unpredictable{15-12} = 0b1111;
1549 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1551 [(opnode GPR:$Rn, GPR:$Rm)]>,
1552 Sched<[WriteCMP, ReadALU, ReadALU]> {
1555 let isCommutable = Commutable;
1558 let Inst{19-16} = Rn;
1559 let Inst{15-12} = 0b0000;
1560 let Inst{11-4} = 0b00000000;
1562 let DecoderMethod = rrDecoderMethod;
1564 let Unpredictable{15-12} = 0b1111;
1566 def rsi : AI1<opcod, (outs),
1567 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1568 opc, "\t$Rn, $shift",
1569 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1570 Sched<[WriteCMPsi, ReadALU]> {
1575 let Inst{19-16} = Rn;
1576 let Inst{15-12} = 0b0000;
1577 let Inst{11-5} = shift{11-5};
1579 let Inst{3-0} = shift{3-0};
1581 let Unpredictable{15-12} = 0b1111;
1583 def rsr : AI1<opcod, (outs),
1584 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1585 opc, "\t$Rn, $shift",
1586 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1587 Sched<[WriteCMPsr, ReadALU]> {
1592 let Inst{19-16} = Rn;
1593 let Inst{15-12} = 0b0000;
1594 let Inst{11-8} = shift{11-8};
1596 let Inst{6-5} = shift{6-5};
1598 let Inst{3-0} = shift{3-0};
1600 let Unpredictable{15-12} = 0b1111;
1606 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1607 /// register and one whose operand is a register rotated by 8/16/24.
1608 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1609 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1610 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1611 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1612 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1613 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1617 let Inst{19-16} = 0b1111;
1618 let Inst{15-12} = Rd;
1619 let Inst{11-10} = rot;
1623 class AI_ext_rrot_np<bits<8> opcod, string opc>
1624 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1625 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1626 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1628 let Inst{19-16} = 0b1111;
1629 let Inst{11-10} = rot;
1632 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1633 /// register and one whose operand is a register rotated by 8/16/24.
1634 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1635 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1636 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1637 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1638 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1639 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1644 let Inst{19-16} = Rn;
1645 let Inst{15-12} = Rd;
1646 let Inst{11-10} = rot;
1647 let Inst{9-4} = 0b000111;
1651 class AI_exta_rrot_np<bits<8> opcod, string opc>
1652 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1653 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1654 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1657 let Inst{19-16} = Rn;
1658 let Inst{11-10} = rot;
1661 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1662 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1663 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
1664 bit Commutable = 0> {
1665 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1666 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1667 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1668 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1670 Sched<[WriteALU, ReadALU]> {
1675 let Inst{15-12} = Rd;
1676 let Inst{19-16} = Rn;
1677 let Inst{11-0} = imm;
1679 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1680 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1681 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1683 Sched<[WriteALU, ReadALU, ReadALU]> {
1687 let Inst{11-4} = 0b00000000;
1689 let isCommutable = Commutable;
1691 let Inst{15-12} = Rd;
1692 let Inst{19-16} = Rn;
1694 def rsi : AsI1<opcod, (outs GPR:$Rd),
1695 (ins GPR:$Rn, so_reg_imm:$shift),
1696 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1697 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1699 Sched<[WriteALUsi, ReadALU]> {
1704 let Inst{19-16} = Rn;
1705 let Inst{15-12} = Rd;
1706 let Inst{11-5} = shift{11-5};
1708 let Inst{3-0} = shift{3-0};
1710 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1711 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1712 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1713 [(set GPRnopc:$Rd, CPSR,
1714 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1716 Sched<[WriteALUsr, ReadALUsr]> {
1721 let Inst{19-16} = Rn;
1722 let Inst{15-12} = Rd;
1723 let Inst{11-8} = shift{11-8};
1725 let Inst{6-5} = shift{6-5};
1727 let Inst{3-0} = shift{3-0};
1732 /// AI1_rsc_irs - Define instructions and patterns for rsc
1733 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1734 multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> {
1735 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1736 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1737 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1738 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1740 Sched<[WriteALU, ReadALU]> {
1745 let Inst{15-12} = Rd;
1746 let Inst{19-16} = Rn;
1747 let Inst{11-0} = imm;
1749 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1750 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1751 [/* pattern left blank */]>,
1752 Sched<[WriteALU, ReadALU, ReadALU]> {
1756 let Inst{11-4} = 0b00000000;
1759 let Inst{15-12} = Rd;
1760 let Inst{19-16} = Rn;
1762 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1763 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1764 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1766 Sched<[WriteALUsi, ReadALU]> {
1771 let Inst{19-16} = Rn;
1772 let Inst{15-12} = Rd;
1773 let Inst{11-5} = shift{11-5};
1775 let Inst{3-0} = shift{3-0};
1777 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1778 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1779 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1781 Sched<[WriteALUsr, ReadALUsr]> {
1786 let Inst{19-16} = Rn;
1787 let Inst{15-12} = Rd;
1788 let Inst{11-8} = shift{11-8};
1790 let Inst{6-5} = shift{6-5};
1792 let Inst{3-0} = shift{3-0};
1797 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1798 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1799 InstrItinClass iir, PatFrag opnode> {
1800 // Note: We use the complex addrmode_imm12 rather than just an input
1801 // GPR and a constrained immediate so that we can use this to match
1802 // frame index references and avoid matching constant pool references.
1803 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1804 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1805 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1808 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1809 let Inst{19-16} = addr{16-13}; // Rn
1810 let Inst{15-12} = Rt;
1811 let Inst{11-0} = addr{11-0}; // imm12
1813 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1814 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1815 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1818 let shift{4} = 0; // Inst{4} = 0
1819 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1820 let Inst{19-16} = shift{16-13}; // Rn
1821 let Inst{15-12} = Rt;
1822 let Inst{11-0} = shift{11-0};
1827 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1828 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1829 InstrItinClass iir, PatFrag opnode> {
1830 // Note: We use the complex addrmode_imm12 rather than just an input
1831 // GPR and a constrained immediate so that we can use this to match
1832 // frame index references and avoid matching constant pool references.
1833 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1834 (ins addrmode_imm12:$addr),
1835 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1836 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1839 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1840 let Inst{19-16} = addr{16-13}; // Rn
1841 let Inst{15-12} = Rt;
1842 let Inst{11-0} = addr{11-0}; // imm12
1844 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1845 (ins ldst_so_reg:$shift),
1846 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1847 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1850 let shift{4} = 0; // Inst{4} = 0
1851 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1852 let Inst{19-16} = shift{16-13}; // Rn
1853 let Inst{15-12} = Rt;
1854 let Inst{11-0} = shift{11-0};
1860 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1861 InstrItinClass iir, PatFrag opnode> {
1862 // Note: We use the complex addrmode_imm12 rather than just an input
1863 // GPR and a constrained immediate so that we can use this to match
1864 // frame index references and avoid matching constant pool references.
1865 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1866 (ins GPR:$Rt, addrmode_imm12:$addr),
1867 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1868 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1871 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1872 let Inst{19-16} = addr{16-13}; // Rn
1873 let Inst{15-12} = Rt;
1874 let Inst{11-0} = addr{11-0}; // imm12
1876 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1877 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1878 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1881 let shift{4} = 0; // Inst{4} = 0
1882 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1883 let Inst{19-16} = shift{16-13}; // Rn
1884 let Inst{15-12} = Rt;
1885 let Inst{11-0} = shift{11-0};
1889 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1890 InstrItinClass iir, PatFrag opnode> {
1891 // Note: We use the complex addrmode_imm12 rather than just an input
1892 // GPR and a constrained immediate so that we can use this to match
1893 // frame index references and avoid matching constant pool references.
1894 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1895 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1896 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1897 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1900 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1901 let Inst{19-16} = addr{16-13}; // Rn
1902 let Inst{15-12} = Rt;
1903 let Inst{11-0} = addr{11-0}; // imm12
1905 def rs : AI2ldst<0b011, 0, isByte, (outs),
1906 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1907 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1908 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1911 let shift{4} = 0; // Inst{4} = 0
1912 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1913 let Inst{19-16} = shift{16-13}; // Rn
1914 let Inst{15-12} = Rt;
1915 let Inst{11-0} = shift{11-0};
1920 //===----------------------------------------------------------------------===//
1922 //===----------------------------------------------------------------------===//
1924 //===----------------------------------------------------------------------===//
1925 // Miscellaneous Instructions.
1928 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1929 /// the function. The first operand is the ID# for this instruction, the second
1930 /// is the index into the MachineConstantPool that this is, the third is the
1931 /// size in bytes of this constant pool entry.
1932 let hasSideEffects = 0, isNotDuplicable = 1 in
1933 def CONSTPOOL_ENTRY :
1934 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1935 i32imm:$size), NoItinerary, []>;
1937 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1938 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1939 /// mode). Used mostly in ARM and Thumb-1 modes.
1940 def JUMPTABLE_ADDRS :
1941 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1942 i32imm:$size), NoItinerary, []>;
1944 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1945 /// that cannot be optimised to use TBB or TBH.
1946 def JUMPTABLE_INSTS :
1947 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1948 i32imm:$size), NoItinerary, []>;
1950 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1951 /// a TBB instruction.
1953 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1954 i32imm:$size), NoItinerary, []>;
1956 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1957 /// a TBH instruction.
1959 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1960 i32imm:$size), NoItinerary, []>;
1963 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1964 // from removing one half of the matched pairs. That breaks PEI, which assumes
1965 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1966 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1967 def ADJCALLSTACKUP :
1968 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1969 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1971 def ADJCALLSTACKDOWN :
1972 PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary,
1973 [(ARMcallseq_start timm:$amt, timm:$amt2)]>;
1976 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1977 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1978 Requires<[IsARM, HasV6]> {
1980 let Inst{27-8} = 0b00110010000011110000;
1981 let Inst{7-0} = imm;
1982 let DecoderMethod = "DecodeHINTInstruction";
1985 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1986 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1987 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1988 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1989 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1990 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1991 def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
1993 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1995 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
1996 Requires<[IsARM, HasV6]> {
2001 let Inst{15-12} = Rd;
2002 let Inst{19-16} = Rn;
2003 let Inst{27-20} = 0b01101000;
2004 let Inst{7-4} = 0b1011;
2005 let Inst{11-8} = 0b1111;
2006 let Unpredictable{11-8} = 0b1111;
2009 // The 16-bit operand $val can be used by a debugger to store more information
2010 // about the breakpoint.
2011 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
2012 "bkpt", "\t$val", []>, Requires<[IsARM]> {
2014 let Inst{3-0} = val{3-0};
2015 let Inst{19-8} = val{15-4};
2016 let Inst{27-20} = 0b00010010;
2017 let Inst{31-28} = 0xe; // AL
2018 let Inst{7-4} = 0b0111;
2020 // default immediate for breakpoint mnemonic
2021 def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>;
2023 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
2024 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
2026 let Inst{3-0} = val{3-0};
2027 let Inst{19-8} = val{15-4};
2028 let Inst{27-20} = 0b00010000;
2029 let Inst{31-28} = 0xe; // AL
2030 let Inst{7-4} = 0b0111;
2033 // Change Processor State
2034 // FIXME: We should use InstAlias to handle the optional operands.
2035 class CPS<dag iops, string asm_ops>
2036 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
2037 []>, Requires<[IsARM]> {
2043 let Inst{31-28} = 0b1111;
2044 let Inst{27-20} = 0b00010000;
2045 let Inst{19-18} = imod;
2046 let Inst{17} = M; // Enabled if mode is set;
2047 let Inst{16-9} = 0b00000000;
2048 let Inst{8-6} = iflags;
2050 let Inst{4-0} = mode;
2053 let DecoderMethod = "DecodeCPSInstruction" in {
2055 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
2056 "$imod\t$iflags, $mode">;
2057 let mode = 0, M = 0 in
2058 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
2060 let imod = 0, iflags = 0, M = 1 in
2061 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
2064 // Preload signals the memory system of possible future data/instruction access.
2065 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
2067 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
2068 IIC_Preload, !strconcat(opc, "\t$addr"),
2069 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
2070 Sched<[WritePreLd]> {
2073 let Inst{31-26} = 0b111101;
2074 let Inst{25} = 0; // 0 for immediate form
2075 let Inst{24} = data;
2076 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2077 let Inst{22} = read;
2078 let Inst{21-20} = 0b01;
2079 let Inst{19-16} = addr{16-13}; // Rn
2080 let Inst{15-12} = 0b1111;
2081 let Inst{11-0} = addr{11-0}; // imm12
2084 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
2085 !strconcat(opc, "\t$shift"),
2086 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
2087 Sched<[WritePreLd]> {
2089 let Inst{31-26} = 0b111101;
2090 let Inst{25} = 1; // 1 for register form
2091 let Inst{24} = data;
2092 let Inst{23} = shift{12}; // U (add = ('U' == 1))
2093 let Inst{22} = read;
2094 let Inst{21-20} = 0b01;
2095 let Inst{19-16} = shift{16-13}; // Rn
2096 let Inst{15-12} = 0b1111;
2097 let Inst{11-0} = shift{11-0};
2102 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
2103 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
2104 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
2106 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
2107 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2109 let Inst{31-10} = 0b1111000100000001000000;
2114 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2115 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2117 let Inst{27-4} = 0b001100100000111100001111;
2118 let Inst{3-0} = opt;
2121 // A8.8.247 UDF - Undefined (Encoding A1)
2122 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2123 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2125 let Inst{31-28} = 0b1110; // AL
2126 let Inst{27-25} = 0b011;
2127 let Inst{24-20} = 0b11111;
2128 let Inst{19-8} = imm16{15-4};
2129 let Inst{7-4} = 0b1111;
2130 let Inst{3-0} = imm16{3-0};
2134 * A5.4 Permanently UNDEFINED instructions.
2136 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2137 * Other UDF encodings generate SIGILL.
2139 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2141 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2143 * 1101 1110 iiii iiii
2144 * It uses the following encoding:
2145 * 1110 0111 1111 1110 1101 1110 1111 0000
2146 * - In ARM: UDF #60896;
2147 * - In Thumb: UDF #254 followed by a branch-to-self.
2149 let isBarrier = 1, isTerminator = 1 in
2150 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2152 Requires<[IsARM,UseNaClTrap]> {
2153 let Inst = 0xe7fedef0;
2155 let isBarrier = 1, isTerminator = 1 in
2156 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2158 Requires<[IsARM,DontUseNaClTrap]> {
2159 let Inst = 0xe7ffdefe;
2162 // Address computation and loads and stores in PIC mode.
2163 let isNotDuplicable = 1 in {
2164 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2166 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2167 Sched<[WriteALU, ReadALU]>;
2169 let AddedComplexity = 10 in {
2170 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2172 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2174 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2176 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2178 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2180 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2182 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2184 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2186 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2188 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2190 let AddedComplexity = 10 in {
2191 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2192 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2194 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2195 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2196 addrmodepc:$addr)]>;
2198 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2199 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2201 } // isNotDuplicable = 1
2204 // LEApcrel - Load a pc-relative address into a register without offending the
2206 let hasSideEffects = 0, isReMaterializable = 1 in
2207 // The 'adr' mnemonic encodes differently if the label is before or after
2208 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2209 // know until then which form of the instruction will be used.
2210 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2211 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2212 Sched<[WriteALU, ReadALU]> {
2215 let Inst{27-25} = 0b001;
2217 let Inst{23-22} = label{13-12};
2220 let Inst{19-16} = 0b1111;
2221 let Inst{15-12} = Rd;
2222 let Inst{11-0} = label{11-0};
2225 let hasSideEffects = 1 in {
2226 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2227 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2229 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2230 (ins i32imm:$label, pred:$p),
2231 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2234 //===----------------------------------------------------------------------===//
2235 // Control Flow Instructions.
2238 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2240 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2241 "bx", "\tlr", [(ARMretflag)]>,
2242 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2243 let Inst{27-0} = 0b0001001011111111111100011110;
2247 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2248 "mov", "\tpc, lr", [(ARMretflag)]>,
2249 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2250 let Inst{27-0} = 0b0001101000001111000000001110;
2253 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2254 // the user-space one).
2255 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2257 [(ARMintretflag imm:$offset)]>;
2260 // Indirect branches
2261 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2263 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2264 [(brind GPR:$dst)]>,
2265 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2267 let Inst{31-4} = 0b1110000100101111111111110001;
2268 let Inst{3-0} = dst;
2271 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2272 "bx", "\t$dst", [/* pattern left blank */]>,
2273 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2275 let Inst{27-4} = 0b000100101111111111110001;
2276 let Inst{3-0} = dst;
2280 // SP is marked as a use to prevent stack-pointer assignments that appear
2281 // immediately before calls from potentially appearing dead.
2283 // FIXME: Do we really need a non-predicated version? If so, it should
2284 // at least be a pseudo instruction expanding to the predicated version
2285 // at MC lowering time.
2286 Defs = [LR], Uses = [SP] in {
2287 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),
2288 IIC_Br, "bl\t$func",
2289 [(ARMcall tglobaladdr:$func)]>,
2290 Requires<[IsARM]>, Sched<[WriteBrL]> {
2291 let Inst{31-28} = 0b1110;
2293 let Inst{23-0} = func;
2294 let DecoderMethod = "DecodeBranchImmInstruction";
2297 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),
2298 IIC_Br, "bl", "\t$func",
2299 [(ARMcall_pred tglobaladdr:$func)]>,
2300 Requires<[IsARM]>, Sched<[WriteBrL]> {
2302 let Inst{23-0} = func;
2303 let DecoderMethod = "DecodeBranchImmInstruction";
2307 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2308 IIC_Br, "blx\t$func",
2309 [(ARMcall GPR:$func)]>,
2310 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2312 let Inst{31-4} = 0b1110000100101111111111110011;
2313 let Inst{3-0} = func;
2316 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2317 IIC_Br, "blx", "\t$func",
2318 [(ARMcall_pred GPR:$func)]>,
2319 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2321 let Inst{27-4} = 0b000100101111111111110011;
2322 let Inst{3-0} = func;
2326 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2327 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2328 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2329 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2332 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2333 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2334 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2336 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2337 // return stack predictor.
2338 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func),
2339 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2340 Requires<[IsARM]>, Sched<[WriteBr]>;
2343 let isBranch = 1, isTerminator = 1 in {
2344 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2345 // a two-value operand where a dag node expects two operands. :(
2346 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target),
2347 IIC_Br, "b", "\t$target",
2348 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2351 let Inst{23-0} = target;
2352 let DecoderMethod = "DecodeBranchImmInstruction";
2355 let isBarrier = 1 in {
2356 // B is "predicable" since it's just a Bcc with an 'always' condition.
2357 let isPredicable = 1 in
2358 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2359 // should be sufficient.
2360 // FIXME: Is B really a Barrier? That doesn't seem right.
2361 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br,
2362 [(br bb:$target)], (Bcc arm_br_target:$target,
2363 (ops 14, zero_reg))>,
2366 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2367 def BR_JTr : ARMPseudoInst<(outs),
2368 (ins GPR:$target, i32imm:$jt),
2370 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2372 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2373 // into i12 and rs suffixed versions.
2374 def BR_JTm : ARMPseudoInst<(outs),
2375 (ins addrmode2:$target, i32imm:$jt),
2377 [(ARMbrjt (i32 (load addrmode2:$target)),
2378 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2379 def BR_JTadd : ARMPseudoInst<(outs),
2380 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2382 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2383 Sched<[WriteBrTbl]>;
2384 } // isNotDuplicable = 1, isIndirectBranch = 1
2390 def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary,
2391 "blx\t$target", []>,
2392 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2393 let Inst{31-25} = 0b1111101;
2395 let Inst{23-0} = target{24-1};
2396 let Inst{24} = target{0};
2400 // Branch and Exchange Jazelle
2401 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2402 [/* pattern left blank */]>, Sched<[WriteBr]> {
2404 let Inst{23-20} = 0b0010;
2405 let Inst{19-8} = 0xfff;
2406 let Inst{7-4} = 0b0010;
2407 let Inst{3-0} = func;
2413 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2414 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2417 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2420 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst),
2422 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>,
2423 Requires<[IsARM]>, Sched<[WriteBr]>;
2425 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2427 (BX GPR:$dst)>, Sched<[WriteBr]>,
2431 // Secure Monitor Call is a system instruction.
2432 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2433 []>, Requires<[IsARM, HasTrustZone]> {
2435 let Inst{23-4} = 0b01100000000000000111;
2436 let Inst{3-0} = opt;
2438 def : MnemonicAlias<"smi", "smc">;
2440 // Supervisor Call (Software Interrupt)
2441 let isCall = 1, Uses = [SP] in {
2442 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2445 let Inst{23-0} = svc;
2449 // Store Return State
2450 class SRSI<bit wb, string asm>
2451 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2452 NoItinerary, asm, "", []> {
2454 let Inst{31-28} = 0b1111;
2455 let Inst{27-25} = 0b100;
2459 let Inst{19-16} = 0b1101; // SP
2460 let Inst{15-5} = 0b00000101000;
2461 let Inst{4-0} = mode;
2464 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2465 let Inst{24-23} = 0;
2467 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2468 let Inst{24-23} = 0;
2470 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2471 let Inst{24-23} = 0b10;
2473 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2474 let Inst{24-23} = 0b10;
2476 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2477 let Inst{24-23} = 0b01;
2479 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2480 let Inst{24-23} = 0b01;
2482 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2483 let Inst{24-23} = 0b11;
2485 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2486 let Inst{24-23} = 0b11;
2489 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2490 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2492 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2493 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2495 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2496 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2498 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2499 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2501 // Return From Exception
2502 class RFEI<bit wb, string asm>
2503 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2504 NoItinerary, asm, "", []> {
2506 let Inst{31-28} = 0b1111;
2507 let Inst{27-25} = 0b100;
2511 let Inst{19-16} = Rn;
2512 let Inst{15-0} = 0xa00;
2515 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2516 let Inst{24-23} = 0;
2518 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2519 let Inst{24-23} = 0;
2521 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2522 let Inst{24-23} = 0b10;
2524 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2525 let Inst{24-23} = 0b10;
2527 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2528 let Inst{24-23} = 0b01;
2530 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2531 let Inst{24-23} = 0b01;
2533 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2534 let Inst{24-23} = 0b11;
2536 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2537 let Inst{24-23} = 0b11;
2540 // Hypervisor Call is a system instruction
2542 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2543 "hvc", "\t$imm", []>,
2544 Requires<[IsARM, HasVirtualization]> {
2547 // Even though HVC isn't predicable, it's encoding includes a condition field.
2548 // The instruction is undefined if the condition field is 0xf otherwise it is
2549 // unpredictable if it isn't condition AL (0xe).
2550 let Inst{31-28} = 0b1110;
2551 let Unpredictable{31-28} = 0b1111;
2552 let Inst{27-24} = 0b0001;
2553 let Inst{23-20} = 0b0100;
2554 let Inst{19-8} = imm{15-4};
2555 let Inst{7-4} = 0b0111;
2556 let Inst{3-0} = imm{3-0};
2560 // Return from exception in Hypervisor mode.
2561 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2562 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2563 Requires<[IsARM, HasVirtualization]> {
2564 let Inst{23-0} = 0b011000000000000001101110;
2567 //===----------------------------------------------------------------------===//
2568 // Load / Store Instructions.
2574 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>;
2575 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2577 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>;
2578 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2581 // Special LDR for loads from non-pc-relative constpools.
2582 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2583 isReMaterializable = 1, isCodeGenOnly = 1 in
2584 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2585 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2589 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2590 let Inst{19-16} = 0b1111;
2591 let Inst{15-12} = Rt;
2592 let Inst{11-0} = addr{11-0}; // imm12
2595 // Loads with zero extension
2596 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2597 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2598 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2600 // Loads with sign extension
2601 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2602 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2603 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2605 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2606 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2607 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2609 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2611 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2612 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2613 Requires<[IsARM, HasV5TE]>;
2616 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2617 NoItinerary, "lda", "\t$Rt, $addr", []>;
2618 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2619 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2620 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2621 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2624 multiclass AI2_ldridx<bit isByte, string opc,
2625 InstrItinClass iii, InstrItinClass iir> {
2626 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2627 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2628 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2631 let Inst{23} = addr{12};
2632 let Inst{19-16} = addr{16-13};
2633 let Inst{11-0} = addr{11-0};
2634 let DecoderMethod = "DecodeLDRPreImm";
2637 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2638 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2639 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2642 let Inst{23} = addr{12};
2643 let Inst{19-16} = addr{16-13};
2644 let Inst{11-0} = addr{11-0};
2646 let DecoderMethod = "DecodeLDRPreReg";
2649 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2650 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2651 IndexModePost, LdFrm, iir,
2652 opc, "\t$Rt, $addr, $offset",
2653 "$addr.base = $Rn_wb", []> {
2659 let Inst{23} = offset{12};
2660 let Inst{19-16} = addr;
2661 let Inst{11-0} = offset{11-0};
2664 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2667 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2668 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2669 IndexModePost, LdFrm, iii,
2670 opc, "\t$Rt, $addr, $offset",
2671 "$addr.base = $Rn_wb", []> {
2677 let Inst{23} = offset{12};
2678 let Inst{19-16} = addr;
2679 let Inst{11-0} = offset{11-0};
2681 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2686 let mayLoad = 1, hasSideEffects = 0 in {
2687 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2688 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2689 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2690 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2693 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2694 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2695 (ins addrmode3_pre:$addr), IndexModePre,
2697 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2699 let Inst{23} = addr{8}; // U bit
2700 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2701 let Inst{19-16} = addr{12-9}; // Rn
2702 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2703 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2704 let DecoderMethod = "DecodeAddrMode3Instruction";
2706 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2707 (ins addr_offset_none:$addr, am3offset:$offset),
2708 IndexModePost, LdMiscFrm, itin,
2709 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2713 let Inst{23} = offset{8}; // U bit
2714 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2715 let Inst{19-16} = addr;
2716 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2717 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2718 let DecoderMethod = "DecodeAddrMode3Instruction";
2722 let mayLoad = 1, hasSideEffects = 0 in {
2723 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2724 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2725 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2726 let hasExtraDefRegAllocReq = 1 in {
2727 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2728 (ins addrmode3_pre:$addr), IndexModePre,
2729 LdMiscFrm, IIC_iLoad_d_ru,
2730 "ldrd", "\t$Rt, $Rt2, $addr!",
2731 "$addr.base = $Rn_wb", []> {
2733 let Inst{23} = addr{8}; // U bit
2734 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2735 let Inst{19-16} = addr{12-9}; // Rn
2736 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2737 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2738 let DecoderMethod = "DecodeAddrMode3Instruction";
2740 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2741 (ins addr_offset_none:$addr, am3offset:$offset),
2742 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2743 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2744 "$addr.base = $Rn_wb", []> {
2747 let Inst{23} = offset{8}; // U bit
2748 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2749 let Inst{19-16} = addr;
2750 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2751 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2752 let DecoderMethod = "DecodeAddrMode3Instruction";
2754 } // hasExtraDefRegAllocReq = 1
2755 } // mayLoad = 1, hasSideEffects = 0
2757 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2758 let mayLoad = 1, hasSideEffects = 0 in {
2759 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2760 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2761 IndexModePost, LdFrm, IIC_iLoad_ru,
2762 "ldrt", "\t$Rt, $addr, $offset",
2763 "$addr.base = $Rn_wb", []> {
2769 let Inst{23} = offset{12};
2770 let Inst{21} = 1; // overwrite
2771 let Inst{19-16} = addr;
2772 let Inst{11-5} = offset{11-5};
2774 let Inst{3-0} = offset{3-0};
2775 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2779 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2780 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2781 IndexModePost, LdFrm, IIC_iLoad_ru,
2782 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2788 let Inst{23} = offset{12};
2789 let Inst{21} = 1; // overwrite
2790 let Inst{19-16} = addr;
2791 let Inst{11-0} = offset{11-0};
2792 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2795 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2796 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2797 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2798 "ldrbt", "\t$Rt, $addr, $offset",
2799 "$addr.base = $Rn_wb", []> {
2805 let Inst{23} = offset{12};
2806 let Inst{21} = 1; // overwrite
2807 let Inst{19-16} = addr;
2808 let Inst{11-5} = offset{11-5};
2810 let Inst{3-0} = offset{3-0};
2811 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2815 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2816 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2817 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2818 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2824 let Inst{23} = offset{12};
2825 let Inst{21} = 1; // overwrite
2826 let Inst{19-16} = addr;
2827 let Inst{11-0} = offset{11-0};
2828 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2831 multiclass AI3ldrT<bits<4> op, string opc> {
2832 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2833 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2834 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2835 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2837 let Inst{23} = offset{8};
2839 let Inst{11-8} = offset{7-4};
2840 let Inst{3-0} = offset{3-0};
2842 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2843 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2844 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2845 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2847 let Inst{23} = Rm{4};
2850 let Unpredictable{11-8} = 0b1111;
2851 let Inst{3-0} = Rm{3-0};
2852 let DecoderMethod = "DecodeLDR";
2856 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2857 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2858 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2862 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2866 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2869 // Pseudo instruction ldr Rt, =immediate
2871 : ARMAsmPseudo<"ldr${q} $Rt, $immediate",
2872 (ins const_pool_asm_imm:$immediate, pred:$q),
2877 // Stores with truncate
2878 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2879 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2880 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2883 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2884 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2885 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2886 Requires<[IsARM, HasV5TE]> {
2892 multiclass AI2_stridx<bit isByte, string opc,
2893 InstrItinClass iii, InstrItinClass iir> {
2894 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2895 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2897 opc, "\t$Rt, $addr!",
2898 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2901 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2902 let Inst{19-16} = addr{16-13}; // Rn
2903 let Inst{11-0} = addr{11-0}; // imm12
2904 let DecoderMethod = "DecodeSTRPreImm";
2907 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2908 (ins GPR:$Rt, ldst_so_reg:$addr),
2909 IndexModePre, StFrm, iir,
2910 opc, "\t$Rt, $addr!",
2911 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2914 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2915 let Inst{19-16} = addr{16-13}; // Rn
2916 let Inst{11-0} = addr{11-0};
2917 let Inst{4} = 0; // Inst{4} = 0
2918 let DecoderMethod = "DecodeSTRPreReg";
2920 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2921 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2922 IndexModePost, StFrm, iir,
2923 opc, "\t$Rt, $addr, $offset",
2924 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2930 let Inst{23} = offset{12};
2931 let Inst{19-16} = addr;
2932 let Inst{11-0} = offset{11-0};
2935 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2938 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2939 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2940 IndexModePost, StFrm, iii,
2941 opc, "\t$Rt, $addr, $offset",
2942 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2948 let Inst{23} = offset{12};
2949 let Inst{19-16} = addr;
2950 let Inst{11-0} = offset{11-0};
2952 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2956 let mayStore = 1, hasSideEffects = 0 in {
2957 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2958 // IIC_iStore_siu depending on whether it the offset register is shifted.
2959 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2960 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2963 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2964 am2offset_reg:$offset),
2965 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2966 am2offset_reg:$offset)>;
2967 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2968 am2offset_imm:$offset),
2969 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2970 am2offset_imm:$offset)>;
2971 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2972 am2offset_reg:$offset),
2973 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2974 am2offset_reg:$offset)>;
2975 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2976 am2offset_imm:$offset),
2977 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2978 am2offset_imm:$offset)>;
2980 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2981 // put the patterns on the instruction definitions directly as ISel wants
2982 // the address base and offset to be separate operands, not a single
2983 // complex operand like we represent the instructions themselves. The
2984 // pseudos map between the two.
2985 let usesCustomInserter = 1,
2986 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2987 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2988 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2991 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2992 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2993 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2996 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2997 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2998 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3001 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3002 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3003 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3006 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3007 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3008 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
3011 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
3016 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
3017 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
3018 StMiscFrm, IIC_iStore_bh_ru,
3019 "strh", "\t$Rt, $addr!",
3020 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
3022 let Inst{23} = addr{8}; // U bit
3023 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
3024 let Inst{19-16} = addr{12-9}; // Rn
3025 let Inst{11-8} = addr{7-4}; // imm7_4/zero
3026 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
3027 let DecoderMethod = "DecodeAddrMode3Instruction";
3030 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3031 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
3032 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
3033 "strh", "\t$Rt, $addr, $offset",
3034 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
3035 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
3036 addr_offset_none:$addr,
3037 am3offset:$offset))]> {
3040 let Inst{23} = offset{8}; // U bit
3041 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
3042 let Inst{19-16} = addr;
3043 let Inst{11-8} = offset{7-4}; // imm7_4/zero
3044 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3045 let DecoderMethod = "DecodeAddrMode3Instruction";
3048 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
3049 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
3050 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
3051 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
3052 "strd", "\t$Rt, $Rt2, $addr!",
3053 "$addr.base = $Rn_wb", []> {
3055 let Inst{23} = addr{8}; // U bit
3056 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
3057 let Inst{19-16} = addr{12-9}; // Rn
3058 let Inst{11-8} = addr{7-4}; // imm7_4/zero
3059 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
3060 let DecoderMethod = "DecodeAddrMode3Instruction";
3063 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
3064 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
3066 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
3067 "strd", "\t$Rt, $Rt2, $addr, $offset",
3068 "$addr.base = $Rn_wb", []> {
3071 let Inst{23} = offset{8}; // U bit
3072 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
3073 let Inst{19-16} = addr;
3074 let Inst{11-8} = offset{7-4}; // imm7_4/zero
3075 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3076 let DecoderMethod = "DecodeAddrMode3Instruction";
3078 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
3080 // STRT, STRBT, and STRHT
3082 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3083 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3084 IndexModePost, StFrm, IIC_iStore_bh_ru,
3085 "strbt", "\t$Rt, $addr, $offset",
3086 "$addr.base = $Rn_wb", []> {
3092 let Inst{23} = offset{12};
3093 let Inst{21} = 1; // overwrite
3094 let Inst{19-16} = addr;
3095 let Inst{11-5} = offset{11-5};
3097 let Inst{3-0} = offset{3-0};
3098 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3102 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3103 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3104 IndexModePost, StFrm, IIC_iStore_bh_ru,
3105 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3111 let Inst{23} = offset{12};
3112 let Inst{21} = 1; // overwrite
3113 let Inst{19-16} = addr;
3114 let Inst{11-0} = offset{11-0};
3115 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3119 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3120 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3122 let mayStore = 1, hasSideEffects = 0 in {
3123 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3124 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3125 IndexModePost, StFrm, IIC_iStore_ru,
3126 "strt", "\t$Rt, $addr, $offset",
3127 "$addr.base = $Rn_wb", []> {
3133 let Inst{23} = offset{12};
3134 let Inst{21} = 1; // overwrite
3135 let Inst{19-16} = addr;
3136 let Inst{11-5} = offset{11-5};
3138 let Inst{3-0} = offset{3-0};
3139 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3143 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3144 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3145 IndexModePost, StFrm, IIC_iStore_ru,
3146 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3152 let Inst{23} = offset{12};
3153 let Inst{21} = 1; // overwrite
3154 let Inst{19-16} = addr;
3155 let Inst{11-0} = offset{11-0};
3156 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3161 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3162 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3164 multiclass AI3strT<bits<4> op, string opc> {
3165 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3166 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3167 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3168 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3170 let Inst{23} = offset{8};
3172 let Inst{11-8} = offset{7-4};
3173 let Inst{3-0} = offset{3-0};
3175 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3176 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3177 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3178 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3180 let Inst{23} = Rm{4};
3183 let Inst{3-0} = Rm{3-0};
3188 defm STRHT : AI3strT<0b1011, "strht">;
3190 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3191 NoItinerary, "stl", "\t$Rt, $addr", []>;
3192 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3193 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3194 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3195 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3197 //===----------------------------------------------------------------------===//
3198 // Load / store multiple Instructions.
3201 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3202 InstrItinClass itin, InstrItinClass itin_upd> {
3203 // IA is the default, so no need for an explicit suffix on the
3204 // mnemonic here. Without it is the canonical spelling.
3206 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3207 IndexModeNone, f, itin,
3208 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3209 let Inst{24-23} = 0b01; // Increment After
3210 let Inst{22} = P_bit;
3211 let Inst{21} = 0; // No writeback
3212 let Inst{20} = L_bit;
3215 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3216 IndexModeUpd, f, itin_upd,
3217 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3218 let Inst{24-23} = 0b01; // Increment After
3219 let Inst{22} = P_bit;
3220 let Inst{21} = 1; // Writeback
3221 let Inst{20} = L_bit;
3223 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3226 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3227 IndexModeNone, f, itin,
3228 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3229 let Inst{24-23} = 0b00; // Decrement After
3230 let Inst{22} = P_bit;
3231 let Inst{21} = 0; // No writeback
3232 let Inst{20} = L_bit;
3235 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3236 IndexModeUpd, f, itin_upd,
3237 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3238 let Inst{24-23} = 0b00; // Decrement After
3239 let Inst{22} = P_bit;
3240 let Inst{21} = 1; // Writeback
3241 let Inst{20} = L_bit;
3243 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3246 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3247 IndexModeNone, f, itin,
3248 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3249 let Inst{24-23} = 0b10; // Decrement Before
3250 let Inst{22} = P_bit;
3251 let Inst{21} = 0; // No writeback
3252 let Inst{20} = L_bit;
3255 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3256 IndexModeUpd, f, itin_upd,
3257 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3258 let Inst{24-23} = 0b10; // Decrement Before
3259 let Inst{22} = P_bit;
3260 let Inst{21} = 1; // Writeback
3261 let Inst{20} = L_bit;
3263 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3266 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3267 IndexModeNone, f, itin,
3268 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3269 let Inst{24-23} = 0b11; // Increment Before
3270 let Inst{22} = P_bit;
3271 let Inst{21} = 0; // No writeback
3272 let Inst{20} = L_bit;
3275 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3276 IndexModeUpd, f, itin_upd,
3277 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3278 let Inst{24-23} = 0b11; // Increment Before
3279 let Inst{22} = P_bit;
3280 let Inst{21} = 1; // Writeback
3281 let Inst{20} = L_bit;
3283 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3287 let hasSideEffects = 0 in {
3289 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3290 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3291 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3293 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3294 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3296 ComplexDeprecationPredicate<"ARMStore">;
3300 // FIXME: remove when we have a way to marking a MI with these properties.
3301 // FIXME: Should pc be an implicit operand like PICADD, etc?
3302 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3303 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3304 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3305 reglist:$regs, variable_ops),
3306 4, IIC_iLoad_mBr, [],
3307 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3308 RegConstraint<"$Rn = $wb">;
3310 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3311 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3314 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3315 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3320 //===----------------------------------------------------------------------===//
3321 // Move Instructions.
3324 let hasSideEffects = 0 in
3325 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3326 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3330 let Inst{19-16} = 0b0000;
3331 let Inst{11-4} = 0b00000000;
3334 let Inst{15-12} = Rd;
3337 // A version for the smaller set of tail call registers.
3338 let hasSideEffects = 0 in
3339 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3340 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3344 let Inst{11-4} = 0b00000000;
3347 let Inst{15-12} = Rd;
3350 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3351 DPSoRegRegFrm, IIC_iMOVsr,
3352 "mov", "\t$Rd, $src",
3353 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3357 let Inst{15-12} = Rd;
3358 let Inst{19-16} = 0b0000;
3359 let Inst{11-8} = src{11-8};
3361 let Inst{6-5} = src{6-5};
3363 let Inst{3-0} = src{3-0};
3367 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3368 DPSoRegImmFrm, IIC_iMOVsr,
3369 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3370 UnaryDP, Sched<[WriteALU]> {
3373 let Inst{15-12} = Rd;
3374 let Inst{19-16} = 0b0000;
3375 let Inst{11-5} = src{11-5};
3377 let Inst{3-0} = src{3-0};
3381 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3382 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3383 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3388 let Inst{15-12} = Rd;
3389 let Inst{19-16} = 0b0000;
3390 let Inst{11-0} = imm;
3393 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3394 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3396 "movw", "\t$Rd, $imm",
3397 [(set GPR:$Rd, imm0_65535:$imm)]>,
3398 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3401 let Inst{15-12} = Rd;
3402 let Inst{11-0} = imm{11-0};
3403 let Inst{19-16} = imm{15-12};
3406 let DecoderMethod = "DecodeArmMOVTWInstruction";
3409 def : InstAlias<"mov${p} $Rd, $imm",
3410 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
3411 Requires<[IsARM, HasV6T2]>;
3413 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3414 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3417 let Constraints = "$src = $Rd" in {
3418 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3419 (ins GPR:$src, imm0_65535_expr:$imm),
3421 "movt", "\t$Rd, $imm",
3423 (or (and GPR:$src, 0xffff),
3424 lo16AllZero:$imm))]>, UnaryDP,
3425 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3428 let Inst{15-12} = Rd;
3429 let Inst{11-0} = imm{11-0};
3430 let Inst{19-16} = imm{15-12};
3433 let DecoderMethod = "DecodeArmMOVTWInstruction";
3436 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3437 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3442 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3443 Requires<[IsARM, HasV6T2]>;
3445 let Uses = [CPSR] in
3446 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3447 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3448 Requires<[IsARM]>, Sched<[WriteALU]>;
3450 // These aren't really mov instructions, but we have to define them this way
3451 // due to flag operands.
3453 let Defs = [CPSR] in {
3454 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3455 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3456 Sched<[WriteALU]>, Requires<[IsARM]>;
3457 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3458 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3459 Sched<[WriteALU]>, Requires<[IsARM]>;
3462 //===----------------------------------------------------------------------===//
3463 // Extend Instructions.
3468 def SXTB : AI_ext_rrot<0b01101010,
3469 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3470 def SXTH : AI_ext_rrot<0b01101011,
3471 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3473 def SXTAB : AI_exta_rrot<0b01101010,
3474 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3475 def SXTAH : AI_exta_rrot<0b01101011,
3476 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3478 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
3479 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3480 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot),
3482 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3484 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3485 def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src),
3486 (SXTB16 GPR:$Src, 0)>;
3488 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3489 def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS),
3490 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3494 let AddedComplexity = 16 in {
3495 def UXTB : AI_ext_rrot<0b01101110,
3496 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3497 def UXTH : AI_ext_rrot<0b01101111,
3498 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3499 def UXTB16 : AI_ext_rrot<0b01101100,
3500 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3502 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3503 // The transformation should probably be done as a combiner action
3504 // instead so we can include a check for masking back in the upper
3505 // eight bits of the source into the lower eight bits of the result.
3506 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3507 // (UXTB16r_rot GPR:$Src, 3)>;
3508 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3509 (UXTB16 GPR:$Src, 1)>;
3510 def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src),
3511 (UXTB16 GPR:$Src, 0)>;
3513 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3514 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3515 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3516 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3518 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
3519 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3520 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
3521 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3524 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3525 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3526 def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS),
3527 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3530 def SBFX : I<(outs GPRnopc:$Rd),
3531 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3532 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3533 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3534 Requires<[IsARM, HasV6T2]> {
3539 let Inst{27-21} = 0b0111101;
3540 let Inst{6-4} = 0b101;
3541 let Inst{20-16} = width;
3542 let Inst{15-12} = Rd;
3543 let Inst{11-7} = lsb;
3547 def UBFX : I<(outs GPRnopc:$Rd),
3548 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3549 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3550 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3551 Requires<[IsARM, HasV6T2]> {
3556 let Inst{27-21} = 0b0111111;
3557 let Inst{6-4} = 0b101;
3558 let Inst{20-16} = width;
3559 let Inst{15-12} = Rd;
3560 let Inst{11-7} = lsb;
3564 //===----------------------------------------------------------------------===//
3565 // Arithmetic Instructions.
3569 defm ADD : AsI1_bin_irs<0b0100, "add",
3570 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>;
3571 defm SUB : AsI1_bin_irs<0b0010, "sub",
3572 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>;
3574 // ADD and SUB with 's' bit set.
3576 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3577 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3578 // AdjustInstrPostInstrSelection where we determine whether or not to
3579 // set the "s" bit based on CPSR liveness.
3581 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3582 // support for an optional CPSR definition that corresponds to the DAG
3583 // node's second value. We can then eliminate the implicit def of CPSR.
3585 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>;
3586 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
3589 defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>;
3590 defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>;
3592 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3593 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3596 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3597 // CPSR and the implicit def of CPSR is not needed.
3598 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
3600 defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>;
3602 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3603 // The assume-no-carry-in form uses the negation of the input since add/sub
3604 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3605 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3607 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3608 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3609 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3610 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3612 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3613 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3614 Requires<[IsARM, HasV6T2]>;
3615 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3616 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3617 Requires<[IsARM, HasV6T2]>;
3619 // The with-carry-in form matches bitwise not instead of the negation.
3620 // Effectively, the inverse interpretation of the carry flag already accounts
3621 // for part of the negation.
3622 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3623 (SBCri GPR:$src, mod_imm_not:$imm)>;
3624 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3625 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3626 Requires<[IsARM, HasV6T2]>;
3628 // Note: These are implemented in C++ code, because they have to generate
3629 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3631 // (mul X, 2^n+1) -> (add (X << n), X)
3632 // (mul X, 2^n-1) -> (rsb X, (X << n))
3634 // ARM Arithmetic Instruction
3635 // GPR:$dst = GPR:$a op GPR:$b
3636 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3637 list<dag> pattern = [],
3638 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3639 string asm = "\t$Rd, $Rn, $Rm">
3640 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3641 Sched<[WriteALU, ReadALU, ReadALU]> {
3645 let Inst{27-20} = op27_20;
3646 let Inst{11-4} = op11_4;
3647 let Inst{19-16} = Rn;
3648 let Inst{15-12} = Rd;
3651 let Unpredictable{11-8} = 0b1111;
3654 // Wrappers around the AAI class
3655 class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc,
3656 list<dag> pattern = []>
3657 : AAI<op27_20, op11_4, opc,
3659 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3662 class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc,
3663 Intrinsic intrinsic>
3664 : AAI<op27_20, op11_4, opc,
3665 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>;
3667 // Saturating add/subtract
3668 let hasSideEffects = 1 in {
3669 def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>;
3670 def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>;
3671 def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>;
3672 def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>;
3674 def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd",
3675 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm,
3678 def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub",
3679 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm,
3680 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
3681 def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub",
3682 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
3683 let DecoderMethod = "DecodeQADDInstruction" in
3684 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd",
3685 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
3688 def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>;
3689 def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>;
3690 def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>;
3691 def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>;
3692 def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>;
3693 def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>;
3694 def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>;
3695 def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>;
3697 // Signed/Unsigned add/subtract
3699 def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>;
3700 def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>;
3701 def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>;
3702 def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>;
3703 def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>;
3704 def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>;
3705 def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>;
3706 def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>;
3707 def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>;
3708 def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>;
3709 def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>;
3710 def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>;
3712 // Signed/Unsigned halving add/subtract
3714 def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>;
3715 def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>;
3716 def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>;
3717 def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>;
3718 def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>;
3719 def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>;
3720 def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>;
3721 def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>;
3722 def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>;
3723 def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>;
3724 def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>;
3725 def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>;
3727 // Unsigned Sum of Absolute Differences [and Accumulate].
3729 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3730 MulFrm /* for convenience */, NoItinerary, "usad8",
3732 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
3733 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3737 let Inst{27-20} = 0b01111000;
3738 let Inst{15-12} = 0b1111;
3739 let Inst{7-4} = 0b0001;
3740 let Inst{19-16} = Rd;
3741 let Inst{11-8} = Rm;
3744 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3745 MulFrm /* for convenience */, NoItinerary, "usada8",
3746 "\t$Rd, $Rn, $Rm, $Ra",
3747 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
3748 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3753 let Inst{27-20} = 0b01111000;
3754 let Inst{7-4} = 0b0001;
3755 let Inst{19-16} = Rd;
3756 let Inst{15-12} = Ra;
3757 let Inst{11-8} = Rm;
3761 // Signed/Unsigned saturate
3762 def SSAT : AI<(outs GPRnopc:$Rd),
3763 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3764 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
3765 Requires<[IsARM,HasV6]>{
3770 let Inst{27-21} = 0b0110101;
3771 let Inst{5-4} = 0b01;
3772 let Inst{20-16} = sat_imm;
3773 let Inst{15-12} = Rd;
3774 let Inst{11-7} = sh{4-0};
3775 let Inst{6} = sh{5};
3779 def SSAT16 : AI<(outs GPRnopc:$Rd),
3780 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3781 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
3782 Requires<[IsARM,HasV6]>{
3786 let Inst{27-20} = 0b01101010;
3787 let Inst{11-4} = 0b11110011;
3788 let Inst{15-12} = Rd;
3789 let Inst{19-16} = sat_imm;
3793 def USAT : AI<(outs GPRnopc:$Rd),
3794 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3795 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
3796 Requires<[IsARM,HasV6]> {
3801 let Inst{27-21} = 0b0110111;
3802 let Inst{5-4} = 0b01;
3803 let Inst{15-12} = Rd;
3804 let Inst{11-7} = sh{4-0};
3805 let Inst{6} = sh{5};
3806 let Inst{20-16} = sat_imm;
3810 def USAT16 : AI<(outs GPRnopc:$Rd),
3811 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3812 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
3813 Requires<[IsARM,HasV6]>{
3817 let Inst{27-20} = 0b01101110;
3818 let Inst{11-4} = 0b11110011;
3819 let Inst{15-12} = Rd;
3820 let Inst{19-16} = sat_imm;
3824 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
3825 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
3826 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
3827 (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
3828 def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
3829 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
3830 def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos),
3831 (SSAT16 imm1_16:$pos, GPRnopc:$a)>;
3832 def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos),
3833 (USAT16 imm0_15:$pos, GPRnopc:$a)>;
3835 //===----------------------------------------------------------------------===//
3836 // Bitwise Instructions.
3839 defm AND : AsI1_bin_irs<0b0000, "and",
3840 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>;
3841 defm ORR : AsI1_bin_irs<0b1100, "orr",
3842 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>;
3843 defm EOR : AsI1_bin_irs<0b0001, "eor",
3844 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>;
3845 defm BIC : AsI1_bin_irs<0b1110, "bic",
3846 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3847 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3849 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3850 // like in the actual instruction encoding. The complexity of mapping the mask
3851 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3852 // instruction description.
3853 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3854 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3855 "bfc", "\t$Rd, $imm", "$src = $Rd",
3856 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3857 Requires<[IsARM, HasV6T2]> {
3860 let Inst{27-21} = 0b0111110;
3861 let Inst{6-0} = 0b0011111;
3862 let Inst{15-12} = Rd;
3863 let Inst{11-7} = imm{4-0}; // lsb
3864 let Inst{20-16} = imm{9-5}; // msb
3867 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3868 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3869 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3870 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3871 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3872 bf_inv_mask_imm:$imm))]>,
3873 Requires<[IsARM, HasV6T2]> {
3877 let Inst{27-21} = 0b0111110;
3878 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3879 let Inst{15-12} = Rd;
3880 let Inst{11-7} = imm{4-0}; // lsb
3881 let Inst{20-16} = imm{9-5}; // width
3885 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3886 "mvn", "\t$Rd, $Rm",
3887 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3891 let Inst{19-16} = 0b0000;
3892 let Inst{11-4} = 0b00000000;
3893 let Inst{15-12} = Rd;
3896 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3897 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3898 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3903 let Inst{19-16} = 0b0000;
3904 let Inst{15-12} = Rd;
3905 let Inst{11-5} = shift{11-5};
3907 let Inst{3-0} = shift{3-0};
3909 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3910 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3911 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3916 let Inst{19-16} = 0b0000;
3917 let Inst{15-12} = Rd;
3918 let Inst{11-8} = shift{11-8};
3920 let Inst{6-5} = shift{6-5};
3922 let Inst{3-0} = shift{3-0};
3924 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3925 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3926 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3927 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3931 let Inst{19-16} = 0b0000;
3932 let Inst{15-12} = Rd;
3933 let Inst{11-0} = imm;
3936 let AddedComplexity = 1 in
3937 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3938 (BICri GPR:$src, mod_imm_not:$imm)>;
3940 //===----------------------------------------------------------------------===//
3941 // Multiply Instructions.
3943 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3944 string opc, string asm, list<dag> pattern>
3945 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3949 let Inst{19-16} = Rd;
3950 let Inst{11-8} = Rm;
3953 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3954 string opc, string asm, list<dag> pattern>
3955 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3960 let Inst{19-16} = RdHi;
3961 let Inst{15-12} = RdLo;
3962 let Inst{11-8} = Rm;
3965 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3966 string opc, string asm, list<dag> pattern>
3967 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3972 let Inst{19-16} = RdHi;
3973 let Inst{15-12} = RdLo;
3974 let Inst{11-8} = Rm;
3978 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3979 // property. Remove them when it's possible to add those properties
3980 // on an individual MachineInstr, not just an instruction description.
3981 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3982 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3983 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3984 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3985 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3986 Requires<[IsARM, HasV6]>,
3987 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
3988 let Inst{15-12} = 0b0000;
3989 let Unpredictable{15-12} = 0b1111;
3992 let Constraints = "@earlyclobber $Rd" in
3993 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3994 pred:$p, cc_out:$s),
3996 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3997 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3998 Requires<[IsARM, NoV6, UseMulOps]>,
3999 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
4002 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
4003 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
4004 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
4005 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
4006 Requires<[IsARM, HasV6, UseMulOps]>,
4007 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
4009 let Inst{15-12} = Ra;
4012 let Constraints = "@earlyclobber $Rd" in
4013 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
4014 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
4015 pred:$p, cc_out:$s), 4, IIC_iMAC32,
4016 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
4017 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
4018 Requires<[IsARM, NoV6]>,
4019 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4021 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4022 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
4023 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4024 Requires<[IsARM, HasV6T2, UseMulOps]>,
4025 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
4030 let Inst{19-16} = Rd;
4031 let Inst{15-12} = Ra;
4032 let Inst{11-8} = Rm;
4036 // Extra precision multiplies with low / high results
4037 let hasSideEffects = 0 in {
4038 let isCommutable = 1 in {
4039 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4040 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4041 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4042 [(set GPR:$RdLo, GPR:$RdHi,
4043 (smullohi GPR:$Rn, GPR:$Rm))]>,
4044 Requires<[IsARM, HasV6]>,
4045 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4047 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4048 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4049 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4050 [(set GPR:$RdLo, GPR:$RdHi,
4051 (umullohi GPR:$Rn, GPR:$Rm))]>,
4052 Requires<[IsARM, HasV6]>,
4053 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>;
4055 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
4056 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4057 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4059 [(set GPR:$RdLo, GPR:$RdHi,
4060 (smullohi GPR:$Rn, GPR:$Rm))],
4061 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4062 Requires<[IsARM, NoV6]>,
4063 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4065 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4066 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4068 [(set GPR:$RdLo, GPR:$RdHi,
4069 (umullohi GPR:$Rn, GPR:$Rm))],
4070 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4071 Requires<[IsARM, NoV6]>,
4072 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4076 // Multiply + accumulate
4077 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4078 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4079 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4080 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4081 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4082 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4083 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4084 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4085 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4086 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4088 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
4089 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4091 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4092 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4093 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
4098 let Inst{19-16} = RdHi;
4099 let Inst{15-12} = RdLo;
4100 let Inst{11-8} = Rm;
4105 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4106 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4107 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4109 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4110 pred:$p, cc_out:$s)>,
4111 Requires<[IsARM, NoV6]>,
4112 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4113 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4114 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4116 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4117 pred:$p, cc_out:$s)>,
4118 Requires<[IsARM, NoV6]>,
4119 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4124 // Most significant word multiply
4125 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4126 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
4127 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4128 Requires<[IsARM, HasV6]>,
4129 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
4130 let Inst{15-12} = 0b1111;
4133 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4134 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
4135 Requires<[IsARM, HasV6]>,
4136 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
4137 let Inst{15-12} = 0b1111;
4140 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4141 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4142 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
4143 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4144 Requires<[IsARM, HasV6, UseMulOps]>,
4145 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4147 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4148 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4149 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
4150 Requires<[IsARM, HasV6]>,
4151 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4153 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
4154 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4155 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4156 Requires<[IsARM, HasV6, UseMulOps]>,
4157 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4159 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
4160 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4161 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
4162 Requires<[IsARM, HasV6]>,
4163 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4165 multiclass AI_smul<string opc> {
4166 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4167 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4168 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16),
4169 (sext_inreg GPR:$Rm, i16)))]>,
4170 Requires<[IsARM, HasV5TE]>,
4171 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4173 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4174 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4175 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16),
4176 (sra GPR:$Rm, (i32 16))))]>,
4177 Requires<[IsARM, HasV5TE]>,
4178 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4180 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4181 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4182 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)),
4183 (sext_inreg GPR:$Rm, i16)))]>,
4184 Requires<[IsARM, HasV5TE]>,
4185 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4187 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4188 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4189 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)),
4190 (sra GPR:$Rm, (i32 16))))]>,
4191 Requires<[IsARM, HasV5TE]>,
4192 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4194 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4195 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4196 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4197 Requires<[IsARM, HasV5TE]>,
4198 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4200 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4201 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4202 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4203 Requires<[IsARM, HasV5TE]>,
4204 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4208 multiclass AI_smla<string opc> {
4209 let DecoderMethod = "DecodeSMLAInstruction" in {
4210 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4211 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4212 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4213 [(set GPRnopc:$Rd, (add GPR:$Ra,
4214 (mul (sext_inreg GPRnopc:$Rn, i16),
4215 (sext_inreg GPRnopc:$Rm, i16))))]>,
4216 Requires<[IsARM, HasV5TE, UseMulOps]>,
4217 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4219 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4220 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4221 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4223 (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16),
4224 (sra GPRnopc:$Rm, (i32 16)))))]>,
4225 Requires<[IsARM, HasV5TE, UseMulOps]>,
4226 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4228 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4229 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4230 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4232 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)),
4233 (sext_inreg GPRnopc:$Rm, i16))))]>,
4234 Requires<[IsARM, HasV5TE, UseMulOps]>,
4235 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4237 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4238 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4239 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4241 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)),
4242 (sra GPRnopc:$Rm, (i32 16)))))]>,
4243 Requires<[IsARM, HasV5TE, UseMulOps]>,
4244 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4246 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4247 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4248 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4250 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4251 Requires<[IsARM, HasV5TE, UseMulOps]>,
4252 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4254 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4255 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4256 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4258 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4259 Requires<[IsARM, HasV5TE, UseMulOps]>,
4260 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4264 defm SMUL : AI_smul<"smul">;
4265 defm SMLA : AI_smla<"smla">;
4267 // Halfword multiply accumulate long: SMLAL<x><y>.
4268 class SMLAL<bits<2> opc1, string asm>
4269 : AMulxyI64<0b0001010, opc1,
4270 (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4271 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4272 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4273 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4274 Requires<[IsARM, HasV5TE]>,
4275 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4277 def SMLALBB : SMLAL<0b00, "smlalbb">;
4278 def SMLALBT : SMLAL<0b10, "smlalbt">;
4279 def SMLALTB : SMLAL<0b01, "smlaltb">;
4280 def SMLALTT : SMLAL<0b11, "smlaltt">;
4282 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4283 (SMLALBB $Rn, $Rm, $RLo, $RHi)>;
4284 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4285 (SMLALBT $Rn, $Rm, $RLo, $RHi)>;
4286 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4287 (SMLALTB $Rn, $Rm, $RLo, $RHi)>;
4288 def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4289 (SMLALTT $Rn, $Rm, $RLo, $RHi)>;
4291 // Helper class for AI_smld.
4292 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4293 InstrItinClass itin, string opc, string asm>
4294 : AI<oops, iops, MulFrm, itin, opc, asm, []>,
4295 Requires<[IsARM, HasV6]> {
4298 let Inst{27-23} = 0b01110;
4299 let Inst{22} = long;
4300 let Inst{21-20} = 0b00;
4301 let Inst{11-8} = Rm;
4308 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4309 InstrItinClass itin, string opc, string asm>
4310 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4312 let Inst{15-12} = 0b1111;
4313 let Inst{19-16} = Rd;
4315 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4316 InstrItinClass itin, string opc, string asm>
4317 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4320 let Inst{19-16} = Rd;
4321 let Inst{15-12} = Ra;
4323 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4324 InstrItinClass itin, string opc, string asm>
4325 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4328 let Inst{19-16} = RdHi;
4329 let Inst{15-12} = RdLo;
4332 multiclass AI_smld<bit sub, string opc> {
4334 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4335 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4336 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
4337 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4339 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4340 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4341 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
4342 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4344 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4345 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4347 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
4348 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4349 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4351 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4352 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4354 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
4355 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4356 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4359 defm SMLA : AI_smld<0, "smla">;
4360 defm SMLS : AI_smld<1, "smls">;
4362 def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4363 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4364 def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4365 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4366 def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4367 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4368 def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4369 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4370 def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4371 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4372 def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4373 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4374 def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4375 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4376 def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4377 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4379 multiclass AI_sdml<bit sub, string opc> {
4381 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4382 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
4383 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
4384 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4385 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
4386 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
4389 defm SMUA : AI_sdml<0, "smua">;
4390 defm SMUS : AI_sdml<1, "smus">;
4392 def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm),
4393 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>;
4394 def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm),
4395 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>;
4396 def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm),
4397 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>;
4398 def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm),
4399 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>;
4401 //===----------------------------------------------------------------------===//
4402 // Division Instructions (ARMv7-A with virtualization extension)
4404 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4405 "sdiv", "\t$Rd, $Rn, $Rm",
4406 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4407 Requires<[IsARM, HasDivideInARM]>,
4410 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4411 "udiv", "\t$Rd, $Rn, $Rm",
4412 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4413 Requires<[IsARM, HasDivideInARM]>,
4416 //===----------------------------------------------------------------------===//
4417 // Misc. Arithmetic Instructions.
4420 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4421 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4422 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4425 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4426 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4427 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4428 Requires<[IsARM, HasV6T2]>,
4431 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4432 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4433 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4436 let AddedComplexity = 5 in
4437 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4438 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4439 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4440 Requires<[IsARM, HasV6]>,
4443 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4444 (REV16 (LDRH addrmode3:$addr))>;
4445 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4446 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4448 let AddedComplexity = 5 in
4449 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4450 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4451 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4452 Requires<[IsARM, HasV6]>,
4455 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4456 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4459 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4460 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4461 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4462 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4463 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4465 Requires<[IsARM, HasV6]>,
4466 Sched<[WriteALUsi, ReadALU]>;
4468 // Alternate cases for PKHBT where identities eliminate some nodes.
4469 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4470 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4471 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4472 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4474 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4475 // will match the pattern below.
4476 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4477 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4478 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4479 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4480 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4482 Requires<[IsARM, HasV6]>,
4483 Sched<[WriteALUsi, ReadALU]>;
4485 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4486 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4487 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4488 // pkhtb src1, src2, asr (17..31).
4489 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4490 (srl GPRnopc:$src2, imm16:$sh)),
4491 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4492 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4493 (sra GPRnopc:$src2, imm16_31:$sh)),
4494 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4495 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4496 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4497 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4499 //===----------------------------------------------------------------------===//
4503 // + CRC32{B,H,W} 0x04C11DB7
4504 // + CRC32C{B,H,W} 0x1EDC6F41
4507 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4508 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4509 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4510 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4511 Requires<[IsARM, HasV8, HasCRC]> {
4516 let Inst{31-28} = 0b1110;
4517 let Inst{27-23} = 0b00010;
4518 let Inst{22-21} = sz;
4520 let Inst{19-16} = Rn;
4521 let Inst{15-12} = Rd;
4522 let Inst{11-10} = 0b00;
4525 let Inst{7-4} = 0b0100;
4528 let Unpredictable{11-8} = 0b1101;
4531 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4532 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4533 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4534 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4535 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4536 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4538 //===----------------------------------------------------------------------===//
4539 // ARMv8.1a Privilege Access Never extension
4543 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4544 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4547 let Inst{31-28} = 0b1111;
4548 let Inst{27-20} = 0b00010001;
4549 let Inst{19-16} = 0b0000;
4550 let Inst{15-10} = 0b000000;
4553 let Inst{7-4} = 0b0000;
4554 let Inst{3-0} = 0b0000;
4556 let Unpredictable{19-16} = 0b1111;
4557 let Unpredictable{15-10} = 0b111111;
4558 let Unpredictable{8} = 0b1;
4559 let Unpredictable{3-0} = 0b1111;
4562 //===----------------------------------------------------------------------===//
4563 // Comparison Instructions...
4566 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4567 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>;
4569 // ARMcmpZ can re-use the above instruction definitions.
4570 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4571 (CMPri GPR:$src, mod_imm:$imm)>;
4572 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4573 (CMPrr GPR:$src, GPR:$rhs)>;
4574 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4575 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4576 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4577 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4579 // CMN register-integer
4580 let isCompare = 1, Defs = [CPSR] in {
4581 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4582 "cmn", "\t$Rn, $imm",
4583 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4584 Sched<[WriteCMP, ReadALU]> {
4589 let Inst{19-16} = Rn;
4590 let Inst{15-12} = 0b0000;
4591 let Inst{11-0} = imm;
4593 let Unpredictable{15-12} = 0b1111;
4596 // CMN register-register/shift
4597 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4598 "cmn", "\t$Rn, $Rm",
4599 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4600 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4603 let isCommutable = 1;
4606 let Inst{19-16} = Rn;
4607 let Inst{15-12} = 0b0000;
4608 let Inst{11-4} = 0b00000000;
4611 let Unpredictable{15-12} = 0b1111;
4614 def CMNzrsi : AI1<0b1011, (outs),
4615 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4616 "cmn", "\t$Rn, $shift",
4617 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4618 GPR:$Rn, so_reg_imm:$shift)]>,
4619 Sched<[WriteCMPsi, ReadALU]> {
4624 let Inst{19-16} = Rn;
4625 let Inst{15-12} = 0b0000;
4626 let Inst{11-5} = shift{11-5};
4628 let Inst{3-0} = shift{3-0};
4630 let Unpredictable{15-12} = 0b1111;
4633 def CMNzrsr : AI1<0b1011, (outs),
4634 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4635 "cmn", "\t$Rn, $shift",
4636 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4637 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4638 Sched<[WriteCMPsr, ReadALU]> {
4643 let Inst{19-16} = Rn;
4644 let Inst{15-12} = 0b0000;
4645 let Inst{11-8} = shift{11-8};
4647 let Inst{6-5} = shift{6-5};
4649 let Inst{3-0} = shift{3-0};
4651 let Unpredictable{15-12} = 0b1111;
4656 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4657 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4659 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4660 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4662 // Note that TST/TEQ don't set all the same flags that CMP does!
4663 defm TST : AI1_cmp_irs<0b1000, "tst",
4664 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4665 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4666 "DecodeTSTInstruction">;
4667 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4668 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4669 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4671 // Pseudo i64 compares for some floating point compares.
4672 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4674 def BCCi64 : PseudoInst<(outs),
4675 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4677 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4680 def BCCZi64 : PseudoInst<(outs),
4681 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4682 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4684 } // usesCustomInserter
4687 // Conditional moves
4688 let hasSideEffects = 0 in {
4690 let isCommutable = 1, isSelect = 1 in
4691 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4692 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4694 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4696 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4698 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4699 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4702 (ARMcmov GPR:$false, so_reg_imm:$shift,
4704 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4705 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4706 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4708 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4710 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4713 let isMoveImm = 1 in
4715 : ARMPseudoInst<(outs GPR:$Rd),
4716 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4718 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4720 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4723 let isMoveImm = 1 in
4724 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4725 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4727 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4729 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4731 // Two instruction predicate mov immediate.
4732 let isMoveImm = 1 in
4734 : ARMPseudoInst<(outs GPR:$Rd),
4735 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4737 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4739 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4741 let isMoveImm = 1 in
4742 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4743 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4745 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4747 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4752 //===----------------------------------------------------------------------===//
4753 // Atomic operations intrinsics
4756 def MemBarrierOptOperand : AsmOperandClass {
4757 let Name = "MemBarrierOpt";
4758 let ParserMethod = "parseMemBarrierOptOperand";
4760 def memb_opt : Operand<i32> {
4761 let PrintMethod = "printMemBOption";
4762 let ParserMatchClass = MemBarrierOptOperand;
4763 let DecoderMethod = "DecodeMemBarrierOption";
4766 def InstSyncBarrierOptOperand : AsmOperandClass {
4767 let Name = "InstSyncBarrierOpt";
4768 let ParserMethod = "parseInstSyncBarrierOptOperand";
4770 def instsyncb_opt : Operand<i32> {
4771 let PrintMethod = "printInstSyncBOption";
4772 let ParserMatchClass = InstSyncBarrierOptOperand;
4773 let DecoderMethod = "DecodeInstSyncBarrierOption";
4776 // Memory barriers protect the atomic sequences
4777 let hasSideEffects = 1 in {
4778 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4779 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4780 Requires<[IsARM, HasDB]> {
4782 let Inst{31-4} = 0xf57ff05;
4783 let Inst{3-0} = opt;
4786 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4787 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4788 Requires<[IsARM, HasDB]> {
4790 let Inst{31-4} = 0xf57ff04;
4791 let Inst{3-0} = opt;
4794 // ISB has only full system option
4795 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4796 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4797 Requires<[IsARM, HasDB]> {
4799 let Inst{31-4} = 0xf57ff06;
4800 let Inst{3-0} = opt;
4804 let usesCustomInserter = 1, Defs = [CPSR] in {
4806 // Pseudo instruction that combines movs + predicated rsbmi
4807 // to implement integer ABS
4808 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4811 let usesCustomInserter = 1 in {
4812 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4813 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4815 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4818 let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in {
4819 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs...
4820 // Copies N registers worth of memory from address %src to address %dst
4821 // and returns the incremented addresses. N scratch register will
4822 // be attached for the copy to use.
4823 def MEMCPY : PseudoInst<
4824 (outs GPR:$newdst, GPR:$newsrc),
4825 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
4827 [(set GPR:$newdst, GPR:$newsrc,
4828 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4831 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4832 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4835 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4836 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4839 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4840 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4843 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4844 (int_arm_strex node:$val, node:$ptr), [{
4845 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4848 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4849 (int_arm_strex node:$val, node:$ptr), [{
4850 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4853 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4854 (int_arm_strex node:$val, node:$ptr), [{
4855 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4858 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4859 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4862 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4863 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4866 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4867 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4870 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4871 (int_arm_stlex node:$val, node:$ptr), [{
4872 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4875 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4876 (int_arm_stlex node:$val, node:$ptr), [{
4877 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4880 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4881 (int_arm_stlex node:$val, node:$ptr), [{
4882 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4885 let mayLoad = 1 in {
4886 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4887 NoItinerary, "ldrexb", "\t$Rt, $addr",
4888 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4889 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4890 NoItinerary, "ldrexh", "\t$Rt, $addr",
4891 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4892 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4893 NoItinerary, "ldrex", "\t$Rt, $addr",
4894 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4895 let hasExtraDefRegAllocReq = 1 in
4896 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4897 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4898 let DecoderMethod = "DecodeDoubleRegLoad";
4901 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4902 NoItinerary, "ldaexb", "\t$Rt, $addr",
4903 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4904 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4905 NoItinerary, "ldaexh", "\t$Rt, $addr",
4906 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4907 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4908 NoItinerary, "ldaex", "\t$Rt, $addr",
4909 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4910 let hasExtraDefRegAllocReq = 1 in
4911 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4912 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4913 let DecoderMethod = "DecodeDoubleRegLoad";
4917 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4918 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4919 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4920 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4921 addr_offset_none:$addr))]>;
4922 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4923 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4924 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4925 addr_offset_none:$addr))]>;
4926 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4927 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4928 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4929 addr_offset_none:$addr))]>;
4930 let hasExtraSrcRegAllocReq = 1 in
4931 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4932 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4933 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4934 let DecoderMethod = "DecodeDoubleRegStore";
4936 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4937 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4939 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4940 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4941 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4943 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4944 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4945 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4947 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4948 let hasExtraSrcRegAllocReq = 1 in
4949 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4950 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4951 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4952 let DecoderMethod = "DecodeDoubleRegStore";
4956 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4958 Requires<[IsARM, HasV6K]> {
4959 let Inst{31-0} = 0b11110101011111111111000000011111;
4962 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4963 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4964 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4965 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4967 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4968 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4969 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4970 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4972 class acquiring_load<PatFrag base>
4973 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4974 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4975 return isAcquireOrStronger(Ordering);
4978 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4979 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4980 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4982 class releasing_store<PatFrag base>
4983 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4984 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4985 return isReleaseOrStronger(Ordering);
4988 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4989 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4990 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4992 let AddedComplexity = 8 in {
4993 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4994 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4995 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4996 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4997 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4998 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
5001 // SWP/SWPB are deprecated in V6/V7 and optional in v7VE.
5002 // FIXME Use InstAlias to generate LDREX/STREX pairs instead.
5003 let mayLoad = 1, mayStore = 1 in {
5004 def SWP : AIswp<0, (outs GPRnopc:$Rt),
5005 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
5006 Requires<[IsARM,PreV8]>;
5007 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
5008 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
5009 Requires<[IsARM,PreV8]>;
5012 //===----------------------------------------------------------------------===//
5013 // Coprocessor Instructions.
5016 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5017 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5018 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5019 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
5020 imm:$CRm, imm:$opc2)]>,
5021 Requires<[IsARM,PreV8]> {
5029 let Inst{3-0} = CRm;
5031 let Inst{7-5} = opc2;
5032 let Inst{11-8} = cop;
5033 let Inst{15-12} = CRd;
5034 let Inst{19-16} = CRn;
5035 let Inst{23-20} = opc1;
5038 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5039 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5040 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5041 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
5042 imm:$CRm, imm:$opc2)]>,
5043 Requires<[IsARM,PreV8]> {
5044 let Inst{31-28} = 0b1111;
5052 let Inst{3-0} = CRm;
5054 let Inst{7-5} = opc2;
5055 let Inst{11-8} = cop;
5056 let Inst{15-12} = CRd;
5057 let Inst{19-16} = CRn;
5058 let Inst{23-20} = opc1;
5061 class ACI<dag oops, dag iops, string opc, string asm,
5062 list<dag> pattern, IndexMode im = IndexModeNone>
5063 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
5064 opc, asm, "", pattern> {
5065 let Inst{27-25} = 0b110;
5067 class ACInoP<dag oops, dag iops, string opc, string asm,
5068 list<dag> pattern, IndexMode im = IndexModeNone>
5069 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
5070 opc, asm, "", pattern> {
5071 let Inst{31-28} = 0b1111;
5072 let Inst{27-25} = 0b110;
5074 multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
5075 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
5076 asm, "\t$cop, $CRd, $addr", pattern> {
5080 let Inst{24} = 1; // P = 1
5081 let Inst{23} = addr{8};
5082 let Inst{22} = Dbit;
5083 let Inst{21} = 0; // W = 0
5084 let Inst{20} = load;
5085 let Inst{19-16} = addr{12-9};
5086 let Inst{15-12} = CRd;
5087 let Inst{11-8} = cop;
5088 let Inst{7-0} = addr{7-0};
5089 let DecoderMethod = "DecodeCopMemInstruction";
5091 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5092 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
5096 let Inst{24} = 1; // P = 1
5097 let Inst{23} = addr{8};
5098 let Inst{22} = Dbit;
5099 let Inst{21} = 1; // W = 1
5100 let Inst{20} = load;
5101 let Inst{19-16} = addr{12-9};
5102 let Inst{15-12} = CRd;
5103 let Inst{11-8} = cop;
5104 let Inst{7-0} = addr{7-0};
5105 let DecoderMethod = "DecodeCopMemInstruction";
5107 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
5108 postidx_imm8s4:$offset),
5109 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
5114 let Inst{24} = 0; // P = 0
5115 let Inst{23} = offset{8};
5116 let Inst{22} = Dbit;
5117 let Inst{21} = 1; // W = 1
5118 let Inst{20} = load;
5119 let Inst{19-16} = addr;
5120 let Inst{15-12} = CRd;
5121 let Inst{11-8} = cop;
5122 let Inst{7-0} = offset{7-0};
5123 let DecoderMethod = "DecodeCopMemInstruction";
5125 def _OPTION : ACI<(outs),
5126 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
5127 coproc_option_imm:$option),
5128 asm, "\t$cop, $CRd, $addr, $option", []> {
5133 let Inst{24} = 0; // P = 0
5134 let Inst{23} = 1; // U = 1
5135 let Inst{22} = Dbit;
5136 let Inst{21} = 0; // W = 0
5137 let Inst{20} = load;
5138 let Inst{19-16} = addr;
5139 let Inst{15-12} = CRd;
5140 let Inst{11-8} = cop;
5141 let Inst{7-0} = option;
5142 let DecoderMethod = "DecodeCopMemInstruction";
5145 multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
5146 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
5147 asm, "\t$cop, $CRd, $addr", pattern> {
5151 let Inst{24} = 1; // P = 1
5152 let Inst{23} = addr{8};
5153 let Inst{22} = Dbit;
5154 let Inst{21} = 0; // W = 0
5155 let Inst{20} = load;
5156 let Inst{19-16} = addr{12-9};
5157 let Inst{15-12} = CRd;
5158 let Inst{11-8} = cop;
5159 let Inst{7-0} = addr{7-0};
5160 let DecoderMethod = "DecodeCopMemInstruction";
5162 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5163 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
5167 let Inst{24} = 1; // P = 1
5168 let Inst{23} = addr{8};
5169 let Inst{22} = Dbit;
5170 let Inst{21} = 1; // W = 1
5171 let Inst{20} = load;
5172 let Inst{19-16} = addr{12-9};
5173 let Inst{15-12} = CRd;
5174 let Inst{11-8} = cop;
5175 let Inst{7-0} = addr{7-0};
5176 let DecoderMethod = "DecodeCopMemInstruction";
5178 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
5179 postidx_imm8s4:$offset),
5180 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
5185 let Inst{24} = 0; // P = 0
5186 let Inst{23} = offset{8};
5187 let Inst{22} = Dbit;
5188 let Inst{21} = 1; // W = 1
5189 let Inst{20} = load;
5190 let Inst{19-16} = addr;
5191 let Inst{15-12} = CRd;
5192 let Inst{11-8} = cop;
5193 let Inst{7-0} = offset{7-0};
5194 let DecoderMethod = "DecodeCopMemInstruction";
5196 def _OPTION : ACInoP<(outs),
5197 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
5198 coproc_option_imm:$option),
5199 asm, "\t$cop, $CRd, $addr, $option", []> {
5204 let Inst{24} = 0; // P = 0
5205 let Inst{23} = 1; // U = 1
5206 let Inst{22} = Dbit;
5207 let Inst{21} = 0; // W = 0
5208 let Inst{20} = load;
5209 let Inst{19-16} = addr;
5210 let Inst{15-12} = CRd;
5211 let Inst{11-8} = cop;
5212 let Inst{7-0} = option;
5213 let DecoderMethod = "DecodeCopMemInstruction";
5217 defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
5218 defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
5219 defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5220 defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5222 defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
5223 defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
5224 defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5225 defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5227 //===----------------------------------------------------------------------===//
5228 // Move between coprocessor and ARM core register.
5231 class MovRCopro<string opc, bit direction, dag oops, dag iops,
5233 : ABI<0b1110, oops, iops, NoItinerary, opc,
5234 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
5235 let Inst{20} = direction;
5245 let Inst{15-12} = Rt;
5246 let Inst{11-8} = cop;
5247 let Inst{23-21} = opc1;
5248 let Inst{7-5} = opc2;
5249 let Inst{3-0} = CRm;
5250 let Inst{19-16} = CRn;
5253 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5255 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5256 c_imm:$CRm, imm0_7:$opc2),
5257 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5258 imm:$CRm, imm:$opc2)]>,
5259 ComplexDeprecationPredicate<"MCR">;
5260 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5261 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5262 c_imm:$CRm, 0, pred:$p)>;
5263 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5264 (outs GPRwithAPSR:$Rt),
5265 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5267 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5268 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5269 c_imm:$CRm, 0, pred:$p)>;
5271 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5272 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5274 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5276 : ABXI<0b1110, oops, iops, NoItinerary,
5277 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5278 let Inst{31-24} = 0b11111110;
5279 let Inst{20} = direction;
5289 let Inst{15-12} = Rt;
5290 let Inst{11-8} = cop;
5291 let Inst{23-21} = opc1;
5292 let Inst{7-5} = opc2;
5293 let Inst{3-0} = CRm;
5294 let Inst{19-16} = CRn;
5297 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5299 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5300 c_imm:$CRm, imm0_7:$opc2),
5301 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5302 imm:$CRm, imm:$opc2)]>,
5303 Requires<[IsARM,PreV8]>;
5304 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5305 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5307 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5308 (outs GPRwithAPSR:$Rt),
5309 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5311 Requires<[IsARM,PreV8]>;
5312 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5313 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5316 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5317 imm:$CRm, imm:$opc2),
5318 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5320 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5322 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5325 let Inst{23-21} = 0b010;
5326 let Inst{20} = direction;
5334 let Inst{15-12} = Rt;
5335 let Inst{19-16} = Rt2;
5336 let Inst{11-8} = cop;
5337 let Inst{7-4} = opc1;
5338 let Inst{3-0} = CRm;
5341 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5342 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5343 GPRnopc:$Rt2, c_imm:$CRm),
5344 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5345 GPRnopc:$Rt2, imm:$CRm)]>;
5346 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5347 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5348 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5350 class MovRRCopro2<string opc, bit direction, dag oops, dag iops,
5351 list<dag> pattern = []>
5352 : ABXI<0b1100, oops, iops, NoItinerary,
5353 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5354 Requires<[IsARM,PreV8]> {
5355 let Inst{31-28} = 0b1111;
5356 let Inst{23-21} = 0b010;
5357 let Inst{20} = direction;
5365 let Inst{15-12} = Rt;
5366 let Inst{19-16} = Rt2;
5367 let Inst{11-8} = cop;
5368 let Inst{7-4} = opc1;
5369 let Inst{3-0} = CRm;
5371 let DecoderMethod = "DecoderForMRRC2AndMCRR2";
5374 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5375 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5376 GPRnopc:$Rt2, c_imm:$CRm),
5377 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5378 GPRnopc:$Rt2, imm:$CRm)]>;
5380 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */,
5381 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5382 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5384 //===----------------------------------------------------------------------===//
5385 // Move between special register and ARM core register
5388 // Move to ARM core register from Special Register
5389 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5390 "mrs", "\t$Rd, apsr", []> {
5392 let Inst{23-16} = 0b00001111;
5393 let Unpredictable{19-17} = 0b111;
5395 let Inst{15-12} = Rd;
5397 let Inst{11-0} = 0b000000000000;
5398 let Unpredictable{11-0} = 0b110100001111;
5401 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,
5404 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5405 // section B9.3.9, with the R bit set to 1.
5406 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5407 "mrs", "\t$Rd, spsr", []> {
5409 let Inst{23-16} = 0b01001111;
5410 let Unpredictable{19-16} = 0b1111;
5412 let Inst{15-12} = Rd;
5414 let Inst{11-0} = 0b000000000000;
5415 let Unpredictable{11-0} = 0b110100001111;
5418 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5419 // separate encoding (distinguished by bit 5.
5420 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5421 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5422 Requires<[IsARM, HasVirtualization]> {
5427 let Inst{22} = banked{5}; // R bit
5428 let Inst{21-20} = 0b00;
5429 let Inst{19-16} = banked{3-0};
5430 let Inst{15-12} = Rd;
5431 let Inst{11-9} = 0b001;
5432 let Inst{8} = banked{4};
5433 let Inst{7-0} = 0b00000000;
5436 // Move from ARM core register to Special Register
5438 // No need to have both system and application versions of MSR (immediate) or
5439 // MSR (register), the encodings are the same and the assembly parser has no way
5440 // to distinguish between them. The mask operand contains the special register
5441 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5442 // accessed in the special register.
5443 let Defs = [CPSR] in
5444 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5445 "msr", "\t$mask, $Rn", []> {
5450 let Inst{22} = mask{4}; // R bit
5451 let Inst{21-20} = 0b10;
5452 let Inst{19-16} = mask{3-0};
5453 let Inst{15-12} = 0b1111;
5454 let Inst{11-4} = 0b00000000;
5458 let Defs = [CPSR] in
5459 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5460 "msr", "\t$mask, $imm", []> {
5465 let Inst{22} = mask{4}; // R bit
5466 let Inst{21-20} = 0b10;
5467 let Inst{19-16} = mask{3-0};
5468 let Inst{15-12} = 0b1111;
5469 let Inst{11-0} = imm;
5472 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5473 // separate encoding (distinguished by bit 5.
5474 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5475 NoItinerary, "msr", "\t$banked, $Rn", []>,
5476 Requires<[IsARM, HasVirtualization]> {
5481 let Inst{22} = banked{5}; // R bit
5482 let Inst{21-20} = 0b10;
5483 let Inst{19-16} = banked{3-0};
5484 let Inst{15-12} = 0b1111;
5485 let Inst{11-9} = 0b001;
5486 let Inst{8} = banked{4};
5487 let Inst{7-4} = 0b0000;
5491 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5492 // are needed to probe the stack when allocating more than
5493 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5494 // ensure that the guard pages used by the OS virtual memory manager are
5495 // allocated in correct sequence.
5496 // The main point of having separate instruction are extra unmodelled effects
5497 // (compared to ordinary calls) like stack pointer change.
5499 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5500 [SDNPHasChain, SDNPSideEffect]>;
5501 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5502 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5504 def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK,
5505 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
5506 let usesCustomInserter = 1, Defs = [CPSR] in
5507 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary,
5508 [(win__dbzchk tGPR:$divisor)]>;
5510 //===----------------------------------------------------------------------===//
5514 // __aeabi_read_tp preserves the registers r1-r3.
5515 // This is a pseudo inst so that we can get the encoding right,
5516 // complete with fixup for the aeabi_read_tp function.
5517 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5518 // is defined in "ARMInstrThumb.td".
5520 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5521 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5522 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5525 //===----------------------------------------------------------------------===//
5526 // SJLJ Exception handling intrinsics
5527 // eh_sjlj_setjmp() is an instruction sequence to store the return
5528 // address and save #0 in R0 for the non-longjmp case.
5529 // Since by its nature we may be coming from some other function to get
5530 // here, and we're using the stack frame for the containing function to
5531 // save/restore registers, we can't keep anything live in regs across
5532 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5533 // when we get here from a longjmp(). We force everything out of registers
5534 // except for our own input by listing the relevant registers in Defs. By
5535 // doing so, we also cause the prologue/epilogue code to actively preserve
5536 // all of the callee-saved resgisters, which is exactly what we want.
5537 // A constant value is passed in $val, and we use the location as a scratch.
5539 // These are pseudo-instructions and are lowered to individual MC-insts, so
5540 // no encoding information is necessary.
5542 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5543 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5544 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5545 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5547 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5548 Requires<[IsARM, HasVFP2]>;
5552 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5553 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5554 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5556 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5557 Requires<[IsARM, NoVFP]>;
5560 // FIXME: Non-IOS version(s)
5561 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5562 Defs = [ R7, LR, SP ] in {
5563 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5565 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5569 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
5570 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
5571 [(ARMeh_sjlj_setup_dispatch)]>;
5573 // eh.sjlj.dispatchsetup pseudo-instruction.
5574 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5575 // the pseudo is expanded (which happens before any passes that need the
5576 // instruction size).
5577 let isBarrier = 1 in
5578 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5581 //===----------------------------------------------------------------------===//
5582 // Non-Instruction Patterns
5585 // ARMv4 indirect branch using (MOVr PC, dst)
5586 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5587 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5588 4, IIC_Br, [(brind GPR:$dst)],
5589 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5590 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5592 // Large immediate handling.
5594 // 32-bit immediate using two piece mod_imms or movw + movt.
5595 // This is a single pseudo instruction, the benefit is that it can be remat'd
5596 // as a single unit instead of having to handle reg inputs.
5597 // FIXME: Remove this when we can do generalized remat.
5598 let isReMaterializable = 1, isMoveImm = 1 in
5599 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5600 [(set GPR:$dst, (arm_i32imm:$src))]>,
5603 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5604 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5605 Requires<[IsARM, DontUseMovt]>;
5607 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5608 // It also makes it possible to rematerialize the instructions.
5609 // FIXME: Remove this when we can do generalized remat and when machine licm
5610 // can properly the instructions.
5611 let isReMaterializable = 1 in {
5612 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5614 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5615 Requires<[IsARM, UseMovt]>;
5617 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5620 (ARMWrapperPIC tglobaladdr:$addr))]>,
5621 Requires<[IsARM, DontUseMovt]>;
5623 let AddedComplexity = 10 in
5624 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5627 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5628 Requires<[IsARM, DontUseMovt]>;
5630 let AddedComplexity = 10 in
5631 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5633 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5634 Requires<[IsARM, UseMovt]>;
5635 } // isReMaterializable
5637 // The many different faces of TLS access.
5638 def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst),
5639 (MOVi32imm tglobaltlsaddr :$dst)>,
5640 Requires<[IsARM, UseMovt]>;
5642 def : Pat<(ARMWrapper tglobaltlsaddr:$src),
5643 (LDRLIT_ga_abs tglobaltlsaddr:$src)>,
5644 Requires<[IsARM, DontUseMovt]>;
5646 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
5647 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovt]>;
5649 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
5650 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
5651 Requires<[IsARM, DontUseMovt]>;
5652 let AddedComplexity = 10 in
5653 def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)),
5654 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>,
5655 Requires<[IsARM, UseMovt]>;
5658 // ConstantPool, GlobalAddress, and JumpTable
5659 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5660 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5661 Requires<[IsARM, UseMovt]>;
5662 def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>,
5663 Requires<[IsARM, UseMovt]>;
5664 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5665 (LEApcrelJT tjumptable:$dst)>;
5667 // TODO: add,sub,and, 3-instr forms?
5669 // Tail calls. These patterns also apply to Thumb mode.
5670 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5671 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5672 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5675 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5676 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5677 (BMOVPCB_CALL texternalsym:$func)>;
5679 // zextload i1 -> zextload i8
5680 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5681 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5683 // extload -> zextload
5684 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5685 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5686 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5687 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5689 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5691 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5692 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5695 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5696 (SMULBB GPR:$a, GPR:$b)>,
5697 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
5698 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5699 (SMULBT GPR:$a, GPR:$b)>,
5700 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
5701 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5702 (SMULTB GPR:$a, GPR:$b)>,
5703 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
5704 def : ARMV5MOPat<(add GPR:$acc,
5705 (mul sext_16_node:$a, sext_16_node:$b)),
5706 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>,
5707 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
5708 def : ARMV5MOPat<(add GPR:$acc,
5709 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5710 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>,
5711 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
5712 def : ARMV5MOPat<(add GPR:$acc,
5713 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5714 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>,
5715 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
5717 def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b),
5718 (SMULBB GPR:$a, GPR:$b)>;
5719 def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b),
5720 (SMULBT GPR:$a, GPR:$b)>;
5721 def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b),
5722 (SMULTB GPR:$a, GPR:$b)>;
5723 def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b),
5724 (SMULTT GPR:$a, GPR:$b)>;
5725 def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b),
5726 (SMULWB GPR:$a, GPR:$b)>;
5727 def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b),
5728 (SMULWT GPR:$a, GPR:$b)>;
5730 def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),
5731 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5732 def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),
5733 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5734 def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),
5735 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5736 def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),
5737 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>;
5738 def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),
5739 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5740 def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),
5741 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;
5743 // Pre-v7 uses MCR for synchronization barriers.
5744 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5745 Requires<[IsARM, HasV6]>;
5747 // SXT/UXT with no rotate
5748 let AddedComplexity = 16 in {
5749 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5750 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5751 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5752 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5753 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5754 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5755 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5758 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5759 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5761 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5762 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5763 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5764 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5766 // Atomic load/store patterns
5767 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5768 (LDRBrs ldst_so_reg:$src)>;
5769 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5770 (LDRBi12 addrmode_imm12:$src)>;
5771 def : ARMPat<(atomic_load_16 addrmode3:$src),
5772 (LDRH addrmode3:$src)>;
5773 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5774 (LDRrs ldst_so_reg:$src)>;
5775 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5776 (LDRi12 addrmode_imm12:$src)>;
5777 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5778 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5779 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5780 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5781 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5782 (STRH GPR:$val, addrmode3:$ptr)>;
5783 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5784 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5785 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5786 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5789 //===----------------------------------------------------------------------===//
5793 include "ARMInstrThumb.td"
5795 //===----------------------------------------------------------------------===//
5799 include "ARMInstrThumb2.td"
5801 //===----------------------------------------------------------------------===//
5802 // Floating Point Support
5805 include "ARMInstrVFP.td"
5807 //===----------------------------------------------------------------------===//
5808 // Advanced SIMD (NEON) Support
5811 include "ARMInstrNEON.td"
5813 //===----------------------------------------------------------------------===//
5814 // Assembler aliases
5818 def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
5819 def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
5820 def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
5822 // System instructions
5823 def : MnemonicAlias<"swi", "svc">;
5825 // Load / Store Multiple
5826 def : MnemonicAlias<"ldmfd", "ldm">;
5827 def : MnemonicAlias<"ldmia", "ldm">;
5828 def : MnemonicAlias<"ldmea", "ldmdb">;
5829 def : MnemonicAlias<"stmfd", "stmdb">;
5830 def : MnemonicAlias<"stmia", "stm">;
5831 def : MnemonicAlias<"stmea", "stm">;
5833 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
5834 // input operands swapped when the shift amount is zero (i.e., unspecified).
5835 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5836 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
5837 Requires<[IsARM, HasV6]>;
5838 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5839 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
5840 Requires<[IsARM, HasV6]>;
5842 // PUSH/POP aliases for STM/LDM
5843 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5844 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5846 // SSAT/USAT optional shift operand.
5847 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5848 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5849 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5850 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5853 // Extend instruction optional rotate operand.
5854 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5855 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5856 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5857 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5858 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5859 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5860 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5861 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5862 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5863 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5864 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5865 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5867 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5868 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5869 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5870 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5871 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5872 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5873 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5874 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5875 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5876 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5877 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5878 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5882 def : MnemonicAlias<"rfefa", "rfeda">;
5883 def : MnemonicAlias<"rfeea", "rfedb">;
5884 def : MnemonicAlias<"rfefd", "rfeia">;
5885 def : MnemonicAlias<"rfeed", "rfeib">;
5886 def : MnemonicAlias<"rfe", "rfeia">;
5889 def : MnemonicAlias<"srsfa", "srsib">;
5890 def : MnemonicAlias<"srsea", "srsia">;
5891 def : MnemonicAlias<"srsfd", "srsdb">;
5892 def : MnemonicAlias<"srsed", "srsda">;
5893 def : MnemonicAlias<"srs", "srsia">;
5896 def : MnemonicAlias<"qsubaddx", "qsax">;
5898 def : MnemonicAlias<"saddsubx", "sasx">;
5899 // SHASX == SHADDSUBX
5900 def : MnemonicAlias<"shaddsubx", "shasx">;
5901 // SHSAX == SHSUBADDX
5902 def : MnemonicAlias<"shsubaddx", "shsax">;
5904 def : MnemonicAlias<"ssubaddx", "ssax">;
5906 def : MnemonicAlias<"uaddsubx", "uasx">;
5907 // UHASX == UHADDSUBX
5908 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5909 // UHSAX == UHSUBADDX
5910 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5911 // UQASX == UQADDSUBX
5912 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5913 // UQSAX == UQSUBADDX
5914 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5916 def : MnemonicAlias<"usubaddx", "usax">;
5918 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5920 def : ARMInstSubst<"mov${s}${p} $Rd, $imm",
5921 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5922 def : ARMInstSubst<"mvn${s}${p} $Rd, $imm",
5923 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5924 // Same for AND <--> BIC
5925 def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm",
5926 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5927 pred:$p, cc_out:$s)>;
5928 def : ARMInstSubst<"bic${s}${p} $Rdn, $imm",
5929 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5930 pred:$p, cc_out:$s)>;
5931 def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm",
5932 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5933 pred:$p, cc_out:$s)>;
5934 def : ARMInstSubst<"and${s}${p} $Rdn, $imm",
5935 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5936 pred:$p, cc_out:$s)>;
5938 // Likewise, "add Rd, mod_imm_neg" -> sub
5939 def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm",
5940 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5941 def : ARMInstSubst<"add${s}${p} $Rd, $imm",
5942 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5943 // Likewise, "sub Rd, mod_imm_neg" -> add
5944 def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm",
5945 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5946 def : ARMInstSubst<"sub${s}${p} $Rd, $imm",
5947 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5950 def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm",
5951 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5952 def : ARMInstSubst<"adc${s}${p} $Rdn, $imm",
5953 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5954 def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm",
5955 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5956 def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm",
5957 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5959 // Same for CMP <--> CMN via mod_imm_neg
5960 def : ARMInstSubst<"cmp${p} $Rd, $imm",
5961 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5962 def : ARMInstSubst<"cmn${p} $Rd, $imm",
5963 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5965 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5966 // LSR, ROR, and RRX instructions.
5967 // FIXME: We need C++ parser hooks to map the alias to the MOV
5968 // encoding. It seems we should be able to do that sort of thing
5969 // in tblgen, but it could get ugly.
5970 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5971 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5972 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5974 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5975 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5977 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5978 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5980 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5981 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5984 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5985 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5986 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5987 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5988 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5990 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5991 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5993 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5994 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5996 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5997 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6001 // "neg" is and alias for "rsb rd, rn, #0"
6002 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
6003 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
6005 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
6006 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
6007 Requires<[IsARM, NoV6]>;
6009 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6010 // the instruction definitions need difference constraints pre-v6.
6011 // Use these aliases for the assembly parsing on pre-v6.
6012 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
6013 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
6014 Requires<[IsARM, NoV6]>;
6015 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
6016 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
6017 pred:$p, cc_out:$s), 0>,
6018 Requires<[IsARM, NoV6]>;
6019 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6020 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6021 Requires<[IsARM, NoV6]>;
6022 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6023 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6024 Requires<[IsARM, NoV6]>;
6025 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6026 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6027 Requires<[IsARM, NoV6]>;
6028 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6029 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6030 Requires<[IsARM, NoV6]>;
6032 // 'it' blocks in ARM mode just validate the predicates. The IT itself
6034 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
6035 ComplexDeprecationPredicate<"IT">;
6037 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
6038 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6040 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;
6042 //===----------------------------------
6043 // Atomic cmpxchg for -O0
6044 //===----------------------------------
6046 // The fast register allocator used during -O0 inserts spills to cover any VRegs
6047 // live across basic block boundaries. When this happens between an LDXR and an
6048 // STXR it can clear the exclusive monitor, causing all cmpxchg attempts to
6051 // Unfortunately, this means we have to have an alternative (expanded
6052 // post-regalloc) path for -O0 compilations. Fortunately this path can be
6053 // significantly more naive than the standard expansion: we conservatively
6054 // assume seq_cst, strong cmpxchg and omit clrex on failure.
6056 let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",
6057 mayLoad = 1, mayStore = 1 in {
6058 def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6059 (ins GPR:$addr, GPR:$desired, GPR:$new),
6060 NoItinerary, []>, Sched<[]>;
6062 def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6063 (ins GPR:$addr, GPR:$desired, GPR:$new),
6064 NoItinerary, []>, Sched<[]>;
6066 def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6067 (ins GPR:$addr, GPR:$desired, GPR:$new),
6068 NoItinerary, []>, Sched<[]>;
6070 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
6071 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new),
6072 NoItinerary, []>, Sched<[]>;
6075 def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary,
6076 [(atomic_fence imm:$ordering, 0)]> {
6077 let hasSideEffects = 1;
6079 let AsmString = "@ COMPILER BARRIER";