1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def imm_sr_XFORM: SDNodeXForm<imm, [{
19 unsigned Imm = N->getZExtValue();
20 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
22 def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; }
23 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
24 uint64_t Imm = N->getZExtValue();
25 return Imm > 0 && Imm <= 32;
27 let PrintMethod = "printThumbSRImm";
28 let ParserMatchClass = ThumbSRImmAsmOperand;
31 def imm0_7_neg : PatLeaf<(i32 imm), [{
32 return (uint32_t)-N->getZExtValue() < 8;
35 def ThumbModImmNeg1_7AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg1_7"; }
36 def mod_imm1_7_neg : Operand<i32>, PatLeaf<(imm), [{
37 unsigned Value = -(unsigned)N->getZExtValue();
38 return 0 < Value && Value < 8;
40 let ParserMatchClass = ThumbModImmNeg1_7AsmOperand;
43 def ThumbModImmNeg8_255AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg8_255"; }
44 def mod_imm8_255_neg : Operand<i32>, PatLeaf<(imm), [{
45 unsigned Value = -(unsigned)N->getZExtValue();
46 return 7 < Value && Value < 256;
48 let ParserMatchClass = ThumbModImmNeg8_255AsmOperand;
52 def imm0_255_comp : PatLeaf<(i32 imm), [{
53 return ~((uint32_t)N->getZExtValue()) < 256;
56 def imm8_255_neg : PatLeaf<(i32 imm), [{
57 unsigned Val = -N->getZExtValue();
58 return Val >= 8 && Val < 256;
61 // Break imm's up into two pieces: an immediate + a left shift. This uses
62 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
63 // to get the val/shift pieces.
64 def thumb_immshifted : PatLeaf<(imm), [{
65 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
68 def thumb_immshifted_val : SDNodeXForm<imm, [{
69 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
70 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
73 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
74 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
75 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
78 def imm256_510 : ImmLeaf<i32, [{
79 return Imm >= 256 && Imm < 511;
82 def thumb_imm256_510_addend : SDNodeXForm<imm, [{
83 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);
86 // Scaled 4 immediate.
87 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
88 def t_imm0_1020s4 : Operand<i32> {
89 let PrintMethod = "printThumbS4ImmOperand";
90 let ParserMatchClass = t_imm0_1020s4_asmoperand;
91 let OperandType = "OPERAND_IMMEDIATE";
94 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
95 def t_imm0_508s4 : Operand<i32> {
96 let PrintMethod = "printThumbS4ImmOperand";
97 let ParserMatchClass = t_imm0_508s4_asmoperand;
98 let OperandType = "OPERAND_IMMEDIATE";
100 // Alias use only, so no printer is necessary.
101 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
102 def t_imm0_508s4_neg : Operand<i32> {
103 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
104 let OperandType = "OPERAND_IMMEDIATE";
107 // Define Thumb specific addressing modes.
109 // unsigned 8-bit, 2-scaled memory offset
110 class OperandUnsignedOffset_b8s2 : AsmOperandClass {
111 let Name = "UnsignedOffset_b8s2";
112 let PredicateMethod = "isUnsignedOffset<8, 2>";
115 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
117 // thumb style PC relative operand. signed, 8 bits magnitude,
118 // two bits shift. can be represented as either [pc, #imm], #imm,
119 // or relocatable expression...
120 def ThumbMemPC : AsmOperandClass {
121 let Name = "ThumbMemPC";
124 let OperandType = "OPERAND_PCREL" in {
125 def t_brtarget : Operand<OtherVT> {
126 let EncoderMethod = "getThumbBRTargetOpValue";
127 let DecoderMethod = "DecodeThumbBROperand";
130 // ADR instruction labels.
131 def t_adrlabel : Operand<i32> {
132 let EncoderMethod = "getThumbAdrLabelOpValue";
133 let PrintMethod = "printAdrLabelOperand<2>";
134 let ParserMatchClass = UnsignedOffset_b8s2;
138 def thumb_br_target : Operand<OtherVT> {
139 let ParserMatchClass = ThumbBranchTarget;
140 let EncoderMethod = "getThumbBranchTargetOpValue";
141 let OperandType = "OPERAND_PCREL";
144 def thumb_bl_target : Operand<i32> {
145 let ParserMatchClass = ThumbBranchTarget;
146 let EncoderMethod = "getThumbBLTargetOpValue";
147 let DecoderMethod = "DecodeThumbBLTargetOperand";
150 // Target for BLX *from* thumb mode.
151 def thumb_blx_target : Operand<i32> {
152 let ParserMatchClass = ARMBranchTarget;
153 let EncoderMethod = "getThumbBLXTargetOpValue";
154 let DecoderMethod = "DecodeThumbBLXOffset";
157 def thumb_bcc_target : Operand<OtherVT> {
158 let ParserMatchClass = ThumbBranchTarget;
159 let EncoderMethod = "getThumbBCCTargetOpValue";
160 let DecoderMethod = "DecodeThumbBCCTargetOperand";
163 def thumb_cb_target : Operand<OtherVT> {
164 let ParserMatchClass = ThumbBranchTarget;
165 let EncoderMethod = "getThumbCBTargetOpValue";
166 let DecoderMethod = "DecodeThumbCmpBROperand";
169 // t_addrmode_pc := <label> => pc + imm8 * 4
171 def t_addrmode_pc : MemOperand {
172 let EncoderMethod = "getAddrModePCOpValue";
173 let DecoderMethod = "DecodeThumbAddrModePC";
174 let PrintMethod = "printThumbLdrLabelOperand";
175 let ParserMatchClass = ThumbMemPC;
179 // t_addrmode_rr := reg + reg
181 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
182 def t_addrmode_rr : MemOperand,
183 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
184 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
185 let PrintMethod = "printThumbAddrModeRROperand";
186 let DecoderMethod = "DecodeThumbAddrModeRR";
187 let ParserMatchClass = t_addrmode_rr_asm_operand;
188 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
191 // t_addrmode_rrs := reg + reg
193 // We use separate scaled versions because the Select* functions need
194 // to explicitly check for a matching constant and return false here so that
195 // the reg+imm forms will match instead. This is a horrible way to do that,
196 // as it forces tight coupling between the methods, but it's how selectiondag
198 def t_addrmode_rrs1 : MemOperand,
199 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
200 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
201 let PrintMethod = "printThumbAddrModeRROperand";
202 let DecoderMethod = "DecodeThumbAddrModeRR";
203 let ParserMatchClass = t_addrmode_rr_asm_operand;
204 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
206 def t_addrmode_rrs2 : MemOperand,
207 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
208 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
209 let DecoderMethod = "DecodeThumbAddrModeRR";
210 let PrintMethod = "printThumbAddrModeRROperand";
211 let ParserMatchClass = t_addrmode_rr_asm_operand;
212 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
214 def t_addrmode_rrs4 : MemOperand,
215 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
216 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
217 let DecoderMethod = "DecodeThumbAddrModeRR";
218 let PrintMethod = "printThumbAddrModeRROperand";
219 let ParserMatchClass = t_addrmode_rr_asm_operand;
220 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
223 // t_addrmode_is4 := reg + imm5 * 4
225 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
226 def t_addrmode_is4 : MemOperand,
227 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
228 let EncoderMethod = "getAddrModeISOpValue";
229 let DecoderMethod = "DecodeThumbAddrModeIS";
230 let PrintMethod = "printThumbAddrModeImm5S4Operand";
231 let ParserMatchClass = t_addrmode_is4_asm_operand;
232 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
235 // t_addrmode_is2 := reg + imm5 * 2
237 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
238 def t_addrmode_is2 : MemOperand,
239 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
240 let EncoderMethod = "getAddrModeISOpValue";
241 let DecoderMethod = "DecodeThumbAddrModeIS";
242 let PrintMethod = "printThumbAddrModeImm5S2Operand";
243 let ParserMatchClass = t_addrmode_is2_asm_operand;
244 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
247 // t_addrmode_is1 := reg + imm5
249 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
250 def t_addrmode_is1 : MemOperand,
251 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
252 let EncoderMethod = "getAddrModeISOpValue";
253 let DecoderMethod = "DecodeThumbAddrModeIS";
254 let PrintMethod = "printThumbAddrModeImm5S1Operand";
255 let ParserMatchClass = t_addrmode_is1_asm_operand;
256 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
259 // t_addrmode_sp := sp + imm8 * 4
261 // FIXME: This really shouldn't have an explicit SP operand at all. It should
262 // be implicit, just like in the instruction encoding itself.
263 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
264 def t_addrmode_sp : MemOperand,
265 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
266 let EncoderMethod = "getAddrModeThumbSPOpValue";
267 let DecoderMethod = "DecodeThumbAddrModeSP";
268 let PrintMethod = "printThumbAddrModeSPOperand";
269 let ParserMatchClass = t_addrmode_sp_asm_operand;
270 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
273 //===----------------------------------------------------------------------===//
274 // Miscellaneous Instructions.
277 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
278 // from removing one half of the matched pairs. That breaks PEI, which assumes
279 // these will always be in pairs, and asserts if it finds otherwise. Better way?
280 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
281 def tADJCALLSTACKUP :
282 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
283 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
284 Requires<[IsThumb, IsThumb1Only]>;
286 def tADJCALLSTACKDOWN :
287 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
288 [(ARMcallseq_start imm:$amt)]>,
289 Requires<[IsThumb, IsThumb1Only]>;
292 class T1SystemEncoding<bits<8> opc>
293 : T1Encoding<0b101111> {
294 let Inst{9-8} = 0b11;
298 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
299 [(int_arm_hint imm0_15:$imm)]>,
300 T1SystemEncoding<0x00>,
301 Requires<[IsThumb, HasV6M]> {
306 // Note: When EmitPriority == 1, the alias will be used for printing
307 class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> {
308 let Predicates = [IsThumb, HasV6M];
311 def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110
312 def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410
313 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408
314 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409
315 def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157
316 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> {
317 let Predicates = [IsThumb2, HasV8];
320 // The imm operand $val can be used by a debugger to store more information
321 // about the breakpoint.
322 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
324 T1Encoding<0b101111> {
325 let Inst{9-8} = 0b10;
330 // default immediate for breakpoint mnemonic
331 def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>;
333 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
334 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
335 let Inst{9-6} = 0b1010;
340 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
341 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> {
344 let Inst{9-5} = 0b10010;
347 let Inst{2-0} = 0b000;
350 // Change Processor State is a system instruction -- for disassembly only.
351 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
352 NoItinerary, "cps$imod $iflags", []>,
360 let Inst{2-0} = iflags;
361 let DecoderMethod = "DecodeThumbCPS";
364 // For both thumb1 and thumb2.
365 let isNotDuplicable = 1, isCodeGenOnly = 1 in
366 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
367 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
368 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
371 let Inst{6-3} = 0b1111; // Rm = pc
375 // ADD <Rd>, sp, #<imm8>
376 // FIXME: This should not be marked as having side effects, and it should be
377 // rematerializable. Clearing the side effect bit causes miscompilations,
378 // probably because the instruction can be moved around.
379 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
380 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
381 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
385 let Inst{10-8} = dst;
387 let DecoderMethod = "DecodeThumbAddSpecialReg";
390 // Thumb1 frame lowering is rather fragile, we hope to be able to use
391 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
392 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),
394 Requires<[IsThumb, IsThumb1Only]> {
398 // ADD sp, sp, #<imm7>
399 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
400 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
401 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
405 let DecoderMethod = "DecodeThumbAddSPImm";
408 // SUB sp, sp, #<imm7>
409 // FIXME: The encoding and the ASM string don't match up.
410 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
411 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
412 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
416 let DecoderMethod = "DecodeThumbAddSPImm";
419 def : tInstSubst<"add${p} sp, $imm",
420 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
421 def : tInstSubst<"add${p} sp, sp, $imm",
422 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
424 // Can optionally specify SP as a three operand instruction.
425 def : tInstAlias<"add${p} sp, sp, $imm",
426 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
427 def : tInstAlias<"sub${p} sp, sp, $imm",
428 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
431 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
432 "add", "\t$Rdn, $sp, $Rn", []>,
433 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
434 // A8.6.9 Encoding T1
436 let Inst{7} = Rdn{3};
437 let Inst{6-3} = 0b1101;
438 let Inst{2-0} = Rdn{2-0};
439 let DecoderMethod = "DecodeThumbAddSPReg";
443 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
444 "add", "\t$Rdn, $Rm", []>,
445 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
446 // A8.6.9 Encoding T2
450 let Inst{2-0} = 0b101;
451 let DecoderMethod = "DecodeThumbAddSPReg";
454 //===----------------------------------------------------------------------===//
455 // Control Flow Instructions.
459 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
460 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
461 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
465 let Inst{2-0} = 0b000;
466 let Unpredictable{2-0} = 0b111;
468 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
469 Requires<[IsThumb, Has8MSecExt]>,
470 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
473 let Inst{2-0} = 0b100;
474 let Unpredictable{1-0} = 0b11;
478 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
479 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
480 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
482 // Alternative return instruction used by vararg functions.
483 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
485 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
488 // All calls clobber the non-callee saved registers. SP is marked as a use to
489 // prevent stack-pointer assignments that appear immediately before calls from
490 // potentially appearing dead.
492 Defs = [LR], Uses = [SP] in {
493 // Also used for Thumb2
494 def tBL : TIx2<0b11110, 0b11, 1,
495 (outs), (ins pred:$p, thumb_bl_target:$func), IIC_Br,
497 [(ARMcall tglobaladdr:$func)]>,
498 Requires<[IsThumb]>, Sched<[WriteBrL]> {
500 let Inst{26} = func{23};
501 let Inst{25-16} = func{20-11};
502 let Inst{13} = func{22};
503 let Inst{11} = func{21};
504 let Inst{10-0} = func{10-0};
507 // ARMv5T and above, also used for Thumb2
508 def tBLXi : TIx2<0b11110, 0b11, 0,
509 (outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br,
510 "blx${p}\t$func", []>,
511 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
513 let Inst{26} = func{23};
514 let Inst{25-16} = func{20-11};
515 let Inst{13} = func{22};
516 let Inst{11} = func{21};
517 let Inst{10-1} = func{10-1};
518 let Inst{0} = 0; // func{0} is assumed zero
521 // Also used for Thumb2
522 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
524 [(ARMcall GPR:$func)]>,
525 Requires<[IsThumb, HasV5T]>,
526 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
528 let Inst{6-3} = func;
529 let Inst{2-0} = 0b000;
532 // ARMv8-M Security Extensions
533 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br,
534 "blxns${p}\t$func", []>,
535 Requires<[IsThumb, Has8MSecExt]>,
536 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
538 let Inst{6-3} = func;
539 let Inst{2-0} = 0b100;
540 let Unpredictable{1-0} = 0b11;
544 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
546 [(ARMcall_nolink tGPR:$func)]>,
547 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
550 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
551 let isPredicable = 1 in
552 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
553 "b", "\t$target", [(br bb:$target)]>,
554 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
556 let Inst{10-0} = target;
557 let AsmMatchConverter = "cvtThumbBranches";
561 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
562 // the clobber of LR.
564 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p),
566 (tBL pred:$p, thumb_bl_target:$target)>,
569 def tBR_JTr : tPseudoInst<(outs),
570 (ins tGPR:$target, i32imm:$jt),
572 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>,
573 Sched<[WriteBrTbl]> {
575 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
579 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
580 // a two-value operand where a dag node expects two operands. :(
581 let isBranch = 1, isTerminator = 1 in
582 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br,
584 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
585 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
589 let Inst{7-0} = target;
590 let AsmMatchConverter = "cvtThumbBranches";
595 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
598 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
600 (tBX GPR:$dst, (ops 14, zero_reg))>,
601 Requires<[IsThumb]>, Sched<[WriteBr]>;
603 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls
604 // on MachO), so it's in ARMInstrThumb2.td.
605 // Non-MachO version:
607 def tTAILJMPdND : tPseudoExpand<(outs),
608 (ins t_brtarget:$dst, pred:$p),
610 (tB t_brtarget:$dst, pred:$p)>,
611 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
616 // A8.6.218 Supervisor Call (Software Interrupt)
617 // A8.6.16 B: Encoding T1
618 // If Inst{11-8} == 0b1111 then SEE SVC
619 let isCall = 1, Uses = [SP] in
620 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
621 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
623 let Inst{15-12} = 0b1101;
624 let Inst{11-8} = 0b1111;
628 // The assembler uses 0xDEFE for a trap instruction.
629 let isBarrier = 1, isTerminator = 1 in
630 def tTRAP : TI<(outs), (ins), IIC_Br,
631 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
635 //===----------------------------------------------------------------------===//
636 // Load Store Instructions.
639 // PC-relative loads need to be matched first as constant pool accesses need to
640 // always be PC-relative. We do this using AddedComplexity, as the pattern is
641 // simpler than the patterns of the other load instructions.
642 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in
643 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
644 "ldr", "\t$Rt, $addr",
645 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
646 T1Encoding<{0,1,0,0,1,?}> {
651 let Inst{7-0} = addr;
654 // SP-relative loads should be matched before standard immediate-offset loads as
655 // it means we avoid having to move SP to another register.
656 let canFoldAsLoad = 1 in
657 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
658 "ldr", "\t$Rt, $addr",
659 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
664 let Inst{7-0} = addr;
667 // Loads: reg/reg and reg/imm5
668 let canFoldAsLoad = 1, isReMaterializable = 1 in
669 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
670 Operand AddrMode_r, Operand AddrMode_i,
671 AddrMode am, InstrItinClass itin_r,
672 InstrItinClass itin_i, string asm,
674 // Immediate-offset loads should be matched before register-offset loads as
675 // when the offset is a constant it's simpler to first check if it fits in the
676 // immediate offset field then fall back to register-offset if it doesn't.
678 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
679 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
680 am, itin_i, asm, "\t$Rt, $addr",
681 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
682 // Register-offset loads are matched last.
684 T1pILdStEncode<reg_opc,
685 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
686 am, itin_r, asm, "\t$Rt, $addr",
687 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
689 // Stores: reg/reg and reg/imm5
690 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
691 Operand AddrMode_r, Operand AddrMode_i,
692 AddrMode am, InstrItinClass itin_r,
693 InstrItinClass itin_i, string asm,
696 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
697 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
698 am, itin_i, asm, "\t$Rt, $addr",
699 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
701 T1pILdStEncode<reg_opc,
702 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
703 am, itin_r, asm, "\t$Rt, $addr",
704 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
708 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr,
709 t_addrmode_is4, AddrModeT1_4,
710 IIC_iLoad_r, IIC_iLoad_i, "ldr",
714 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr,
715 t_addrmode_is1, AddrModeT1_1,
716 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
720 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr,
721 t_addrmode_is2, AddrModeT1_2,
722 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
725 let AddedComplexity = 10 in
726 def tLDRSB : // A8.6.80
727 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
728 AddrModeT1_1, IIC_iLoad_bh_r,
729 "ldrsb", "\t$Rt, $addr",
730 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
732 let AddedComplexity = 10 in
733 def tLDRSH : // A8.6.84
734 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
735 AddrModeT1_2, IIC_iLoad_bh_r,
736 "ldrsh", "\t$Rt, $addr",
737 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
740 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
741 "str", "\t$Rt, $addr",
742 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
747 let Inst{7-0} = addr;
750 // A8.6.194 & A8.6.192
751 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr,
752 t_addrmode_is4, AddrModeT1_4,
753 IIC_iStore_r, IIC_iStore_i, "str",
756 // A8.6.197 & A8.6.195
757 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr,
758 t_addrmode_is1, AddrModeT1_1,
759 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
762 // A8.6.207 & A8.6.205
763 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr,
764 t_addrmode_is2, AddrModeT1_2,
765 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
769 //===----------------------------------------------------------------------===//
770 // Load / store multiple Instructions.
773 // These require base address to be written back or one of the loaded regs.
774 let hasSideEffects = 0 in {
776 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
777 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
778 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
782 let Inst{7-0} = regs;
785 // Writeback version is just a pseudo, as there's no encoding difference.
786 // Writeback happens iff the base register is not in the destination register
788 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
790 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
791 "$Rn = $wb", IIC_iLoad_mu>,
792 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
794 let OutOperandList = (outs GPR:$wb);
795 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
797 let isCodeGenOnly = 1;
799 list<Predicate> Predicates = [IsThumb];
802 // There is no non-writeback version of STM for Thumb.
803 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
804 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
805 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
806 AddrModeNone, 2, IIC_iStore_mu,
807 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
808 T1Encoding<{1,1,0,0,0,?}> {
812 let Inst{7-0} = regs;
817 def : InstAlias<"ldm${p} $Rn!, $regs",
818 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
819 Requires<[IsThumb, IsThumb1Only]>;
821 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
822 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
824 "pop${p}\t$regs", []>,
825 T1Misc<{1,1,0,?,?,?,?}> {
827 let Inst{8} = regs{15};
828 let Inst{7-0} = regs{7-0};
831 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
832 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
834 "push${p}\t$regs", []>,
835 T1Misc<{0,1,0,?,?,?,?}> {
837 let Inst{8} = regs{14};
838 let Inst{7-0} = regs{7-0};
841 //===----------------------------------------------------------------------===//
842 // Arithmetic Instructions.
845 // Helper classes for encoding T1pI patterns:
846 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
847 string opc, string asm, list<dag> pattern>
848 : T1pI<oops, iops, itin, opc, asm, pattern>,
849 T1DataProcessing<opA> {
855 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
856 string opc, string asm, list<dag> pattern>
857 : T1pI<oops, iops, itin, opc, asm, pattern>,
865 // Helper classes for encoding T1sI patterns:
866 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
867 string opc, string asm, list<dag> pattern>
868 : T1sI<oops, iops, itin, opc, asm, pattern>,
869 T1DataProcessing<opA> {
875 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
876 string opc, string asm, list<dag> pattern>
877 : T1sI<oops, iops, itin, opc, asm, pattern>,
886 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
887 string opc, string asm, list<dag> pattern>
888 : T1sI<oops, iops, itin, opc, asm, pattern>,
896 // Helper classes for encoding T1sIt patterns:
897 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
898 string opc, string asm, list<dag> pattern>
899 : T1sIt<oops, iops, itin, opc, asm, pattern>,
900 T1DataProcessing<opA> {
906 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
907 string opc, string asm, list<dag> pattern>
908 : T1sIt<oops, iops, itin, opc, asm, pattern>,
912 let Inst{10-8} = Rdn;
913 let Inst{7-0} = imm8;
917 // Add with carry register
918 let isCommutable = 1, Uses = [CPSR] in
920 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
921 "adc", "\t$Rdn, $Rm",
922 []>, Sched<[WriteALU]>;
925 def tADDi3 : // A8.6.4 T1
926 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
928 "add", "\t$Rd, $Rm, $imm3",
929 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
932 let Inst{8-6} = imm3;
935 def tADDi8 : // A8.6.4 T2
936 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
937 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
938 "add", "\t$Rdn, $imm8",
939 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
943 let isCommutable = 1 in
944 def tADDrr : // A8.6.6 T1
945 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
947 "add", "\t$Rd, $Rn, $Rm",
948 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
950 /// Similar to the above except these set the 's' bit so the
951 /// instruction modifies the CPSR register.
953 /// These opcodes will be converted to the real non-S opcodes by
954 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
955 let hasPostISelHook = 1, Defs = [CPSR] in {
956 let isCommutable = 1, Uses = [CPSR] in
957 def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
959 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
961 Requires<[IsThumb1Only]>,
964 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
966 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
968 Requires<[IsThumb1Only]>,
971 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
973 [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn,
975 Requires<[IsThumb1Only]>,
978 let isCommutable = 1 in
979 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
981 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,
983 Requires<[IsThumb1Only]>,
987 let hasSideEffects = 0 in
988 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
989 "add", "\t$Rdn, $Rm", []>,
990 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
994 let Inst{7} = Rdn{3};
996 let Inst{2-0} = Rdn{2-0};
1000 def : tInstSubst<"sub${s}${p} $rd, $rn, $imm",
1001 (tADDi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;
1002 def : tInstSubst<"sub${s}${p} $rdn, $imm",
1003 (tADDi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>;
1007 let isCommutable = 1 in
1008 def tAND : // A8.6.12
1009 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1011 "and", "\t$Rdn, $Rm",
1012 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1015 def tASRri : // A8.6.14
1016 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1018 "asr", "\t$Rd, $Rm, $imm5",
1019 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1022 let Inst{10-6} = imm5;
1026 def tASRrr : // A8.6.15
1027 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1029 "asr", "\t$Rdn, $Rm",
1030 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1033 def tBIC : // A8.6.20
1034 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1036 "bic", "\t$Rdn, $Rm",
1037 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
1041 let isCompare = 1, Defs = [CPSR] in {
1042 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1043 // Compare-to-zero still works out, just not the relationals
1044 //def tCMN : // A8.6.33
1045 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
1047 // "cmn", "\t$lhs, $rhs",
1048 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
1050 def tCMNz : // A8.6.33
1051 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1053 "cmn", "\t$Rn, $Rm",
1054 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1056 } // isCompare = 1, Defs = [CPSR]
1059 let isCompare = 1, Defs = [CPSR] in {
1060 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
1061 "cmp", "\t$Rn, $imm8",
1062 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
1063 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
1067 let Inst{10-8} = Rn;
1068 let Inst{7-0} = imm8;
1072 def tCMPr : // A8.6.36 T1
1073 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1075 "cmp", "\t$Rn, $Rm",
1076 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
1078 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1079 "cmp", "\t$Rn, $Rm", []>,
1080 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
1084 let Inst{7} = Rn{3};
1086 let Inst{2-0} = Rn{2-0};
1088 } // isCompare = 1, Defs = [CPSR]
1092 let isCommutable = 1 in
1093 def tEOR : // A8.6.45
1094 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1096 "eor", "\t$Rdn, $Rm",
1097 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1100 def tLSLri : // A8.6.88
1101 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1103 "lsl", "\t$Rd, $Rm, $imm5",
1104 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1107 let Inst{10-6} = imm5;
1111 def tLSLrr : // A8.6.89
1112 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1114 "lsl", "\t$Rdn, $Rm",
1115 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1118 def tLSRri : // A8.6.90
1119 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1121 "lsr", "\t$Rd, $Rm, $imm5",
1122 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1125 let Inst{10-6} = imm5;
1129 def tLSRrr : // A8.6.91
1130 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1132 "lsr", "\t$Rdn, $Rm",
1133 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1136 let isMoveImm = 1 in
1137 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1138 "mov", "\t$Rd, $imm8",
1139 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1140 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1144 let Inst{10-8} = Rd;
1145 let Inst{7-0} = imm8;
1147 // Because we have an explicit tMOVSr below, we need an alias to handle
1148 // the immediate "movs" form here. Blech.
1149 def : tInstAlias <"movs $Rdn, $imm",
1150 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1152 // A7-73: MOV(2) - mov setting flag.
1154 let hasSideEffects = 0 in {
1155 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1157 "mov", "\t$Rd, $Rm", "", []>,
1158 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1162 let Inst{7} = Rd{3};
1164 let Inst{2-0} = Rd{2-0};
1166 let Defs = [CPSR] in
1167 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1168 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1172 let Inst{15-6} = 0b0000000000;
1178 // Multiply register
1179 let isCommutable = 1 in
1180 def tMUL : // A8.6.105 T1
1181 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1182 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1183 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1184 T1DataProcessing<0b1101> {
1189 let AsmMatchConverter = "cvtThumbMultiply";
1192 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1195 // Move inverse register
1196 def tMVN : // A8.6.107
1197 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1198 "mvn", "\t$Rd, $Rn",
1199 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1201 // Bitwise or register
1202 let isCommutable = 1 in
1203 def tORR : // A8.6.114
1204 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1206 "orr", "\t$Rdn, $Rm",
1207 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1210 def tREV : // A8.6.134
1211 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1213 "rev", "\t$Rd, $Rm",
1214 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1215 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1217 def tREV16 : // A8.6.135
1218 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1220 "rev16", "\t$Rd, $Rm",
1221 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1222 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1224 def tREVSH : // A8.6.136
1225 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1227 "revsh", "\t$Rd, $Rm",
1228 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1229 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1231 // Rotate right register
1232 def tROR : // A8.6.139
1233 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1235 "ror", "\t$Rdn, $Rm",
1236 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1240 def tRSB : // A8.6.141
1241 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1243 "rsb", "\t$Rd, $Rn, #0",
1244 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1246 // Subtract with carry register
1247 let Uses = [CPSR] in
1248 def tSBC : // A8.6.151
1249 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1251 "sbc", "\t$Rdn, $Rm",
1255 // Subtract immediate
1256 def tSUBi3 : // A8.6.210 T1
1257 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1259 "sub", "\t$Rd, $Rm, $imm3",
1260 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1263 let Inst{8-6} = imm3;
1266 def tSUBi8 : // A8.6.210 T2
1267 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1268 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1269 "sub", "\t$Rdn, $imm8",
1270 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1273 def : tInstSubst<"add${s}${p} $rd, $rn, $imm",
1274 (tSUBi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;
1277 def : tInstSubst<"add${s}${p} $rdn, $imm",
1278 (tSUBi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>;
1281 // Subtract register
1282 def tSUBrr : // A8.6.212
1283 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1285 "sub", "\t$Rd, $Rn, $Rm",
1286 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1289 /// Similar to the above except these set the 's' bit so the
1290 /// instruction modifies the CPSR register.
1292 /// These opcodes will be converted to the real non-S opcodes by
1293 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1294 let hasPostISelHook = 1, Defs = [CPSR] in {
1295 let Uses = [CPSR] in
1296 def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1298 [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm,
1300 Requires<[IsThumb1Only]>,
1303 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1305 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm,
1307 Requires<[IsThumb1Only]>,
1310 def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1312 [(set tGPR:$Rdn, CPSR, (ARMsubc tGPR:$Rn,
1314 Requires<[IsThumb1Only]>,
1317 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1319 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,
1321 Requires<[IsThumb1Only]>,
1326 def tSXTB : // A8.6.222
1327 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1329 "sxtb", "\t$Rd, $Rm",
1330 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1331 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1334 // Sign-extend short
1335 def tSXTH : // A8.6.224
1336 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1338 "sxth", "\t$Rd, $Rm",
1339 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1340 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1344 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1345 def tTST : // A8.6.230
1346 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1347 "tst", "\t$Rn, $Rm",
1348 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1351 // A8.8.247 UDF - Undefined (Encoding T1)
1352 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
1353 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 {
1355 let Inst{15-12} = 0b1101;
1356 let Inst{11-8} = 0b1110;
1357 let Inst{7-0} = imm8;
1360 def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0",
1361 [(int_arm_undefined 249)]>, Encoding16,
1362 Requires<[IsThumb, IsWindows]> {
1364 let isTerminator = 1;
1368 def tUXTB : // A8.6.262
1369 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1371 "uxtb", "\t$Rd, $Rm",
1372 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1373 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1376 // Zero-extend short
1377 def tUXTH : // A8.6.264
1378 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1380 "uxth", "\t$Rd, $Rm",
1381 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1382 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1384 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1385 // Expanded after instruction selection into a branch sequence.
1386 let usesCustomInserter = 1 in // Expanded after instruction selection.
1387 def tMOVCCr_pseudo :
1388 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p),
1390 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>;
1392 // tLEApcrel - Load a pc-relative address into a register without offending the
1395 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1396 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1397 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1400 let Inst{10-8} = Rd;
1401 let Inst{7-0} = addr;
1402 let DecoderMethod = "DecodeThumbAddSpecialReg";
1405 let hasSideEffects = 0, isReMaterializable = 1 in
1406 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1407 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1409 let hasSideEffects = 1 in
1410 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1411 (ins i32imm:$label, pred:$p),
1412 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1414 // Thumb-1 doesn't have the TBB or TBH instructions, but we can synthesize them
1415 // and make use of the same compressed jump table format as Thumb-2.
1417 def tTBB_JT : tPseudoInst<(outs),
1418 (ins tGPR:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
1421 def tTBH_JT : tPseudoInst<(outs),
1422 (ins tGPR:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
1426 //===----------------------------------------------------------------------===//
1430 // __aeabi_read_tp preserves the registers r1-r3.
1431 // This is a pseudo inst so that we can get the encoding right,
1432 // complete with fixup for the aeabi_read_tp function.
1433 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1434 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1435 [(set R0, ARMthread_pointer)]>,
1438 //===----------------------------------------------------------------------===//
1439 // SJLJ Exception handling intrinsics
1442 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1443 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1444 // from some other function to get here, and we're using the stack frame for the
1445 // containing function to save/restore registers, we can't keep anything live in
1446 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1447 // tromped upon when we get here from a longjmp(). We force everything out of
1448 // registers except for our own input by listing the relevant registers in
1449 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1450 // preserve all of the callee-saved resgisters, which is exactly what we want.
1451 // $val is a scratch register for our use.
1452 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1453 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1454 usesCustomInserter = 1 in
1455 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1456 AddrModeNone, 0, NoItinerary, "","",
1457 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1459 // FIXME: Non-IOS version(s)
1460 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1461 Defs = [ R7, LR, SP ] in
1462 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1463 AddrModeNone, 0, IndexModeNone,
1464 Pseudo, NoItinerary, "", "",
1465 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1466 Requires<[IsThumb,IsNotWindows]>;
1468 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1469 Defs = [ R11, LR, SP ] in
1470 def tInt_WIN_eh_sjlj_longjmp
1471 : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone,
1472 Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1473 Requires<[IsThumb,IsWindows]>;
1475 //===----------------------------------------------------------------------===//
1476 // Non-Instruction Patterns
1480 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1481 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1482 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1483 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1485 // Bswap 16 with load/store
1486 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
1487 (tREV16 (tLDRHi t_addrmode_is2:$addr))>;
1488 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)),
1489 (tREV16 (tLDRHr t_addrmode_rr:$addr))>;
1490 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1491 t_addrmode_is2:$addr),
1492 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;
1493 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1494 t_addrmode_rr:$addr),
1495 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>;
1498 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1501 def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),
1504 (ARMWrapperPIC tglobaladdr:$addr))]>,
1505 Requires<[IsThumb, DontUseMovt]>;
1507 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
1510 (ARMWrapper tglobaladdr:$src))]>,
1511 Requires<[IsThumb, DontUseMovt]>;
1514 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
1515 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
1516 Requires<[IsThumb, DontUseMovt]>;
1517 def : Pat<(ARMWrapper tglobaltlsaddr:$addr),
1518 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>,
1519 Requires<[IsThumb, DontUseMovt]>;
1523 def : T1Pat<(ARMWrapperJT tjumptable:$dst),
1524 (tLEApcrelJT tjumptable:$dst)>;
1527 def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>,
1528 Requires<[IsThumb]>;
1530 // zextload i1 -> zextload i8
1531 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1532 (tLDRBi t_addrmode_is1:$addr)>;
1533 def : T1Pat<(zextloadi1 t_addrmode_rr:$addr),
1534 (tLDRBr t_addrmode_rr:$addr)>;
1536 // extload from the stack -> word load from the stack, as it avoids having to
1537 // materialize the base in a separate register. This only works when a word
1538 // load puts the byte/halfword value in the same place in the register that the
1539 // byte/halfword load would, i.e. when little-endian.
1540 def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1541 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1542 def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1543 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1544 def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1545 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1547 // extload -> zextload
1548 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1549 def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1550 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1551 def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1552 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1553 def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>;
1555 // post-inc loads and stores
1557 // post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is
1558 // different to how ISel expects them for a post-inc load, so use a pseudo
1559 // and expand it just after ISel.
1560 let usesCustomInserter = 1, mayLoad =1,
1561 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in
1562 def tLDR_postidx: tPseudoInst<(outs rGPR:$Rt, rGPR:$Rn_wb),
1563 (ins rGPR:$Rn, pred:$p),
1567 // post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def
1568 // multiple registers) is the same in ISel as MachineInstr, so there's no need
1570 def : T1Pat<(post_store rGPR:$Rt, rGPR:$Rn, 4),
1571 (tSTMIA_UPD rGPR:$Rn, rGPR:$Rt)>;
1573 // If it's impossible to use [r,r] address mode for sextload, select to
1574 // ldr{b|h} + sxt{b|h} instead.
1575 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1576 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1577 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1578 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1579 (tSXTB (tLDRBr t_addrmode_rr:$addr))>,
1580 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1581 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1582 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1583 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1584 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1585 (tSXTH (tLDRHr t_addrmode_rr:$addr))>,
1586 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1588 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1589 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1590 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1591 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>;
1592 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1593 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1594 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1595 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>;
1597 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1598 (tLDRBi t_addrmode_is1:$src)>;
1599 def : T1Pat<(atomic_load_8 t_addrmode_rr:$src),
1600 (tLDRBr t_addrmode_rr:$src)>;
1601 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1602 (tLDRHi t_addrmode_is2:$src)>;
1603 def : T1Pat<(atomic_load_16 t_addrmode_rr:$src),
1604 (tLDRHr t_addrmode_rr:$src)>;
1605 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1606 (tLDRi t_addrmode_is4:$src)>;
1607 def : T1Pat<(atomic_load_32 t_addrmode_rr:$src),
1608 (tLDRr t_addrmode_rr:$src)>;
1609 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1610 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1611 def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val),
1612 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>;
1613 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1614 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1615 def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val),
1616 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>;
1617 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1618 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1619 def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val),
1620 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>;
1622 // Large immediate handling.
1625 def : T1Pat<(i32 thumb_immshifted:$src),
1626 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1627 (thumb_immshifted_shamt imm:$src))>;
1629 def : T1Pat<(i32 imm0_255_comp:$src),
1630 (tMVN (tMOVi8 (imm_not_XFORM imm:$src)))>;
1632 def : T1Pat<(i32 imm256_510:$src),
1633 (tADDi8 (tMOVi8 255),
1634 (thumb_imm256_510_addend imm:$src))>;
1636 // Pseudo instruction that combines ldr from constpool and add pc. This should
1637 // be expanded into two instructions late to allow if-conversion and
1639 let isReMaterializable = 1 in
1640 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1642 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1644 Requires<[IsThumb, IsThumb1Only]>;
1646 // Pseudo-instruction for merged POP and return.
1647 // FIXME: remove when we have a way to marking a MI with these properties.
1648 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1649 hasExtraDefRegAllocReq = 1 in
1650 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1652 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1654 // Indirect branch using "mov pc, $Rm"
1655 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1656 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1657 2, IIC_Br, [(brind GPR:$Rm)],
1658 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1662 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1663 // encoding is available on ARMv6K, but we don't differentiate that finely.
1664 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>;
1667 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1668 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1669 // a useful extension and assembles to defined behaviour (the insn does
1671 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1672 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1674 // "neg" is and alias for "rsb rd, rn, #0"
1675 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1676 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1679 // Implied destination operand forms for shifts.
1680 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1681 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1682 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1683 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1684 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1685 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1687 // Pseudo instruction ldr Rt, =immediate
1689 : tAsmPseudo<"ldr${p} $Rt, $immediate",
1690 (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;