1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
61 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
62 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
63 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
67 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
68 // described for so_imm_notSext def below, with sign extension from 16
70 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
71 APInt apIntN = N->getAPIntValue();
72 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
73 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
76 // t2_so_imm - Match a 32-bit immediate operand, which is an
77 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
78 // immediate splatted into multiple bytes of the word.
79 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
80 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
81 return ARM_AM::getT2SOImmVal(Imm) != -1;
83 let ParserMatchClass = t2_so_imm_asmoperand;
84 let EncoderMethod = "getT2SOImmOpValue";
85 let DecoderMethod = "DecodeT2SOImm";
88 // t2_so_imm_not - Match an immediate that is a complement
90 // Note: this pattern doesn't require an encoder method and such, as it's
91 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
92 // is handled by the destination instructions, which use t2_so_imm.
93 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
94 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
95 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
96 }], t2_so_imm_not_XFORM> {
97 let ParserMatchClass = t2_so_imm_not_asmoperand;
100 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
101 // if the upper 16 bits are zero.
102 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
103 APInt apIntN = N->getAPIntValue();
104 if (!apIntN.isIntN(16)) return false;
105 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
106 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
107 }], t2_so_imm_notSext16_XFORM> {
108 let ParserMatchClass = t2_so_imm_not_asmoperand;
111 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
112 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
113 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
114 int64_t Value = -(int)N->getZExtValue();
115 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
116 }], t2_so_imm_neg_XFORM> {
117 let ParserMatchClass = t2_so_imm_neg_asmoperand;
120 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
121 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
122 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
123 return Imm >= 0 && Imm < 4096;
125 let ParserMatchClass = imm0_4095_asmoperand;
128 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
129 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
130 return (uint32_t)(-N->getZExtValue()) < 4096;
132 let ParserMatchClass = imm0_4095_neg_asmoperand;
135 def imm1_255_neg : PatLeaf<(i32 imm), [{
136 uint32_t Val = -N->getZExtValue();
137 return (Val > 0 && Val < 255);
140 def imm0_255_not : PatLeaf<(i32 imm), [{
141 return (uint32_t)(~N->getZExtValue()) < 255;
144 def lo5AllOne : PatLeaf<(i32 imm), [{
145 // Returns true if all low 5-bits are 1.
146 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
149 // Define Thumb2 specific addressing modes.
151 // t2addrmode_imm12 := reg + imm12
152 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
153 def t2addrmode_imm12 : MemOperand,
154 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
155 let PrintMethod = "printAddrModeImm12Operand<false>";
156 let EncoderMethod = "getAddrModeImm12OpValue";
157 let DecoderMethod = "DecodeT2AddrModeImm12";
158 let ParserMatchClass = t2addrmode_imm12_asmoperand;
159 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
162 // t2ldrlabel := imm12
163 def t2ldrlabel : Operand<i32> {
164 let EncoderMethod = "getAddrModeImm12OpValue";
165 let PrintMethod = "printThumbLdrLabelOperand";
168 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
169 def t2ldr_pcrel_imm12 : Operand<i32> {
170 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
171 // used for assembler pseudo instruction and maps to t2ldrlabel, so
172 // doesn't need encoder or print methods of its own.
175 // ADR instruction labels.
176 def t2adrlabel : Operand<i32> {
177 let EncoderMethod = "getT2AdrLabelOpValue";
178 let PrintMethod = "printAdrLabelOperand<0>";
181 // t2addrmode_posimm8 := reg + imm8
182 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
183 def t2addrmode_posimm8 : MemOperand {
184 let PrintMethod = "printT2AddrModeImm8Operand<false>";
185 let EncoderMethod = "getT2AddrModeImm8OpValue";
186 let DecoderMethod = "DecodeT2AddrModeImm8";
187 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
188 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
191 // t2addrmode_negimm8 := reg - imm8
192 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
193 def t2addrmode_negimm8 : MemOperand,
194 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
195 let PrintMethod = "printT2AddrModeImm8Operand<false>";
196 let EncoderMethod = "getT2AddrModeImm8OpValue";
197 let DecoderMethod = "DecodeT2AddrModeImm8";
198 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
202 // t2addrmode_imm8 := reg +/- imm8
203 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
204 class T2AddrMode_Imm8 : MemOperand,
205 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
206 let EncoderMethod = "getT2AddrModeImm8OpValue";
207 let DecoderMethod = "DecodeT2AddrModeImm8";
208 let ParserMatchClass = MemImm8OffsetAsmOperand;
209 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
212 def t2addrmode_imm8 : T2AddrMode_Imm8 {
213 let PrintMethod = "printT2AddrModeImm8Operand<false>";
216 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
217 let PrintMethod = "printT2AddrModeImm8Operand<true>";
220 def t2am_imm8_offset : MemOperand,
221 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
222 [], [SDNPWantRoot]> {
223 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
224 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
225 let DecoderMethod = "DecodeT2Imm8";
228 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
229 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
230 class T2AddrMode_Imm8s4 : MemOperand {
231 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
232 let DecoderMethod = "DecodeT2AddrModeImm8s4";
233 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
234 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
237 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
238 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
241 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
242 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
245 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
246 def t2am_imm8s4_offset : MemOperand {
247 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
248 let EncoderMethod = "getT2Imm8s4OpValue";
249 let DecoderMethod = "DecodeT2Imm8S4";
252 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
253 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
254 let Name = "MemImm0_1020s4Offset";
256 def t2addrmode_imm0_1020s4 : MemOperand,
257 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
258 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
259 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
260 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
261 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
262 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
265 // t2addrmode_so_reg := reg + (reg << imm2)
266 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
267 def t2addrmode_so_reg : MemOperand,
268 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
269 let PrintMethod = "printT2AddrModeSoRegOperand";
270 let EncoderMethod = "getT2AddrModeSORegOpValue";
271 let DecoderMethod = "DecodeT2AddrModeSOReg";
272 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
273 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
276 // Addresses for the TBB/TBH instructions.
277 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
278 def addrmode_tbb : MemOperand {
279 let PrintMethod = "printAddrModeTBB";
280 let ParserMatchClass = addrmode_tbb_asmoperand;
281 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
283 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
284 def addrmode_tbh : MemOperand {
285 let PrintMethod = "printAddrModeTBH";
286 let ParserMatchClass = addrmode_tbh_asmoperand;
287 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
290 //===----------------------------------------------------------------------===//
291 // Multiclass helpers...
295 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
296 string opc, string asm, list<dag> pattern>
297 : T2I<oops, iops, itin, opc, asm, pattern> {
302 let Inst{26} = imm{11};
303 let Inst{14-12} = imm{10-8};
304 let Inst{7-0} = imm{7-0};
308 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : T2sI<oops, iops, itin, opc, asm, pattern> {
316 let Inst{26} = imm{11};
317 let Inst{14-12} = imm{10-8};
318 let Inst{7-0} = imm{7-0};
321 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
322 string opc, string asm, list<dag> pattern>
323 : T2I<oops, iops, itin, opc, asm, pattern> {
327 let Inst{19-16} = Rn;
328 let Inst{26} = imm{11};
329 let Inst{14-12} = imm{10-8};
330 let Inst{7-0} = imm{7-0};
334 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2I<oops, iops, itin, opc, asm, pattern> {
341 let Inst{3-0} = ShiftedRm{3-0};
342 let Inst{5-4} = ShiftedRm{6-5};
343 let Inst{14-12} = ShiftedRm{11-9};
344 let Inst{7-6} = ShiftedRm{8-7};
347 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : T2sI<oops, iops, itin, opc, asm, pattern> {
354 let Inst{3-0} = ShiftedRm{3-0};
355 let Inst{5-4} = ShiftedRm{6-5};
356 let Inst{14-12} = ShiftedRm{11-9};
357 let Inst{7-6} = ShiftedRm{8-7};
360 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : T2I<oops, iops, itin, opc, asm, pattern> {
366 let Inst{19-16} = Rn;
367 let Inst{3-0} = ShiftedRm{3-0};
368 let Inst{5-4} = ShiftedRm{6-5};
369 let Inst{14-12} = ShiftedRm{11-9};
370 let Inst{7-6} = ShiftedRm{8-7};
373 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
374 string opc, string asm, list<dag> pattern>
375 : T2I<oops, iops, itin, opc, asm, pattern> {
383 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
384 string opc, string asm, list<dag> pattern>
385 : T2sI<oops, iops, itin, opc, asm, pattern> {
393 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
394 string opc, string asm, list<dag> pattern>
395 : T2I<oops, iops, itin, opc, asm, pattern> {
399 let Inst{19-16} = Rn;
404 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
405 string opc, string asm, list<dag> pattern>
406 : T2I<oops, iops, itin, opc, asm, pattern> {
412 let Inst{19-16} = Rn;
413 let Inst{26} = imm{11};
414 let Inst{14-12} = imm{10-8};
415 let Inst{7-0} = imm{7-0};
418 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
419 string opc, string asm, list<dag> pattern>
420 : T2sI<oops, iops, itin, opc, asm, pattern> {
426 let Inst{19-16} = Rn;
427 let Inst{26} = imm{11};
428 let Inst{14-12} = imm{10-8};
429 let Inst{7-0} = imm{7-0};
432 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
433 string opc, string asm, list<dag> pattern>
434 : T2I<oops, iops, itin, opc, asm, pattern> {
441 let Inst{14-12} = imm{4-2};
442 let Inst{7-6} = imm{1-0};
445 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
446 string opc, string asm, list<dag> pattern>
447 : T2sI<oops, iops, itin, opc, asm, pattern> {
454 let Inst{14-12} = imm{4-2};
455 let Inst{7-6} = imm{1-0};
458 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
459 string opc, string asm, list<dag> pattern>
460 : T2I<oops, iops, itin, opc, asm, pattern> {
466 let Inst{19-16} = Rn;
470 class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
471 string asm, list<dag> pattern>
472 : T2XI<oops, iops, itin, asm, pattern> {
478 let Inst{19-16} = Rn;
482 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
483 string opc, string asm, list<dag> pattern>
484 : T2sI<oops, iops, itin, opc, asm, pattern> {
490 let Inst{19-16} = Rn;
494 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : T2I<oops, iops, itin, opc, asm, pattern> {
502 let Inst{19-16} = Rn;
503 let Inst{3-0} = ShiftedRm{3-0};
504 let Inst{5-4} = ShiftedRm{6-5};
505 let Inst{14-12} = ShiftedRm{11-9};
506 let Inst{7-6} = ShiftedRm{8-7};
509 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
510 string opc, string asm, list<dag> pattern>
511 : T2sI<oops, iops, itin, opc, asm, pattern> {
517 let Inst{19-16} = Rn;
518 let Inst{3-0} = ShiftedRm{3-0};
519 let Inst{5-4} = ShiftedRm{6-5};
520 let Inst{14-12} = ShiftedRm{11-9};
521 let Inst{7-6} = ShiftedRm{8-7};
524 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
525 string opc, string asm, list<dag> pattern>
526 : T2I<oops, iops, itin, opc, asm, pattern> {
532 let Inst{19-16} = Rn;
533 let Inst{15-12} = Ra;
538 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
539 string opc, list<dag> pattern>
540 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
541 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern> {
547 let Inst{31-23} = 0b111110111;
548 let Inst{22-20} = opc22_20;
549 let Inst{19-16} = Rn;
550 let Inst{15-12} = RdLo;
551 let Inst{11-8} = RdHi;
552 let Inst{7-4} = opc7_4;
555 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
556 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
557 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
558 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
559 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi"> {
565 let Inst{31-23} = 0b111110111;
566 let Inst{22-20} = opc22_20;
567 let Inst{19-16} = Rn;
568 let Inst{15-12} = RdLo;
569 let Inst{11-8} = RdHi;
570 let Inst{7-4} = opc7_4;
575 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
576 /// binary operation that produces a value. These are predicable and can be
577 /// changed to modify CPSR.
578 multiclass T2I_bin_irs<bits<4> opcod, string opc,
579 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
580 SDPatternOperator opnode, bit Commutable = 0,
583 def ri : T2sTwoRegImm<
584 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
585 opc, "\t$Rd, $Rn, $imm",
586 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
587 Sched<[WriteALU, ReadALU]> {
588 let Inst{31-27} = 0b11110;
590 let Inst{24-21} = opcod;
594 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
595 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
596 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
597 Sched<[WriteALU, ReadALU, ReadALU]> {
598 let isCommutable = Commutable;
599 let Inst{31-27} = 0b11101;
600 let Inst{26-25} = 0b01;
601 let Inst{24-21} = opcod;
602 let Inst{14-12} = 0b000; // imm3
603 let Inst{7-6} = 0b00; // imm2
604 let Inst{5-4} = 0b00; // type
607 def rs : T2sTwoRegShiftedReg<
608 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
609 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
610 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
611 Sched<[WriteALUsi, ReadALU]> {
612 let Inst{31-27} = 0b11101;
613 let Inst{26-25} = 0b01;
614 let Inst{24-21} = opcod;
616 // Assembly aliases for optional destination operand when it's the same
617 // as the source operand.
618 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
619 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
620 t2_so_imm:$imm, pred:$p,
622 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
623 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
626 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
627 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
628 t2_so_reg:$shift, pred:$p,
632 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
633 // the ".w" suffix to indicate that they are wide.
634 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
635 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
636 SDPatternOperator opnode, bit Commutable = 0> :
637 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
638 // Assembler aliases w/ the ".w" suffix.
639 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
640 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
642 // Assembler aliases w/o the ".w" suffix.
643 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
644 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
646 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
647 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
648 pred:$p, cc_out:$s)>;
650 // and with the optional destination operand, too.
651 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
652 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
653 pred:$p, cc_out:$s)>;
654 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
655 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
657 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
658 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
659 pred:$p, cc_out:$s)>;
662 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
663 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
664 /// it is equivalent to the T2I_bin_irs counterpart.
665 multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {
667 def ri : T2sTwoRegImm<
668 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
669 opc, ".w\t$Rd, $Rn, $imm",
670 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
671 Sched<[WriteALU, ReadALU]> {
672 let Inst{31-27} = 0b11110;
674 let Inst{24-21} = opcod;
678 def rr : T2sThreeReg<
679 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
680 opc, "\t$Rd, $Rn, $Rm",
681 [/* For disassembly only; pattern left blank */]>,
682 Sched<[WriteALU, ReadALU, ReadALU]> {
683 let Inst{31-27} = 0b11101;
684 let Inst{26-25} = 0b01;
685 let Inst{24-21} = opcod;
686 let Inst{14-12} = 0b000; // imm3
687 let Inst{7-6} = 0b00; // imm2
688 let Inst{5-4} = 0b00; // type
691 def rs : T2sTwoRegShiftedReg<
692 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
693 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
694 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
695 Sched<[WriteALUsi, ReadALU]> {
696 let Inst{31-27} = 0b11101;
697 let Inst{26-25} = 0b01;
698 let Inst{24-21} = opcod;
702 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
703 /// instruction modifies the CPSR register.
705 /// These opcodes will be converted to the real non-S opcodes by
706 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
707 let hasPostISelHook = 1, Defs = [CPSR] in {
708 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
709 InstrItinClass iis, SDNode opnode,
710 bit Commutable = 0> {
712 def ri : t2PseudoInst<(outs rGPR:$Rd),
713 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
715 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
717 Sched<[WriteALU, ReadALU]>;
719 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
721 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
723 Sched<[WriteALU, ReadALU, ReadALU]> {
724 let isCommutable = Commutable;
727 def rs : t2PseudoInst<(outs rGPR:$Rd),
728 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
730 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
731 t2_so_reg:$ShiftedRm))]>,
732 Sched<[WriteALUsi, ReadALUsr]>;
736 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
737 /// operands are reversed.
738 let hasPostISelHook = 1, Defs = [CPSR] in {
739 multiclass T2I_rbin_s_is<SDNode opnode> {
741 def ri : t2PseudoInst<(outs rGPR:$Rd),
742 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
744 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
746 Sched<[WriteALU, ReadALU]>;
748 def rs : t2PseudoInst<(outs rGPR:$Rd),
749 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
751 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
753 Sched<[WriteALUsi, ReadALU]>;
757 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
758 /// patterns for a binary operation that produces a value.
759 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
760 bit Commutable = 0> {
762 // The register-immediate version is re-materializable. This is useful
763 // in particular for taking the address of a local.
764 let isReMaterializable = 1 in {
765 def ri : T2sTwoRegImm<
766 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
767 opc, ".w\t$Rd, $Rn, $imm",
768 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
769 Sched<[WriteALU, ReadALU]> {
770 let Inst{31-27} = 0b11110;
773 let Inst{23-21} = op23_21;
779 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
780 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
781 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
782 Sched<[WriteALU, ReadALU]> {
786 let Inst{31-27} = 0b11110;
787 let Inst{26} = imm{11};
788 let Inst{25-24} = 0b10;
789 let Inst{23-21} = op23_21;
790 let Inst{20} = 0; // The S bit.
791 let Inst{19-16} = Rn;
793 let Inst{14-12} = imm{10-8};
795 let Inst{7-0} = imm{7-0};
798 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
799 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
800 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
801 Sched<[WriteALU, ReadALU, ReadALU]> {
802 let isCommutable = Commutable;
803 let Inst{31-27} = 0b11101;
804 let Inst{26-25} = 0b01;
806 let Inst{23-21} = op23_21;
807 let Inst{14-12} = 0b000; // imm3
808 let Inst{7-6} = 0b00; // imm2
809 let Inst{5-4} = 0b00; // type
812 def rs : T2sTwoRegShiftedReg<
813 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
814 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
815 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
816 Sched<[WriteALUsi, ReadALU]> {
817 let Inst{31-27} = 0b11101;
818 let Inst{26-25} = 0b01;
820 let Inst{23-21} = op23_21;
824 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
825 /// for a binary operation that produces a value and use the carry
826 /// bit. It's not predicable.
827 let Defs = [CPSR], Uses = [CPSR] in {
828 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
829 bit Commutable = 0> {
831 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
832 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
833 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
834 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
835 let Inst{31-27} = 0b11110;
837 let Inst{24-21} = opcod;
841 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
842 opc, ".w\t$Rd, $Rn, $Rm",
843 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
844 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
845 let isCommutable = Commutable;
846 let Inst{31-27} = 0b11101;
847 let Inst{26-25} = 0b01;
848 let Inst{24-21} = opcod;
849 let Inst{14-12} = 0b000; // imm3
850 let Inst{7-6} = 0b00; // imm2
851 let Inst{5-4} = 0b00; // type
854 def rs : T2sTwoRegShiftedReg<
855 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
856 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
857 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
858 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
859 let Inst{31-27} = 0b11101;
860 let Inst{26-25} = 0b01;
861 let Inst{24-21} = opcod;
866 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
867 // rotate operation that produces a value.
868 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
870 def ri : T2sTwoRegShiftImm<
871 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
872 opc, ".w\t$Rd, $Rm, $imm",
873 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
875 let Inst{31-27} = 0b11101;
876 let Inst{26-21} = 0b010010;
877 let Inst{19-16} = 0b1111; // Rn
878 let Inst{5-4} = opcod;
881 def rr : T2sThreeReg<
882 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
883 opc, ".w\t$Rd, $Rn, $Rm",
884 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
886 let Inst{31-27} = 0b11111;
887 let Inst{26-23} = 0b0100;
888 let Inst{22-21} = opcod;
889 let Inst{15-12} = 0b1111;
890 let Inst{7-4} = 0b0000;
893 // Optional destination register
894 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
895 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
897 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
898 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
901 // Assembler aliases w/o the ".w" suffix.
902 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
903 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
905 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
906 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
909 // and with the optional destination operand, too.
910 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
911 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
913 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
914 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
918 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
919 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
920 /// a explicit result, only implicitly set CPSR.
921 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
922 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
923 SDPatternOperator opnode> {
924 let isCompare = 1, Defs = [CPSR] in {
926 def ri : T2OneRegCmpImm<
927 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
928 opc, ".w\t$Rn, $imm",
929 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
930 let Inst{31-27} = 0b11110;
932 let Inst{24-21} = opcod;
933 let Inst{20} = 1; // The S bit.
935 let Inst{11-8} = 0b1111; // Rd
938 def rr : T2TwoRegCmp<
939 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
941 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
942 let Inst{31-27} = 0b11101;
943 let Inst{26-25} = 0b01;
944 let Inst{24-21} = opcod;
945 let Inst{20} = 1; // The S bit.
946 let Inst{14-12} = 0b000; // imm3
947 let Inst{11-8} = 0b1111; // Rd
948 let Inst{7-6} = 0b00; // imm2
949 let Inst{5-4} = 0b00; // type
952 def rs : T2OneRegCmpShiftedReg<
953 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
954 opc, ".w\t$Rn, $ShiftedRm",
955 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
956 Sched<[WriteCMPsi]> {
957 let Inst{31-27} = 0b11101;
958 let Inst{26-25} = 0b01;
959 let Inst{24-21} = opcod;
960 let Inst{20} = 1; // The S bit.
961 let Inst{11-8} = 0b1111; // Rd
965 // Assembler aliases w/o the ".w" suffix.
966 // No alias here for 'rr' version as not all instantiations of this
967 // multiclass want one (CMP in particular, does not).
968 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
969 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
970 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
971 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
974 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
975 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
976 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
978 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
979 opc, ".w\t$Rt, $addr",
980 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
983 let Inst{31-25} = 0b1111100;
984 let Inst{24} = signed;
986 let Inst{22-21} = opcod;
987 let Inst{20} = 1; // load
988 let Inst{19-16} = addr{16-13}; // Rn
989 let Inst{15-12} = Rt;
990 let Inst{11-0} = addr{11-0}; // imm
992 let DecoderMethod = "DecodeT2LoadImm12";
994 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
996 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
999 let Inst{31-27} = 0b11111;
1000 let Inst{26-25} = 0b00;
1001 let Inst{24} = signed;
1003 let Inst{22-21} = opcod;
1004 let Inst{20} = 1; // load
1005 let Inst{19-16} = addr{12-9}; // Rn
1006 let Inst{15-12} = Rt;
1008 // Offset: index==TRUE, wback==FALSE
1009 let Inst{10} = 1; // The P bit.
1010 let Inst{9} = addr{8}; // U
1011 let Inst{8} = 0; // The W bit.
1012 let Inst{7-0} = addr{7-0}; // imm
1014 let DecoderMethod = "DecodeT2LoadImm8";
1016 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1017 opc, ".w\t$Rt, $addr",
1018 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
1019 let Inst{31-27} = 0b11111;
1020 let Inst{26-25} = 0b00;
1021 let Inst{24} = signed;
1023 let Inst{22-21} = opcod;
1024 let Inst{20} = 1; // load
1025 let Inst{11-6} = 0b000000;
1028 let Inst{15-12} = Rt;
1031 let Inst{19-16} = addr{9-6}; // Rn
1032 let Inst{3-0} = addr{5-2}; // Rm
1033 let Inst{5-4} = addr{1-0}; // imm
1035 let DecoderMethod = "DecodeT2LoadShift";
1038 // pci variant is very similar to i12, but supports negative offsets
1040 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1041 opc, ".w\t$Rt, $addr",
1042 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1043 let isReMaterializable = 1;
1044 let Inst{31-27} = 0b11111;
1045 let Inst{26-25} = 0b00;
1046 let Inst{24} = signed;
1047 let Inst{22-21} = opcod;
1048 let Inst{20} = 1; // load
1049 let Inst{19-16} = 0b1111; // Rn
1052 let Inst{15-12} = Rt{3-0};
1055 let Inst{23} = addr{12}; // add = (U == '1')
1056 let Inst{11-0} = addr{11-0};
1058 let DecoderMethod = "DecodeT2LoadLabel";
1062 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1063 multiclass T2I_st<bits<2> opcod, string opc,
1064 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1066 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1067 opc, ".w\t$Rt, $addr",
1068 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1069 let Inst{31-27} = 0b11111;
1070 let Inst{26-23} = 0b0001;
1071 let Inst{22-21} = opcod;
1072 let Inst{20} = 0; // !load
1075 let Inst{15-12} = Rt;
1078 let addr{12} = 1; // add = TRUE
1079 let Inst{19-16} = addr{16-13}; // Rn
1080 let Inst{23} = addr{12}; // U
1081 let Inst{11-0} = addr{11-0}; // imm
1083 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1084 opc, "\t$Rt, $addr",
1085 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1086 let Inst{31-27} = 0b11111;
1087 let Inst{26-23} = 0b0000;
1088 let Inst{22-21} = opcod;
1089 let Inst{20} = 0; // !load
1091 // Offset: index==TRUE, wback==FALSE
1092 let Inst{10} = 1; // The P bit.
1093 let Inst{8} = 0; // The W bit.
1096 let Inst{15-12} = Rt;
1099 let Inst{19-16} = addr{12-9}; // Rn
1100 let Inst{9} = addr{8}; // U
1101 let Inst{7-0} = addr{7-0}; // imm
1103 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1104 opc, ".w\t$Rt, $addr",
1105 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1106 let Inst{31-27} = 0b11111;
1107 let Inst{26-23} = 0b0000;
1108 let Inst{22-21} = opcod;
1109 let Inst{20} = 0; // !load
1110 let Inst{11-6} = 0b000000;
1113 let Inst{15-12} = Rt;
1116 let Inst{19-16} = addr{9-6}; // Rn
1117 let Inst{3-0} = addr{5-2}; // Rm
1118 let Inst{5-4} = addr{1-0}; // imm
1122 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1123 /// register and one whose operand is a register rotated by 8/16/24.
1124 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1125 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1126 opc, ".w\t$Rd, $Rm$rot",
1127 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1128 Requires<[IsThumb2]> {
1129 let Inst{31-27} = 0b11111;
1130 let Inst{26-23} = 0b0100;
1131 let Inst{22-20} = opcod;
1132 let Inst{19-16} = 0b1111; // Rn
1133 let Inst{15-12} = 0b1111;
1137 let Inst{5-4} = rot{1-0}; // rotate
1140 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1141 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1142 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1143 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1144 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1145 Requires<[HasT2ExtractPack, IsThumb2]> {
1147 let Inst{31-27} = 0b11111;
1148 let Inst{26-23} = 0b0100;
1149 let Inst{22-20} = opcod;
1150 let Inst{19-16} = 0b1111; // Rn
1151 let Inst{15-12} = 0b1111;
1153 let Inst{5-4} = rot;
1156 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1158 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1159 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1160 opc, "\t$Rd, $Rm$rot", []>,
1161 Requires<[IsThumb2, HasT2ExtractPack]> {
1163 let Inst{31-27} = 0b11111;
1164 let Inst{26-23} = 0b0100;
1165 let Inst{22-20} = opcod;
1166 let Inst{19-16} = 0b1111; // Rn
1167 let Inst{15-12} = 0b1111;
1169 let Inst{5-4} = rot;
1172 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1173 /// register and one whose operand is a register rotated by 8/16/24.
1174 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1175 : T2ThreeReg<(outs rGPR:$Rd),
1176 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1177 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1178 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1179 Requires<[HasT2ExtractPack, IsThumb2]> {
1181 let Inst{31-27} = 0b11111;
1182 let Inst{26-23} = 0b0100;
1183 let Inst{22-20} = opcod;
1184 let Inst{15-12} = 0b1111;
1186 let Inst{5-4} = rot;
1189 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1190 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1191 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1192 Requires<[HasT2ExtractPack, IsThumb2]> {
1194 let Inst{31-27} = 0b11111;
1195 let Inst{26-23} = 0b0100;
1196 let Inst{22-20} = opcod;
1197 let Inst{15-12} = 0b1111;
1199 let Inst{5-4} = rot;
1202 //===----------------------------------------------------------------------===//
1204 //===----------------------------------------------------------------------===//
1206 //===----------------------------------------------------------------------===//
1207 // Miscellaneous Instructions.
1210 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1211 string asm, list<dag> pattern>
1212 : T2XI<oops, iops, itin, asm, pattern> {
1216 let Inst{11-8} = Rd;
1217 let Inst{26} = label{11};
1218 let Inst{14-12} = label{10-8};
1219 let Inst{7-0} = label{7-0};
1222 // LEApcrel - Load a pc-relative address into a register without offending the
1224 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1225 (ins t2adrlabel:$addr, pred:$p),
1226 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1227 Sched<[WriteALU, ReadALU]> {
1228 let Inst{31-27} = 0b11110;
1229 let Inst{25-24} = 0b10;
1230 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1233 let Inst{19-16} = 0b1111; // Rn
1238 let Inst{11-8} = Rd;
1239 let Inst{23} = addr{12};
1240 let Inst{21} = addr{12};
1241 let Inst{26} = addr{11};
1242 let Inst{14-12} = addr{10-8};
1243 let Inst{7-0} = addr{7-0};
1245 let DecoderMethod = "DecodeT2Adr";
1248 let hasSideEffects = 0, isReMaterializable = 1 in
1249 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1250 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1251 let hasSideEffects = 1 in
1252 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1253 (ins i32imm:$label, pred:$p),
1255 []>, Sched<[WriteALU, ReadALU]>;
1258 //===----------------------------------------------------------------------===//
1259 // Load / store Instructions.
1263 let canFoldAsLoad = 1, isReMaterializable = 1 in
1264 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
1266 // Loads with zero extension
1267 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1268 GPRnopc, zextloadi16>;
1269 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1270 GPRnopc, zextloadi8>;
1272 // Loads with sign extension
1273 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1274 GPRnopc, sextloadi16>;
1275 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1276 GPRnopc, sextloadi8>;
1278 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1280 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1281 (ins t2addrmode_imm8s4:$addr),
1282 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1283 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1285 // zextload i1 -> zextload i8
1286 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1287 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1288 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1289 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1290 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1291 (t2LDRBs t2addrmode_so_reg:$addr)>;
1292 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1293 (t2LDRBpci tconstpool:$addr)>;
1295 // extload -> zextload
1296 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1298 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1299 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1300 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1301 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1302 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1303 (t2LDRBs t2addrmode_so_reg:$addr)>;
1304 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1305 (t2LDRBpci tconstpool:$addr)>;
1307 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1308 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1309 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1310 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1311 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1312 (t2LDRBs t2addrmode_so_reg:$addr)>;
1313 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1314 (t2LDRBpci tconstpool:$addr)>;
1316 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1317 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1318 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1319 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1320 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1321 (t2LDRHs t2addrmode_so_reg:$addr)>;
1322 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1323 (t2LDRHpci tconstpool:$addr)>;
1325 // FIXME: The destination register of the loads and stores can't be PC, but
1326 // can be SP. We need another regclass (similar to rGPR) to represent
1327 // that. Not a pressing issue since these are selected manually,
1332 let mayLoad = 1, hasSideEffects = 0 in {
1333 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1334 (ins t2addrmode_imm8_pre:$addr),
1335 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1336 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1338 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1339 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1340 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1341 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1343 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1344 (ins t2addrmode_imm8_pre:$addr),
1345 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1346 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1348 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1349 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1350 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1351 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1353 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1354 (ins t2addrmode_imm8_pre:$addr),
1355 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1356 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1358 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1359 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1360 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1361 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1363 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1364 (ins t2addrmode_imm8_pre:$addr),
1365 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1366 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1369 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1370 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1371 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1372 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1374 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1375 (ins t2addrmode_imm8_pre:$addr),
1376 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1377 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1380 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1381 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1382 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1383 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1384 } // mayLoad = 1, hasSideEffects = 0
1386 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1387 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1388 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1389 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1390 "\t$Rt, $addr", []> {
1393 let Inst{31-27} = 0b11111;
1394 let Inst{26-25} = 0b00;
1395 let Inst{24} = signed;
1397 let Inst{22-21} = type;
1398 let Inst{20} = 1; // load
1399 let Inst{19-16} = addr{12-9};
1400 let Inst{15-12} = Rt;
1402 let Inst{10-8} = 0b110; // PUW.
1403 let Inst{7-0} = addr{7-0};
1405 let DecoderMethod = "DecodeT2LoadT";
1408 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1409 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1410 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1411 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1412 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1414 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
1415 string opc, string asm, list<dag> pattern>
1416 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
1417 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
1421 let Inst{31-27} = 0b11101;
1422 let Inst{26-24} = 0b000;
1423 let Inst{23-20} = bits23_20;
1424 let Inst{11-6} = 0b111110;
1425 let Inst{5-4} = bit54;
1426 let Inst{3-0} = 0b1111;
1428 // Encode instruction operands
1429 let Inst{19-16} = addr;
1430 let Inst{15-12} = Rt;
1433 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1434 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>;
1435 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1436 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>;
1437 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1438 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>;
1441 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;
1442 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1443 rGPR, truncstorei8>;
1444 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1445 rGPR, truncstorei16>;
1448 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1449 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1450 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1451 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1455 let mayStore = 1, hasSideEffects = 0 in {
1456 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1457 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1458 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1459 "str", "\t$Rt, $addr!",
1460 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1462 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1463 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1464 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1465 "strh", "\t$Rt, $addr!",
1466 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1468 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1469 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1470 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1471 "strb", "\t$Rt, $addr!",
1472 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1473 } // mayStore = 1, hasSideEffects = 0
1475 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1476 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1477 t2am_imm8_offset:$offset),
1478 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1479 "str", "\t$Rt, $Rn$offset",
1480 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1481 [(set GPRnopc:$Rn_wb,
1482 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1483 t2am_imm8_offset:$offset))]>;
1485 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1486 (ins rGPR:$Rt, addr_offset_none:$Rn,
1487 t2am_imm8_offset:$offset),
1488 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1489 "strh", "\t$Rt, $Rn$offset",
1490 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1491 [(set GPRnopc:$Rn_wb,
1492 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1493 t2am_imm8_offset:$offset))]>;
1495 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1496 (ins rGPR:$Rt, addr_offset_none:$Rn,
1497 t2am_imm8_offset:$offset),
1498 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1499 "strb", "\t$Rt, $Rn$offset",
1500 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1501 [(set GPRnopc:$Rn_wb,
1502 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1503 t2am_imm8_offset:$offset))]>;
1505 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1506 // put the patterns on the instruction definitions directly as ISel wants
1507 // the address base and offset to be separate operands, not a single
1508 // complex operand like we represent the instructions themselves. The
1509 // pseudos map between the two.
1510 let usesCustomInserter = 1,
1511 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1512 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1513 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1515 [(set GPRnopc:$Rn_wb,
1516 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1517 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1518 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1520 [(set GPRnopc:$Rn_wb,
1521 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1522 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1523 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1525 [(set GPRnopc:$Rn_wb,
1526 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1529 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1531 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1532 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1533 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1534 "\t$Rt, $addr", []> {
1535 let Inst{31-27} = 0b11111;
1536 let Inst{26-25} = 0b00;
1537 let Inst{24} = 0; // not signed
1539 let Inst{22-21} = type;
1540 let Inst{20} = 0; // store
1542 let Inst{10-8} = 0b110; // PUW
1546 let Inst{15-12} = Rt;
1547 let Inst{19-16} = addr{12-9};
1548 let Inst{7-0} = addr{7-0};
1551 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1552 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1553 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1555 // ldrd / strd pre / post variants
1558 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1559 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1560 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1561 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1565 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1566 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1567 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1568 "$addr.base = $wb", []>;
1571 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1572 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1573 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1574 "$addr.base = $wb", []> {
1575 let DecoderMethod = "DecodeT2STRDPreInstruction";
1579 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1580 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1581 t2am_imm8s4_offset:$imm),
1582 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1583 "$addr.base = $wb", []>;
1585 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
1586 string opc, string asm, list<dag> pattern>
1587 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
1588 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
1592 let Inst{31-27} = 0b11101;
1593 let Inst{26-20} = 0b0001100;
1594 let Inst{11-6} = 0b111110;
1595 let Inst{5-4} = bit54;
1596 let Inst{3-0} = 0b1111;
1598 // Encode instruction operands
1599 let Inst{19-16} = addr;
1600 let Inst{15-12} = Rt;
1603 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1604 "stl", "\t$Rt, $addr", []>;
1605 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1606 "stlb", "\t$Rt, $addr", []>;
1607 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1608 "stlh", "\t$Rt, $addr", []>;
1610 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1611 // data/instruction access.
1612 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1613 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1614 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1616 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1618 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1619 Sched<[WritePreLd]> {
1620 let Inst{31-25} = 0b1111100;
1621 let Inst{24} = instr;
1624 let Inst{21} = write;
1626 let Inst{15-12} = 0b1111;
1629 let Inst{19-16} = addr{16-13}; // Rn
1630 let Inst{11-0} = addr{11-0}; // imm12
1632 let DecoderMethod = "DecodeT2LoadImm12";
1635 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1637 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1638 Sched<[WritePreLd]> {
1639 let Inst{31-25} = 0b1111100;
1640 let Inst{24} = instr;
1641 let Inst{23} = 0; // U = 0
1643 let Inst{21} = write;
1645 let Inst{15-12} = 0b1111;
1646 let Inst{11-8} = 0b1100;
1649 let Inst{19-16} = addr{12-9}; // Rn
1650 let Inst{7-0} = addr{7-0}; // imm8
1652 let DecoderMethod = "DecodeT2LoadImm8";
1655 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1657 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1658 Sched<[WritePreLd]> {
1659 let Inst{31-25} = 0b1111100;
1660 let Inst{24} = instr;
1661 let Inst{23} = 0; // add = TRUE for T1
1663 let Inst{21} = write;
1665 let Inst{15-12} = 0b1111;
1666 let Inst{11-6} = 0b000000;
1669 let Inst{19-16} = addr{9-6}; // Rn
1670 let Inst{3-0} = addr{5-2}; // Rm
1671 let Inst{5-4} = addr{1-0}; // imm2
1673 let DecoderMethod = "DecodeT2LoadShift";
1677 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1678 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1679 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1681 // pci variant is very similar to i12, but supports negative offsets
1682 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1683 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1684 IIC_Preload, opc, "\t$addr",
1685 [(ARMPreload (ARMWrapper tconstpool:$addr),
1686 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1687 let Inst{31-25} = 0b1111100;
1688 let Inst{24} = inst;
1689 let Inst{22-20} = 0b001;
1690 let Inst{19-16} = 0b1111;
1691 let Inst{15-12} = 0b1111;
1694 let Inst{23} = addr{12}; // add = (U == '1')
1695 let Inst{11-0} = addr{11-0}; // imm12
1697 let DecoderMethod = "DecodeT2LoadLabel";
1700 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1701 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1703 //===----------------------------------------------------------------------===//
1704 // Load / store multiple Instructions.
1707 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1708 InstrItinClass itin_upd, bit L_bit> {
1710 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1711 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1715 let Inst{31-27} = 0b11101;
1716 let Inst{26-25} = 0b00;
1717 let Inst{24-23} = 0b01; // Increment After
1719 let Inst{21} = 0; // No writeback
1720 let Inst{20} = L_bit;
1721 let Inst{19-16} = Rn;
1722 let Inst{15-0} = regs;
1725 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1726 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1730 let Inst{31-27} = 0b11101;
1731 let Inst{26-25} = 0b00;
1732 let Inst{24-23} = 0b01; // Increment After
1734 let Inst{21} = 1; // Writeback
1735 let Inst{20} = L_bit;
1736 let Inst{19-16} = Rn;
1737 let Inst{15-0} = regs;
1740 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1741 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1745 let Inst{31-27} = 0b11101;
1746 let Inst{26-25} = 0b00;
1747 let Inst{24-23} = 0b10; // Decrement Before
1749 let Inst{21} = 0; // No writeback
1750 let Inst{20} = L_bit;
1751 let Inst{19-16} = Rn;
1752 let Inst{15-0} = regs;
1755 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1756 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1760 let Inst{31-27} = 0b11101;
1761 let Inst{26-25} = 0b00;
1762 let Inst{24-23} = 0b10; // Decrement Before
1764 let Inst{21} = 1; // Writeback
1765 let Inst{20} = L_bit;
1766 let Inst{19-16} = Rn;
1767 let Inst{15-0} = regs;
1771 let hasSideEffects = 0 in {
1773 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1774 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1776 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1777 InstrItinClass itin_upd, bit L_bit> {
1779 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1780 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1784 let Inst{31-27} = 0b11101;
1785 let Inst{26-25} = 0b00;
1786 let Inst{24-23} = 0b01; // Increment After
1788 let Inst{21} = 0; // No writeback
1789 let Inst{20} = L_bit;
1790 let Inst{19-16} = Rn;
1792 let Inst{14} = regs{14};
1794 let Inst{12-0} = regs{12-0};
1797 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1798 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1802 let Inst{31-27} = 0b11101;
1803 let Inst{26-25} = 0b00;
1804 let Inst{24-23} = 0b01; // Increment After
1806 let Inst{21} = 1; // Writeback
1807 let Inst{20} = L_bit;
1808 let Inst{19-16} = Rn;
1810 let Inst{14} = regs{14};
1812 let Inst{12-0} = regs{12-0};
1815 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1816 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1820 let Inst{31-27} = 0b11101;
1821 let Inst{26-25} = 0b00;
1822 let Inst{24-23} = 0b10; // Decrement Before
1824 let Inst{21} = 0; // No writeback
1825 let Inst{20} = L_bit;
1826 let Inst{19-16} = Rn;
1828 let Inst{14} = regs{14};
1830 let Inst{12-0} = regs{12-0};
1833 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1834 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1838 let Inst{31-27} = 0b11101;
1839 let Inst{26-25} = 0b00;
1840 let Inst{24-23} = 0b10; // Decrement Before
1842 let Inst{21} = 1; // Writeback
1843 let Inst{20} = L_bit;
1844 let Inst{19-16} = Rn;
1846 let Inst{14} = regs{14};
1848 let Inst{12-0} = regs{12-0};
1853 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1854 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1859 //===----------------------------------------------------------------------===//
1860 // Move Instructions.
1863 let hasSideEffects = 0 in
1864 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1865 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1866 let Inst{31-27} = 0b11101;
1867 let Inst{26-25} = 0b01;
1868 let Inst{24-21} = 0b0010;
1869 let Inst{19-16} = 0b1111; // Rn
1870 let Inst{14-12} = 0b000;
1871 let Inst{7-4} = 0b0000;
1873 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1874 pred:$p, zero_reg)>;
1875 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1877 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1880 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1881 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1882 AddedComplexity = 1 in
1883 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1884 "mov", ".w\t$Rd, $imm",
1885 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1886 let Inst{31-27} = 0b11110;
1888 let Inst{24-21} = 0b0010;
1889 let Inst{19-16} = 0b1111; // Rn
1893 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1894 // Use aliases to get that to play nice here.
1895 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1897 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1900 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1901 pred:$p, zero_reg)>;
1902 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1903 pred:$p, zero_reg)>;
1905 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1906 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1907 "movw", "\t$Rd, $imm",
1908 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
1909 Requires<[IsThumb, HasV8MBaseline]> {
1910 let Inst{31-27} = 0b11110;
1912 let Inst{24-21} = 0b0010;
1913 let Inst{20} = 0; // The S bit.
1919 let Inst{11-8} = Rd;
1920 let Inst{19-16} = imm{15-12};
1921 let Inst{26} = imm{11};
1922 let Inst{14-12} = imm{10-8};
1923 let Inst{7-0} = imm{7-0};
1924 let DecoderMethod = "DecodeT2MOVTWInstruction";
1927 def : InstAlias<"mov${p} $Rd, $imm",
1928 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
1929 Requires<[IsThumb, HasV8MBaseline]>;
1931 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1932 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1934 let Constraints = "$src = $Rd" in {
1935 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1936 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1937 "movt", "\t$Rd, $imm",
1939 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1941 Requires<[IsThumb, HasV8MBaseline]> {
1942 let Inst{31-27} = 0b11110;
1944 let Inst{24-21} = 0b0110;
1945 let Inst{20} = 0; // The S bit.
1951 let Inst{11-8} = Rd;
1952 let Inst{19-16} = imm{15-12};
1953 let Inst{26} = imm{11};
1954 let Inst{14-12} = imm{10-8};
1955 let Inst{7-0} = imm{7-0};
1956 let DecoderMethod = "DecodeT2MOVTWInstruction";
1959 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1960 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1961 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
1964 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1966 //===----------------------------------------------------------------------===//
1967 // Extend Instructions.
1972 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1973 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1974 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1975 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1976 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1978 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1979 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1980 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1981 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1982 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1984 // A simple right-shift can also be used in most cases (the exception is the
1985 // SXTH operations with a rotate of 24: there the non-contiguous bits are
1987 def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
1988 (srl rGPR:$Rm, rot_imm:$rot), i8)),
1989 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
1990 def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
1991 (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
1992 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
1993 def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
1994 (rotr rGPR:$Rm, (i32 24)), i16)),
1995 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
1996 def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
1997 (or (srl rGPR:$Rm, (i32 24)),
1998 (shl rGPR:$Rm, (i32 8))), i16)),
1999 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
2003 let AddedComplexity = 16 in {
2004 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
2005 UnOpFrag<(and node:$Src, 0x000000FF)>>;
2006 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
2007 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2008 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
2009 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2011 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2012 // The transformation should probably be done as a combiner action
2013 // instead so we can include a check for masking back in the upper
2014 // eight bits of the source into the lower eight bits of the result.
2015 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2016 // (t2UXTB16 rGPR:$Src, 3)>,
2017 // Requires<[HasT2ExtractPack, IsThumb2]>;
2018 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2019 (t2UXTB16 rGPR:$Src, 1)>,
2020 Requires<[HasT2ExtractPack, IsThumb2]>;
2022 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
2023 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2024 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
2025 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2026 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
2028 def : Thumb2ExtractPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),
2030 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2031 def : Thumb2ExtractPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
2033 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2037 //===----------------------------------------------------------------------===//
2038 // Arithmetic Instructions.
2042 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
2043 defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
2045 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2047 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
2048 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
2049 // AdjustInstrPostInstrSelection where we determine whether or not to
2050 // set the "s" bit based on CPSR liveness.
2052 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2053 // support for an optional CPSR definition that corresponds to the DAG
2054 // node's second value. We can then eliminate the implicit def of CPSR.
2055 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;
2056 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;
2058 let hasPostISelHook = 1 in {
2059 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>;
2060 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>;
2064 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;
2066 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2067 // CPSR and the implicit def of CPSR is not needed.
2068 defm t2RSBS : T2I_rbin_s_is <ARMsubc>;
2070 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2071 // The assume-no-carry-in form uses the negation of the input since add/sub
2072 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2073 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2075 // The AddedComplexity preferences the first variant over the others since
2076 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2077 let AddedComplexity = 1 in
2078 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2079 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2080 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2081 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2082 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2083 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2084 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2085 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2087 let AddedComplexity = 1 in
2088 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2089 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2090 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2091 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2092 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2093 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2094 // The with-carry-in form matches bitwise not instead of the negation.
2095 // Effectively, the inverse interpretation of the carry flag already accounts
2096 // for part of the negation.
2097 let AddedComplexity = 1 in
2098 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2099 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2100 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2101 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2102 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2103 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2105 // Select Bytes -- for disassembly only
2107 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2108 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2109 Requires<[IsThumb2, HasDSP]> {
2110 let Inst{31-27} = 0b11111;
2111 let Inst{26-24} = 0b010;
2113 let Inst{22-20} = 0b010;
2114 let Inst{15-12} = 0b1111;
2116 let Inst{6-4} = 0b000;
2119 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2120 // And Miscellaneous operations -- for disassembly only
2121 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2122 list<dag> pat = [/* For disassembly only; pattern left blank */],
2123 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2124 string asm = "\t$Rd, $Rn, $Rm">
2125 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2126 Requires<[IsThumb2, HasDSP]> {
2127 let Inst{31-27} = 0b11111;
2128 let Inst{26-23} = 0b0101;
2129 let Inst{22-20} = op22_20;
2130 let Inst{15-12} = 0b1111;
2131 let Inst{7-4} = op7_4;
2137 let Inst{11-8} = Rd;
2138 let Inst{19-16} = Rn;
2142 // Saturating add/subtract -- for disassembly only
2144 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2145 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2146 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2147 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2148 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2149 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2150 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2151 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2152 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2153 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2154 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2155 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2156 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2157 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2158 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2159 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2160 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2161 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2162 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2163 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2164 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2165 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2167 // Signed/Unsigned add/subtract -- for disassembly only
2169 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2170 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2171 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2172 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2173 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2174 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2175 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2176 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2177 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2178 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2179 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2180 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2182 // Signed/Unsigned halving add/subtract -- for disassembly only
2184 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2185 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2186 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2187 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2188 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2189 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2190 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2191 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2192 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2193 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2194 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2195 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2197 // Helper class for disassembly only
2198 // A6.3.16 & A6.3.17
2199 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2200 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2201 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2202 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2203 let Inst{31-27} = 0b11111;
2204 let Inst{26-24} = 0b011;
2205 let Inst{23} = long;
2206 let Inst{22-20} = op22_20;
2207 let Inst{7-4} = op7_4;
2210 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2211 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2212 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2213 let Inst{31-27} = 0b11111;
2214 let Inst{26-24} = 0b011;
2215 let Inst{23} = long;
2216 let Inst{22-20} = op22_20;
2217 let Inst{7-4} = op7_4;
2220 // Unsigned Sum of Absolute Differences [and Accumulate].
2221 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2222 (ins rGPR:$Rn, rGPR:$Rm),
2223 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2224 Requires<[IsThumb2, HasDSP]> {
2225 let Inst{15-12} = 0b1111;
2227 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2228 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2229 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2230 Requires<[IsThumb2, HasDSP]>;
2232 // Signed/Unsigned saturate.
2233 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2234 string opc, string asm, list<dag> pattern>
2235 : T2I<oops, iops, itin, opc, asm, pattern> {
2241 let Inst{11-8} = Rd;
2242 let Inst{19-16} = Rn;
2243 let Inst{4-0} = sat_imm;
2244 let Inst{21} = sh{5};
2245 let Inst{14-12} = sh{4-2};
2246 let Inst{7-6} = sh{1-0};
2251 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2252 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
2253 Requires<[IsThumb2]> {
2254 let Inst{31-27} = 0b11110;
2255 let Inst{25-22} = 0b1100;
2261 def t2SSAT16: T2SatI<
2262 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2263 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2264 Requires<[IsThumb2, HasDSP]> {
2265 let Inst{31-27} = 0b11110;
2266 let Inst{25-22} = 0b1100;
2269 let Inst{21} = 1; // sh = '1'
2270 let Inst{14-12} = 0b000; // imm3 = '000'
2271 let Inst{7-6} = 0b00; // imm2 = '00'
2272 let Inst{5-4} = 0b00;
2277 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2278 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
2279 Requires<[IsThumb2]> {
2280 let Inst{31-27} = 0b11110;
2281 let Inst{25-22} = 0b1110;
2286 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2288 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2289 Requires<[IsThumb2, HasDSP]> {
2290 let Inst{31-22} = 0b1111001110;
2293 let Inst{21} = 1; // sh = '1'
2294 let Inst{14-12} = 0b000; // imm3 = '000'
2295 let Inst{7-6} = 0b00; // imm2 = '00'
2296 let Inst{5-4} = 0b00;
2299 def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos), (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
2300 def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos), (t2USAT imm0_31:$pos, GPR:$a, 0)>;
2301 def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
2302 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2304 //===----------------------------------------------------------------------===//
2305 // Shift and rotate Instructions.
2308 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31, shl>;
2309 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2310 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;
2311 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, rotr>;
2313 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2314 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2315 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2317 let Uses = [CPSR] in {
2318 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2319 "rrx", "\t$Rd, $Rm",
2320 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2321 let Inst{31-27} = 0b11101;
2322 let Inst{26-25} = 0b01;
2323 let Inst{24-21} = 0b0010;
2324 let Inst{19-16} = 0b1111; // Rn
2325 let Inst{14-12} = 0b000;
2326 let Inst{7-4} = 0b0011;
2330 let isCodeGenOnly = 1, Defs = [CPSR] in {
2331 def t2MOVsrl_flag : T2TwoRegShiftImm<
2332 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2333 "lsrs", ".w\t$Rd, $Rm, #1",
2334 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2336 let Inst{31-27} = 0b11101;
2337 let Inst{26-25} = 0b01;
2338 let Inst{24-21} = 0b0010;
2339 let Inst{20} = 1; // The S bit.
2340 let Inst{19-16} = 0b1111; // Rn
2341 let Inst{5-4} = 0b01; // Shift type.
2342 // Shift amount = Inst{14-12:7-6} = 1.
2343 let Inst{14-12} = 0b000;
2344 let Inst{7-6} = 0b01;
2346 def t2MOVsra_flag : T2TwoRegShiftImm<
2347 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2348 "asrs", ".w\t$Rd, $Rm, #1",
2349 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2351 let Inst{31-27} = 0b11101;
2352 let Inst{26-25} = 0b01;
2353 let Inst{24-21} = 0b0010;
2354 let Inst{20} = 1; // The S bit.
2355 let Inst{19-16} = 0b1111; // Rn
2356 let Inst{5-4} = 0b10; // Shift type.
2357 // Shift amount = Inst{14-12:7-6} = 1.
2358 let Inst{14-12} = 0b000;
2359 let Inst{7-6} = 0b01;
2363 //===----------------------------------------------------------------------===//
2364 // Bitwise Instructions.
2367 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2368 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>;
2369 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2370 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>;
2371 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2372 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>;
2374 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2375 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2376 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2378 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2379 string opc, string asm, list<dag> pattern>
2380 : T2I<oops, iops, itin, opc, asm, pattern> {
2385 let Inst{11-8} = Rd;
2386 let Inst{4-0} = msb{4-0};
2387 let Inst{14-12} = lsb{4-2};
2388 let Inst{7-6} = lsb{1-0};
2391 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2392 string opc, string asm, list<dag> pattern>
2393 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2396 let Inst{19-16} = Rn;
2399 let Constraints = "$src = $Rd" in
2400 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2401 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2402 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2403 let Inst{31-27} = 0b11110;
2404 let Inst{26} = 0; // should be 0.
2406 let Inst{24-20} = 0b10110;
2407 let Inst{19-16} = 0b1111; // Rn
2409 let Inst{5} = 0; // should be 0.
2412 let msb{4-0} = imm{9-5};
2413 let lsb{4-0} = imm{4-0};
2416 def t2SBFX: T2TwoRegBitFI<
2417 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2418 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2419 let Inst{31-27} = 0b11110;
2421 let Inst{24-20} = 0b10100;
2425 def t2UBFX: T2TwoRegBitFI<
2426 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2427 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2428 let Inst{31-27} = 0b11110;
2430 let Inst{24-20} = 0b11100;
2434 // A8.8.247 UDF - Undefined (Encoding T2)
2435 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2436 [(int_arm_undefined imm0_65535:$imm16)]> {
2438 let Inst{31-29} = 0b111;
2439 let Inst{28-27} = 0b10;
2440 let Inst{26-20} = 0b1111111;
2441 let Inst{19-16} = imm16{15-12};
2443 let Inst{14-12} = 0b010;
2444 let Inst{11-0} = imm16{11-0};
2447 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2448 let Constraints = "$src = $Rd" in {
2449 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2450 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2451 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2452 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2453 bf_inv_mask_imm:$imm))]> {
2454 let Inst{31-27} = 0b11110;
2455 let Inst{26} = 0; // should be 0.
2457 let Inst{24-20} = 0b10110;
2459 let Inst{5} = 0; // should be 0.
2462 let msb{4-0} = imm{9-5};
2463 let lsb{4-0} = imm{4-0};
2467 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2468 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2469 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2471 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2472 /// unary operation that produces a value. These are predicable and can be
2473 /// changed to modify CPSR.
2474 multiclass T2I_un_irs<bits<4> opcod, string opc,
2475 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2477 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2479 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2481 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2482 let isAsCheapAsAMove = Cheap;
2483 let isReMaterializable = ReMat;
2484 let isMoveImm = MoveImm;
2485 let Inst{31-27} = 0b11110;
2487 let Inst{24-21} = opcod;
2488 let Inst{19-16} = 0b1111; // Rn
2492 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2493 opc, ".w\t$Rd, $Rm",
2494 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2495 let Inst{31-27} = 0b11101;
2496 let Inst{26-25} = 0b01;
2497 let Inst{24-21} = opcod;
2498 let Inst{19-16} = 0b1111; // Rn
2499 let Inst{14-12} = 0b000; // imm3
2500 let Inst{7-6} = 0b00; // imm2
2501 let Inst{5-4} = 0b00; // type
2504 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2505 opc, ".w\t$Rd, $ShiftedRm",
2506 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2508 let Inst{31-27} = 0b11101;
2509 let Inst{26-25} = 0b01;
2510 let Inst{24-21} = opcod;
2511 let Inst{19-16} = 0b1111; // Rn
2515 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2516 let AddedComplexity = 1 in
2517 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2518 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2521 let AddedComplexity = 1 in
2522 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2523 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2525 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2526 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2527 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2530 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2531 // will match the extended, not the original bitWidth for $src.
2532 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2533 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2536 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2537 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2538 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2539 Requires<[IsThumb2]>;
2541 def : T2Pat<(t2_so_imm_not:$src),
2542 (t2MVNi t2_so_imm_not:$src)>;
2544 //===----------------------------------------------------------------------===//
2545 // Multiply Instructions.
2547 let isCommutable = 1 in
2548 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2549 "mul", "\t$Rd, $Rn, $Rm",
2550 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2551 let Inst{31-27} = 0b11111;
2552 let Inst{26-23} = 0b0110;
2553 let Inst{22-20} = 0b000;
2554 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2555 let Inst{7-4} = 0b0000; // Multiply
2558 class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
2559 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2560 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2561 Requires<[IsThumb2, UseMulOps]> {
2562 let Inst{31-27} = 0b11111;
2563 let Inst{26-23} = 0b0110;
2564 let Inst{22-20} = 0b000;
2565 let Inst{7-4} = op7_4;
2568 def t2MLA : T2FourRegMLA<0b0000, "mla",
2569 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
2571 def t2MLS: T2FourRegMLA<0b0001, "mls",
2572 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
2575 // Extra precision multiplies with low / high results
2576 let hasSideEffects = 0 in {
2577 let isCommutable = 1 in {
2578 def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>;
2579 def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>;
2582 // Multiply + accumulate
2583 def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
2584 def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
2585 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
2588 // Rounding variants of the below included for disassembly only
2590 // Most significant word multiply
2591 class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
2592 : T2ThreeReg<(outs rGPR:$Rd),
2593 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2594 opc, "\t$Rd, $Rn, $Rm", pattern>,
2595 Requires<[IsThumb2, HasDSP]> {
2596 let Inst{31-27} = 0b11111;
2597 let Inst{26-23} = 0b0110;
2598 let Inst{22-20} = 0b101;
2599 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2600 let Inst{7-4} = op7_4;
2602 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
2604 def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
2606 class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
2608 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2609 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2610 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2611 let Inst{31-27} = 0b11111;
2612 let Inst{26-23} = 0b0110;
2613 let Inst{22-20} = op22_20;
2614 let Inst{7-4} = op7_4;
2617 def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
2618 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
2619 def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
2620 def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
2621 def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
2623 class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
2625 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
2626 "\t$Rd, $Rn, $Rm", pattern>,
2627 Requires<[IsThumb2, HasDSP]> {
2628 let Inst{31-27} = 0b11111;
2629 let Inst{26-23} = 0b0110;
2630 let Inst{22-20} = op22_20;
2631 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2632 let Inst{7-6} = 0b00;
2633 let Inst{5-4} = op5_4;
2636 def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
2637 [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
2638 (sext_inreg rGPR:$Rm, i16)))]>;
2639 def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
2640 [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
2641 (sra rGPR:$Rm, (i32 16))))]>;
2642 def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
2643 [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
2644 (sext_inreg rGPR:$Rm, i16)))]>;
2645 def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
2646 [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
2647 (sra rGPR:$Rm, (i32 16))))]>;
2648 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
2649 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
2651 def : Thumb2DSPPat<(mul sext_16_node:$Rm, sext_16_node:$Rn),
2652 (t2SMULBB rGPR:$Rm, rGPR:$Rn)>;
2653 def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16))),
2654 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;
2655 def : Thumb2DSPPat<(mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm),
2656 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;
2658 class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc,
2660 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
2661 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2662 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2663 let Inst{31-27} = 0b11111;
2664 let Inst{26-23} = 0b0110;
2665 let Inst{22-20} = op22_20;
2666 let Inst{7-6} = 0b00;
2667 let Inst{5-4} = op5_4;
2670 def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",
2671 [(set rGPR:$Rd, (add rGPR:$Ra,
2672 (mul (sext_inreg rGPR:$Rn, i16),
2673 (sext_inreg rGPR:$Rm, i16))))]>;
2674 def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",
2675 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
2676 (sra rGPR:$Rm, (i32 16)))))]>;
2677 def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
2678 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
2679 (sext_inreg rGPR:$Rm, i16))))]>;
2680 def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
2681 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
2682 (sra rGPR:$Rm, (i32 16)))))]>;
2683 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb", []>;
2684 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", []>;
2686 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),
2687 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2688 def : Thumb2DSPMulPat<(add rGPR:$Ra,
2689 (mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16)))),
2690 (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2691 def : Thumb2DSPMulPat<(add rGPR:$Ra,
2692 (mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm)),
2693 (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2695 class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern>
2696 : T2FourReg_mac<1, op22_20, op7_4,
2697 (outs rGPR:$Ra, rGPR:$Rd),
2698 (ins rGPR:$Rn, rGPR:$Rm),
2699 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
2700 Requires<[IsThumb2, HasDSP]>;
2702 // Halfword multiple accumulate long: SMLAL<x><y>
2703 def t2SMLALBB : T2SMLAL<0b100, 0b1000, "smlalbb", []>;
2704 def t2SMLALBT : T2SMLAL<0b100, 0b1001, "smlalbt", []>;
2705 def t2SMLALTB : T2SMLAL<0b100, 0b1010, "smlaltb", []>;
2706 def t2SMLALTT : T2SMLAL<0b100, 0b1011, "smlaltt", []>;
2708 class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc>
2709 : T2ThreeReg_mac<0, op22_20, op7_4,
2711 (ins rGPR:$Rn, rGPR:$Rm),
2712 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
2713 Requires<[IsThumb2, HasDSP]> {
2714 let Inst{15-12} = 0b1111;
2717 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2718 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">;
2719 def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">;
2720 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">;
2721 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">;
2723 class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc>
2724 : T2FourReg_mac<0, op22_20, op7_4,
2726 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
2727 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>,
2728 Requires<[IsThumb2, HasDSP]>;
2730 def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad">;
2731 def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx">;
2732 def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">;
2733 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">;
2735 class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
2736 : T2FourReg_mac<1, op22_20, op7_4,
2737 (outs rGPR:$Ra, rGPR:$Rd),
2738 (ins rGPR:$Rn, rGPR:$Rm),
2739 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
2740 Requires<[IsThumb2, HasDSP]>;
2742 def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
2743 def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
2744 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
2745 def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
2747 //===----------------------------------------------------------------------===//
2748 // Division Instructions.
2749 // Signed and unsigned division on v7-M
2751 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2752 "sdiv", "\t$Rd, $Rn, $Rm",
2753 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2754 Requires<[HasDivide, IsThumb, HasV8MBaseline]> {
2755 let Inst{31-27} = 0b11111;
2756 let Inst{26-21} = 0b011100;
2758 let Inst{15-12} = 0b1111;
2759 let Inst{7-4} = 0b1111;
2762 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2763 "udiv", "\t$Rd, $Rn, $Rm",
2764 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2765 Requires<[HasDivide, IsThumb, HasV8MBaseline]> {
2766 let Inst{31-27} = 0b11111;
2767 let Inst{26-21} = 0b011101;
2769 let Inst{15-12} = 0b1111;
2770 let Inst{7-4} = 0b1111;
2773 //===----------------------------------------------------------------------===//
2774 // Misc. Arithmetic Instructions.
2777 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2778 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2779 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2780 let Inst{31-27} = 0b11111;
2781 let Inst{26-22} = 0b01010;
2782 let Inst{21-20} = op1;
2783 let Inst{15-12} = 0b1111;
2784 let Inst{7-6} = 0b10;
2785 let Inst{5-4} = op2;
2789 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2790 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2793 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2794 "rbit", "\t$Rd, $Rm",
2795 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
2798 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2799 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2802 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2803 "rev16", ".w\t$Rd, $Rm",
2804 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2807 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2808 "revsh", ".w\t$Rd, $Rm",
2809 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2812 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2813 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2814 (t2REVSH rGPR:$Rm)>;
2816 def t2PKHBT : T2ThreeReg<
2817 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2818 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2819 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2820 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2822 Requires<[HasT2ExtractPack, IsThumb2]>,
2823 Sched<[WriteALUsi, ReadALU]> {
2824 let Inst{31-27} = 0b11101;
2825 let Inst{26-25} = 0b01;
2826 let Inst{24-20} = 0b01100;
2827 let Inst{5} = 0; // BT form
2831 let Inst{14-12} = sh{4-2};
2832 let Inst{7-6} = sh{1-0};
2835 // Alternate cases for PKHBT where identities eliminate some nodes.
2836 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2837 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2838 Requires<[HasT2ExtractPack, IsThumb2]>;
2839 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2840 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2841 Requires<[HasT2ExtractPack, IsThumb2]>;
2843 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2844 // will match the pattern below.
2845 def t2PKHTB : T2ThreeReg<
2846 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2847 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2848 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2849 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2851 Requires<[HasT2ExtractPack, IsThumb2]>,
2852 Sched<[WriteALUsi, ReadALU]> {
2853 let Inst{31-27} = 0b11101;
2854 let Inst{26-25} = 0b01;
2855 let Inst{24-20} = 0b01100;
2856 let Inst{5} = 1; // TB form
2860 let Inst{14-12} = sh{4-2};
2861 let Inst{7-6} = sh{1-0};
2864 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2865 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2866 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
2867 // pkhtb src1, src2, asr (17..31).
2868 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
2869 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
2870 Requires<[HasT2ExtractPack, IsThumb2]>;
2871 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
2872 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2873 Requires<[HasT2ExtractPack, IsThumb2]>;
2874 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2875 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2876 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2877 Requires<[HasT2ExtractPack, IsThumb2]>;
2879 //===----------------------------------------------------------------------===//
2880 // CRC32 Instructions
2883 // + CRC32{B,H,W} 0x04C11DB7
2884 // + CRC32C{B,H,W} 0x1EDC6F41
2887 class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
2888 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
2889 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
2890 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
2891 Requires<[IsThumb2, HasV8, HasCRC]> {
2892 let Inst{31-27} = 0b11111;
2893 let Inst{26-21} = 0b010110;
2895 let Inst{15-12} = 0b1111;
2896 let Inst{7-6} = 0b10;
2900 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
2901 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
2902 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
2903 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
2904 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
2905 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
2907 //===----------------------------------------------------------------------===//
2908 // Comparison Instructions...
2910 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2911 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>;
2913 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2914 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2915 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2916 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2917 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2918 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2920 let isCompare = 1, Defs = [CPSR] in {
2922 def t2CMNri : T2OneRegCmpImm<
2923 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
2924 "cmn", ".w\t$Rn, $imm",
2925 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
2926 Sched<[WriteCMP, ReadALU]> {
2927 let Inst{31-27} = 0b11110;
2929 let Inst{24-21} = 0b1000;
2930 let Inst{20} = 1; // The S bit.
2932 let Inst{11-8} = 0b1111; // Rd
2935 def t2CMNzrr : T2TwoRegCmp<
2936 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
2937 "cmn", ".w\t$Rn, $Rm",
2938 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2939 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
2940 let Inst{31-27} = 0b11101;
2941 let Inst{26-25} = 0b01;
2942 let Inst{24-21} = 0b1000;
2943 let Inst{20} = 1; // The S bit.
2944 let Inst{14-12} = 0b000; // imm3
2945 let Inst{11-8} = 0b1111; // Rd
2946 let Inst{7-6} = 0b00; // imm2
2947 let Inst{5-4} = 0b00; // type
2950 def t2CMNzrs : T2OneRegCmpShiftedReg<
2951 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
2952 "cmn", ".w\t$Rn, $ShiftedRm",
2953 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2954 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
2955 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
2956 let Inst{31-27} = 0b11101;
2957 let Inst{26-25} = 0b01;
2958 let Inst{24-21} = 0b1000;
2959 let Inst{20} = 1; // The S bit.
2960 let Inst{11-8} = 0b1111; // Rd
2964 // Assembler aliases w/o the ".w" suffix.
2965 // No alias here for 'rr' version as not all instantiations of this multiclass
2966 // want one (CMP in particular, does not).
2967 def : t2InstAlias<"cmn${p} $Rn, $imm",
2968 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
2969 def : t2InstAlias<"cmn${p} $Rn, $shift",
2970 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
2972 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2973 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2975 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2976 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2978 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2979 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2980 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2981 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2982 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2983 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2985 // Conditional moves
2986 let hasSideEffects = 0 in {
2988 let isCommutable = 1, isSelect = 1 in
2989 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2990 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
2992 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
2994 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
2996 let isMoveImm = 1 in
2998 : t2PseudoInst<(outs rGPR:$Rd),
2999 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3001 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3003 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3005 let isCodeGenOnly = 1 in {
3006 let isMoveImm = 1 in
3008 : t2PseudoInst<(outs rGPR:$Rd),
3009 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3011 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3013 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3015 let isMoveImm = 1 in
3017 : t2PseudoInst<(outs rGPR:$Rd),
3018 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3021 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3023 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3025 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3026 : t2PseudoInst<(outs rGPR:$Rd),
3027 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3029 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3030 (opnode rGPR:$Rm, (i32 ty:$imm)),
3032 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3034 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3035 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3036 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3037 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3039 let isMoveImm = 1 in
3041 : t2PseudoInst<(outs rGPR:$dst),
3042 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3044 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3046 RegConstraint<"$false = $dst">;
3047 } // isCodeGenOnly = 1
3051 //===----------------------------------------------------------------------===//
3052 // Atomic operations intrinsics
3055 // memory barriers protect the atomic sequences
3056 let hasSideEffects = 1 in {
3057 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3058 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
3059 Requires<[IsThumb, HasDB]> {
3061 let Inst{31-4} = 0xf3bf8f5;
3062 let Inst{3-0} = opt;
3065 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3066 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
3067 Requires<[IsThumb, HasDB]> {
3069 let Inst{31-4} = 0xf3bf8f4;
3070 let Inst{3-0} = opt;
3073 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3074 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
3075 Requires<[IsThumb, HasDB]> {
3077 let Inst{31-4} = 0xf3bf8f6;
3078 let Inst{3-0} = opt;
3082 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3083 InstrItinClass itin, string opc, string asm, string cstr,
3084 list<dag> pattern, bits<4> rt2 = 0b1111>
3085 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3086 let Inst{31-27} = 0b11101;
3087 let Inst{26-20} = 0b0001101;
3088 let Inst{11-8} = rt2;
3089 let Inst{7-4} = opcod;
3090 let Inst{3-0} = 0b1111;
3094 let Inst{19-16} = addr;
3095 let Inst{15-12} = Rt;
3097 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3098 InstrItinClass itin, string opc, string asm, string cstr,
3099 list<dag> pattern, bits<4> rt2 = 0b1111>
3100 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3101 let Inst{31-27} = 0b11101;
3102 let Inst{26-20} = 0b0001100;
3103 let Inst{11-8} = rt2;
3104 let Inst{7-4} = opcod;
3110 let Inst{19-16} = addr;
3111 let Inst{15-12} = Rt;
3114 let mayLoad = 1 in {
3115 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3116 AddrModeNone, 4, NoItinerary,
3117 "ldrexb", "\t$Rt, $addr", "",
3118 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>,
3119 Requires<[IsThumb, HasV8MBaseline]>;
3120 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3121 AddrModeNone, 4, NoItinerary,
3122 "ldrexh", "\t$Rt, $addr", "",
3123 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,
3124 Requires<[IsThumb, HasV8MBaseline]>;
3125 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3126 AddrModeNone, 4, NoItinerary,
3127 "ldrex", "\t$Rt, $addr", "",
3128 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,
3129 Requires<[IsThumb, HasV8MBaseline]> {
3132 let Inst{31-27} = 0b11101;
3133 let Inst{26-20} = 0b0000101;
3134 let Inst{19-16} = addr{11-8};
3135 let Inst{15-12} = Rt;
3136 let Inst{11-8} = 0b1111;
3137 let Inst{7-0} = addr{7-0};
3139 let hasExtraDefRegAllocReq = 1 in
3140 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3141 (ins addr_offset_none:$addr),
3142 AddrModeNone, 4, NoItinerary,
3143 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3145 Requires<[IsThumb2, IsNotMClass]> {
3147 let Inst{11-8} = Rt2;
3149 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3150 AddrModeNone, 4, NoItinerary,
3151 "ldaexb", "\t$Rt, $addr", "",
3152 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
3153 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3154 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3155 AddrModeNone, 4, NoItinerary,
3156 "ldaexh", "\t$Rt, $addr", "",
3157 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
3158 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3159 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3160 AddrModeNone, 4, NoItinerary,
3161 "ldaex", "\t$Rt, $addr", "",
3162 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
3163 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
3166 let Inst{31-27} = 0b11101;
3167 let Inst{26-20} = 0b0001101;
3168 let Inst{19-16} = addr;
3169 let Inst{15-12} = Rt;
3170 let Inst{11-8} = 0b1111;
3171 let Inst{7-0} = 0b11101111;
3173 let hasExtraDefRegAllocReq = 1 in
3174 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3175 (ins addr_offset_none:$addr),
3176 AddrModeNone, 4, NoItinerary,
3177 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3178 [], {?, ?, ?, ?}>, Requires<[IsThumb,
3179 HasAcquireRelease, HasV7Clrex, IsNotMClass]> {
3181 let Inst{11-8} = Rt2;
3187 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3188 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3189 (ins rGPR:$Rt, addr_offset_none:$addr),
3190 AddrModeNone, 4, NoItinerary,
3191 "strexb", "\t$Rd, $Rt, $addr", "",
3193 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3194 Requires<[IsThumb, HasV8MBaseline]>;
3195 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3196 (ins rGPR:$Rt, addr_offset_none:$addr),
3197 AddrModeNone, 4, NoItinerary,
3198 "strexh", "\t$Rd, $Rt, $addr", "",
3200 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3201 Requires<[IsThumb, HasV8MBaseline]>;
3203 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3204 t2addrmode_imm0_1020s4:$addr),
3205 AddrModeNone, 4, NoItinerary,
3206 "strex", "\t$Rd, $Rt, $addr", "",
3208 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,
3209 Requires<[IsThumb, HasV8MBaseline]> {
3213 let Inst{31-27} = 0b11101;
3214 let Inst{26-20} = 0b0000100;
3215 let Inst{19-16} = addr{11-8};
3216 let Inst{15-12} = Rt;
3217 let Inst{11-8} = Rd;
3218 let Inst{7-0} = addr{7-0};
3220 let hasExtraSrcRegAllocReq = 1 in
3221 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3222 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3223 AddrModeNone, 4, NoItinerary,
3224 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3226 Requires<[IsThumb2, IsNotMClass]> {
3228 let Inst{11-8} = Rt2;
3230 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3231 (ins rGPR:$Rt, addr_offset_none:$addr),
3232 AddrModeNone, 4, NoItinerary,
3233 "stlexb", "\t$Rd, $Rt, $addr", "",
3235 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3236 Requires<[IsThumb, HasAcquireRelease,
3239 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3240 (ins rGPR:$Rt, addr_offset_none:$addr),
3241 AddrModeNone, 4, NoItinerary,
3242 "stlexh", "\t$Rd, $Rt, $addr", "",
3244 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3245 Requires<[IsThumb, HasAcquireRelease,
3248 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3249 addr_offset_none:$addr),
3250 AddrModeNone, 4, NoItinerary,
3251 "stlex", "\t$Rd, $Rt, $addr", "",
3253 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
3254 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
3258 let Inst{31-27} = 0b11101;
3259 let Inst{26-20} = 0b0001100;
3260 let Inst{19-16} = addr;
3261 let Inst{15-12} = Rt;
3262 let Inst{11-4} = 0b11111110;
3265 let hasExtraSrcRegAllocReq = 1 in
3266 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3267 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3268 AddrModeNone, 4, NoItinerary,
3269 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3270 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,
3271 HasV7Clrex, IsNotMClass]> {
3273 let Inst{11-8} = Rt2;
3277 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3278 Requires<[IsThumb, HasV7Clrex]> {
3279 let Inst{31-16} = 0xf3bf;
3280 let Inst{15-14} = 0b10;
3283 let Inst{11-8} = 0b1111;
3284 let Inst{7-4} = 0b0010;
3285 let Inst{3-0} = 0b1111;
3288 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3289 (t2LDREXB addr_offset_none:$addr)>,
3290 Requires<[IsThumb, HasV8MBaseline]>;
3291 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3292 (t2LDREXH addr_offset_none:$addr)>,
3293 Requires<[IsThumb, HasV8MBaseline]>;
3294 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3295 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>,
3296 Requires<[IsThumb, HasV8MBaseline]>;
3297 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3298 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>,
3299 Requires<[IsThumb, HasV8MBaseline]>;
3301 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3302 (t2LDAEXB addr_offset_none:$addr)>,
3303 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3304 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3305 (t2LDAEXH addr_offset_none:$addr)>,
3306 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3307 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3308 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>,
3309 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3310 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3311 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>,
3312 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3314 //===----------------------------------------------------------------------===//
3315 // SJLJ Exception handling intrinsics
3316 // eh_sjlj_setjmp() is an instruction sequence to store the return
3317 // address and save #0 in R0 for the non-longjmp case.
3318 // Since by its nature we may be coming from some other function to get
3319 // here, and we're using the stack frame for the containing function to
3320 // save/restore registers, we can't keep anything live in regs across
3321 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3322 // when we get here from a longjmp(). We force everything out of registers
3323 // except for our own input by listing the relevant registers in Defs. By
3324 // doing so, we also cause the prologue/epilogue code to actively preserve
3325 // all of the callee-saved resgisters, which is exactly what we want.
3326 // $val is a scratch register for our use.
3328 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3329 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3330 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3331 usesCustomInserter = 1 in {
3332 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3333 AddrModeNone, 0, NoItinerary, "", "",
3334 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3335 Requires<[IsThumb2, HasVFP2]>;
3339 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3340 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3341 usesCustomInserter = 1 in {
3342 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3343 AddrModeNone, 0, NoItinerary, "", "",
3344 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3345 Requires<[IsThumb2, NoVFP]>;
3349 //===----------------------------------------------------------------------===//
3350 // Control-Flow Instructions
3353 // FIXME: remove when we have a way to marking a MI with these properties.
3354 // FIXME: Should pc be an implicit operand like PICADD, etc?
3355 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3356 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3357 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3358 reglist:$regs, variable_ops),
3359 4, IIC_iLoad_mBr, [],
3360 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3361 RegConstraint<"$Rn = $wb">;
3363 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3364 let isPredicable = 1 in
3365 def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br,
3367 [(br bb:$target)]>, Sched<[WriteBr]>,
3368 Requires<[IsThumb, HasV8MBaseline]> {
3369 let Inst{31-27} = 0b11110;
3370 let Inst{15-14} = 0b10;
3374 let Inst{26} = target{23};
3375 let Inst{13} = target{22};
3376 let Inst{11} = target{21};
3377 let Inst{25-16} = target{20-11};
3378 let Inst{10-0} = target{10-0};
3379 let DecoderMethod = "DecodeT2BInstruction";
3380 let AsmMatchConverter = "cvtThumbBranches";
3383 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
3385 // available in both v8-M.Baseline and Thumb2 targets
3386 def t2BR_JT : t2basePseudoInst<(outs),
3387 (ins GPR:$target, GPR:$index, i32imm:$jt),
3389 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,
3392 // FIXME: Add a case that can be predicated.
3393 def t2TBB_JT : t2PseudoInst<(outs),
3394 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3397 def t2TBH_JT : t2PseudoInst<(outs),
3398 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3401 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3402 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3405 let Inst{31-20} = 0b111010001101;
3406 let Inst{19-16} = Rn;
3407 let Inst{15-5} = 0b11110000000;
3408 let Inst{4} = 0; // B form
3411 let DecoderMethod = "DecodeThumbTableBranch";
3414 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3415 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3418 let Inst{31-20} = 0b111010001101;
3419 let Inst{19-16} = Rn;
3420 let Inst{15-5} = 0b11110000000;
3421 let Inst{4} = 1; // H form
3424 let DecoderMethod = "DecodeThumbTableBranch";
3426 } // isNotDuplicable, isIndirectBranch
3428 } // isBranch, isTerminator, isBarrier
3430 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3431 // a two-value operand where a dag node expects ", "two operands. :(
3432 let isBranch = 1, isTerminator = 1 in
3433 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3435 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3436 let Inst{31-27} = 0b11110;
3437 let Inst{15-14} = 0b10;
3441 let Inst{25-22} = p;
3444 let Inst{26} = target{20};
3445 let Inst{11} = target{19};
3446 let Inst{13} = target{18};
3447 let Inst{21-16} = target{17-12};
3448 let Inst{10-0} = target{11-1};
3450 let DecoderMethod = "DecodeThumb2BCCInstruction";
3451 let AsmMatchConverter = "cvtThumbBranches";
3454 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
3456 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3459 def tTAILJMPd: tPseudoExpand<(outs),
3460 (ins thumb_br_target:$dst, pred:$p),
3462 (t2B thumb_br_target:$dst, pred:$p)>,
3463 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3467 let Defs = [ITSTATE] in
3468 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3469 AddrModeNone, 2, IIC_iALUx,
3470 "it$mask\t$cc", "", []>,
3471 ComplexDeprecationPredicate<"IT"> {
3472 // 16-bit instruction.
3473 let Inst{31-16} = 0x0000;
3474 let Inst{15-8} = 0b10111111;
3479 let Inst{3-0} = mask;
3481 let DecoderMethod = "DecodeIT";
3484 // Branch and Exchange Jazelle -- for disassembly only
3486 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
3487 def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
3488 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
3490 let Inst{31-27} = 0b11110;
3492 let Inst{25-20} = 0b111100;
3493 let Inst{19-16} = func;
3494 let Inst{15-0} = 0b1000111100000000;
3497 // Compare and branch on zero / non-zero
3498 let isBranch = 1, isTerminator = 1 in {
3499 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3500 "cbz\t$Rn, $target", []>,
3501 T1Misc<{0,0,?,1,?,?,?}>,
3502 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3506 let Inst{9} = target{5};
3507 let Inst{7-3} = target{4-0};
3511 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3512 "cbnz\t$Rn, $target", []>,
3513 T1Misc<{1,0,?,1,?,?,?}>,
3514 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3518 let Inst{9} = target{5};
3519 let Inst{7-3} = target{4-0};
3525 // Change Processor State is a system instruction.
3526 // FIXME: Since the asm parser has currently no clean way to handle optional
3527 // operands, create 3 versions of the same instruction. Once there's a clean
3528 // framework to represent optional operands, change this behavior.
3529 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3530 !strconcat("cps", asm_op), []>,
3531 Requires<[IsThumb2, IsNotMClass]> {
3537 let Inst{31-11} = 0b111100111010111110000;
3538 let Inst{10-9} = imod;
3540 let Inst{7-5} = iflags;
3541 let Inst{4-0} = mode;
3542 let DecoderMethod = "DecodeT2CPSInstruction";
3546 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3547 "$imod\t$iflags, $mode">;
3548 let mode = 0, M = 0 in
3549 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3550 "$imod.w\t$iflags">;
3551 let imod = 0, iflags = 0, M = 1 in
3552 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3554 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3555 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3556 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3558 // A6.3.4 Branches and miscellaneous control
3559 // Table A6-14 Change Processor State, and hint instructions
3560 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
3561 [(int_arm_hint imm0_239:$imm)]> {
3563 let Inst{31-3} = 0b11110011101011111000000000000;
3564 let Inst{7-0} = imm;
3567 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
3568 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
3569 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
3570 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
3571 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
3572 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
3573 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
3574 let Predicates = [IsThumb2, HasV8];
3576 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
3577 let Predicates = [IsThumb2, HasRAS];
3579 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
3580 let Predicates = [IsThumb2, HasRAS];
3583 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
3584 [(int_arm_dbg imm0_15:$opt)]> {
3586 let Inst{31-20} = 0b111100111010;
3587 let Inst{19-16} = 0b1111;
3588 let Inst{15-8} = 0b10000000;
3589 let Inst{7-4} = 0b1111;
3590 let Inst{3-0} = opt;
3593 // Secure Monitor Call is a system instruction.
3594 // Option = Inst{19-16}
3595 let isCall = 1, Uses = [SP] in
3596 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3597 []>, Requires<[IsThumb2, HasTrustZone]> {
3598 let Inst{31-27} = 0b11110;
3599 let Inst{26-20} = 0b1111111;
3600 let Inst{15-12} = 0b1000;
3603 let Inst{19-16} = opt;
3606 class T2DCPS<bits<2> opt, string opc>
3607 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3608 let Inst{31-27} = 0b11110;
3609 let Inst{26-20} = 0b1111000;
3610 let Inst{19-16} = 0b1111;
3611 let Inst{15-12} = 0b1000;
3612 let Inst{11-2} = 0b0000000000;
3613 let Inst{1-0} = opt;
3616 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
3617 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
3618 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
3620 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3621 string opc, string asm, list<dag> pattern>
3622 : T2I<oops, iops, itin, opc, asm, pattern>,
3623 Requires<[IsThumb2,IsNotMClass]> {
3625 let Inst{31-25} = 0b1110100;
3626 let Inst{24-23} = Op;
3629 let Inst{20-16} = 0b01101;
3630 let Inst{15-5} = 0b11000000000;
3631 let Inst{4-0} = mode{4-0};
3634 // Store Return State is a system instruction.
3635 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3636 "srsdb", "\tsp!, $mode", []>;
3637 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3638 "srsdb","\tsp, $mode", []>;
3639 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3640 "srsia","\tsp!, $mode", []>;
3641 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3642 "srsia","\tsp, $mode", []>;
3645 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3646 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3648 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3649 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3651 // Return From Exception is a system instruction.
3652 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3653 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3654 string opc, string asm, list<dag> pattern>
3655 : T2I<oops, iops, itin, opc, asm, pattern>,
3656 Requires<[IsThumb2,IsNotMClass]> {
3657 let Inst{31-20} = op31_20{11-0};
3660 let Inst{19-16} = Rn;
3661 let Inst{15-0} = 0xc000;
3664 def t2RFEDBW : T2RFE<0b111010000011,
3665 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3666 [/* For disassembly only; pattern left blank */]>;
3667 def t2RFEDB : T2RFE<0b111010000001,
3668 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3669 [/* For disassembly only; pattern left blank */]>;
3670 def t2RFEIAW : T2RFE<0b111010011011,
3671 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3672 [/* For disassembly only; pattern left blank */]>;
3673 def t2RFEIA : T2RFE<0b111010011001,
3674 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3675 [/* For disassembly only; pattern left blank */]>;
3677 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
3678 // Exception return instruction is "subs pc, lr, #imm".
3679 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3680 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
3681 "subs", "\tpc, lr, $imm",
3682 [(ARMintretflag imm0_255:$imm)]>,
3683 Requires<[IsThumb2,IsNotMClass]> {
3684 let Inst{31-8} = 0b111100111101111010001111;
3687 let Inst{7-0} = imm;
3690 // Hypervisor Call is a system instruction.
3692 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
3693 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
3695 let Inst{31-20} = 0b111101111110;
3696 let Inst{19-16} = imm16{15-12};
3697 let Inst{15-12} = 0b1000;
3698 let Inst{11-0} = imm16{11-0};
3702 // Alias for HVC without the ".w" optional width specifier
3703 def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
3705 // ERET - Return from exception in Hypervisor mode.
3706 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
3707 // includes virtualization extensions.
3708 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
3709 Requires<[IsThumb2, HasVirtualization]>;
3711 //===----------------------------------------------------------------------===//
3712 // Non-Instruction Patterns
3715 // 32-bit immediate using movw + movt.
3716 // This is a single pseudo instruction to make it re-materializable.
3717 // FIXME: Remove this when we can do generalized remat.
3718 let isReMaterializable = 1, isMoveImm = 1 in
3719 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3720 [(set rGPR:$dst, (i32 imm:$src))]>,
3721 Requires<[IsThumb, UseMovt]>;
3723 // Pseudo instruction that combines movw + movt + add pc (if pic).
3724 // It also makes it possible to rematerialize the instructions.
3725 // FIXME: Remove this when we can do generalized remat and when machine licm
3726 // can properly the instructions.
3727 let isReMaterializable = 1 in {
3728 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3730 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3731 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3735 def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst),
3736 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>,
3737 Requires<[IsThumb2, UseMovt]>;
3738 def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst),
3739 (t2MOVi32imm tglobaltlsaddr:$dst)>,
3740 Requires<[IsThumb2, UseMovt]>;
3742 // ConstantPool, GlobalAddress, and JumpTable
3743 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3744 def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>,
3745 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3746 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3747 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3749 def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;
3751 // Pseudo instruction that combines ldr from constpool and add pc. This should
3752 // be expanded into two instructions late to allow if-conversion and
3754 let canFoldAsLoad = 1, isReMaterializable = 1 in
3755 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3757 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3759 Requires<[IsThumb2]>;
3761 // Pseudo isntruction that combines movs + predicated rsbmi
3762 // to implement integer ABS
3763 let usesCustomInserter = 1, Defs = [CPSR] in {
3764 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3765 NoItinerary, []>, Requires<[IsThumb2]>;
3768 //===----------------------------------------------------------------------===//
3769 // Coprocessor load/store -- for disassembly only
3771 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern>
3772 : T2I<oops, iops, NoItinerary, opc, asm, pattern> {
3773 let Inst{31-28} = op31_28;
3774 let Inst{27-25} = 0b110;
3777 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> {
3778 def _OFFSET : T2CI<op31_28,
3779 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3780 asm, "\t$cop, $CRd, $addr", pattern> {
3784 let Inst{24} = 1; // P = 1
3785 let Inst{23} = addr{8};
3786 let Inst{22} = Dbit;
3787 let Inst{21} = 0; // W = 0
3788 let Inst{20} = load;
3789 let Inst{19-16} = addr{12-9};
3790 let Inst{15-12} = CRd;
3791 let Inst{11-8} = cop;
3792 let Inst{7-0} = addr{7-0};
3793 let DecoderMethod = "DecodeCopMemInstruction";
3795 def _PRE : T2CI<op31_28,
3796 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3797 asm, "\t$cop, $CRd, $addr!", []> {
3801 let Inst{24} = 1; // P = 1
3802 let Inst{23} = addr{8};
3803 let Inst{22} = Dbit;
3804 let Inst{21} = 1; // W = 1
3805 let Inst{20} = load;
3806 let Inst{19-16} = addr{12-9};
3807 let Inst{15-12} = CRd;
3808 let Inst{11-8} = cop;
3809 let Inst{7-0} = addr{7-0};
3810 let DecoderMethod = "DecodeCopMemInstruction";
3812 def _POST: T2CI<op31_28,
3813 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3814 postidx_imm8s4:$offset),
3815 asm, "\t$cop, $CRd, $addr, $offset", []> {
3820 let Inst{24} = 0; // P = 0
3821 let Inst{23} = offset{8};
3822 let Inst{22} = Dbit;
3823 let Inst{21} = 1; // W = 1
3824 let Inst{20} = load;
3825 let Inst{19-16} = addr;
3826 let Inst{15-12} = CRd;
3827 let Inst{11-8} = cop;
3828 let Inst{7-0} = offset{7-0};
3829 let DecoderMethod = "DecodeCopMemInstruction";
3831 def _OPTION : T2CI<op31_28, (outs),
3832 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3833 coproc_option_imm:$option),
3834 asm, "\t$cop, $CRd, $addr, $option", []> {
3839 let Inst{24} = 0; // P = 0
3840 let Inst{23} = 1; // U = 1
3841 let Inst{22} = Dbit;
3842 let Inst{21} = 0; // W = 0
3843 let Inst{20} = load;
3844 let Inst{19-16} = addr;
3845 let Inst{15-12} = CRd;
3846 let Inst{11-8} = cop;
3847 let Inst{7-0} = option;
3848 let DecoderMethod = "DecodeCopMemInstruction";
3852 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3853 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3854 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3855 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3857 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3858 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3859 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3860 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3863 //===----------------------------------------------------------------------===//
3864 // Move between special register and ARM core register -- for disassembly only
3866 // Move to ARM core register from Special Register
3870 // A/R class can only move from CPSR or SPSR.
3871 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3872 []>, Requires<[IsThumb2,IsNotMClass]> {
3874 let Inst{31-12} = 0b11110011111011111000;
3875 let Inst{11-8} = Rd;
3876 let Inst{7-0} = 0b00000000;
3879 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3881 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3882 []>, Requires<[IsThumb2,IsNotMClass]> {
3884 let Inst{31-12} = 0b11110011111111111000;
3885 let Inst{11-8} = Rd;
3886 let Inst{7-0} = 0b00000000;
3889 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
3890 NoItinerary, "mrs", "\t$Rd, $banked", []>,
3891 Requires<[IsThumb, HasVirtualization]> {
3895 let Inst{31-21} = 0b11110011111;
3896 let Inst{20} = banked{5}; // R bit
3897 let Inst{19-16} = banked{3-0};
3898 let Inst{15-12} = 0b1000;
3899 let Inst{11-8} = Rd;
3900 let Inst{7-5} = 0b001;
3901 let Inst{4} = banked{4};
3902 let Inst{3-0} = 0b0000;
3908 // This MRS has a mask field in bits 7-0 and can take more values than
3909 // the A/R class (a full msr_mask).
3910 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
3911 "mrs", "\t$Rd, $SYSm", []>,
3912 Requires<[IsThumb,IsMClass]> {
3915 let Inst{31-12} = 0b11110011111011111000;
3916 let Inst{11-8} = Rd;
3917 let Inst{7-0} = SYSm;
3919 let Unpredictable{20-16} = 0b11111;
3920 let Unpredictable{13} = 0b1;
3924 // Move from ARM core register to Special Register
3928 // No need to have both system and application versions, the encodings are the
3929 // same and the assembly parser has no way to distinguish between them. The mask
3930 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3931 // the mask with the fields to be accessed in the special register.
3932 let Defs = [CPSR] in
3933 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3934 NoItinerary, "msr", "\t$mask, $Rn", []>,
3935 Requires<[IsThumb2,IsNotMClass]> {
3938 let Inst{31-21} = 0b11110011100;
3939 let Inst{20} = mask{4}; // R Bit
3940 let Inst{19-16} = Rn;
3941 let Inst{15-12} = 0b1000;
3942 let Inst{11-8} = mask{3-0};
3946 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
3947 // separate encoding (distinguished by bit 5.
3948 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
3949 NoItinerary, "msr", "\t$banked, $Rn", []>,
3950 Requires<[IsThumb, HasVirtualization]> {
3954 let Inst{31-21} = 0b11110011100;
3955 let Inst{20} = banked{5}; // R bit
3956 let Inst{19-16} = Rn;
3957 let Inst{15-12} = 0b1000;
3958 let Inst{11-8} = banked{3-0};
3959 let Inst{7-5} = 0b001;
3960 let Inst{4} = banked{4};
3961 let Inst{3-0} = 0b0000;
3967 // Move from ARM core register to Special Register
3968 let Defs = [CPSR] in
3969 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3970 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3971 Requires<[IsThumb,IsMClass]> {
3974 let Inst{31-21} = 0b11110011100;
3976 let Inst{19-16} = Rn;
3977 let Inst{15-12} = 0b1000;
3978 let Inst{11-10} = SYSm{11-10};
3979 let Inst{9-8} = 0b00;
3980 let Inst{7-0} = SYSm{7-0};
3982 let Unpredictable{20} = 0b1;
3983 let Unpredictable{13} = 0b1;
3984 let Unpredictable{9-8} = 0b11;
3988 //===----------------------------------------------------------------------===//
3989 // Move between coprocessor and ARM core register
3992 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3994 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3996 let Inst{27-24} = 0b1110;
3997 let Inst{20} = direction;
4007 let Inst{15-12} = Rt;
4008 let Inst{11-8} = cop;
4009 let Inst{23-21} = opc1;
4010 let Inst{7-5} = opc2;
4011 let Inst{3-0} = CRm;
4012 let Inst{19-16} = CRn;
4015 class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4016 list<dag> pattern = []>
4017 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4018 let Inst{27-24} = 0b1100;
4019 let Inst{23-21} = 0b010;
4020 let Inst{20} = direction;
4028 let Inst{15-12} = Rt;
4029 let Inst{19-16} = Rt2;
4030 let Inst{11-8} = cop;
4031 let Inst{7-4} = opc1;
4032 let Inst{3-0} = CRm;
4035 /* from ARM core register to coprocessor */
4036 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4038 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4039 c_imm:$CRm, imm0_7:$opc2),
4040 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4041 imm:$CRm, imm:$opc2)]>,
4042 ComplexDeprecationPredicate<"MCR">;
4043 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4044 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4045 c_imm:$CRm, 0, pred:$p)>;
4046 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4047 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4048 c_imm:$CRm, imm0_7:$opc2),
4049 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4050 imm:$CRm, imm:$opc2)]> {
4051 let Predicates = [IsThumb2, PreV8];
4053 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4054 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4055 c_imm:$CRm, 0, pred:$p)>;
4057 /* from coprocessor to ARM core register */
4058 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4059 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4060 c_imm:$CRm, imm0_7:$opc2), []>;
4061 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4062 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4063 c_imm:$CRm, 0, pred:$p)>;
4065 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4066 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4067 c_imm:$CRm, imm0_7:$opc2), []> {
4068 let Predicates = [IsThumb2, PreV8];
4070 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4071 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4072 c_imm:$CRm, 0, pred:$p)>;
4074 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4075 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4077 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4078 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4081 /* from ARM core register to coprocessor */
4082 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),
4083 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4085 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4087 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),
4088 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4090 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
4091 GPR:$Rt2, imm:$CRm)]> {
4092 let Predicates = [IsThumb2, PreV8];
4095 /* from coprocessor to ARM core register */
4096 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4097 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>;
4099 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),
4100 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> {
4101 let Predicates = [IsThumb2, PreV8];
4104 //===----------------------------------------------------------------------===//
4105 // Other Coprocessor Instructions.
4108 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4109 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4110 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4111 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4112 imm:$CRm, imm:$opc2)]> {
4113 let Inst{27-24} = 0b1110;
4122 let Inst{3-0} = CRm;
4124 let Inst{7-5} = opc2;
4125 let Inst{11-8} = cop;
4126 let Inst{15-12} = CRd;
4127 let Inst{19-16} = CRn;
4128 let Inst{23-20} = opc1;
4130 let Predicates = [IsThumb2, PreV8];
4133 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4134 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4135 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4136 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4137 imm:$CRm, imm:$opc2)]> {
4138 let Inst{27-24} = 0b1110;
4147 let Inst{3-0} = CRm;
4149 let Inst{7-5} = opc2;
4150 let Inst{11-8} = cop;
4151 let Inst{15-12} = CRd;
4152 let Inst{19-16} = CRn;
4153 let Inst{23-20} = opc1;
4155 let Predicates = [IsThumb2, PreV8];
4160 //===----------------------------------------------------------------------===//
4161 // ARMv8.1 Privilege Access Never extension
4165 def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
4166 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4171 let Inst{2-0} = 0b000;
4173 let Unpredictable{4} = 0b1;
4174 let Unpredictable{2-0} = 0b111;
4177 //===----------------------------------------------------------------------===//
4178 // ARMv8-M Security Extensions instructions
4181 let hasSideEffects = 1 in
4182 def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
4183 Requires<[Has8MSecExt]> {
4184 let Inst = 0xe97fe97f;
4187 class T2TT<bits<2> at, string asm, list<dag> pattern>
4188 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
4193 let Inst{31-20} = 0b111010000100;
4194 let Inst{19-16} = Rn;
4195 let Inst{15-12} = 0b1111;
4196 let Inst{11-8} = Rt;
4198 let Inst{5-0} = 0b000000;
4200 let Unpredictable{5-0} = 0b111111;
4203 def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
4204 def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
4205 def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
4206 def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
4208 //===----------------------------------------------------------------------===//
4209 // Non-Instruction Patterns
4212 // SXT/UXT with no rotate
4213 let AddedComplexity = 16 in {
4214 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4215 Requires<[IsThumb2]>;
4216 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4217 Requires<[IsThumb2]>;
4218 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4219 Requires<[HasT2ExtractPack, IsThumb2]>;
4220 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4221 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4222 Requires<[HasT2ExtractPack, IsThumb2]>;
4223 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4224 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4225 Requires<[HasT2ExtractPack, IsThumb2]>;
4228 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4229 Requires<[IsThumb2]>;
4230 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4231 Requires<[IsThumb2]>;
4232 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4233 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4234 Requires<[HasT2ExtractPack, IsThumb2]>;
4235 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4236 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4237 Requires<[HasT2ExtractPack, IsThumb2]>;
4239 // Atomic load/store patterns
4240 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4241 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4242 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4243 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4244 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4245 (t2LDRBs t2addrmode_so_reg:$addr)>;
4246 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4247 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4248 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4249 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4250 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4251 (t2LDRHs t2addrmode_so_reg:$addr)>;
4252 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4253 (t2LDRi12 t2addrmode_imm12:$addr)>;
4254 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4255 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4256 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4257 (t2LDRs t2addrmode_so_reg:$addr)>;
4258 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4259 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4260 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4261 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4262 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4263 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4264 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4265 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4266 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4267 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4268 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4269 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4270 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4271 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4272 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4273 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4274 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4275 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4277 let AddedComplexity = 8 in {
4278 def : T2Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4279 def : T2Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4280 def : T2Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
4281 def : T2Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
4282 def : T2Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
4283 def : T2Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;
4287 //===----------------------------------------------------------------------===//
4288 // Assembler aliases
4291 // Aliases for ADC without the ".w" optional width specifier.
4292 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4293 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4294 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4295 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4296 pred:$p, cc_out:$s)>;
4298 // Aliases for SBC without the ".w" optional width specifier.
4299 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4300 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4301 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4302 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4303 pred:$p, cc_out:$s)>;
4305 // Aliases for ADD without the ".w" optional width specifier.
4306 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4307 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4309 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4310 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4311 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4312 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4313 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4314 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4315 pred:$p, cc_out:$s)>;
4316 // ... and with the destination and source register combined.
4317 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4318 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4319 def : t2InstAlias<"add${p} $Rdn, $imm",
4320 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4321 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4322 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4323 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4324 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4325 pred:$p, cc_out:$s)>;
4327 // add w/ negative immediates is just a sub.
4328 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4329 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4331 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4332 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4333 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4334 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4336 def : t2InstAlias<"add${p} $Rdn, $imm",
4337 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4339 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4340 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4342 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4343 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4344 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4345 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4347 def : t2InstAlias<"addw${p} $Rdn, $imm",
4348 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4351 // Aliases for SUB without the ".w" optional width specifier.
4352 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4353 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4354 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4355 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4356 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4357 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4358 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4359 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4360 pred:$p, cc_out:$s)>;
4361 // ... and with the destination and source register combined.
4362 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4363 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4364 def : t2InstAlias<"sub${p} $Rdn, $imm",
4365 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4366 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4367 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4368 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4369 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4370 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4371 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4372 pred:$p, cc_out:$s)>;
4374 // Alias for compares without the ".w" optional width specifier.
4375 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4376 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4377 def : t2InstAlias<"teq${p} $Rn, $Rm",
4378 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4379 def : t2InstAlias<"tst${p} $Rn, $Rm",
4380 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4383 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4384 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4385 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4387 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4389 def : t2InstAlias<"ldr${p} $Rt, $addr",
4390 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4391 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4392 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4393 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4394 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4395 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4396 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4397 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4398 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4400 def : t2InstAlias<"ldr${p} $Rt, $addr",
4401 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4402 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4403 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4404 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4405 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4406 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4407 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4408 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4409 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4411 def : t2InstAlias<"ldr${p} $Rt, $addr",
4412 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4413 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4414 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4415 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4416 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4417 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4418 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4419 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4420 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4422 // Alias for MVN with(out) the ".w" optional width specifier.
4423 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4424 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4425 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4426 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4427 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4428 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4430 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
4431 // input operands swapped when the shift amount is zero (i.e., unspecified).
4432 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4433 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4434 Requires<[HasT2ExtractPack, IsThumb2]>;
4435 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4436 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
4437 Requires<[HasT2ExtractPack, IsThumb2]>;
4439 // PUSH/POP aliases for STM/LDM
4440 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4441 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4442 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4443 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4445 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4446 def : t2InstAlias<"stm${p} $Rn, $regs",
4447 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4448 def : t2InstAlias<"stm${p} $Rn!, $regs",
4449 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4451 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4452 def : t2InstAlias<"ldm${p} $Rn, $regs",
4453 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4454 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4455 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4457 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4458 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4459 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4460 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4461 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4463 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4464 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4465 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4466 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4467 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4469 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4470 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4471 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4472 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4475 // Alias for RSB without the ".w" optional width specifier, and with optional
4476 // implied destination register.
4477 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4478 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4479 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4480 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4481 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4482 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4483 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4484 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4487 // SSAT/USAT optional shift operand.
4488 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4489 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4490 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4491 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4493 // STM w/o the .w suffix.
4494 def : t2InstAlias<"stm${p} $Rn, $regs",
4495 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4497 // Alias for STR, STRB, and STRH without the ".w" optional
4499 def : t2InstAlias<"str${p} $Rt, $addr",
4500 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4501 def : t2InstAlias<"strb${p} $Rt, $addr",
4502 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4503 def : t2InstAlias<"strh${p} $Rt, $addr",
4504 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4506 def : t2InstAlias<"str${p} $Rt, $addr",
4507 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4508 def : t2InstAlias<"strb${p} $Rt, $addr",
4509 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4510 def : t2InstAlias<"strh${p} $Rt, $addr",
4511 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4513 // Extend instruction optional rotate operand.
4514 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4515 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4516 Requires<[HasT2ExtractPack, IsThumb2]>;
4517 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4518 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4519 Requires<[HasT2ExtractPack, IsThumb2]>;
4520 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4521 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4522 Requires<[HasT2ExtractPack, IsThumb2]>;
4523 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4524 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4525 Requires<[HasT2ExtractPack, IsThumb2]>;
4527 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4528 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4529 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4530 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4531 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4532 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4533 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4534 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4536 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4537 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4538 Requires<[HasT2ExtractPack, IsThumb2]>;
4539 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4540 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4541 Requires<[HasT2ExtractPack, IsThumb2]>;
4542 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4543 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4544 Requires<[HasT2ExtractPack, IsThumb2]>;
4545 def : InstAlias<"uxtb16${p} $Rd, $Rm",
4546 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4547 Requires<[HasT2ExtractPack, IsThumb2]>;
4549 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4550 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4551 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4552 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4553 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4554 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4555 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4556 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4558 // Extend instruction w/o the ".w" optional width specifier.
4559 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4560 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4561 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4562 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4563 Requires<[HasT2ExtractPack, IsThumb2]>;
4564 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4565 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4567 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4568 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4569 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4570 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4571 Requires<[HasT2ExtractPack, IsThumb2]>;
4572 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4573 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4576 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4578 def : t2InstAlias<"mov${p} $Rd, $imm",
4579 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4580 def : t2InstAlias<"mvn${p} $Rd, $imm",
4581 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4582 // Same for AND <--> BIC
4583 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4584 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4585 pred:$p, cc_out:$s)>;
4586 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4587 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4588 pred:$p, cc_out:$s)>;
4589 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4590 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4591 pred:$p, cc_out:$s)>;
4592 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4593 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4594 pred:$p, cc_out:$s)>;
4595 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4596 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4597 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4598 pred:$p, cc_out:$s)>;
4599 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4600 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4601 pred:$p, cc_out:$s)>;
4602 // Same for CMP <--> CMN via t2_so_imm_neg
4603 def : t2InstAlias<"cmp${p} $Rd, $imm",
4604 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4605 def : t2InstAlias<"cmn${p} $Rd, $imm",
4606 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4609 // Wide 'mul' encoding can be specified with only two operands.
4610 def : t2InstAlias<"mul${p} $Rn, $Rm",
4611 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4613 // "neg" is and alias for "rsb rd, rn, #0"
4614 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4615 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4617 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4618 // these, unfortunately.
4619 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4620 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4621 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4622 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4624 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4625 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4626 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4627 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4629 // ADR w/o the .w suffix
4630 def : t2InstAlias<"adr${p} $Rd, $addr",
4631 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4633 // LDR(literal) w/ alternate [pc, #imm] syntax.
4634 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4635 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4636 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4637 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4638 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4639 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4640 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4641 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4642 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4643 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4644 // Version w/ the .w suffix.
4645 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4646 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
4647 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4648 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4649 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4650 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4651 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4652 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4653 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4654 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4656 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4657 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4659 // Pseudo instruction ldr Rt, =immediate
4661 : t2AsmPseudo<"ldr${p} $Rt, $immediate",
4662 (ins GPRnopc:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
4663 // Version w/ the .w suffix.
4664 def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
4665 (t2LDRConstPool GPRnopc:$Rt,
4666 const_pool_asm_imm:$immediate, pred:$p)>;
4668 // PLD/PLDW/PLI with alternate literal form.
4669 def : t2InstAlias<"pld${p} $addr",
4670 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4671 def : InstAlias<"pli${p} $addr",
4672 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
4673 Requires<[IsThumb2,HasV7]>;