1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
61 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
62 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
63 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
67 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
68 // described for so_imm_notSext def below, with sign extension from 16
70 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
71 APInt apIntN = N->getAPIntValue();
72 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
73 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
76 // t2_so_imm - Match a 32-bit immediate operand, which is an
77 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
78 // immediate splatted into multiple bytes of the word.
79 def t2_so_imm_asmoperand : AsmOperandClass {
81 let RenderMethod = "addImmOperands";
84 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
85 return ARM_AM::getT2SOImmVal(Imm) != -1;
87 let ParserMatchClass = t2_so_imm_asmoperand;
88 let EncoderMethod = "getT2SOImmOpValue";
89 let DecoderMethod = "DecodeT2SOImm";
92 // t2_so_imm_not - Match an immediate that is a complement
94 // Note: this pattern doesn't require an encoder method and such, as it's
95 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
96 // is handled by the destination instructions, which use t2_so_imm.
97 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
98 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
99 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
100 }], t2_so_imm_not_XFORM> {
101 let ParserMatchClass = t2_so_imm_not_asmoperand;
104 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
105 // if the upper 16 bits are zero.
106 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
107 APInt apIntN = N->getAPIntValue();
108 if (!apIntN.isIntN(16)) return false;
109 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
110 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
111 }], t2_so_imm_notSext16_XFORM> {
112 let ParserMatchClass = t2_so_imm_not_asmoperand;
115 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
116 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
117 def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{
118 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
119 }], t2_so_imm_neg_XFORM> {
120 let ParserMatchClass = t2_so_imm_neg_asmoperand;
123 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].
124 def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; }
125 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
126 return Imm >= 0 && Imm < 4096;
128 let ParserMatchClass = imm0_4095_asmoperand;
131 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
132 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
133 return (uint32_t)(-N->getZExtValue()) < 4096;
135 let ParserMatchClass = imm0_4095_neg_asmoperand;
138 def imm1_255_neg : PatLeaf<(i32 imm), [{
139 uint32_t Val = -N->getZExtValue();
140 return (Val > 0 && Val < 255);
143 def imm0_255_not : PatLeaf<(i32 imm), [{
144 return (uint32_t)(~N->getZExtValue()) < 255;
147 def lo5AllOne : PatLeaf<(i32 imm), [{
148 // Returns true if all low 5-bits are 1.
149 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
152 // Define Thumb2 specific addressing modes.
154 // t2addrmode_imm12 := reg + imm12
155 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
156 def t2addrmode_imm12 : MemOperand,
157 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
158 let PrintMethod = "printAddrModeImm12Operand<false>";
159 let EncoderMethod = "getAddrModeImm12OpValue";
160 let DecoderMethod = "DecodeT2AddrModeImm12";
161 let ParserMatchClass = t2addrmode_imm12_asmoperand;
162 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
165 // t2ldrlabel := imm12
166 def t2ldrlabel : Operand<i32> {
167 let EncoderMethod = "getAddrModeImm12OpValue";
168 let PrintMethod = "printThumbLdrLabelOperand";
171 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
172 def t2ldr_pcrel_imm12 : Operand<i32> {
173 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
174 // used for assembler pseudo instruction and maps to t2ldrlabel, so
175 // doesn't need encoder or print methods of its own.
178 // ADR instruction labels.
179 def t2adrlabel : Operand<i32> {
180 let EncoderMethod = "getT2AdrLabelOpValue";
181 let PrintMethod = "printAdrLabelOperand<0>";
184 // t2addrmode_posimm8 := reg + imm8
185 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
186 def t2addrmode_posimm8 : MemOperand {
187 let PrintMethod = "printT2AddrModeImm8Operand<false>";
188 let EncoderMethod = "getT2AddrModeImm8OpValue";
189 let DecoderMethod = "DecodeT2AddrModeImm8";
190 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
191 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
194 // t2addrmode_negimm8 := reg - imm8
195 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
196 def t2addrmode_negimm8 : MemOperand,
197 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
198 let PrintMethod = "printT2AddrModeImm8Operand<false>";
199 let EncoderMethod = "getT2AddrModeImm8OpValue";
200 let DecoderMethod = "DecodeT2AddrModeImm8";
201 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
202 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
205 // t2addrmode_imm8 := reg +/- imm8
206 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
207 class T2AddrMode_Imm8 : MemOperand,
208 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
209 let EncoderMethod = "getT2AddrModeImm8OpValue";
210 let DecoderMethod = "DecodeT2AddrModeImm8";
211 let ParserMatchClass = MemImm8OffsetAsmOperand;
212 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
215 def t2addrmode_imm8 : T2AddrMode_Imm8 {
216 let PrintMethod = "printT2AddrModeImm8Operand<false>";
219 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
220 let PrintMethod = "printT2AddrModeImm8Operand<true>";
223 def t2am_imm8_offset : MemOperand,
224 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
225 [], [SDNPWantRoot]> {
226 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
227 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
228 let DecoderMethod = "DecodeT2Imm8";
231 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
232 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
233 class T2AddrMode_Imm8s4 : MemOperand {
234 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
235 let DecoderMethod = "DecodeT2AddrModeImm8s4";
236 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
237 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
240 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
241 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
244 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
245 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
248 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
249 def t2am_imm8s4_offset : MemOperand {
250 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
251 let EncoderMethod = "getT2Imm8s4OpValue";
252 let DecoderMethod = "DecodeT2Imm8S4";
255 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
256 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
257 let Name = "MemImm0_1020s4Offset";
259 def t2addrmode_imm0_1020s4 : MemOperand,
260 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
261 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
262 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
263 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
264 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
265 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
268 // t2addrmode_so_reg := reg + (reg << imm2)
269 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
270 def t2addrmode_so_reg : MemOperand,
271 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
272 let PrintMethod = "printT2AddrModeSoRegOperand";
273 let EncoderMethod = "getT2AddrModeSORegOpValue";
274 let DecoderMethod = "DecodeT2AddrModeSOReg";
275 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
276 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
279 // Addresses for the TBB/TBH instructions.
280 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
281 def addrmode_tbb : MemOperand {
282 let PrintMethod = "printAddrModeTBB";
283 let ParserMatchClass = addrmode_tbb_asmoperand;
284 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
286 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
287 def addrmode_tbh : MemOperand {
288 let PrintMethod = "printAddrModeTBH";
289 let ParserMatchClass = addrmode_tbh_asmoperand;
290 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
293 //===----------------------------------------------------------------------===//
294 // Multiclass helpers...
298 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
299 string opc, string asm, list<dag> pattern>
300 : T2I<oops, iops, itin, opc, asm, pattern> {
305 let Inst{26} = imm{11};
306 let Inst{14-12} = imm{10-8};
307 let Inst{7-0} = imm{7-0};
311 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
312 string opc, string asm, list<dag> pattern>
313 : T2sI<oops, iops, itin, opc, asm, pattern> {
319 let Inst{26} = imm{11};
320 let Inst{14-12} = imm{10-8};
321 let Inst{7-0} = imm{7-0};
324 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
325 string opc, string asm, list<dag> pattern>
326 : T2I<oops, iops, itin, opc, asm, pattern> {
330 let Inst{19-16} = Rn;
331 let Inst{26} = imm{11};
332 let Inst{14-12} = imm{10-8};
333 let Inst{7-0} = imm{7-0};
337 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
338 string opc, string asm, list<dag> pattern>
339 : T2I<oops, iops, itin, opc, asm, pattern> {
344 let Inst{3-0} = ShiftedRm{3-0};
345 let Inst{5-4} = ShiftedRm{6-5};
346 let Inst{14-12} = ShiftedRm{11-9};
347 let Inst{7-6} = ShiftedRm{8-7};
350 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : T2sI<oops, iops, itin, opc, asm, pattern> {
357 let Inst{3-0} = ShiftedRm{3-0};
358 let Inst{5-4} = ShiftedRm{6-5};
359 let Inst{14-12} = ShiftedRm{11-9};
360 let Inst{7-6} = ShiftedRm{8-7};
363 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
364 string opc, string asm, list<dag> pattern>
365 : T2I<oops, iops, itin, opc, asm, pattern> {
369 let Inst{19-16} = Rn;
370 let Inst{3-0} = ShiftedRm{3-0};
371 let Inst{5-4} = ShiftedRm{6-5};
372 let Inst{14-12} = ShiftedRm{11-9};
373 let Inst{7-6} = ShiftedRm{8-7};
376 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
377 string opc, string asm, list<dag> pattern>
378 : T2I<oops, iops, itin, opc, asm, pattern> {
386 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
387 string opc, string asm, list<dag> pattern>
388 : T2sI<oops, iops, itin, opc, asm, pattern> {
396 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
397 string opc, string asm, list<dag> pattern>
398 : T2I<oops, iops, itin, opc, asm, pattern> {
402 let Inst{19-16} = Rn;
407 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
408 string opc, string asm, list<dag> pattern>
409 : T2I<oops, iops, itin, opc, asm, pattern> {
415 let Inst{19-16} = Rn;
416 let Inst{26} = imm{11};
417 let Inst{14-12} = imm{10-8};
418 let Inst{7-0} = imm{7-0};
421 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
422 string opc, string asm, list<dag> pattern>
423 : T2sI<oops, iops, itin, opc, asm, pattern> {
429 let Inst{19-16} = Rn;
430 let Inst{26} = imm{11};
431 let Inst{14-12} = imm{10-8};
432 let Inst{7-0} = imm{7-0};
435 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
436 string opc, string asm, list<dag> pattern>
437 : T2I<oops, iops, itin, opc, asm, pattern> {
444 let Inst{14-12} = imm{4-2};
445 let Inst{7-6} = imm{1-0};
448 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
449 string opc, string asm, list<dag> pattern>
450 : T2sI<oops, iops, itin, opc, asm, pattern> {
457 let Inst{14-12} = imm{4-2};
458 let Inst{7-6} = imm{1-0};
461 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
462 string opc, string asm, list<dag> pattern>
463 : T2I<oops, iops, itin, opc, asm, pattern> {
469 let Inst{19-16} = Rn;
473 class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
474 string asm, list<dag> pattern>
475 : T2XI<oops, iops, itin, asm, pattern> {
481 let Inst{19-16} = Rn;
485 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
486 string opc, string asm, list<dag> pattern>
487 : T2sI<oops, iops, itin, opc, asm, pattern> {
493 let Inst{19-16} = Rn;
497 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
498 string opc, string asm, list<dag> pattern>
499 : T2I<oops, iops, itin, opc, asm, pattern> {
505 let Inst{19-16} = Rn;
506 let Inst{3-0} = ShiftedRm{3-0};
507 let Inst{5-4} = ShiftedRm{6-5};
508 let Inst{14-12} = ShiftedRm{11-9};
509 let Inst{7-6} = ShiftedRm{8-7};
512 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
513 string opc, string asm, list<dag> pattern>
514 : T2sI<oops, iops, itin, opc, asm, pattern> {
520 let Inst{19-16} = Rn;
521 let Inst{3-0} = ShiftedRm{3-0};
522 let Inst{5-4} = ShiftedRm{6-5};
523 let Inst{14-12} = ShiftedRm{11-9};
524 let Inst{7-6} = ShiftedRm{8-7};
527 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
528 string opc, string asm, list<dag> pattern>
529 : T2I<oops, iops, itin, opc, asm, pattern> {
535 let Inst{19-16} = Rn;
536 let Inst{15-12} = Ra;
541 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
542 string opc, list<dag> pattern>
543 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
544 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
545 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> {
551 let Inst{31-23} = 0b111110111;
552 let Inst{22-20} = opc22_20;
553 let Inst{19-16} = Rn;
554 let Inst{15-12} = RdLo;
555 let Inst{11-8} = RdHi;
556 let Inst{7-4} = opc7_4;
559 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
560 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
561 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
562 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
563 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
564 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
570 let Inst{31-23} = 0b111110111;
571 let Inst{22-20} = opc22_20;
572 let Inst{19-16} = Rn;
573 let Inst{15-12} = RdLo;
574 let Inst{11-8} = RdHi;
575 let Inst{7-4} = opc7_4;
580 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
581 /// binary operation that produces a value. These are predicable and can be
582 /// changed to modify CPSR.
583 multiclass T2I_bin_irs<bits<4> opcod, string opc,
584 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
585 SDPatternOperator opnode, bit Commutable = 0,
588 def ri : T2sTwoRegImm<
589 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
590 opc, "\t$Rd, $Rn, $imm",
591 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
592 Sched<[WriteALU, ReadALU]> {
593 let Inst{31-27} = 0b11110;
595 let Inst{24-21} = opcod;
599 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
600 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
601 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
602 Sched<[WriteALU, ReadALU, ReadALU]> {
603 let isCommutable = Commutable;
604 let Inst{31-27} = 0b11101;
605 let Inst{26-25} = 0b01;
606 let Inst{24-21} = opcod;
607 let Inst{14-12} = 0b000; // imm3
608 let Inst{7-6} = 0b00; // imm2
609 let Inst{5-4} = 0b00; // type
612 def rs : T2sTwoRegShiftedReg<
613 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
614 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
615 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
616 Sched<[WriteALUsi, ReadALU]> {
617 let Inst{31-27} = 0b11101;
618 let Inst{26-25} = 0b01;
619 let Inst{24-21} = opcod;
621 // Assembly aliases for optional destination operand when it's the same
622 // as the source operand.
623 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
624 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
625 t2_so_imm:$imm, pred:$p,
627 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
628 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
631 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
632 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
633 t2_so_reg:$shift, pred:$p,
637 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
638 // the ".w" suffix to indicate that they are wide.
639 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
640 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
641 SDPatternOperator opnode, bit Commutable = 0> :
642 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
643 // Assembler aliases w/ the ".w" suffix.
644 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
645 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
647 // Assembler aliases w/o the ".w" suffix.
648 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
649 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
651 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
652 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
653 pred:$p, cc_out:$s)>;
655 // and with the optional destination operand, too.
656 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
657 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
658 pred:$p, cc_out:$s)>;
659 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
660 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
662 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
663 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
664 pred:$p, cc_out:$s)>;
667 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
668 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
669 /// it is equivalent to the T2I_bin_irs counterpart.
670 multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {
672 def ri : T2sTwoRegImm<
673 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
674 opc, ".w\t$Rd, $Rn, $imm",
675 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
676 Sched<[WriteALU, ReadALU]> {
677 let Inst{31-27} = 0b11110;
679 let Inst{24-21} = opcod;
683 def rr : T2sThreeReg<
684 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
685 opc, "\t$Rd, $Rn, $Rm",
686 [/* For disassembly only; pattern left blank */]>,
687 Sched<[WriteALU, ReadALU, ReadALU]> {
688 let Inst{31-27} = 0b11101;
689 let Inst{26-25} = 0b01;
690 let Inst{24-21} = opcod;
691 let Inst{14-12} = 0b000; // imm3
692 let Inst{7-6} = 0b00; // imm2
693 let Inst{5-4} = 0b00; // type
696 def rs : T2sTwoRegShiftedReg<
697 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
698 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
699 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
700 Sched<[WriteALUsi, ReadALU]> {
701 let Inst{31-27} = 0b11101;
702 let Inst{26-25} = 0b01;
703 let Inst{24-21} = opcod;
707 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
708 /// instruction modifies the CPSR register.
710 /// These opcodes will be converted to the real non-S opcodes by
711 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
712 let hasPostISelHook = 1, Defs = [CPSR] in {
713 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
714 InstrItinClass iis, SDNode opnode,
715 bit Commutable = 0> {
717 def ri : t2PseudoInst<(outs rGPR:$Rd),
718 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
720 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
722 Sched<[WriteALU, ReadALU]>;
724 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
726 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
728 Sched<[WriteALU, ReadALU, ReadALU]> {
729 let isCommutable = Commutable;
732 def rs : t2PseudoInst<(outs rGPR:$Rd),
733 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
735 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
736 t2_so_reg:$ShiftedRm))]>,
737 Sched<[WriteALUsi, ReadALUsr]>;
741 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
742 /// operands are reversed.
743 let hasPostISelHook = 1, Defs = [CPSR] in {
744 multiclass T2I_rbin_s_is<SDNode opnode> {
746 def ri : t2PseudoInst<(outs rGPR:$Rd),
747 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
749 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
751 Sched<[WriteALU, ReadALU]>;
753 def rs : t2PseudoInst<(outs rGPR:$Rd),
754 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
756 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
758 Sched<[WriteALUsi, ReadALU]>;
762 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
763 /// patterns for a binary operation that produces a value.
764 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
765 bit Commutable = 0> {
767 // The register-immediate version is re-materializable. This is useful
768 // in particular for taking the address of a local.
769 let isReMaterializable = 1 in {
770 def ri : T2sTwoRegImm<
771 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
772 opc, ".w\t$Rd, $Rn, $imm",
773 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
774 Sched<[WriteALU, ReadALU]> {
775 let Inst{31-27} = 0b11110;
778 let Inst{23-21} = op23_21;
784 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
785 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
786 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
787 Sched<[WriteALU, ReadALU]> {
791 let Inst{31-27} = 0b11110;
792 let Inst{26} = imm{11};
793 let Inst{25-24} = 0b10;
794 let Inst{23-21} = op23_21;
795 let Inst{20} = 0; // The S bit.
796 let Inst{19-16} = Rn;
798 let Inst{14-12} = imm{10-8};
800 let Inst{7-0} = imm{7-0};
803 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
804 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
805 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
806 Sched<[WriteALU, ReadALU, ReadALU]> {
807 let isCommutable = Commutable;
808 let Inst{31-27} = 0b11101;
809 let Inst{26-25} = 0b01;
811 let Inst{23-21} = op23_21;
812 let Inst{14-12} = 0b000; // imm3
813 let Inst{7-6} = 0b00; // imm2
814 let Inst{5-4} = 0b00; // type
817 def rs : T2sTwoRegShiftedReg<
818 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
819 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
820 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
821 Sched<[WriteALUsi, ReadALU]> {
822 let Inst{31-27} = 0b11101;
823 let Inst{26-25} = 0b01;
825 let Inst{23-21} = op23_21;
829 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
830 /// for a binary operation that produces a value and use the carry
831 /// bit. It's not predicable.
832 let Defs = [CPSR], Uses = [CPSR] in {
833 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
834 bit Commutable = 0> {
836 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
837 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
838 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
839 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
840 let Inst{31-27} = 0b11110;
842 let Inst{24-21} = opcod;
846 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
847 opc, ".w\t$Rd, $Rn, $Rm",
848 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
849 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
850 let isCommutable = Commutable;
851 let Inst{31-27} = 0b11101;
852 let Inst{26-25} = 0b01;
853 let Inst{24-21} = opcod;
854 let Inst{14-12} = 0b000; // imm3
855 let Inst{7-6} = 0b00; // imm2
856 let Inst{5-4} = 0b00; // type
859 def rs : T2sTwoRegShiftedReg<
860 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
861 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
862 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
863 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
864 let Inst{31-27} = 0b11101;
865 let Inst{26-25} = 0b01;
866 let Inst{24-21} = opcod;
871 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
872 // rotate operation that produces a value.
873 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
875 def ri : T2sTwoRegShiftImm<
876 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
877 opc, ".w\t$Rd, $Rm, $imm",
878 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
880 let Inst{31-27} = 0b11101;
881 let Inst{26-21} = 0b010010;
882 let Inst{19-16} = 0b1111; // Rn
883 let Inst{5-4} = opcod;
886 def rr : T2sThreeReg<
887 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
888 opc, ".w\t$Rd, $Rn, $Rm",
889 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
891 let Inst{31-27} = 0b11111;
892 let Inst{26-23} = 0b0100;
893 let Inst{22-21} = opcod;
894 let Inst{15-12} = 0b1111;
895 let Inst{7-4} = 0b0000;
898 // Optional destination register
899 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
900 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
902 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
903 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
906 // Assembler aliases w/o the ".w" suffix.
907 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
908 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
910 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
911 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
914 // and with the optional destination operand, too.
915 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
916 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
918 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
919 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
923 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
924 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
925 /// a explicit result, only implicitly set CPSR.
926 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
927 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
928 SDPatternOperator opnode> {
929 let isCompare = 1, Defs = [CPSR] in {
931 def ri : T2OneRegCmpImm<
932 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
933 opc, ".w\t$Rn, $imm",
934 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
935 let Inst{31-27} = 0b11110;
937 let Inst{24-21} = opcod;
938 let Inst{20} = 1; // The S bit.
940 let Inst{11-8} = 0b1111; // Rd
943 def rr : T2TwoRegCmp<
944 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
946 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
947 let Inst{31-27} = 0b11101;
948 let Inst{26-25} = 0b01;
949 let Inst{24-21} = opcod;
950 let Inst{20} = 1; // The S bit.
951 let Inst{14-12} = 0b000; // imm3
952 let Inst{11-8} = 0b1111; // Rd
953 let Inst{7-6} = 0b00; // imm2
954 let Inst{5-4} = 0b00; // type
957 def rs : T2OneRegCmpShiftedReg<
958 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
959 opc, ".w\t$Rn, $ShiftedRm",
960 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
961 Sched<[WriteCMPsi]> {
962 let Inst{31-27} = 0b11101;
963 let Inst{26-25} = 0b01;
964 let Inst{24-21} = opcod;
965 let Inst{20} = 1; // The S bit.
966 let Inst{11-8} = 0b1111; // Rd
970 // Assembler aliases w/o the ".w" suffix.
971 // No alias here for 'rr' version as not all instantiations of this
972 // multiclass want one (CMP in particular, does not).
973 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
974 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
975 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
976 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
979 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
980 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
981 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
983 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
984 opc, ".w\t$Rt, $addr",
985 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
989 let Inst{31-25} = 0b1111100;
990 let Inst{24} = signed;
992 let Inst{22-21} = opcod;
993 let Inst{20} = 1; // load
994 let Inst{19-16} = addr{16-13}; // Rn
995 let Inst{15-12} = Rt;
996 let Inst{11-0} = addr{11-0}; // imm
998 let DecoderMethod = "DecodeT2LoadImm12";
1000 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1001 opc, "\t$Rt, $addr",
1002 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1006 let Inst{31-27} = 0b11111;
1007 let Inst{26-25} = 0b00;
1008 let Inst{24} = signed;
1010 let Inst{22-21} = opcod;
1011 let Inst{20} = 1; // load
1012 let Inst{19-16} = addr{12-9}; // Rn
1013 let Inst{15-12} = Rt;
1015 // Offset: index==TRUE, wback==FALSE
1016 let Inst{10} = 1; // The P bit.
1017 let Inst{9} = addr{8}; // U
1018 let Inst{8} = 0; // The W bit.
1019 let Inst{7-0} = addr{7-0}; // imm
1021 let DecoderMethod = "DecodeT2LoadImm8";
1023 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1024 opc, ".w\t$Rt, $addr",
1025 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]>,
1027 let Inst{31-27} = 0b11111;
1028 let Inst{26-25} = 0b00;
1029 let Inst{24} = signed;
1031 let Inst{22-21} = opcod;
1032 let Inst{20} = 1; // load
1033 let Inst{11-6} = 0b000000;
1036 let Inst{15-12} = Rt;
1039 let Inst{19-16} = addr{9-6}; // Rn
1040 let Inst{3-0} = addr{5-2}; // Rm
1041 let Inst{5-4} = addr{1-0}; // imm
1043 let DecoderMethod = "DecodeT2LoadShift";
1046 // pci variant is very similar to i12, but supports negative offsets
1048 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1049 opc, ".w\t$Rt, $addr",
1050 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>,
1052 let isReMaterializable = 1;
1053 let Inst{31-27} = 0b11111;
1054 let Inst{26-25} = 0b00;
1055 let Inst{24} = signed;
1056 let Inst{22-21} = opcod;
1057 let Inst{20} = 1; // load
1058 let Inst{19-16} = 0b1111; // Rn
1061 let Inst{15-12} = Rt{3-0};
1064 let Inst{23} = addr{12}; // add = (U == '1')
1065 let Inst{11-0} = addr{11-0};
1067 let DecoderMethod = "DecodeT2LoadLabel";
1071 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1072 multiclass T2I_st<bits<2> opcod, string opc,
1073 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1075 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1076 opc, ".w\t$Rt, $addr",
1077 [(opnode target:$Rt, t2addrmode_imm12:$addr)]>,
1079 let Inst{31-27} = 0b11111;
1080 let Inst{26-23} = 0b0001;
1081 let Inst{22-21} = opcod;
1082 let Inst{20} = 0; // !load
1085 let Inst{15-12} = Rt;
1088 let addr{12} = 1; // add = TRUE
1089 let Inst{19-16} = addr{16-13}; // Rn
1090 let Inst{23} = addr{12}; // U
1091 let Inst{11-0} = addr{11-0}; // imm
1093 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1094 opc, "\t$Rt, $addr",
1095 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]>,
1097 let Inst{31-27} = 0b11111;
1098 let Inst{26-23} = 0b0000;
1099 let Inst{22-21} = opcod;
1100 let Inst{20} = 0; // !load
1102 // Offset: index==TRUE, wback==FALSE
1103 let Inst{10} = 1; // The P bit.
1104 let Inst{8} = 0; // The W bit.
1107 let Inst{15-12} = Rt;
1110 let Inst{19-16} = addr{12-9}; // Rn
1111 let Inst{9} = addr{8}; // U
1112 let Inst{7-0} = addr{7-0}; // imm
1114 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1115 opc, ".w\t$Rt, $addr",
1116 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]>,
1118 let Inst{31-27} = 0b11111;
1119 let Inst{26-23} = 0b0000;
1120 let Inst{22-21} = opcod;
1121 let Inst{20} = 0; // !load
1122 let Inst{11-6} = 0b000000;
1125 let Inst{15-12} = Rt;
1128 let Inst{19-16} = addr{9-6}; // Rn
1129 let Inst{3-0} = addr{5-2}; // Rm
1130 let Inst{5-4} = addr{1-0}; // imm
1134 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1135 /// register and one whose operand is a register rotated by 8/16/24.
1136 class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops,
1137 string opc, string oprs,
1139 : T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> {
1141 let Inst{31-27} = 0b11111;
1142 let Inst{26-23} = 0b0100;
1143 let Inst{22-20} = opcod;
1144 let Inst{19-16} = 0b1111; // Rn
1145 let Inst{15-12} = 0b1111;
1147 let Inst{5-4} = rot; // rotate
1150 class T2I_ext_rrot<bits<3> opcod, string opc>
1151 : T2I_ext_rrot_base<opcod,
1153 (ins rGPR:$Rm, rot_imm:$rot),
1154 opc, ".w\t$Rd, $Rm$rot", []>,
1155 Requires<[IsThumb2]>,
1156 Sched<[WriteALU, ReadALU]>;
1158 // UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier.
1159 class T2I_ext_rrot_xtb16<bits<3> opcod, string opc>
1160 : T2I_ext_rrot_base<opcod,
1162 (ins rGPR:$Rm, rot_imm:$rot),
1163 opc, "\t$Rd, $Rm$rot", []>,
1164 Requires<[HasDSP, IsThumb2]>,
1165 Sched<[WriteALU, ReadALU]>;
1167 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1168 /// register and one whose operand is a register rotated by 8/16/24.
1169 class T2I_exta_rrot<bits<3> opcod, string opc>
1170 : T2ThreeReg<(outs rGPR:$Rd),
1171 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1172 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1173 Requires<[HasDSP, IsThumb2]>,
1174 Sched<[WriteALU, ReadALU]> {
1176 let Inst{31-27} = 0b11111;
1177 let Inst{26-23} = 0b0100;
1178 let Inst{22-20} = opcod;
1179 let Inst{15-12} = 0b1111;
1181 let Inst{5-4} = rot;
1184 //===----------------------------------------------------------------------===//
1186 //===----------------------------------------------------------------------===//
1188 //===----------------------------------------------------------------------===//
1189 // Miscellaneous Instructions.
1192 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1193 string asm, list<dag> pattern>
1194 : T2XI<oops, iops, itin, asm, pattern> {
1198 let Inst{11-8} = Rd;
1199 let Inst{26} = label{11};
1200 let Inst{14-12} = label{10-8};
1201 let Inst{7-0} = label{7-0};
1204 // LEApcrel - Load a pc-relative address into a register without offending the
1206 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1207 (ins t2adrlabel:$addr, pred:$p),
1208 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1209 Sched<[WriteALU, ReadALU]> {
1210 let Inst{31-27} = 0b11110;
1211 let Inst{25-24} = 0b10;
1212 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1215 let Inst{19-16} = 0b1111; // Rn
1220 let Inst{11-8} = Rd;
1221 let Inst{23} = addr{12};
1222 let Inst{21} = addr{12};
1223 let Inst{26} = addr{11};
1224 let Inst{14-12} = addr{10-8};
1225 let Inst{7-0} = addr{7-0};
1227 let DecoderMethod = "DecodeT2Adr";
1230 let hasSideEffects = 0, isReMaterializable = 1 in
1231 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1232 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1233 let hasSideEffects = 1 in
1234 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1235 (ins i32imm:$label, pred:$p),
1237 []>, Sched<[WriteALU, ReadALU]>;
1240 //===----------------------------------------------------------------------===//
1241 // Load / store Instructions.
1245 let canFoldAsLoad = 1, isReMaterializable = 1 in
1246 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
1248 // Loads with zero extension
1249 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1250 GPRnopc, zextloadi16>;
1251 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1252 GPRnopc, zextloadi8>;
1254 // Loads with sign extension
1255 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1256 GPRnopc, sextloadi16>;
1257 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1258 GPRnopc, sextloadi8>;
1260 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1262 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1263 (ins t2addrmode_imm8s4:$addr),
1264 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>,
1266 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1268 // zextload i1 -> zextload i8
1269 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1270 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1271 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1272 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1273 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1274 (t2LDRBs t2addrmode_so_reg:$addr)>;
1275 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1276 (t2LDRBpci tconstpool:$addr)>;
1278 // extload -> zextload
1279 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1281 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1282 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1283 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1284 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1285 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1286 (t2LDRBs t2addrmode_so_reg:$addr)>;
1287 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1288 (t2LDRBpci tconstpool:$addr)>;
1290 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1291 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1292 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1293 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1294 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1295 (t2LDRBs t2addrmode_so_reg:$addr)>;
1296 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1297 (t2LDRBpci tconstpool:$addr)>;
1299 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1300 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1301 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1302 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1303 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1304 (t2LDRHs t2addrmode_so_reg:$addr)>;
1305 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1306 (t2LDRHpci tconstpool:$addr)>;
1308 // FIXME: The destination register of the loads and stores can't be PC, but
1309 // can be SP. We need another regclass (similar to rGPR) to represent
1310 // that. Not a pressing issue since these are selected manually,
1315 let mayLoad = 1, hasSideEffects = 0 in {
1316 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1317 (ins t2addrmode_imm8_pre:$addr),
1318 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1319 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1322 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1323 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1324 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1325 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1328 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1329 (ins t2addrmode_imm8_pre:$addr),
1330 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1331 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1334 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1335 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1336 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1337 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1339 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1340 (ins t2addrmode_imm8_pre:$addr),
1341 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1342 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1345 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1346 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1347 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1348 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1351 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1352 (ins t2addrmode_imm8_pre:$addr),
1353 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1354 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1355 []>, Sched<[WriteLd]>;
1357 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1358 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1359 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1360 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1363 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1364 (ins t2addrmode_imm8_pre:$addr),
1365 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1366 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1367 []>, Sched<[WriteLd]>;
1369 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1370 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1371 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1372 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1374 } // mayLoad = 1, hasSideEffects = 0
1376 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1377 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1378 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1379 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1380 "\t$Rt, $addr", []>, Sched<[WriteLd]> {
1383 let Inst{31-27} = 0b11111;
1384 let Inst{26-25} = 0b00;
1385 let Inst{24} = signed;
1387 let Inst{22-21} = type;
1388 let Inst{20} = 1; // load
1389 let Inst{19-16} = addr{12-9};
1390 let Inst{15-12} = Rt;
1392 let Inst{10-8} = 0b110; // PUW.
1393 let Inst{7-0} = addr{7-0};
1395 let DecoderMethod = "DecodeT2LoadT";
1398 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1399 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1400 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1401 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1402 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1404 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
1405 string opc, string asm, list<dag> pattern>
1406 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
1407 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
1411 let Inst{31-27} = 0b11101;
1412 let Inst{26-24} = 0b000;
1413 let Inst{23-20} = bits23_20;
1414 let Inst{11-6} = 0b111110;
1415 let Inst{5-4} = bit54;
1416 let Inst{3-0} = 0b1111;
1418 // Encode instruction operands
1419 let Inst{19-16} = addr;
1420 let Inst{15-12} = Rt;
1423 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1424 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>,
1426 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1427 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>,
1429 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1430 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>,
1434 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;
1435 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1436 rGPR, truncstorei8>;
1437 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1438 rGPR, truncstorei16>;
1441 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1442 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1443 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1444 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>,
1449 let mayStore = 1, hasSideEffects = 0 in {
1450 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1451 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1452 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1453 "str", "\t$Rt, $addr!",
1454 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1457 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1458 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1459 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1460 "strh", "\t$Rt, $addr!",
1461 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1464 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1465 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1466 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1467 "strb", "\t$Rt, $addr!",
1468 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1470 } // mayStore = 1, hasSideEffects = 0
1472 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1473 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1474 t2am_imm8_offset:$offset),
1475 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1476 "str", "\t$Rt, $Rn$offset",
1477 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1478 [(set GPRnopc:$Rn_wb,
1479 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1480 t2am_imm8_offset:$offset))]>,
1483 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1484 (ins rGPR:$Rt, addr_offset_none:$Rn,
1485 t2am_imm8_offset:$offset),
1486 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1487 "strh", "\t$Rt, $Rn$offset",
1488 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1489 [(set GPRnopc:$Rn_wb,
1490 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1491 t2am_imm8_offset:$offset))]>,
1494 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1495 (ins rGPR:$Rt, addr_offset_none:$Rn,
1496 t2am_imm8_offset:$offset),
1497 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1498 "strb", "\t$Rt, $Rn$offset",
1499 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1500 [(set GPRnopc:$Rn_wb,
1501 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1502 t2am_imm8_offset:$offset))]>,
1505 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1506 // put the patterns on the instruction definitions directly as ISel wants
1507 // the address base and offset to be separate operands, not a single
1508 // complex operand like we represent the instructions themselves. The
1509 // pseudos map between the two.
1510 let usesCustomInserter = 1,
1511 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1512 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1513 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1515 [(set GPRnopc:$Rn_wb,
1516 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1518 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1519 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1521 [(set GPRnopc:$Rn_wb,
1522 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1524 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1525 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1527 [(set GPRnopc:$Rn_wb,
1528 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1532 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1534 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1535 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1536 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1537 "\t$Rt, $addr", []>, Sched<[WriteST]> {
1538 let Inst{31-27} = 0b11111;
1539 let Inst{26-25} = 0b00;
1540 let Inst{24} = 0; // not signed
1542 let Inst{22-21} = type;
1543 let Inst{20} = 0; // store
1545 let Inst{10-8} = 0b110; // PUW
1549 let Inst{15-12} = Rt;
1550 let Inst{19-16} = addr{12-9};
1551 let Inst{7-0} = addr{7-0};
1554 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1555 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1556 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1558 // ldrd / strd pre / post variants
1561 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1562 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1563 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1565 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1569 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1570 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1571 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1572 "$addr.base = $wb", []>, Sched<[WriteLd]>;
1575 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1576 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1577 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1578 "$addr.base = $wb", []>, Sched<[WriteST]> {
1579 let DecoderMethod = "DecodeT2STRDPreInstruction";
1583 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1584 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1585 t2am_imm8s4_offset:$imm),
1586 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1587 "$addr.base = $wb", []>, Sched<[WriteST]>;
1589 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
1590 string opc, string asm, list<dag> pattern>
1591 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
1592 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]>,
1597 let Inst{31-27} = 0b11101;
1598 let Inst{26-20} = 0b0001100;
1599 let Inst{11-6} = 0b111110;
1600 let Inst{5-4} = bit54;
1601 let Inst{3-0} = 0b1111;
1603 // Encode instruction operands
1604 let Inst{19-16} = addr;
1605 let Inst{15-12} = Rt;
1608 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1609 "stl", "\t$Rt, $addr", []>;
1610 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1611 "stlb", "\t$Rt, $addr", []>;
1612 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1613 "stlh", "\t$Rt, $addr", []>;
1615 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1616 // data/instruction access.
1617 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1618 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1619 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1621 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1623 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1624 Sched<[WritePreLd]> {
1625 let Inst{31-25} = 0b1111100;
1626 let Inst{24} = instr;
1629 let Inst{21} = write;
1631 let Inst{15-12} = 0b1111;
1634 let Inst{19-16} = addr{16-13}; // Rn
1635 let Inst{11-0} = addr{11-0}; // imm12
1637 let DecoderMethod = "DecodeT2LoadImm12";
1640 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1642 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1643 Sched<[WritePreLd]> {
1644 let Inst{31-25} = 0b1111100;
1645 let Inst{24} = instr;
1646 let Inst{23} = 0; // U = 0
1648 let Inst{21} = write;
1650 let Inst{15-12} = 0b1111;
1651 let Inst{11-8} = 0b1100;
1654 let Inst{19-16} = addr{12-9}; // Rn
1655 let Inst{7-0} = addr{7-0}; // imm8
1657 let DecoderMethod = "DecodeT2LoadImm8";
1660 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1662 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1663 Sched<[WritePreLd]> {
1664 let Inst{31-25} = 0b1111100;
1665 let Inst{24} = instr;
1666 let Inst{23} = 0; // add = TRUE for T1
1668 let Inst{21} = write;
1670 let Inst{15-12} = 0b1111;
1671 let Inst{11-6} = 0b000000;
1674 let Inst{19-16} = addr{9-6}; // Rn
1675 let Inst{3-0} = addr{5-2}; // Rm
1676 let Inst{5-4} = addr{1-0}; // imm2
1678 let DecoderMethod = "DecodeT2LoadShift";
1682 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1683 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1684 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1686 // pci variant is very similar to i12, but supports negative offsets
1687 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1688 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1689 IIC_Preload, opc, "\t$addr",
1690 [(ARMPreload (ARMWrapper tconstpool:$addr),
1691 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1692 let Inst{31-25} = 0b1111100;
1693 let Inst{24} = inst;
1694 let Inst{22-20} = 0b001;
1695 let Inst{19-16} = 0b1111;
1696 let Inst{15-12} = 0b1111;
1699 let Inst{23} = addr{12}; // add = (U == '1')
1700 let Inst{11-0} = addr{11-0}; // imm12
1702 let DecoderMethod = "DecodeT2LoadLabel";
1705 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1706 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1708 //===----------------------------------------------------------------------===//
1709 // Load / store multiple Instructions.
1712 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1713 InstrItinClass itin_upd, bit L_bit> {
1715 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1716 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1720 let Inst{31-27} = 0b11101;
1721 let Inst{26-25} = 0b00;
1722 let Inst{24-23} = 0b01; // Increment After
1724 let Inst{21} = 0; // No writeback
1725 let Inst{20} = L_bit;
1726 let Inst{19-16} = Rn;
1727 let Inst{15-0} = regs;
1730 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1731 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1735 let Inst{31-27} = 0b11101;
1736 let Inst{26-25} = 0b00;
1737 let Inst{24-23} = 0b01; // Increment After
1739 let Inst{21} = 1; // Writeback
1740 let Inst{20} = L_bit;
1741 let Inst{19-16} = Rn;
1742 let Inst{15-0} = regs;
1745 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1746 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1750 let Inst{31-27} = 0b11101;
1751 let Inst{26-25} = 0b00;
1752 let Inst{24-23} = 0b10; // Decrement Before
1754 let Inst{21} = 0; // No writeback
1755 let Inst{20} = L_bit;
1756 let Inst{19-16} = Rn;
1757 let Inst{15-0} = regs;
1760 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1761 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1765 let Inst{31-27} = 0b11101;
1766 let Inst{26-25} = 0b00;
1767 let Inst{24-23} = 0b10; // Decrement Before
1769 let Inst{21} = 1; // Writeback
1770 let Inst{20} = L_bit;
1771 let Inst{19-16} = Rn;
1772 let Inst{15-0} = regs;
1776 let hasSideEffects = 0 in {
1778 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1779 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1781 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1782 InstrItinClass itin_upd, bit L_bit> {
1784 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1785 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1789 let Inst{31-27} = 0b11101;
1790 let Inst{26-25} = 0b00;
1791 let Inst{24-23} = 0b01; // Increment After
1793 let Inst{21} = 0; // No writeback
1794 let Inst{20} = L_bit;
1795 let Inst{19-16} = Rn;
1797 let Inst{14} = regs{14};
1799 let Inst{12-0} = regs{12-0};
1802 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1803 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1807 let Inst{31-27} = 0b11101;
1808 let Inst{26-25} = 0b00;
1809 let Inst{24-23} = 0b01; // Increment After
1811 let Inst{21} = 1; // Writeback
1812 let Inst{20} = L_bit;
1813 let Inst{19-16} = Rn;
1815 let Inst{14} = regs{14};
1817 let Inst{12-0} = regs{12-0};
1820 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1821 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1825 let Inst{31-27} = 0b11101;
1826 let Inst{26-25} = 0b00;
1827 let Inst{24-23} = 0b10; // Decrement Before
1829 let Inst{21} = 0; // No writeback
1830 let Inst{20} = L_bit;
1831 let Inst{19-16} = Rn;
1833 let Inst{14} = regs{14};
1835 let Inst{12-0} = regs{12-0};
1838 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1839 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1843 let Inst{31-27} = 0b11101;
1844 let Inst{26-25} = 0b00;
1845 let Inst{24-23} = 0b10; // Decrement Before
1847 let Inst{21} = 1; // Writeback
1848 let Inst{20} = L_bit;
1849 let Inst{19-16} = Rn;
1851 let Inst{14} = regs{14};
1853 let Inst{12-0} = regs{12-0};
1858 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1859 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1864 //===----------------------------------------------------------------------===//
1865 // Move Instructions.
1868 let hasSideEffects = 0 in
1869 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,
1870 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1871 let Inst{31-27} = 0b11101;
1872 let Inst{26-25} = 0b01;
1873 let Inst{24-21} = 0b0010;
1874 let Inst{19-16} = 0b1111; // Rn
1875 let Inst{14-12} = 0b000;
1876 let Inst{7-4} = 0b0000;
1878 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
1879 pred:$p, zero_reg)>;
1880 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
1882 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
1885 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1886 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1887 AddedComplexity = 1 in
1888 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1889 "mov", ".w\t$Rd, $imm",
1890 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1891 let Inst{31-27} = 0b11110;
1893 let Inst{24-21} = 0b0010;
1894 let Inst{19-16} = 0b1111; // Rn
1898 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1899 // Use aliases to get that to play nice here.
1900 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1902 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1905 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1906 pred:$p, zero_reg)>;
1907 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1908 pred:$p, zero_reg)>;
1910 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1911 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1912 "movw", "\t$Rd, $imm",
1913 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
1914 Requires<[IsThumb, HasV8MBaseline]> {
1915 let Inst{31-27} = 0b11110;
1917 let Inst{24-21} = 0b0010;
1918 let Inst{20} = 0; // The S bit.
1924 let Inst{11-8} = Rd;
1925 let Inst{19-16} = imm{15-12};
1926 let Inst{26} = imm{11};
1927 let Inst{14-12} = imm{10-8};
1928 let Inst{7-0} = imm{7-0};
1929 let DecoderMethod = "DecodeT2MOVTWInstruction";
1932 def : InstAlias<"mov${p} $Rd, $imm",
1933 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
1934 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;
1936 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1937 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1940 let Constraints = "$src = $Rd" in {
1941 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1942 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1943 "movt", "\t$Rd, $imm",
1945 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1947 Requires<[IsThumb, HasV8MBaseline]> {
1948 let Inst{31-27} = 0b11110;
1950 let Inst{24-21} = 0b0110;
1951 let Inst{20} = 0; // The S bit.
1957 let Inst{11-8} = Rd;
1958 let Inst{19-16} = imm{15-12};
1959 let Inst{26} = imm{11};
1960 let Inst{14-12} = imm{10-8};
1961 let Inst{7-0} = imm{7-0};
1962 let DecoderMethod = "DecodeT2MOVTWInstruction";
1965 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1966 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1967 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
1970 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1972 //===----------------------------------------------------------------------===//
1973 // Extend Instructions.
1978 def t2SXTB : T2I_ext_rrot<0b100, "sxtb">;
1979 def t2SXTH : T2I_ext_rrot<0b000, "sxth">;
1980 def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;
1982 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">;
1983 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;
1984 def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">;
1986 def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8),
1987 (t2SXTB rGPR:$Rn, rot_imm:$rot)>;
1988 def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16),
1989 (t2SXTH rGPR:$Rn, rot_imm:$rot)>;
1990 def : Thumb2DSPPat<(add rGPR:$Rn,
1991 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)),
1992 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
1993 def : Thumb2DSPPat<(add rGPR:$Rn,
1994 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)),
1995 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
1998 // A simple right-shift can also be used in most cases (the exception is the
1999 // SXTH operations with a rotate of 24: there the non-contiguous bits are
2001 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2002 (srl rGPR:$Rm, rot_imm:$rot), i8)),
2003 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2004 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2005 (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
2006 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2007 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2008 (rotr rGPR:$Rm, (i32 24)), i16)),
2009 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
2010 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2011 (or (srl rGPR:$Rm, (i32 24)),
2012 (shl rGPR:$Rm, (i32 8))), i16)),
2013 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
2017 let AddedComplexity = 16 in {
2018 def t2UXTB : T2I_ext_rrot<0b101, "uxtb">;
2019 def t2UXTH : T2I_ext_rrot<0b001, "uxth">;
2020 def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">;
2022 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF),
2023 (t2UXTB rGPR:$Rm, rot_imm:$rot)>;
2024 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF),
2025 (t2UXTH rGPR:$Rm, rot_imm:$rot)>;
2026 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF),
2027 (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>;
2029 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2030 // The transformation should probably be done as a combiner action
2031 // instead so we can include a check for masking back in the upper
2032 // eight bits of the source into the lower eight bits of the result.
2033 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2034 // (t2UXTB16 rGPR:$Src, 3)>,
2035 // Requires<[HasDSP, IsThumb2]>;
2036 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2037 (t2UXTB16 rGPR:$Src, 1)>,
2038 Requires<[HasDSP, IsThumb2]>;
2040 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">;
2041 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">;
2042 def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">;
2044 def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
2046 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2047 def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
2049 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2050 def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),
2052 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2053 def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
2055 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2059 //===----------------------------------------------------------------------===//
2060 // Arithmetic Instructions.
2064 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
2065 defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
2067 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2069 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
2070 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
2071 // AdjustInstrPostInstrSelection where we determine whether or not to
2072 // set the "s" bit based on CPSR liveness.
2074 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2075 // support for an optional CPSR definition that corresponds to the DAG
2076 // node's second value. We can then eliminate the implicit def of CPSR.
2077 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;
2078 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;
2080 let hasPostISelHook = 1 in {
2081 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>;
2082 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>;
2085 def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm",
2086 (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
2087 def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm",
2088 (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
2090 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
2091 (t2SUBri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2092 def : t2InstSubst<"addw${p} $rd, $rn, $imm",
2093 (t2SUBri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2094 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
2095 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2096 def : t2InstSubst<"subw${p} $rd, $rn, $imm",
2097 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2099 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;
2101 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2102 // CPSR and the implicit def of CPSR is not needed.
2103 defm t2RSBS : T2I_rbin_s_is <ARMsubc>;
2105 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2106 // The assume-no-carry-in form uses the negation of the input since add/sub
2107 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2108 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2110 // The AddedComplexity preferences the first variant over the others since
2111 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2112 let AddedComplexity = 1 in
2113 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2114 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2115 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2116 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2117 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2118 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2119 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2120 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2122 let AddedComplexity = 1 in
2123 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2124 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2125 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2126 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2127 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2128 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2129 // The with-carry-in form matches bitwise not instead of the negation.
2130 // Effectively, the inverse interpretation of the carry flag already accounts
2131 // for part of the negation.
2132 let AddedComplexity = 1 in
2133 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2134 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2135 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2136 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2137 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2138 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2140 // Select Bytes -- for disassembly only
2142 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2143 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2144 Requires<[IsThumb2, HasDSP]> {
2145 let Inst{31-27} = 0b11111;
2146 let Inst{26-24} = 0b010;
2148 let Inst{22-20} = 0b010;
2149 let Inst{15-12} = 0b1111;
2151 let Inst{6-4} = 0b000;
2154 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2155 // And Miscellaneous operations -- for disassembly only
2156 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2157 list<dag> pat = [/* For disassembly only; pattern left blank */],
2158 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2159 string asm = "\t$Rd, $Rn, $Rm">
2160 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2161 Requires<[IsThumb2, HasDSP]> {
2162 let Inst{31-27} = 0b11111;
2163 let Inst{26-23} = 0b0101;
2164 let Inst{22-20} = op22_20;
2165 let Inst{15-12} = 0b1111;
2166 let Inst{7-4} = op7_4;
2172 let Inst{11-8} = Rd;
2173 let Inst{19-16} = Rn;
2177 // Saturating add/subtract -- for disassembly only
2179 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2180 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2181 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2182 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2183 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2184 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2185 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2186 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2187 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2188 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2189 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2190 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2191 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2192 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2193 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2194 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2195 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2196 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2197 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2198 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2199 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2200 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2202 // Signed/Unsigned add/subtract -- for disassembly only
2204 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2205 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2206 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2207 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2208 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2209 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2210 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2211 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2212 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2213 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2214 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2215 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2217 // Signed/Unsigned halving add/subtract -- for disassembly only
2219 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2220 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2221 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2222 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2223 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2224 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2225 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2226 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2227 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2228 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2229 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2230 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2232 // Helper class for disassembly only
2233 // A6.3.16 & A6.3.17
2234 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2235 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2236 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2237 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2238 let Inst{31-27} = 0b11111;
2239 let Inst{26-24} = 0b011;
2240 let Inst{23} = long;
2241 let Inst{22-20} = op22_20;
2242 let Inst{7-4} = op7_4;
2245 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2246 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2247 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2248 let Inst{31-27} = 0b11111;
2249 let Inst{26-24} = 0b011;
2250 let Inst{23} = long;
2251 let Inst{22-20} = op22_20;
2252 let Inst{7-4} = op7_4;
2255 // Unsigned Sum of Absolute Differences [and Accumulate].
2256 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2257 (ins rGPR:$Rn, rGPR:$Rm),
2258 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2259 Requires<[IsThumb2, HasDSP]> {
2260 let Inst{15-12} = 0b1111;
2262 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2263 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2264 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2265 Requires<[IsThumb2, HasDSP]>;
2267 // Signed/Unsigned saturate.
2268 class T2SatI<dag iops, string opc, string asm>
2269 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {
2275 let Inst{31-24} = 0b11110011;
2276 let Inst{21} = sh{5};
2278 let Inst{19-16} = Rn;
2280 let Inst{14-12} = sh{4-2};
2281 let Inst{11-8} = Rd;
2282 let Inst{7-6} = sh{1-0};
2284 let Inst{4-0} = sat_imm;
2287 def t2SSAT: T2SatI<(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2288 "ssat", "\t$Rd, $sat_imm, $Rn$sh">,
2289 Requires<[IsThumb2]> {
2290 let Inst{23-22} = 0b00;
2294 def t2SSAT16: T2SatI<(ins imm1_16:$sat_imm, rGPR:$Rn),
2295 "ssat16", "\t$Rd, $sat_imm, $Rn">,
2296 Requires<[IsThumb2, HasDSP]> {
2297 let Inst{23-22} = 0b00;
2302 def t2USAT: T2SatI<(ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2303 "usat", "\t$Rd, $sat_imm, $Rn$sh">,
2304 Requires<[IsThumb2]> {
2305 let Inst{23-22} = 0b10;
2308 def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn),
2309 "usat16", "\t$Rd, $sat_imm, $Rn">,
2310 Requires<[IsThumb2, HasDSP]> {
2311 let Inst{23-22} = 0b10;
2316 def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos), (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
2317 def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos), (t2USAT imm0_31:$pos, GPR:$a, 0)>;
2318 def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
2319 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2321 //===----------------------------------------------------------------------===//
2322 // Shift and rotate Instructions.
2325 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
2326 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2327 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;
2328 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, rotr>;
2330 // LSL #0 is actually MOV, and has slightly different permitted registers to
2331 // LSL with non-zero shift
2332 def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0",
2333 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2334 def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",
2335 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2337 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2338 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2339 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2341 let Uses = [CPSR] in {
2342 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2343 "rrx", "\t$Rd, $Rm",
2344 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2345 let Inst{31-27} = 0b11101;
2346 let Inst{26-25} = 0b01;
2347 let Inst{24-21} = 0b0010;
2348 let Inst{19-16} = 0b1111; // Rn
2349 let Inst{14-12} = 0b000;
2350 let Inst{7-4} = 0b0011;
2354 let isCodeGenOnly = 1, Defs = [CPSR] in {
2355 def t2MOVsrl_flag : T2TwoRegShiftImm<
2356 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2357 "lsrs", ".w\t$Rd, $Rm, #1",
2358 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2360 let Inst{31-27} = 0b11101;
2361 let Inst{26-25} = 0b01;
2362 let Inst{24-21} = 0b0010;
2363 let Inst{20} = 1; // The S bit.
2364 let Inst{19-16} = 0b1111; // Rn
2365 let Inst{5-4} = 0b01; // Shift type.
2366 // Shift amount = Inst{14-12:7-6} = 1.
2367 let Inst{14-12} = 0b000;
2368 let Inst{7-6} = 0b01;
2370 def t2MOVsra_flag : T2TwoRegShiftImm<
2371 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2372 "asrs", ".w\t$Rd, $Rm, #1",
2373 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2375 let Inst{31-27} = 0b11101;
2376 let Inst{26-25} = 0b01;
2377 let Inst{24-21} = 0b0010;
2378 let Inst{20} = 1; // The S bit.
2379 let Inst{19-16} = 0b1111; // Rn
2380 let Inst{5-4} = 0b10; // Shift type.
2381 // Shift amount = Inst{14-12:7-6} = 1.
2382 let Inst{14-12} = 0b000;
2383 let Inst{7-6} = 0b01;
2387 //===----------------------------------------------------------------------===//
2388 // Bitwise Instructions.
2391 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2392 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>;
2393 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2394 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>;
2395 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2396 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>;
2398 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2399 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2400 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2402 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2403 string opc, string asm, list<dag> pattern>
2404 : T2I<oops, iops, itin, opc, asm, pattern> {
2409 let Inst{11-8} = Rd;
2410 let Inst{4-0} = msb{4-0};
2411 let Inst{14-12} = lsb{4-2};
2412 let Inst{7-6} = lsb{1-0};
2415 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2416 string opc, string asm, list<dag> pattern>
2417 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2420 let Inst{19-16} = Rn;
2423 let Constraints = "$src = $Rd" in
2424 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2425 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2426 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2427 let Inst{31-27} = 0b11110;
2428 let Inst{26} = 0; // should be 0.
2430 let Inst{24-20} = 0b10110;
2431 let Inst{19-16} = 0b1111; // Rn
2433 let Inst{5} = 0; // should be 0.
2436 let msb{4-0} = imm{9-5};
2437 let lsb{4-0} = imm{4-0};
2440 def t2SBFX: T2TwoRegBitFI<
2441 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2442 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2443 let Inst{31-27} = 0b11110;
2445 let Inst{24-20} = 0b10100;
2449 def t2UBFX: T2TwoRegBitFI<
2450 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2451 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2452 let Inst{31-27} = 0b11110;
2454 let Inst{24-20} = 0b11100;
2458 // A8.8.247 UDF - Undefined (Encoding T2)
2459 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2460 [(int_arm_undefined imm0_65535:$imm16)]> {
2462 let Inst{31-29} = 0b111;
2463 let Inst{28-27} = 0b10;
2464 let Inst{26-20} = 0b1111111;
2465 let Inst{19-16} = imm16{15-12};
2467 let Inst{14-12} = 0b010;
2468 let Inst{11-0} = imm16{11-0};
2471 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2472 let Constraints = "$src = $Rd" in {
2473 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2474 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2475 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2476 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2477 bf_inv_mask_imm:$imm))]> {
2478 let Inst{31-27} = 0b11110;
2479 let Inst{26} = 0; // should be 0.
2481 let Inst{24-20} = 0b10110;
2483 let Inst{5} = 0; // should be 0.
2486 let msb{4-0} = imm{9-5};
2487 let lsb{4-0} = imm{4-0};
2491 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2492 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2493 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2495 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2496 /// unary operation that produces a value. These are predicable and can be
2497 /// changed to modify CPSR.
2498 multiclass T2I_un_irs<bits<4> opcod, string opc,
2499 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2501 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2503 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2505 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2506 let isAsCheapAsAMove = Cheap;
2507 let isReMaterializable = ReMat;
2508 let isMoveImm = MoveImm;
2509 let Inst{31-27} = 0b11110;
2511 let Inst{24-21} = opcod;
2512 let Inst{19-16} = 0b1111; // Rn
2516 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2517 opc, ".w\t$Rd, $Rm",
2518 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2519 let Inst{31-27} = 0b11101;
2520 let Inst{26-25} = 0b01;
2521 let Inst{24-21} = opcod;
2522 let Inst{19-16} = 0b1111; // Rn
2523 let Inst{14-12} = 0b000; // imm3
2524 let Inst{7-6} = 0b00; // imm2
2525 let Inst{5-4} = 0b00; // type
2528 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2529 opc, ".w\t$Rd, $ShiftedRm",
2530 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2532 let Inst{31-27} = 0b11101;
2533 let Inst{26-25} = 0b01;
2534 let Inst{24-21} = opcod;
2535 let Inst{19-16} = 0b1111; // Rn
2539 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2540 let AddedComplexity = 1 in
2541 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2542 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2545 let AddedComplexity = 1 in
2546 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2547 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2549 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2550 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2551 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2554 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2555 // will match the extended, not the original bitWidth for $src.
2556 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2557 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2560 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2561 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2562 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2563 Requires<[IsThumb2]>;
2565 def : T2Pat<(t2_so_imm_not:$src),
2566 (t2MVNi t2_so_imm_not:$src)>;
2568 //===----------------------------------------------------------------------===//
2569 // Multiply Instructions.
2571 let isCommutable = 1 in
2572 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2573 "mul", "\t$Rd, $Rn, $Rm",
2574 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>,
2575 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
2576 let Inst{31-27} = 0b11111;
2577 let Inst{26-23} = 0b0110;
2578 let Inst{22-20} = 0b000;
2579 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2580 let Inst{7-4} = 0b0000; // Multiply
2583 class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
2584 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2585 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2586 Requires<[IsThumb2, UseMulOps]>,
2587 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2588 let Inst{31-27} = 0b11111;
2589 let Inst{26-23} = 0b0110;
2590 let Inst{22-20} = 0b000;
2591 let Inst{7-4} = op7_4;
2594 def t2MLA : T2FourRegMLA<0b0000, "mla",
2595 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
2597 def t2MLS: T2FourRegMLA<0b0001, "mls",
2598 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
2601 // Extra precision multiplies with low / high results
2602 let hasSideEffects = 0 in {
2603 let isCommutable = 1 in {
2604 def t2SMULL : T2MulLong<0b000, 0b0000, "smull",
2605 [(set rGPR:$RdLo, rGPR:$RdHi,
2606 (smullohi rGPR:$Rn, rGPR:$Rm))]>;
2607 def t2UMULL : T2MulLong<0b010, 0b0000, "umull",
2608 [(set rGPR:$RdLo, rGPR:$RdHi,
2609 (umullohi rGPR:$Rn, rGPR:$Rm))]>;
2612 // Multiply + accumulate
2613 def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
2614 def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
2615 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
2618 // Rounding variants of the below included for disassembly only
2620 // Most significant word multiply
2621 class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
2622 : T2ThreeReg<(outs rGPR:$Rd),
2623 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2624 opc, "\t$Rd, $Rn, $Rm", pattern>,
2625 Requires<[IsThumb2, HasDSP]>,
2626 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
2627 let Inst{31-27} = 0b11111;
2628 let Inst{26-23} = 0b0110;
2629 let Inst{22-20} = 0b101;
2630 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2631 let Inst{7-4} = op7_4;
2633 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
2635 def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
2637 class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
2639 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2640 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2641 Requires<[IsThumb2, HasDSP, UseMulOps]>,
2642 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2643 let Inst{31-27} = 0b11111;
2644 let Inst{26-23} = 0b0110;
2645 let Inst{22-20} = op22_20;
2646 let Inst{7-4} = op7_4;
2649 def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
2650 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
2651 def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
2652 def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
2653 def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
2655 class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
2657 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
2658 "\t$Rd, $Rn, $Rm", pattern>,
2659 Requires<[IsThumb2, HasDSP]>,
2660 Sched<[WriteMUL16, ReadMUL, ReadMUL]> {
2661 let Inst{31-27} = 0b11111;
2662 let Inst{26-23} = 0b0110;
2663 let Inst{22-20} = op22_20;
2664 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2665 let Inst{7-6} = 0b00;
2666 let Inst{5-4} = op5_4;
2669 def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
2670 [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
2671 (sext_inreg rGPR:$Rm, i16)))]>;
2672 def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
2673 [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
2674 (sra rGPR:$Rm, (i32 16))))]>;
2675 def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
2676 [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
2677 (sext_inreg rGPR:$Rm, i16)))]>;
2678 def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
2679 [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
2680 (sra rGPR:$Rm, (i32 16))))]>;
2681 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
2682 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;
2683 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",
2684 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;
2686 def : Thumb2DSPPat<(mul sext_16_node:$Rm, sext_16_node:$Rn),
2687 (t2SMULBB rGPR:$Rm, rGPR:$Rn)>;
2688 def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16))),
2689 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;
2690 def : Thumb2DSPPat<(mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm),
2691 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;
2693 class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc,
2695 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
2696 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2697 Requires<[IsThumb2, HasDSP, UseMulOps]>,
2698 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]> {
2699 let Inst{31-27} = 0b11111;
2700 let Inst{26-23} = 0b0110;
2701 let Inst{22-20} = op22_20;
2702 let Inst{7-6} = 0b00;
2703 let Inst{5-4} = op5_4;
2706 def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",
2707 [(set rGPR:$Rd, (add rGPR:$Ra,
2708 (mul (sext_inreg rGPR:$Rn, i16),
2709 (sext_inreg rGPR:$Rm, i16))))]>;
2710 def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",
2711 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
2712 (sra rGPR:$Rm, (i32 16)))))]>;
2713 def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
2714 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
2715 (sext_inreg rGPR:$Rm, i16))))]>;
2716 def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
2717 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
2718 (sra rGPR:$Rm, (i32 16)))))]>;
2719 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
2720 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
2721 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
2722 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
2724 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),
2725 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2726 def : Thumb2DSPMulPat<(add rGPR:$Ra,
2727 (mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16)))),
2728 (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2729 def : Thumb2DSPMulPat<(add rGPR:$Ra,
2730 (mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm)),
2731 (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2733 // Halfword multiple accumulate long: SMLAL<x><y>
2734 def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">,
2735 Requires<[IsThumb2, HasDSP]>;
2736 def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">,
2737 Requires<[IsThumb2, HasDSP]>;
2738 def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">,
2739 Requires<[IsThumb2, HasDSP]>;
2740 def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">,
2741 Requires<[IsThumb2, HasDSP]>;
2743 def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2744 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>;
2745 def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2746 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>;
2747 def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2748 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>;
2749 def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2750 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>;
2752 class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc>
2753 : T2ThreeReg_mac<0, op22_20, op7_4,
2755 (ins rGPR:$Rn, rGPR:$Rm),
2756 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
2757 Requires<[IsThumb2, HasDSP]>,
2758 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2759 let Inst{15-12} = 0b1111;
2762 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2763 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">;
2764 def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">;
2765 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">;
2766 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">;
2768 class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc>
2769 : T2FourReg_mac<0, op22_20, op7_4,
2771 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
2772 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>,
2773 Requires<[IsThumb2, HasDSP]>;
2775 def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad">;
2776 def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx">;
2777 def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">;
2778 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">;
2780 class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
2781 : T2FourReg_mac<1, op22_20, op7_4,
2782 (outs rGPR:$Ra, rGPR:$Rd),
2783 (ins rGPR:$Rn, rGPR:$Rm),
2784 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
2785 Requires<[IsThumb2, HasDSP]>,
2786 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
2788 def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
2789 def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
2790 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
2791 def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
2793 //===----------------------------------------------------------------------===//
2794 // Division Instructions.
2795 // Signed and unsigned division on v7-M
2797 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2798 "sdiv", "\t$Rd, $Rn, $Rm",
2799 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2800 Requires<[HasDivide, IsThumb, HasV8MBaseline]>,
2802 let Inst{31-27} = 0b11111;
2803 let Inst{26-21} = 0b011100;
2805 let Inst{15-12} = 0b1111;
2806 let Inst{7-4} = 0b1111;
2809 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2810 "udiv", "\t$Rd, $Rn, $Rm",
2811 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2812 Requires<[HasDivide, IsThumb, HasV8MBaseline]>,
2814 let Inst{31-27} = 0b11111;
2815 let Inst{26-21} = 0b011101;
2817 let Inst{15-12} = 0b1111;
2818 let Inst{7-4} = 0b1111;
2821 //===----------------------------------------------------------------------===//
2822 // Misc. Arithmetic Instructions.
2825 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2826 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2827 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2828 let Inst{31-27} = 0b11111;
2829 let Inst{26-22} = 0b01010;
2830 let Inst{21-20} = op1;
2831 let Inst{15-12} = 0b1111;
2832 let Inst{7-6} = 0b10;
2833 let Inst{5-4} = op2;
2837 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2838 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2841 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2842 "rbit", "\t$Rd, $Rm",
2843 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
2846 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2847 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2850 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2851 "rev16", ".w\t$Rd, $Rm",
2852 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2855 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2856 "revsh", ".w\t$Rd, $Rm",
2857 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2860 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2861 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2862 (t2REVSH rGPR:$Rm)>;
2864 def t2PKHBT : T2ThreeReg<
2865 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2866 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2867 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2868 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2870 Requires<[HasDSP, IsThumb2]>,
2871 Sched<[WriteALUsi, ReadALU]> {
2872 let Inst{31-27} = 0b11101;
2873 let Inst{26-25} = 0b01;
2874 let Inst{24-20} = 0b01100;
2875 let Inst{5} = 0; // BT form
2879 let Inst{14-12} = sh{4-2};
2880 let Inst{7-6} = sh{1-0};
2883 // Alternate cases for PKHBT where identities eliminate some nodes.
2884 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2885 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2886 Requires<[HasDSP, IsThumb2]>;
2887 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2888 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2889 Requires<[HasDSP, IsThumb2]>;
2891 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2892 // will match the pattern below.
2893 def t2PKHTB : T2ThreeReg<
2894 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2895 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2896 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2897 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2899 Requires<[HasDSP, IsThumb2]>,
2900 Sched<[WriteALUsi, ReadALU]> {
2901 let Inst{31-27} = 0b11101;
2902 let Inst{26-25} = 0b01;
2903 let Inst{24-20} = 0b01100;
2904 let Inst{5} = 1; // TB form
2908 let Inst{14-12} = sh{4-2};
2909 let Inst{7-6} = sh{1-0};
2912 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2913 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2914 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
2915 // pkhtb src1, src2, asr (17..31).
2916 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
2917 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
2918 Requires<[HasDSP, IsThumb2]>;
2919 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
2920 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2921 Requires<[HasDSP, IsThumb2]>;
2922 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2923 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2924 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2925 Requires<[HasDSP, IsThumb2]>;
2927 //===----------------------------------------------------------------------===//
2928 // CRC32 Instructions
2931 // + CRC32{B,H,W} 0x04C11DB7
2932 // + CRC32C{B,H,W} 0x1EDC6F41
2935 class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
2936 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
2937 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
2938 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
2939 Requires<[IsThumb2, HasV8, HasCRC]> {
2940 let Inst{31-27} = 0b11111;
2941 let Inst{26-21} = 0b010110;
2943 let Inst{15-12} = 0b1111;
2944 let Inst{7-6} = 0b10;
2948 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
2949 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
2950 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
2951 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
2952 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
2953 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
2955 //===----------------------------------------------------------------------===//
2956 // Comparison Instructions...
2958 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2959 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>;
2961 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2962 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2963 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2964 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2965 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2966 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2968 let isCompare = 1, Defs = [CPSR] in {
2970 def t2CMNri : T2OneRegCmpImm<
2971 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
2972 "cmn", ".w\t$Rn, $imm",
2973 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
2974 Sched<[WriteCMP, ReadALU]> {
2975 let Inst{31-27} = 0b11110;
2977 let Inst{24-21} = 0b1000;
2978 let Inst{20} = 1; // The S bit.
2980 let Inst{11-8} = 0b1111; // Rd
2983 def t2CMNzrr : T2TwoRegCmp<
2984 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
2985 "cmn", ".w\t$Rn, $Rm",
2986 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2987 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
2988 let Inst{31-27} = 0b11101;
2989 let Inst{26-25} = 0b01;
2990 let Inst{24-21} = 0b1000;
2991 let Inst{20} = 1; // The S bit.
2992 let Inst{14-12} = 0b000; // imm3
2993 let Inst{11-8} = 0b1111; // Rd
2994 let Inst{7-6} = 0b00; // imm2
2995 let Inst{5-4} = 0b00; // type
2998 def t2CMNzrs : T2OneRegCmpShiftedReg<
2999 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3000 "cmn", ".w\t$Rn, $ShiftedRm",
3001 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3002 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3003 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3004 let Inst{31-27} = 0b11101;
3005 let Inst{26-25} = 0b01;
3006 let Inst{24-21} = 0b1000;
3007 let Inst{20} = 1; // The S bit.
3008 let Inst{11-8} = 0b1111; // Rd
3012 // Assembler aliases w/o the ".w" suffix.
3013 // No alias here for 'rr' version as not all instantiations of this multiclass
3014 // want one (CMP in particular, does not).
3015 def : t2InstAlias<"cmn${p} $Rn, $imm",
3016 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3017 def : t2InstAlias<"cmn${p} $Rn, $shift",
3018 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3020 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3021 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3023 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3024 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3026 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3027 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3028 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3029 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
3030 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3031 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3033 // Conditional moves
3034 let hasSideEffects = 0 in {
3036 let isCommutable = 1, isSelect = 1 in
3037 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3038 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
3040 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3042 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3044 let isMoveImm = 1 in
3046 : t2PseudoInst<(outs rGPR:$Rd),
3047 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3049 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3051 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3053 let isCodeGenOnly = 1 in {
3054 let isMoveImm = 1 in
3056 : t2PseudoInst<(outs rGPR:$Rd),
3057 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3059 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3061 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3063 let isMoveImm = 1 in
3065 : t2PseudoInst<(outs rGPR:$Rd),
3066 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3069 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3071 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3073 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3074 : t2PseudoInst<(outs rGPR:$Rd),
3075 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3077 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3078 (opnode rGPR:$Rm, (i32 ty:$imm)),
3080 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3082 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3083 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3084 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3085 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3087 let isMoveImm = 1 in
3089 : t2PseudoInst<(outs rGPR:$dst),
3090 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3092 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3094 RegConstraint<"$false = $dst">;
3095 } // isCodeGenOnly = 1
3099 //===----------------------------------------------------------------------===//
3100 // Atomic operations intrinsics
3103 // memory barriers protect the atomic sequences
3104 let hasSideEffects = 1 in {
3105 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3106 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
3107 Requires<[IsThumb, HasDB]> {
3109 let Inst{31-4} = 0xf3bf8f5;
3110 let Inst{3-0} = opt;
3113 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3114 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
3115 Requires<[IsThumb, HasDB]> {
3117 let Inst{31-4} = 0xf3bf8f4;
3118 let Inst{3-0} = opt;
3121 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3122 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
3123 Requires<[IsThumb, HasDB]> {
3125 let Inst{31-4} = 0xf3bf8f6;
3126 let Inst{3-0} = opt;
3130 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3131 InstrItinClass itin, string opc, string asm, string cstr,
3132 list<dag> pattern, bits<4> rt2 = 0b1111>
3133 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3134 let Inst{31-27} = 0b11101;
3135 let Inst{26-20} = 0b0001101;
3136 let Inst{11-8} = rt2;
3137 let Inst{7-4} = opcod;
3138 let Inst{3-0} = 0b1111;
3142 let Inst{19-16} = addr;
3143 let Inst{15-12} = Rt;
3145 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3146 InstrItinClass itin, string opc, string asm, string cstr,
3147 list<dag> pattern, bits<4> rt2 = 0b1111>
3148 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3149 let Inst{31-27} = 0b11101;
3150 let Inst{26-20} = 0b0001100;
3151 let Inst{11-8} = rt2;
3152 let Inst{7-4} = opcod;
3158 let Inst{19-16} = addr;
3159 let Inst{15-12} = Rt;
3162 let mayLoad = 1 in {
3163 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3164 AddrModeNone, 4, NoItinerary,
3165 "ldrexb", "\t$Rt, $addr", "",
3166 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>,
3167 Requires<[IsThumb, HasV8MBaseline]>;
3168 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3169 AddrModeNone, 4, NoItinerary,
3170 "ldrexh", "\t$Rt, $addr", "",
3171 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,
3172 Requires<[IsThumb, HasV8MBaseline]>;
3173 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3174 AddrModeNone, 4, NoItinerary,
3175 "ldrex", "\t$Rt, $addr", "",
3176 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,
3177 Requires<[IsThumb, HasV8MBaseline]> {
3180 let Inst{31-27} = 0b11101;
3181 let Inst{26-20} = 0b0000101;
3182 let Inst{19-16} = addr{11-8};
3183 let Inst{15-12} = Rt;
3184 let Inst{11-8} = 0b1111;
3185 let Inst{7-0} = addr{7-0};
3187 let hasExtraDefRegAllocReq = 1 in
3188 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3189 (ins addr_offset_none:$addr),
3190 AddrModeNone, 4, NoItinerary,
3191 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3193 Requires<[IsThumb2, IsNotMClass]> {
3195 let Inst{11-8} = Rt2;
3197 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3198 AddrModeNone, 4, NoItinerary,
3199 "ldaexb", "\t$Rt, $addr", "",
3200 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
3201 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3202 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3203 AddrModeNone, 4, NoItinerary,
3204 "ldaexh", "\t$Rt, $addr", "",
3205 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
3206 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3207 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3208 AddrModeNone, 4, NoItinerary,
3209 "ldaex", "\t$Rt, $addr", "",
3210 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
3211 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
3214 let Inst{31-27} = 0b11101;
3215 let Inst{26-20} = 0b0001101;
3216 let Inst{19-16} = addr;
3217 let Inst{15-12} = Rt;
3218 let Inst{11-8} = 0b1111;
3219 let Inst{7-0} = 0b11101111;
3221 let hasExtraDefRegAllocReq = 1 in
3222 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3223 (ins addr_offset_none:$addr),
3224 AddrModeNone, 4, NoItinerary,
3225 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3226 [], {?, ?, ?, ?}>, Requires<[IsThumb,
3227 HasAcquireRelease, HasV7Clrex, IsNotMClass]> {
3229 let Inst{11-8} = Rt2;
3235 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3236 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3237 (ins rGPR:$Rt, addr_offset_none:$addr),
3238 AddrModeNone, 4, NoItinerary,
3239 "strexb", "\t$Rd, $Rt, $addr", "",
3241 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3242 Requires<[IsThumb, HasV8MBaseline]>;
3243 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3244 (ins rGPR:$Rt, addr_offset_none:$addr),
3245 AddrModeNone, 4, NoItinerary,
3246 "strexh", "\t$Rd, $Rt, $addr", "",
3248 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3249 Requires<[IsThumb, HasV8MBaseline]>;
3251 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3252 t2addrmode_imm0_1020s4:$addr),
3253 AddrModeNone, 4, NoItinerary,
3254 "strex", "\t$Rd, $Rt, $addr", "",
3256 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,
3257 Requires<[IsThumb, HasV8MBaseline]> {
3261 let Inst{31-27} = 0b11101;
3262 let Inst{26-20} = 0b0000100;
3263 let Inst{19-16} = addr{11-8};
3264 let Inst{15-12} = Rt;
3265 let Inst{11-8} = Rd;
3266 let Inst{7-0} = addr{7-0};
3268 let hasExtraSrcRegAllocReq = 1 in
3269 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3270 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3271 AddrModeNone, 4, NoItinerary,
3272 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3274 Requires<[IsThumb2, IsNotMClass]> {
3276 let Inst{11-8} = Rt2;
3278 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3279 (ins rGPR:$Rt, addr_offset_none:$addr),
3280 AddrModeNone, 4, NoItinerary,
3281 "stlexb", "\t$Rd, $Rt, $addr", "",
3283 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3284 Requires<[IsThumb, HasAcquireRelease,
3287 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3288 (ins rGPR:$Rt, addr_offset_none:$addr),
3289 AddrModeNone, 4, NoItinerary,
3290 "stlexh", "\t$Rd, $Rt, $addr", "",
3292 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3293 Requires<[IsThumb, HasAcquireRelease,
3296 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3297 addr_offset_none:$addr),
3298 AddrModeNone, 4, NoItinerary,
3299 "stlex", "\t$Rd, $Rt, $addr", "",
3301 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
3302 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
3306 let Inst{31-27} = 0b11101;
3307 let Inst{26-20} = 0b0001100;
3308 let Inst{19-16} = addr;
3309 let Inst{15-12} = Rt;
3310 let Inst{11-4} = 0b11111110;
3313 let hasExtraSrcRegAllocReq = 1 in
3314 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3315 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3316 AddrModeNone, 4, NoItinerary,
3317 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3318 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,
3319 HasV7Clrex, IsNotMClass]> {
3321 let Inst{11-8} = Rt2;
3325 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3326 Requires<[IsThumb, HasV7Clrex]> {
3327 let Inst{31-16} = 0xf3bf;
3328 let Inst{15-14} = 0b10;
3331 let Inst{11-8} = 0b1111;
3332 let Inst{7-4} = 0b0010;
3333 let Inst{3-0} = 0b1111;
3336 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3337 (t2LDREXB addr_offset_none:$addr)>,
3338 Requires<[IsThumb, HasV8MBaseline]>;
3339 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3340 (t2LDREXH addr_offset_none:$addr)>,
3341 Requires<[IsThumb, HasV8MBaseline]>;
3342 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3343 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>,
3344 Requires<[IsThumb, HasV8MBaseline]>;
3345 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3346 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>,
3347 Requires<[IsThumb, HasV8MBaseline]>;
3349 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3350 (t2LDAEXB addr_offset_none:$addr)>,
3351 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3352 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3353 (t2LDAEXH addr_offset_none:$addr)>,
3354 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3355 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3356 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>,
3357 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3358 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3359 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>,
3360 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3362 //===----------------------------------------------------------------------===//
3363 // SJLJ Exception handling intrinsics
3364 // eh_sjlj_setjmp() is an instruction sequence to store the return
3365 // address and save #0 in R0 for the non-longjmp case.
3366 // Since by its nature we may be coming from some other function to get
3367 // here, and we're using the stack frame for the containing function to
3368 // save/restore registers, we can't keep anything live in regs across
3369 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3370 // when we get here from a longjmp(). We force everything out of registers
3371 // except for our own input by listing the relevant registers in Defs. By
3372 // doing so, we also cause the prologue/epilogue code to actively preserve
3373 // all of the callee-saved resgisters, which is exactly what we want.
3374 // $val is a scratch register for our use.
3376 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3377 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3378 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3379 usesCustomInserter = 1 in {
3380 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3381 AddrModeNone, 0, NoItinerary, "", "",
3382 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3383 Requires<[IsThumb2, HasVFP2]>;
3387 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3388 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3389 usesCustomInserter = 1 in {
3390 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3391 AddrModeNone, 0, NoItinerary, "", "",
3392 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3393 Requires<[IsThumb2, NoVFP]>;
3397 //===----------------------------------------------------------------------===//
3398 // Control-Flow Instructions
3401 // FIXME: remove when we have a way to marking a MI with these properties.
3402 // FIXME: Should pc be an implicit operand like PICADD, etc?
3403 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3404 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3405 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3406 reglist:$regs, variable_ops),
3407 4, IIC_iLoad_mBr, [],
3408 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3409 RegConstraint<"$Rn = $wb">;
3411 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3412 let isPredicable = 1 in
3413 def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br,
3415 [(br bb:$target)]>, Sched<[WriteBr]>,
3416 Requires<[IsThumb, HasV8MBaseline]> {
3417 let Inst{31-27} = 0b11110;
3418 let Inst{15-14} = 0b10;
3422 let Inst{26} = target{23};
3423 let Inst{13} = target{22};
3424 let Inst{11} = target{21};
3425 let Inst{25-16} = target{20-11};
3426 let Inst{10-0} = target{10-0};
3427 let DecoderMethod = "DecodeT2BInstruction";
3428 let AsmMatchConverter = "cvtThumbBranches";
3431 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
3433 // available in both v8-M.Baseline and Thumb2 targets
3434 def t2BR_JT : t2basePseudoInst<(outs),
3435 (ins GPR:$target, GPR:$index, i32imm:$jt),
3437 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,
3440 // FIXME: Add a case that can be predicated.
3441 def t2TBB_JT : t2PseudoInst<(outs),
3442 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3445 def t2TBH_JT : t2PseudoInst<(outs),
3446 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3449 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3450 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3453 let Inst{31-20} = 0b111010001101;
3454 let Inst{19-16} = Rn;
3455 let Inst{15-5} = 0b11110000000;
3456 let Inst{4} = 0; // B form
3459 let DecoderMethod = "DecodeThumbTableBranch";
3462 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3463 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3466 let Inst{31-20} = 0b111010001101;
3467 let Inst{19-16} = Rn;
3468 let Inst{15-5} = 0b11110000000;
3469 let Inst{4} = 1; // H form
3472 let DecoderMethod = "DecodeThumbTableBranch";
3474 } // isNotDuplicable, isIndirectBranch
3476 } // isBranch, isTerminator, isBarrier
3478 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3479 // a two-value operand where a dag node expects ", "two operands. :(
3480 let isBranch = 1, isTerminator = 1 in
3481 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3483 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3484 let Inst{31-27} = 0b11110;
3485 let Inst{15-14} = 0b10;
3489 let Inst{25-22} = p;
3492 let Inst{26} = target{20};
3493 let Inst{11} = target{19};
3494 let Inst{13} = target{18};
3495 let Inst{21-16} = target{17-12};
3496 let Inst{10-0} = target{11-1};
3498 let DecoderMethod = "DecodeThumb2BCCInstruction";
3499 let AsmMatchConverter = "cvtThumbBranches";
3502 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
3504 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3507 def tTAILJMPd: tPseudoExpand<(outs),
3508 (ins thumb_br_target:$dst, pred:$p),
3510 (t2B thumb_br_target:$dst, pred:$p)>,
3511 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3515 let Defs = [ITSTATE] in
3516 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3517 AddrModeNone, 2, IIC_iALUx,
3518 "it$mask\t$cc", "", []>,
3519 ComplexDeprecationPredicate<"IT"> {
3520 // 16-bit instruction.
3521 let Inst{31-16} = 0x0000;
3522 let Inst{15-8} = 0b10111111;
3527 let Inst{3-0} = mask;
3529 let DecoderMethod = "DecodeIT";
3532 // Branch and Exchange Jazelle -- for disassembly only
3534 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
3535 def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
3536 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
3538 let Inst{31-27} = 0b11110;
3540 let Inst{25-20} = 0b111100;
3541 let Inst{19-16} = func;
3542 let Inst{15-0} = 0b1000111100000000;
3545 // Compare and branch on zero / non-zero
3546 let isBranch = 1, isTerminator = 1 in {
3547 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3548 "cbz\t$Rn, $target", []>,
3549 T1Misc<{0,0,?,1,?,?,?}>,
3550 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3554 let Inst{9} = target{5};
3555 let Inst{7-3} = target{4-0};
3559 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3560 "cbnz\t$Rn, $target", []>,
3561 T1Misc<{1,0,?,1,?,?,?}>,
3562 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3566 let Inst{9} = target{5};
3567 let Inst{7-3} = target{4-0};
3573 // Change Processor State is a system instruction.
3574 // FIXME: Since the asm parser has currently no clean way to handle optional
3575 // operands, create 3 versions of the same instruction. Once there's a clean
3576 // framework to represent optional operands, change this behavior.
3577 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3578 !strconcat("cps", asm_op), []>,
3579 Requires<[IsThumb2, IsNotMClass]> {
3585 let Inst{31-11} = 0b111100111010111110000;
3586 let Inst{10-9} = imod;
3588 let Inst{7-5} = iflags;
3589 let Inst{4-0} = mode;
3590 let DecoderMethod = "DecodeT2CPSInstruction";
3594 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3595 "$imod\t$iflags, $mode">;
3596 let mode = 0, M = 0 in
3597 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3598 "$imod.w\t$iflags">;
3599 let imod = 0, iflags = 0, M = 1 in
3600 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3602 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3603 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3604 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3606 // A6.3.4 Branches and miscellaneous control
3607 // Table A6-14 Change Processor State, and hint instructions
3608 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
3609 [(int_arm_hint imm0_239:$imm)]> {
3611 let Inst{31-3} = 0b11110011101011111000000000000;
3612 let Inst{7-0} = imm;
3615 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
3616 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
3617 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
3618 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
3619 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
3620 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
3621 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
3622 let Predicates = [IsThumb2, HasV8];
3624 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
3625 let Predicates = [IsThumb2, HasRAS];
3627 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
3628 let Predicates = [IsThumb2, HasRAS];
3631 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
3632 [(int_arm_dbg imm0_15:$opt)]> {
3634 let Inst{31-20} = 0b111100111010;
3635 let Inst{19-16} = 0b1111;
3636 let Inst{15-8} = 0b10000000;
3637 let Inst{7-4} = 0b1111;
3638 let Inst{3-0} = opt;
3641 // Secure Monitor Call is a system instruction.
3642 // Option = Inst{19-16}
3643 let isCall = 1, Uses = [SP] in
3644 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3645 []>, Requires<[IsThumb2, HasTrustZone]> {
3646 let Inst{31-27} = 0b11110;
3647 let Inst{26-20} = 0b1111111;
3648 let Inst{15-12} = 0b1000;
3651 let Inst{19-16} = opt;
3654 class T2DCPS<bits<2> opt, string opc>
3655 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3656 let Inst{31-27} = 0b11110;
3657 let Inst{26-20} = 0b1111000;
3658 let Inst{19-16} = 0b1111;
3659 let Inst{15-12} = 0b1000;
3660 let Inst{11-2} = 0b0000000000;
3661 let Inst{1-0} = opt;
3664 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
3665 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
3666 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
3668 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3669 string opc, string asm, list<dag> pattern>
3670 : T2I<oops, iops, itin, opc, asm, pattern>,
3671 Requires<[IsThumb2,IsNotMClass]> {
3673 let Inst{31-25} = 0b1110100;
3674 let Inst{24-23} = Op;
3677 let Inst{20-16} = 0b01101;
3678 let Inst{15-5} = 0b11000000000;
3679 let Inst{4-0} = mode{4-0};
3682 // Store Return State is a system instruction.
3683 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3684 "srsdb", "\tsp!, $mode", []>;
3685 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3686 "srsdb","\tsp, $mode", []>;
3687 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3688 "srsia","\tsp!, $mode", []>;
3689 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3690 "srsia","\tsp, $mode", []>;
3693 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3694 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3696 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3697 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3699 // Return From Exception is a system instruction.
3700 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3701 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3702 string opc, string asm, list<dag> pattern>
3703 : T2I<oops, iops, itin, opc, asm, pattern>,
3704 Requires<[IsThumb2,IsNotMClass]> {
3705 let Inst{31-20} = op31_20{11-0};
3708 let Inst{19-16} = Rn;
3709 let Inst{15-0} = 0xc000;
3712 def t2RFEDBW : T2RFE<0b111010000011,
3713 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3714 [/* For disassembly only; pattern left blank */]>;
3715 def t2RFEDB : T2RFE<0b111010000001,
3716 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3717 [/* For disassembly only; pattern left blank */]>;
3718 def t2RFEIAW : T2RFE<0b111010011011,
3719 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3720 [/* For disassembly only; pattern left blank */]>;
3721 def t2RFEIA : T2RFE<0b111010011001,
3722 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3723 [/* For disassembly only; pattern left blank */]>;
3725 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
3726 // Exception return instruction is "subs pc, lr, #imm".
3727 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3728 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
3729 "subs", "\tpc, lr, $imm",
3730 [(ARMintretflag imm0_255:$imm)]>,
3731 Requires<[IsThumb2,IsNotMClass]> {
3732 let Inst{31-8} = 0b111100111101111010001111;
3735 let Inst{7-0} = imm;
3738 // Hypervisor Call is a system instruction.
3740 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
3741 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
3743 let Inst{31-20} = 0b111101111110;
3744 let Inst{19-16} = imm16{15-12};
3745 let Inst{15-12} = 0b1000;
3746 let Inst{11-0} = imm16{11-0};
3750 // Alias for HVC without the ".w" optional width specifier
3751 def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
3753 // ERET - Return from exception in Hypervisor mode.
3754 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
3755 // includes virtualization extensions.
3756 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
3757 Requires<[IsThumb2, HasVirtualization]>;
3759 //===----------------------------------------------------------------------===//
3760 // Non-Instruction Patterns
3763 // 32-bit immediate using movw + movt.
3764 // This is a single pseudo instruction to make it re-materializable.
3765 // FIXME: Remove this when we can do generalized remat.
3766 let isReMaterializable = 1, isMoveImm = 1 in
3767 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3768 [(set rGPR:$dst, (i32 imm:$src))]>,
3769 Requires<[IsThumb, UseMovt]>;
3771 // Pseudo instruction that combines movw + movt + add pc (if pic).
3772 // It also makes it possible to rematerialize the instructions.
3773 // FIXME: Remove this when we can do generalized remat and when machine licm
3774 // can properly the instructions.
3775 let isReMaterializable = 1 in {
3776 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3778 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3779 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3783 def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst),
3784 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>,
3785 Requires<[IsThumb2, UseMovt]>;
3786 def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst),
3787 (t2MOVi32imm tglobaltlsaddr:$dst)>,
3788 Requires<[IsThumb2, UseMovt]>;
3790 // ConstantPool, GlobalAddress, and JumpTable
3791 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3792 def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>,
3793 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3794 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3795 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3797 def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;
3799 // Pseudo instruction that combines ldr from constpool and add pc. This should
3800 // be expanded into two instructions late to allow if-conversion and
3802 let canFoldAsLoad = 1, isReMaterializable = 1 in
3803 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3805 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3807 Requires<[IsThumb2]>;
3809 // Pseudo isntruction that combines movs + predicated rsbmi
3810 // to implement integer ABS
3811 let usesCustomInserter = 1, Defs = [CPSR] in {
3812 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3813 NoItinerary, []>, Requires<[IsThumb2]>;
3816 //===----------------------------------------------------------------------===//
3817 // Coprocessor load/store -- for disassembly only
3819 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern>
3820 : T2I<oops, iops, NoItinerary, opc, asm, pattern> {
3821 let Inst{31-28} = op31_28;
3822 let Inst{27-25} = 0b110;
3825 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> {
3826 def _OFFSET : T2CI<op31_28,
3827 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3828 asm, "\t$cop, $CRd, $addr", pattern> {
3832 let Inst{24} = 1; // P = 1
3833 let Inst{23} = addr{8};
3834 let Inst{22} = Dbit;
3835 let Inst{21} = 0; // W = 0
3836 let Inst{20} = load;
3837 let Inst{19-16} = addr{12-9};
3838 let Inst{15-12} = CRd;
3839 let Inst{11-8} = cop;
3840 let Inst{7-0} = addr{7-0};
3841 let DecoderMethod = "DecodeCopMemInstruction";
3843 def _PRE : T2CI<op31_28,
3844 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3845 asm, "\t$cop, $CRd, $addr!", []> {
3849 let Inst{24} = 1; // P = 1
3850 let Inst{23} = addr{8};
3851 let Inst{22} = Dbit;
3852 let Inst{21} = 1; // W = 1
3853 let Inst{20} = load;
3854 let Inst{19-16} = addr{12-9};
3855 let Inst{15-12} = CRd;
3856 let Inst{11-8} = cop;
3857 let Inst{7-0} = addr{7-0};
3858 let DecoderMethod = "DecodeCopMemInstruction";
3860 def _POST: T2CI<op31_28,
3861 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3862 postidx_imm8s4:$offset),
3863 asm, "\t$cop, $CRd, $addr, $offset", []> {
3868 let Inst{24} = 0; // P = 0
3869 let Inst{23} = offset{8};
3870 let Inst{22} = Dbit;
3871 let Inst{21} = 1; // W = 1
3872 let Inst{20} = load;
3873 let Inst{19-16} = addr;
3874 let Inst{15-12} = CRd;
3875 let Inst{11-8} = cop;
3876 let Inst{7-0} = offset{7-0};
3877 let DecoderMethod = "DecodeCopMemInstruction";
3879 def _OPTION : T2CI<op31_28, (outs),
3880 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3881 coproc_option_imm:$option),
3882 asm, "\t$cop, $CRd, $addr, $option", []> {
3887 let Inst{24} = 0; // P = 0
3888 let Inst{23} = 1; // U = 1
3889 let Inst{22} = Dbit;
3890 let Inst{21} = 0; // W = 0
3891 let Inst{20} = load;
3892 let Inst{19-16} = addr;
3893 let Inst{15-12} = CRd;
3894 let Inst{11-8} = cop;
3895 let Inst{7-0} = option;
3896 let DecoderMethod = "DecodeCopMemInstruction";
3900 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3901 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3902 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3903 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3905 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3906 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
3907 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3908 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
3911 //===----------------------------------------------------------------------===//
3912 // Move between special register and ARM core register -- for disassembly only
3914 // Move to ARM core register from Special Register
3918 // A/R class can only move from CPSR or SPSR.
3919 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3920 []>, Requires<[IsThumb2,IsNotMClass]> {
3922 let Inst{31-12} = 0b11110011111011111000;
3923 let Inst{11-8} = Rd;
3924 let Inst{7-0} = 0b00000000;
3927 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3929 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3930 []>, Requires<[IsThumb2,IsNotMClass]> {
3932 let Inst{31-12} = 0b11110011111111111000;
3933 let Inst{11-8} = Rd;
3934 let Inst{7-0} = 0b00000000;
3937 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
3938 NoItinerary, "mrs", "\t$Rd, $banked", []>,
3939 Requires<[IsThumb, HasVirtualization]> {
3943 let Inst{31-21} = 0b11110011111;
3944 let Inst{20} = banked{5}; // R bit
3945 let Inst{19-16} = banked{3-0};
3946 let Inst{15-12} = 0b1000;
3947 let Inst{11-8} = Rd;
3948 let Inst{7-5} = 0b001;
3949 let Inst{4} = banked{4};
3950 let Inst{3-0} = 0b0000;
3956 // This MRS has a mask field in bits 7-0 and can take more values than
3957 // the A/R class (a full msr_mask).
3958 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
3959 "mrs", "\t$Rd, $SYSm", []>,
3960 Requires<[IsThumb,IsMClass]> {
3963 let Inst{31-12} = 0b11110011111011111000;
3964 let Inst{11-8} = Rd;
3965 let Inst{7-0} = SYSm;
3967 let Unpredictable{20-16} = 0b11111;
3968 let Unpredictable{13} = 0b1;
3972 // Move from ARM core register to Special Register
3976 // No need to have both system and application versions, the encodings are the
3977 // same and the assembly parser has no way to distinguish between them. The mask
3978 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3979 // the mask with the fields to be accessed in the special register.
3980 let Defs = [CPSR] in
3981 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3982 NoItinerary, "msr", "\t$mask, $Rn", []>,
3983 Requires<[IsThumb2,IsNotMClass]> {
3986 let Inst{31-21} = 0b11110011100;
3987 let Inst{20} = mask{4}; // R Bit
3988 let Inst{19-16} = Rn;
3989 let Inst{15-12} = 0b1000;
3990 let Inst{11-8} = mask{3-0};
3994 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
3995 // separate encoding (distinguished by bit 5.
3996 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
3997 NoItinerary, "msr", "\t$banked, $Rn", []>,
3998 Requires<[IsThumb, HasVirtualization]> {
4002 let Inst{31-21} = 0b11110011100;
4003 let Inst{20} = banked{5}; // R bit
4004 let Inst{19-16} = Rn;
4005 let Inst{15-12} = 0b1000;
4006 let Inst{11-8} = banked{3-0};
4007 let Inst{7-5} = 0b001;
4008 let Inst{4} = banked{4};
4009 let Inst{3-0} = 0b0000;
4015 // Move from ARM core register to Special Register
4016 let Defs = [CPSR] in
4017 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
4018 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
4019 Requires<[IsThumb,IsMClass]> {
4022 let Inst{31-21} = 0b11110011100;
4024 let Inst{19-16} = Rn;
4025 let Inst{15-12} = 0b1000;
4026 let Inst{11-10} = SYSm{11-10};
4027 let Inst{9-8} = 0b00;
4028 let Inst{7-0} = SYSm{7-0};
4030 let Unpredictable{20} = 0b1;
4031 let Unpredictable{13} = 0b1;
4032 let Unpredictable{9-8} = 0b11;
4036 //===----------------------------------------------------------------------===//
4037 // Move between coprocessor and ARM core register
4040 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4042 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4044 let Inst{27-24} = 0b1110;
4045 let Inst{20} = direction;
4055 let Inst{15-12} = Rt;
4056 let Inst{11-8} = cop;
4057 let Inst{23-21} = opc1;
4058 let Inst{7-5} = opc2;
4059 let Inst{3-0} = CRm;
4060 let Inst{19-16} = CRn;
4063 class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4064 list<dag> pattern = []>
4065 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4066 let Inst{27-24} = 0b1100;
4067 let Inst{23-21} = 0b010;
4068 let Inst{20} = direction;
4076 let Inst{15-12} = Rt;
4077 let Inst{19-16} = Rt2;
4078 let Inst{11-8} = cop;
4079 let Inst{7-4} = opc1;
4080 let Inst{3-0} = CRm;
4083 /* from ARM core register to coprocessor */
4084 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4086 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4087 c_imm:$CRm, imm0_7:$opc2),
4088 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4089 imm:$CRm, imm:$opc2)]>,
4090 ComplexDeprecationPredicate<"MCR">;
4091 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4092 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4093 c_imm:$CRm, 0, pred:$p)>;
4094 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4095 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4096 c_imm:$CRm, imm0_7:$opc2),
4097 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4098 imm:$CRm, imm:$opc2)]> {
4099 let Predicates = [IsThumb2, PreV8];
4101 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4102 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4103 c_imm:$CRm, 0, pred:$p)>;
4105 /* from coprocessor to ARM core register */
4106 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4107 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4108 c_imm:$CRm, imm0_7:$opc2), []>;
4109 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4110 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4111 c_imm:$CRm, 0, pred:$p)>;
4113 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4114 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4115 c_imm:$CRm, imm0_7:$opc2), []> {
4116 let Predicates = [IsThumb2, PreV8];
4118 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4119 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4120 c_imm:$CRm, 0, pred:$p)>;
4122 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4123 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4125 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4126 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4129 /* from ARM core register to coprocessor */
4130 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),
4131 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4133 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4135 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),
4136 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4138 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
4139 GPR:$Rt2, imm:$CRm)]> {
4140 let Predicates = [IsThumb2, PreV8];
4143 /* from coprocessor to ARM core register */
4144 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4145 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>;
4147 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),
4148 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> {
4149 let Predicates = [IsThumb2, PreV8];
4152 //===----------------------------------------------------------------------===//
4153 // Other Coprocessor Instructions.
4156 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4157 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4158 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4159 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4160 imm:$CRm, imm:$opc2)]> {
4161 let Inst{27-24} = 0b1110;
4170 let Inst{3-0} = CRm;
4172 let Inst{7-5} = opc2;
4173 let Inst{11-8} = cop;
4174 let Inst{15-12} = CRd;
4175 let Inst{19-16} = CRn;
4176 let Inst{23-20} = opc1;
4178 let Predicates = [IsThumb2, PreV8];
4181 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4182 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4183 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4184 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4185 imm:$CRm, imm:$opc2)]> {
4186 let Inst{27-24} = 0b1110;
4195 let Inst{3-0} = CRm;
4197 let Inst{7-5} = opc2;
4198 let Inst{11-8} = cop;
4199 let Inst{15-12} = CRd;
4200 let Inst{19-16} = CRn;
4201 let Inst{23-20} = opc1;
4203 let Predicates = [IsThumb2, PreV8];
4208 //===----------------------------------------------------------------------===//
4209 // ARMv8.1 Privilege Access Never extension
4213 def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
4214 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4219 let Inst{2-0} = 0b000;
4221 let Unpredictable{4} = 0b1;
4222 let Unpredictable{2-0} = 0b111;
4225 //===----------------------------------------------------------------------===//
4226 // ARMv8-M Security Extensions instructions
4229 let hasSideEffects = 1 in
4230 def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
4231 Requires<[Has8MSecExt]> {
4232 let Inst = 0xe97fe97f;
4235 class T2TT<bits<2> at, string asm, list<dag> pattern>
4236 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
4241 let Inst{31-20} = 0b111010000100;
4242 let Inst{19-16} = Rn;
4243 let Inst{15-12} = 0b1111;
4244 let Inst{11-8} = Rt;
4246 let Inst{5-0} = 0b000000;
4248 let Unpredictable{5-0} = 0b111111;
4251 def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
4252 def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
4253 def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
4254 def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
4256 //===----------------------------------------------------------------------===//
4257 // Non-Instruction Patterns
4260 // SXT/UXT with no rotate
4261 let AddedComplexity = 16 in {
4262 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4263 Requires<[IsThumb2]>;
4264 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4265 Requires<[IsThumb2]>;
4266 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4267 Requires<[HasDSP, IsThumb2]>;
4268 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4269 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4270 Requires<[HasDSP, IsThumb2]>;
4271 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4272 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4273 Requires<[HasDSP, IsThumb2]>;
4276 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4277 Requires<[IsThumb2]>;
4278 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4279 Requires<[IsThumb2]>;
4280 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4281 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4282 Requires<[HasDSP, IsThumb2]>;
4283 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4284 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4285 Requires<[HasDSP, IsThumb2]>;
4287 // Atomic load/store patterns
4288 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4289 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4290 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4291 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4292 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4293 (t2LDRBs t2addrmode_so_reg:$addr)>;
4294 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4295 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4296 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4297 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4298 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4299 (t2LDRHs t2addrmode_so_reg:$addr)>;
4300 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4301 (t2LDRi12 t2addrmode_imm12:$addr)>;
4302 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4303 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4304 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4305 (t2LDRs t2addrmode_so_reg:$addr)>;
4306 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4307 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4308 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4309 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4310 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4311 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4312 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4313 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4314 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4315 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4316 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4317 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4318 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4319 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4320 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4321 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4322 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4323 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4325 let AddedComplexity = 8 in {
4326 def : T2Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4327 def : T2Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4328 def : T2Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
4329 def : T2Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
4330 def : T2Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
4331 def : T2Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;
4335 //===----------------------------------------------------------------------===//
4336 // Assembler aliases
4339 // Aliases for ADC without the ".w" optional width specifier.
4340 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4341 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4342 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4343 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4344 pred:$p, cc_out:$s)>;
4346 // Aliases for SBC without the ".w" optional width specifier.
4347 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4348 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4349 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4350 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4351 pred:$p, cc_out:$s)>;
4353 // Aliases for ADD without the ".w" optional width specifier.
4354 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4355 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4357 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4358 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4359 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4360 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4361 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4362 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4363 pred:$p, cc_out:$s)>;
4364 // ... and with the destination and source register combined.
4365 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4366 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4367 def : t2InstAlias<"add${p} $Rdn, $imm",
4368 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4369 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4370 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4371 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4372 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4373 pred:$p, cc_out:$s)>;
4375 // add w/ negative immediates is just a sub.
4376 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4377 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4379 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
4380 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4381 def : t2InstSubst<"add${s}${p} $Rdn, $imm",
4382 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4384 def : t2InstSubst<"add${p} $Rdn, $imm",
4385 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4387 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4388 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4390 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
4391 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4392 def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",
4393 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4395 def : t2InstSubst<"addw${p} $Rdn, $imm",
4396 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4399 // Aliases for SUB without the ".w" optional width specifier.
4400 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4401 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4402 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4403 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4404 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4405 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4406 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4407 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4408 pred:$p, cc_out:$s)>;
4409 // ... and with the destination and source register combined.
4410 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4411 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4412 def : t2InstAlias<"sub${p} $Rdn, $imm",
4413 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4414 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4415 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4416 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4417 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4418 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4419 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4420 pred:$p, cc_out:$s)>;
4422 // Alias for compares without the ".w" optional width specifier.
4423 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4424 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4425 def : t2InstAlias<"teq${p} $Rn, $Rm",
4426 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4427 def : t2InstAlias<"tst${p} $Rn, $Rm",
4428 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4431 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4432 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4433 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4435 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4437 def : t2InstAlias<"ldr${p} $Rt, $addr",
4438 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4439 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4440 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4441 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4442 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4443 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4444 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4445 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4446 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4448 def : t2InstAlias<"ldr${p} $Rt, $addr",
4449 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4450 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4451 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4452 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4453 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4454 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4455 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4456 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4457 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4459 def : t2InstAlias<"ldr${p} $Rt, $addr",
4460 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4461 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4462 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4463 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4464 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4465 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4466 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4467 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4468 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4470 // Alias for MVN with(out) the ".w" optional width specifier.
4471 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4472 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4473 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4474 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4475 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4476 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4478 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
4479 // input operands swapped when the shift amount is zero (i.e., unspecified).
4480 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4481 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4482 Requires<[HasDSP, IsThumb2]>;
4483 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4484 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
4485 Requires<[HasDSP, IsThumb2]>;
4487 // PUSH/POP aliases for STM/LDM
4488 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4489 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4490 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4491 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4493 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4494 def : t2InstAlias<"stm${p} $Rn, $regs",
4495 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4496 def : t2InstAlias<"stm${p} $Rn!, $regs",
4497 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4499 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4500 def : t2InstAlias<"ldm${p} $Rn, $regs",
4501 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4502 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4503 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4505 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4506 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4507 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4508 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4509 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4511 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4512 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4513 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4514 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4515 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4517 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4518 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4519 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4520 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4523 // Alias for RSB without the ".w" optional width specifier, and with optional
4524 // implied destination register.
4525 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4526 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4527 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4528 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4529 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4530 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4531 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4532 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4535 // SSAT/USAT optional shift operand.
4536 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4537 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4538 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4539 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4541 // STM w/o the .w suffix.
4542 def : t2InstAlias<"stm${p} $Rn, $regs",
4543 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4545 // Alias for STR, STRB, and STRH without the ".w" optional
4547 def : t2InstAlias<"str${p} $Rt, $addr",
4548 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4549 def : t2InstAlias<"strb${p} $Rt, $addr",
4550 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4551 def : t2InstAlias<"strh${p} $Rt, $addr",
4552 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4554 def : t2InstAlias<"str${p} $Rt, $addr",
4555 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4556 def : t2InstAlias<"strb${p} $Rt, $addr",
4557 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4558 def : t2InstAlias<"strh${p} $Rt, $addr",
4559 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4561 // Extend instruction optional rotate operand.
4562 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4563 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4564 Requires<[HasDSP, IsThumb2]>;
4565 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4566 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4567 Requires<[HasDSP, IsThumb2]>;
4568 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4569 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4570 Requires<[HasDSP, IsThumb2]>;
4571 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4572 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4573 Requires<[HasDSP, IsThumb2]>;
4575 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4576 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4577 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4578 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4579 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4580 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4581 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4582 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4584 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4585 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4586 Requires<[HasDSP, IsThumb2]>;
4587 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4588 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4589 Requires<[HasDSP, IsThumb2]>;
4590 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4591 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4592 Requires<[HasDSP, IsThumb2]>;
4593 def : InstAlias<"uxtb16${p} $Rd, $Rm",
4594 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4595 Requires<[HasDSP, IsThumb2]>;
4597 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4598 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4599 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4600 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4601 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4602 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4603 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4604 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4606 // Extend instruction w/o the ".w" optional width specifier.
4607 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4608 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4609 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4610 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4611 Requires<[HasDSP, IsThumb2]>;
4612 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4613 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4615 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4616 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4617 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4618 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4619 Requires<[HasDSP, IsThumb2]>;
4620 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4621 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4624 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4626 def : t2InstSubst<"mov${p} $Rd, $imm",
4627 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4628 def : t2InstSubst<"mvn${s}${p} $Rd, $imm",
4629 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
4630 // Same for AND <--> BIC
4631 def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm",
4632 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4633 pred:$p, cc_out:$s)>;
4634 def : t2InstSubst<"bic${s}${p} $Rdn, $imm",
4635 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4636 pred:$p, cc_out:$s)>;
4637 def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",
4638 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4639 pred:$p, cc_out:$s)>;
4640 def : t2InstSubst<"and${s}${p} $Rdn, $imm",
4641 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4642 pred:$p, cc_out:$s)>;
4643 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4644 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4645 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4646 pred:$p, cc_out:$s)>;
4647 def : t2InstSubst<"add${s}${p} $Rd, $imm",
4648 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4649 pred:$p, cc_out:$s)>;
4650 // Same for CMP <--> CMN via t2_so_imm_neg
4651 def : t2InstSubst<"cmp${p} $Rd, $imm",
4652 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4653 def : t2InstSubst<"cmn${p} $Rd, $imm",
4654 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4657 // Wide 'mul' encoding can be specified with only two operands.
4658 def : t2InstAlias<"mul${p} $Rn, $Rm",
4659 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4661 // "neg" is and alias for "rsb rd, rn, #0"
4662 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4663 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4665 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4666 // these, unfortunately.
4667 // FIXME: LSL #0 in the shift should allow SP to be used as either the
4668 // source or destination (but not both).
4669 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4670 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4671 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4672 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4674 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4675 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4676 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4677 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4679 // ADR w/o the .w suffix
4680 def : t2InstAlias<"adr${p} $Rd, $addr",
4681 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4683 // LDR(literal) w/ alternate [pc, #imm] syntax.
4684 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4685 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4686 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4687 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4688 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4689 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4690 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4691 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4692 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4693 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4694 // Version w/ the .w suffix.
4695 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4696 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
4697 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4698 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4699 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4700 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4701 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4702 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4703 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4704 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4706 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4707 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4709 // Pseudo instruction ldr Rt, =immediate
4711 : t2AsmPseudo<"ldr${p} $Rt, $immediate",
4712 (ins GPRnopc:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
4713 // Version w/ the .w suffix.
4714 def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
4715 (t2LDRConstPool GPRnopc:$Rt,
4716 const_pool_asm_imm:$immediate, pred:$p)>;
4718 // PLD/PLDW/PLI with alternate literal form.
4719 def : t2InstAlias<"pld${p} $addr",
4720 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4721 def : InstAlias<"pli${p} $addr",
4722 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
4723 Requires<[IsThumb2,HasV7]>;