1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
61 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
62 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
63 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
67 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
68 // described for so_imm_notSext def below, with sign extension from 16
70 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
71 APInt apIntN = N->getAPIntValue();
72 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
73 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
76 // t2_so_imm - Match a 32-bit immediate operand, which is an
77 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
78 // immediate splatted into multiple bytes of the word.
79 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
80 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
81 return ARM_AM::getT2SOImmVal(Imm) != -1;
83 let ParserMatchClass = t2_so_imm_asmoperand;
84 let EncoderMethod = "getT2SOImmOpValue";
85 let DecoderMethod = "DecodeT2SOImm";
88 // t2_so_imm_not - Match an immediate that is a complement
90 // Note: this pattern doesn't require an encoder method and such, as it's
91 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
92 // is handled by the destination instructions, which use t2_so_imm.
93 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
94 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
95 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
96 }], t2_so_imm_not_XFORM> {
97 let ParserMatchClass = t2_so_imm_not_asmoperand;
100 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
101 // if the upper 16 bits are zero.
102 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
103 APInt apIntN = N->getAPIntValue();
104 if (!apIntN.isIntN(16)) return false;
105 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
106 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
107 }], t2_so_imm_notSext16_XFORM> {
108 let ParserMatchClass = t2_so_imm_not_asmoperand;
111 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
112 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
113 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
114 int64_t Value = -(int)N->getZExtValue();
115 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
116 }], t2_so_imm_neg_XFORM> {
117 let ParserMatchClass = t2_so_imm_neg_asmoperand;
120 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
121 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
122 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
123 return Imm >= 0 && Imm < 4096;
125 let ParserMatchClass = imm0_4095_asmoperand;
128 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
129 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
130 return (uint32_t)(-N->getZExtValue()) < 4096;
132 let ParserMatchClass = imm0_4095_neg_asmoperand;
135 def imm1_255_neg : PatLeaf<(i32 imm), [{
136 uint32_t Val = -N->getZExtValue();
137 return (Val > 0 && Val < 255);
140 def imm0_255_not : PatLeaf<(i32 imm), [{
141 return (uint32_t)(~N->getZExtValue()) < 255;
144 def lo5AllOne : PatLeaf<(i32 imm), [{
145 // Returns true if all low 5-bits are 1.
146 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
149 // Define Thumb2 specific addressing modes.
151 // t2addrmode_imm12 := reg + imm12
152 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
153 def t2addrmode_imm12 : MemOperand,
154 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
155 let PrintMethod = "printAddrModeImm12Operand<false>";
156 let EncoderMethod = "getAddrModeImm12OpValue";
157 let DecoderMethod = "DecodeT2AddrModeImm12";
158 let ParserMatchClass = t2addrmode_imm12_asmoperand;
159 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
162 // t2ldrlabel := imm12
163 def t2ldrlabel : Operand<i32> {
164 let EncoderMethod = "getAddrModeImm12OpValue";
165 let PrintMethod = "printThumbLdrLabelOperand";
168 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
169 def t2ldr_pcrel_imm12 : Operand<i32> {
170 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
171 // used for assembler pseudo instruction and maps to t2ldrlabel, so
172 // doesn't need encoder or print methods of its own.
175 // ADR instruction labels.
176 def t2adrlabel : Operand<i32> {
177 let EncoderMethod = "getT2AdrLabelOpValue";
178 let PrintMethod = "printAdrLabelOperand<0>";
181 // t2addrmode_posimm8 := reg + imm8
182 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
183 def t2addrmode_posimm8 : MemOperand {
184 let PrintMethod = "printT2AddrModeImm8Operand<false>";
185 let EncoderMethod = "getT2AddrModeImm8OpValue";
186 let DecoderMethod = "DecodeT2AddrModeImm8";
187 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
188 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
191 // t2addrmode_negimm8 := reg - imm8
192 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
193 def t2addrmode_negimm8 : MemOperand,
194 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
195 let PrintMethod = "printT2AddrModeImm8Operand<false>";
196 let EncoderMethod = "getT2AddrModeImm8OpValue";
197 let DecoderMethod = "DecodeT2AddrModeImm8";
198 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
202 // t2addrmode_imm8 := reg +/- imm8
203 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
204 class T2AddrMode_Imm8 : MemOperand,
205 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
206 let EncoderMethod = "getT2AddrModeImm8OpValue";
207 let DecoderMethod = "DecodeT2AddrModeImm8";
208 let ParserMatchClass = MemImm8OffsetAsmOperand;
209 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
212 def t2addrmode_imm8 : T2AddrMode_Imm8 {
213 let PrintMethod = "printT2AddrModeImm8Operand<false>";
216 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
217 let PrintMethod = "printT2AddrModeImm8Operand<true>";
220 def t2am_imm8_offset : MemOperand,
221 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
222 [], [SDNPWantRoot]> {
223 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
224 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
225 let DecoderMethod = "DecodeT2Imm8";
228 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
229 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
230 class T2AddrMode_Imm8s4 : MemOperand {
231 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
232 let DecoderMethod = "DecodeT2AddrModeImm8s4";
233 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
234 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
237 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
238 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
241 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
242 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
245 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
246 def t2am_imm8s4_offset : MemOperand {
247 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
248 let EncoderMethod = "getT2Imm8s4OpValue";
249 let DecoderMethod = "DecodeT2Imm8S4";
252 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
253 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
254 let Name = "MemImm0_1020s4Offset";
256 def t2addrmode_imm0_1020s4 : MemOperand,
257 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
258 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
259 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
260 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
261 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
262 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
265 // t2addrmode_so_reg := reg + (reg << imm2)
266 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
267 def t2addrmode_so_reg : MemOperand,
268 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
269 let PrintMethod = "printT2AddrModeSoRegOperand";
270 let EncoderMethod = "getT2AddrModeSORegOpValue";
271 let DecoderMethod = "DecodeT2AddrModeSOReg";
272 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
273 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
276 // Addresses for the TBB/TBH instructions.
277 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
278 def addrmode_tbb : MemOperand {
279 let PrintMethod = "printAddrModeTBB";
280 let ParserMatchClass = addrmode_tbb_asmoperand;
281 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
283 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
284 def addrmode_tbh : MemOperand {
285 let PrintMethod = "printAddrModeTBH";
286 let ParserMatchClass = addrmode_tbh_asmoperand;
287 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
290 //===----------------------------------------------------------------------===//
291 // Multiclass helpers...
295 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
296 string opc, string asm, list<dag> pattern>
297 : T2I<oops, iops, itin, opc, asm, pattern> {
302 let Inst{26} = imm{11};
303 let Inst{14-12} = imm{10-8};
304 let Inst{7-0} = imm{7-0};
308 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : T2sI<oops, iops, itin, opc, asm, pattern> {
316 let Inst{26} = imm{11};
317 let Inst{14-12} = imm{10-8};
318 let Inst{7-0} = imm{7-0};
321 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
322 string opc, string asm, list<dag> pattern>
323 : T2I<oops, iops, itin, opc, asm, pattern> {
327 let Inst{19-16} = Rn;
328 let Inst{26} = imm{11};
329 let Inst{14-12} = imm{10-8};
330 let Inst{7-0} = imm{7-0};
334 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2I<oops, iops, itin, opc, asm, pattern> {
341 let Inst{3-0} = ShiftedRm{3-0};
342 let Inst{5-4} = ShiftedRm{6-5};
343 let Inst{14-12} = ShiftedRm{11-9};
344 let Inst{7-6} = ShiftedRm{8-7};
347 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : T2sI<oops, iops, itin, opc, asm, pattern> {
354 let Inst{3-0} = ShiftedRm{3-0};
355 let Inst{5-4} = ShiftedRm{6-5};
356 let Inst{14-12} = ShiftedRm{11-9};
357 let Inst{7-6} = ShiftedRm{8-7};
360 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : T2I<oops, iops, itin, opc, asm, pattern> {
366 let Inst{19-16} = Rn;
367 let Inst{3-0} = ShiftedRm{3-0};
368 let Inst{5-4} = ShiftedRm{6-5};
369 let Inst{14-12} = ShiftedRm{11-9};
370 let Inst{7-6} = ShiftedRm{8-7};
373 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
374 string opc, string asm, list<dag> pattern>
375 : T2I<oops, iops, itin, opc, asm, pattern> {
383 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
384 string opc, string asm, list<dag> pattern>
385 : T2sI<oops, iops, itin, opc, asm, pattern> {
393 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
394 string opc, string asm, list<dag> pattern>
395 : T2I<oops, iops, itin, opc, asm, pattern> {
399 let Inst{19-16} = Rn;
404 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
405 string opc, string asm, list<dag> pattern>
406 : T2I<oops, iops, itin, opc, asm, pattern> {
412 let Inst{19-16} = Rn;
413 let Inst{26} = imm{11};
414 let Inst{14-12} = imm{10-8};
415 let Inst{7-0} = imm{7-0};
418 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
419 string opc, string asm, list<dag> pattern>
420 : T2sI<oops, iops, itin, opc, asm, pattern> {
426 let Inst{19-16} = Rn;
427 let Inst{26} = imm{11};
428 let Inst{14-12} = imm{10-8};
429 let Inst{7-0} = imm{7-0};
432 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
433 string opc, string asm, list<dag> pattern>
434 : T2I<oops, iops, itin, opc, asm, pattern> {
441 let Inst{14-12} = imm{4-2};
442 let Inst{7-6} = imm{1-0};
445 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
446 string opc, string asm, list<dag> pattern>
447 : T2sI<oops, iops, itin, opc, asm, pattern> {
454 let Inst{14-12} = imm{4-2};
455 let Inst{7-6} = imm{1-0};
458 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
459 string opc, string asm, list<dag> pattern>
460 : T2I<oops, iops, itin, opc, asm, pattern> {
466 let Inst{19-16} = Rn;
470 class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
471 string asm, list<dag> pattern>
472 : T2XI<oops, iops, itin, asm, pattern> {
478 let Inst{19-16} = Rn;
482 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
483 string opc, string asm, list<dag> pattern>
484 : T2sI<oops, iops, itin, opc, asm, pattern> {
490 let Inst{19-16} = Rn;
494 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : T2I<oops, iops, itin, opc, asm, pattern> {
502 let Inst{19-16} = Rn;
503 let Inst{3-0} = ShiftedRm{3-0};
504 let Inst{5-4} = ShiftedRm{6-5};
505 let Inst{14-12} = ShiftedRm{11-9};
506 let Inst{7-6} = ShiftedRm{8-7};
509 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
510 string opc, string asm, list<dag> pattern>
511 : T2sI<oops, iops, itin, opc, asm, pattern> {
517 let Inst{19-16} = Rn;
518 let Inst{3-0} = ShiftedRm{3-0};
519 let Inst{5-4} = ShiftedRm{6-5};
520 let Inst{14-12} = ShiftedRm{11-9};
521 let Inst{7-6} = ShiftedRm{8-7};
524 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
525 string opc, string asm, list<dag> pattern>
526 : T2I<oops, iops, itin, opc, asm, pattern> {
532 let Inst{19-16} = Rn;
533 let Inst{15-12} = Ra;
538 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
539 dag oops, dag iops, InstrItinClass itin,
540 string opc, string asm, list<dag> pattern>
541 : T2I<oops, iops, itin, opc, asm, pattern> {
547 let Inst{31-23} = 0b111110111;
548 let Inst{22-20} = opc22_20;
549 let Inst{19-16} = Rn;
550 let Inst{15-12} = RdLo;
551 let Inst{11-8} = RdHi;
552 let Inst{7-4} = opc7_4;
555 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
556 dag oops, dag iops, InstrItinClass itin,
557 string opc, string asm, list<dag> pattern>
558 : T2I<oops, iops, itin, opc, asm, pattern> {
564 let Inst{31-23} = 0b111110111;
565 let Inst{22-20} = opc22_20;
566 let Inst{19-16} = Rn;
567 let Inst{15-12} = RdLo;
568 let Inst{11-8} = RdHi;
569 let Inst{7-4} = opc7_4;
574 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
575 /// binary operation that produces a value. These are predicable and can be
576 /// changed to modify CPSR.
577 multiclass T2I_bin_irs<bits<4> opcod, string opc,
578 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
579 SDPatternOperator opnode, bit Commutable = 0,
582 def ri : T2sTwoRegImm<
583 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
584 opc, "\t$Rd, $Rn, $imm",
585 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
586 Sched<[WriteALU, ReadALU]> {
587 let Inst{31-27} = 0b11110;
589 let Inst{24-21} = opcod;
593 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
594 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
595 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
596 Sched<[WriteALU, ReadALU, ReadALU]> {
597 let isCommutable = Commutable;
598 let Inst{31-27} = 0b11101;
599 let Inst{26-25} = 0b01;
600 let Inst{24-21} = opcod;
601 let Inst{14-12} = 0b000; // imm3
602 let Inst{7-6} = 0b00; // imm2
603 let Inst{5-4} = 0b00; // type
606 def rs : T2sTwoRegShiftedReg<
607 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
608 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
609 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
610 Sched<[WriteALUsi, ReadALU]> {
611 let Inst{31-27} = 0b11101;
612 let Inst{26-25} = 0b01;
613 let Inst{24-21} = opcod;
615 // Assembly aliases for optional destination operand when it's the same
616 // as the source operand.
617 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
618 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
619 t2_so_imm:$imm, pred:$p,
621 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
622 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
625 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
626 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
627 t2_so_reg:$shift, pred:$p,
631 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
632 // the ".w" suffix to indicate that they are wide.
633 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
634 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
635 SDPatternOperator opnode, bit Commutable = 0> :
636 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
637 // Assembler aliases w/ the ".w" suffix.
638 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
639 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
641 // Assembler aliases w/o the ".w" suffix.
642 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
643 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
645 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
646 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
647 pred:$p, cc_out:$s)>;
649 // and with the optional destination operand, too.
650 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
651 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
652 pred:$p, cc_out:$s)>;
653 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
654 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
656 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
657 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
658 pred:$p, cc_out:$s)>;
661 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
662 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
663 /// it is equivalent to the T2I_bin_irs counterpart.
664 multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {
666 def ri : T2sTwoRegImm<
667 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
668 opc, ".w\t$Rd, $Rn, $imm",
669 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
670 Sched<[WriteALU, ReadALU]> {
671 let Inst{31-27} = 0b11110;
673 let Inst{24-21} = opcod;
677 def rr : T2sThreeReg<
678 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
679 opc, "\t$Rd, $Rn, $Rm",
680 [/* For disassembly only; pattern left blank */]>,
681 Sched<[WriteALU, ReadALU, ReadALU]> {
682 let Inst{31-27} = 0b11101;
683 let Inst{26-25} = 0b01;
684 let Inst{24-21} = opcod;
685 let Inst{14-12} = 0b000; // imm3
686 let Inst{7-6} = 0b00; // imm2
687 let Inst{5-4} = 0b00; // type
690 def rs : T2sTwoRegShiftedReg<
691 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
692 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
693 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
694 Sched<[WriteALUsi, ReadALU]> {
695 let Inst{31-27} = 0b11101;
696 let Inst{26-25} = 0b01;
697 let Inst{24-21} = opcod;
701 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
702 /// instruction modifies the CPSR register.
704 /// These opcodes will be converted to the real non-S opcodes by
705 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
706 let hasPostISelHook = 1, Defs = [CPSR] in {
707 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
708 InstrItinClass iis, SDNode opnode,
709 bit Commutable = 0> {
711 def ri : t2PseudoInst<(outs rGPR:$Rd),
712 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
714 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
716 Sched<[WriteALU, ReadALU]>;
718 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
720 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
722 Sched<[WriteALU, ReadALU, ReadALU]> {
723 let isCommutable = Commutable;
726 def rs : t2PseudoInst<(outs rGPR:$Rd),
727 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
729 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
730 t2_so_reg:$ShiftedRm))]>,
731 Sched<[WriteALUsi, ReadALUsr]>;
735 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
736 /// operands are reversed.
737 let hasPostISelHook = 1, Defs = [CPSR] in {
738 multiclass T2I_rbin_s_is<SDNode opnode> {
740 def ri : t2PseudoInst<(outs rGPR:$Rd),
741 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
743 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
745 Sched<[WriteALU, ReadALU]>;
747 def rs : t2PseudoInst<(outs rGPR:$Rd),
748 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
750 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
752 Sched<[WriteALUsi, ReadALU]>;
756 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
757 /// patterns for a binary operation that produces a value.
758 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
759 bit Commutable = 0> {
761 // The register-immediate version is re-materializable. This is useful
762 // in particular for taking the address of a local.
763 let isReMaterializable = 1 in {
764 def ri : T2sTwoRegImm<
765 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
766 opc, ".w\t$Rd, $Rn, $imm",
767 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
768 Sched<[WriteALU, ReadALU]> {
769 let Inst{31-27} = 0b11110;
772 let Inst{23-21} = op23_21;
778 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
779 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
780 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
781 Sched<[WriteALU, ReadALU]> {
785 let Inst{31-27} = 0b11110;
786 let Inst{26} = imm{11};
787 let Inst{25-24} = 0b10;
788 let Inst{23-21} = op23_21;
789 let Inst{20} = 0; // The S bit.
790 let Inst{19-16} = Rn;
792 let Inst{14-12} = imm{10-8};
794 let Inst{7-0} = imm{7-0};
797 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
798 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
799 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
800 Sched<[WriteALU, ReadALU, ReadALU]> {
801 let isCommutable = Commutable;
802 let Inst{31-27} = 0b11101;
803 let Inst{26-25} = 0b01;
805 let Inst{23-21} = op23_21;
806 let Inst{14-12} = 0b000; // imm3
807 let Inst{7-6} = 0b00; // imm2
808 let Inst{5-4} = 0b00; // type
811 def rs : T2sTwoRegShiftedReg<
812 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
813 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
814 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
815 Sched<[WriteALUsi, ReadALU]> {
816 let Inst{31-27} = 0b11101;
817 let Inst{26-25} = 0b01;
819 let Inst{23-21} = op23_21;
823 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
824 /// for a binary operation that produces a value and use the carry
825 /// bit. It's not predicable.
826 let Defs = [CPSR], Uses = [CPSR] in {
827 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
828 bit Commutable = 0> {
830 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
831 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
832 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
833 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
834 let Inst{31-27} = 0b11110;
836 let Inst{24-21} = opcod;
840 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
841 opc, ".w\t$Rd, $Rn, $Rm",
842 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
843 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
844 let isCommutable = Commutable;
845 let Inst{31-27} = 0b11101;
846 let Inst{26-25} = 0b01;
847 let Inst{24-21} = opcod;
848 let Inst{14-12} = 0b000; // imm3
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
853 def rs : T2sTwoRegShiftedReg<
854 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
855 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
856 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
857 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
858 let Inst{31-27} = 0b11101;
859 let Inst{26-25} = 0b01;
860 let Inst{24-21} = opcod;
865 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
866 // rotate operation that produces a value.
867 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
869 def ri : T2sTwoRegShiftImm<
870 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
871 opc, ".w\t$Rd, $Rm, $imm",
872 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
874 let Inst{31-27} = 0b11101;
875 let Inst{26-21} = 0b010010;
876 let Inst{19-16} = 0b1111; // Rn
877 let Inst{5-4} = opcod;
880 def rr : T2sThreeReg<
881 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
882 opc, ".w\t$Rd, $Rn, $Rm",
883 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
885 let Inst{31-27} = 0b11111;
886 let Inst{26-23} = 0b0100;
887 let Inst{22-21} = opcod;
888 let Inst{15-12} = 0b1111;
889 let Inst{7-4} = 0b0000;
892 // Optional destination register
893 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
894 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
896 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
897 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
900 // Assembler aliases w/o the ".w" suffix.
901 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
902 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
904 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
905 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
908 // and with the optional destination operand, too.
909 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
910 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
912 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
913 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
917 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
918 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
919 /// a explicit result, only implicitly set CPSR.
920 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
921 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
922 SDPatternOperator opnode> {
923 let isCompare = 1, Defs = [CPSR] in {
925 def ri : T2OneRegCmpImm<
926 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
927 opc, ".w\t$Rn, $imm",
928 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
929 let Inst{31-27} = 0b11110;
931 let Inst{24-21} = opcod;
932 let Inst{20} = 1; // The S bit.
934 let Inst{11-8} = 0b1111; // Rd
937 def rr : T2TwoRegCmp<
938 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
940 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
941 let Inst{31-27} = 0b11101;
942 let Inst{26-25} = 0b01;
943 let Inst{24-21} = opcod;
944 let Inst{20} = 1; // The S bit.
945 let Inst{14-12} = 0b000; // imm3
946 let Inst{11-8} = 0b1111; // Rd
947 let Inst{7-6} = 0b00; // imm2
948 let Inst{5-4} = 0b00; // type
951 def rs : T2OneRegCmpShiftedReg<
952 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
953 opc, ".w\t$Rn, $ShiftedRm",
954 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
955 Sched<[WriteCMPsi]> {
956 let Inst{31-27} = 0b11101;
957 let Inst{26-25} = 0b01;
958 let Inst{24-21} = opcod;
959 let Inst{20} = 1; // The S bit.
960 let Inst{11-8} = 0b1111; // Rd
964 // Assembler aliases w/o the ".w" suffix.
965 // No alias here for 'rr' version as not all instantiations of this
966 // multiclass want one (CMP in particular, does not).
967 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
968 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
969 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
970 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
973 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
974 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
975 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
977 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
978 opc, ".w\t$Rt, $addr",
979 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
982 let Inst{31-25} = 0b1111100;
983 let Inst{24} = signed;
985 let Inst{22-21} = opcod;
986 let Inst{20} = 1; // load
987 let Inst{19-16} = addr{16-13}; // Rn
988 let Inst{15-12} = Rt;
989 let Inst{11-0} = addr{11-0}; // imm
991 let DecoderMethod = "DecodeT2LoadImm12";
993 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
995 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
998 let Inst{31-27} = 0b11111;
999 let Inst{26-25} = 0b00;
1000 let Inst{24} = signed;
1002 let Inst{22-21} = opcod;
1003 let Inst{20} = 1; // load
1004 let Inst{19-16} = addr{12-9}; // Rn
1005 let Inst{15-12} = Rt;
1007 // Offset: index==TRUE, wback==FALSE
1008 let Inst{10} = 1; // The P bit.
1009 let Inst{9} = addr{8}; // U
1010 let Inst{8} = 0; // The W bit.
1011 let Inst{7-0} = addr{7-0}; // imm
1013 let DecoderMethod = "DecodeT2LoadImm8";
1015 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1016 opc, ".w\t$Rt, $addr",
1017 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
1018 let Inst{31-27} = 0b11111;
1019 let Inst{26-25} = 0b00;
1020 let Inst{24} = signed;
1022 let Inst{22-21} = opcod;
1023 let Inst{20} = 1; // load
1024 let Inst{11-6} = 0b000000;
1027 let Inst{15-12} = Rt;
1030 let Inst{19-16} = addr{9-6}; // Rn
1031 let Inst{3-0} = addr{5-2}; // Rm
1032 let Inst{5-4} = addr{1-0}; // imm
1034 let DecoderMethod = "DecodeT2LoadShift";
1037 // pci variant is very similar to i12, but supports negative offsets
1039 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1040 opc, ".w\t$Rt, $addr",
1041 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1042 let isReMaterializable = 1;
1043 let Inst{31-27} = 0b11111;
1044 let Inst{26-25} = 0b00;
1045 let Inst{24} = signed;
1046 let Inst{22-21} = opcod;
1047 let Inst{20} = 1; // load
1048 let Inst{19-16} = 0b1111; // Rn
1051 let Inst{15-12} = Rt{3-0};
1054 let Inst{23} = addr{12}; // add = (U == '1')
1055 let Inst{11-0} = addr{11-0};
1057 let DecoderMethod = "DecodeT2LoadLabel";
1061 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1062 multiclass T2I_st<bits<2> opcod, string opc,
1063 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1065 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1066 opc, ".w\t$Rt, $addr",
1067 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1068 let Inst{31-27} = 0b11111;
1069 let Inst{26-23} = 0b0001;
1070 let Inst{22-21} = opcod;
1071 let Inst{20} = 0; // !load
1074 let Inst{15-12} = Rt;
1077 let addr{12} = 1; // add = TRUE
1078 let Inst{19-16} = addr{16-13}; // Rn
1079 let Inst{23} = addr{12}; // U
1080 let Inst{11-0} = addr{11-0}; // imm
1082 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1083 opc, "\t$Rt, $addr",
1084 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1085 let Inst{31-27} = 0b11111;
1086 let Inst{26-23} = 0b0000;
1087 let Inst{22-21} = opcod;
1088 let Inst{20} = 0; // !load
1090 // Offset: index==TRUE, wback==FALSE
1091 let Inst{10} = 1; // The P bit.
1092 let Inst{8} = 0; // The W bit.
1095 let Inst{15-12} = Rt;
1098 let Inst{19-16} = addr{12-9}; // Rn
1099 let Inst{9} = addr{8}; // U
1100 let Inst{7-0} = addr{7-0}; // imm
1102 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1103 opc, ".w\t$Rt, $addr",
1104 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1105 let Inst{31-27} = 0b11111;
1106 let Inst{26-23} = 0b0000;
1107 let Inst{22-21} = opcod;
1108 let Inst{20} = 0; // !load
1109 let Inst{11-6} = 0b000000;
1112 let Inst{15-12} = Rt;
1115 let Inst{19-16} = addr{9-6}; // Rn
1116 let Inst{3-0} = addr{5-2}; // Rm
1117 let Inst{5-4} = addr{1-0}; // imm
1121 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1122 /// register and one whose operand is a register rotated by 8/16/24.
1123 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1124 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1125 opc, ".w\t$Rd, $Rm$rot",
1126 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1127 Requires<[IsThumb2]> {
1128 let Inst{31-27} = 0b11111;
1129 let Inst{26-23} = 0b0100;
1130 let Inst{22-20} = opcod;
1131 let Inst{19-16} = 0b1111; // Rn
1132 let Inst{15-12} = 0b1111;
1136 let Inst{5-4} = rot{1-0}; // rotate
1139 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1140 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1141 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1142 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1143 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1144 Requires<[HasT2ExtractPack, IsThumb2]> {
1146 let Inst{31-27} = 0b11111;
1147 let Inst{26-23} = 0b0100;
1148 let Inst{22-20} = opcod;
1149 let Inst{19-16} = 0b1111; // Rn
1150 let Inst{15-12} = 0b1111;
1152 let Inst{5-4} = rot;
1155 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1157 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1158 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1159 opc, "\t$Rd, $Rm$rot", []>,
1160 Requires<[IsThumb2, HasT2ExtractPack]> {
1162 let Inst{31-27} = 0b11111;
1163 let Inst{26-23} = 0b0100;
1164 let Inst{22-20} = opcod;
1165 let Inst{19-16} = 0b1111; // Rn
1166 let Inst{15-12} = 0b1111;
1168 let Inst{5-4} = rot;
1171 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1172 /// register and one whose operand is a register rotated by 8/16/24.
1173 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1174 : T2ThreeReg<(outs rGPR:$Rd),
1175 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1176 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1177 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1178 Requires<[HasT2ExtractPack, IsThumb2]> {
1180 let Inst{31-27} = 0b11111;
1181 let Inst{26-23} = 0b0100;
1182 let Inst{22-20} = opcod;
1183 let Inst{15-12} = 0b1111;
1185 let Inst{5-4} = rot;
1188 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1189 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1190 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1191 Requires<[HasT2ExtractPack, IsThumb2]> {
1193 let Inst{31-27} = 0b11111;
1194 let Inst{26-23} = 0b0100;
1195 let Inst{22-20} = opcod;
1196 let Inst{15-12} = 0b1111;
1198 let Inst{5-4} = rot;
1201 //===----------------------------------------------------------------------===//
1203 //===----------------------------------------------------------------------===//
1205 //===----------------------------------------------------------------------===//
1206 // Miscellaneous Instructions.
1209 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1210 string asm, list<dag> pattern>
1211 : T2XI<oops, iops, itin, asm, pattern> {
1215 let Inst{11-8} = Rd;
1216 let Inst{26} = label{11};
1217 let Inst{14-12} = label{10-8};
1218 let Inst{7-0} = label{7-0};
1221 // LEApcrel - Load a pc-relative address into a register without offending the
1223 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1224 (ins t2adrlabel:$addr, pred:$p),
1225 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1226 Sched<[WriteALU, ReadALU]> {
1227 let Inst{31-27} = 0b11110;
1228 let Inst{25-24} = 0b10;
1229 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1232 let Inst{19-16} = 0b1111; // Rn
1237 let Inst{11-8} = Rd;
1238 let Inst{23} = addr{12};
1239 let Inst{21} = addr{12};
1240 let Inst{26} = addr{11};
1241 let Inst{14-12} = addr{10-8};
1242 let Inst{7-0} = addr{7-0};
1244 let DecoderMethod = "DecodeT2Adr";
1247 let hasSideEffects = 0, isReMaterializable = 1 in
1248 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1249 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1250 let hasSideEffects = 1 in
1251 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1252 (ins i32imm:$label, pred:$p),
1254 []>, Sched<[WriteALU, ReadALU]>;
1257 //===----------------------------------------------------------------------===//
1258 // Load / store Instructions.
1262 let canFoldAsLoad = 1, isReMaterializable = 1 in
1263 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
1265 // Loads with zero extension
1266 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1267 GPRnopc, zextloadi16>;
1268 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1269 GPRnopc, zextloadi8>;
1271 // Loads with sign extension
1272 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1273 GPRnopc, sextloadi16>;
1274 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1275 GPRnopc, sextloadi8>;
1277 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1279 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1280 (ins t2addrmode_imm8s4:$addr),
1281 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1282 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1284 // zextload i1 -> zextload i8
1285 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1286 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1287 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1288 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1289 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1290 (t2LDRBs t2addrmode_so_reg:$addr)>;
1291 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1292 (t2LDRBpci tconstpool:$addr)>;
1294 // extload -> zextload
1295 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1297 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1298 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1299 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1300 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1301 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1302 (t2LDRBs t2addrmode_so_reg:$addr)>;
1303 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1304 (t2LDRBpci tconstpool:$addr)>;
1306 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1307 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1308 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1309 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1310 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1311 (t2LDRBs t2addrmode_so_reg:$addr)>;
1312 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1313 (t2LDRBpci tconstpool:$addr)>;
1315 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1316 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1317 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1318 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1319 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1320 (t2LDRHs t2addrmode_so_reg:$addr)>;
1321 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1322 (t2LDRHpci tconstpool:$addr)>;
1324 // FIXME: The destination register of the loads and stores can't be PC, but
1325 // can be SP. We need another regclass (similar to rGPR) to represent
1326 // that. Not a pressing issue since these are selected manually,
1331 let mayLoad = 1, hasSideEffects = 0 in {
1332 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1333 (ins t2addrmode_imm8_pre:$addr),
1334 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1335 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1337 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1338 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1339 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1340 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1342 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1343 (ins t2addrmode_imm8_pre:$addr),
1344 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1345 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1347 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1348 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1349 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1350 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1352 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1353 (ins t2addrmode_imm8_pre:$addr),
1354 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1355 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1357 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1358 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1359 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1360 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1362 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1363 (ins t2addrmode_imm8_pre:$addr),
1364 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1365 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1368 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1369 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1370 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1371 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1373 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1374 (ins t2addrmode_imm8_pre:$addr),
1375 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1376 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1379 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1380 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1381 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1382 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1383 } // mayLoad = 1, hasSideEffects = 0
1385 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1386 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1387 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1388 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1389 "\t$Rt, $addr", []> {
1392 let Inst{31-27} = 0b11111;
1393 let Inst{26-25} = 0b00;
1394 let Inst{24} = signed;
1396 let Inst{22-21} = type;
1397 let Inst{20} = 1; // load
1398 let Inst{19-16} = addr{12-9};
1399 let Inst{15-12} = Rt;
1401 let Inst{10-8} = 0b110; // PUW.
1402 let Inst{7-0} = addr{7-0};
1404 let DecoderMethod = "DecodeT2LoadT";
1407 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1408 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1409 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1410 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1411 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1413 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
1414 string opc, string asm, list<dag> pattern>
1415 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
1416 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
1420 let Inst{31-27} = 0b11101;
1421 let Inst{26-24} = 0b000;
1422 let Inst{23-20} = bits23_20;
1423 let Inst{11-6} = 0b111110;
1424 let Inst{5-4} = bit54;
1425 let Inst{3-0} = 0b1111;
1427 // Encode instruction operands
1428 let Inst{19-16} = addr;
1429 let Inst{15-12} = Rt;
1432 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1433 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>;
1434 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1435 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>;
1436 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1437 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>;
1440 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;
1441 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1442 rGPR, truncstorei8>;
1443 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1444 rGPR, truncstorei16>;
1447 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1448 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1449 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1450 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1454 let mayStore = 1, hasSideEffects = 0 in {
1455 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1456 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1457 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1458 "str", "\t$Rt, $addr!",
1459 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1461 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1462 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1463 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1464 "strh", "\t$Rt, $addr!",
1465 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1467 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1468 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1469 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1470 "strb", "\t$Rt, $addr!",
1471 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1472 } // mayStore = 1, hasSideEffects = 0
1474 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1475 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1476 t2am_imm8_offset:$offset),
1477 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1478 "str", "\t$Rt, $Rn$offset",
1479 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1480 [(set GPRnopc:$Rn_wb,
1481 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1482 t2am_imm8_offset:$offset))]>;
1484 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1485 (ins rGPR:$Rt, addr_offset_none:$Rn,
1486 t2am_imm8_offset:$offset),
1487 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1488 "strh", "\t$Rt, $Rn$offset",
1489 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1490 [(set GPRnopc:$Rn_wb,
1491 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1492 t2am_imm8_offset:$offset))]>;
1494 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1495 (ins rGPR:$Rt, addr_offset_none:$Rn,
1496 t2am_imm8_offset:$offset),
1497 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1498 "strb", "\t$Rt, $Rn$offset",
1499 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1500 [(set GPRnopc:$Rn_wb,
1501 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1502 t2am_imm8_offset:$offset))]>;
1504 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1505 // put the patterns on the instruction definitions directly as ISel wants
1506 // the address base and offset to be separate operands, not a single
1507 // complex operand like we represent the instructions themselves. The
1508 // pseudos map between the two.
1509 let usesCustomInserter = 1,
1510 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1511 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1512 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1514 [(set GPRnopc:$Rn_wb,
1515 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1516 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1517 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1519 [(set GPRnopc:$Rn_wb,
1520 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1521 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1522 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1524 [(set GPRnopc:$Rn_wb,
1525 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1528 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1530 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1531 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1532 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1533 "\t$Rt, $addr", []> {
1534 let Inst{31-27} = 0b11111;
1535 let Inst{26-25} = 0b00;
1536 let Inst{24} = 0; // not signed
1538 let Inst{22-21} = type;
1539 let Inst{20} = 0; // store
1541 let Inst{10-8} = 0b110; // PUW
1545 let Inst{15-12} = Rt;
1546 let Inst{19-16} = addr{12-9};
1547 let Inst{7-0} = addr{7-0};
1550 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1551 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1552 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1554 // ldrd / strd pre / post variants
1557 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1558 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1559 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1560 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1564 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1565 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1566 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1567 "$addr.base = $wb", []>;
1570 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1571 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1572 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1573 "$addr.base = $wb", []> {
1574 let DecoderMethod = "DecodeT2STRDPreInstruction";
1578 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1579 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1580 t2am_imm8s4_offset:$imm),
1581 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1582 "$addr.base = $wb", []>;
1584 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
1585 string opc, string asm, list<dag> pattern>
1586 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
1587 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
1591 let Inst{31-27} = 0b11101;
1592 let Inst{26-20} = 0b0001100;
1593 let Inst{11-6} = 0b111110;
1594 let Inst{5-4} = bit54;
1595 let Inst{3-0} = 0b1111;
1597 // Encode instruction operands
1598 let Inst{19-16} = addr;
1599 let Inst{15-12} = Rt;
1602 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1603 "stl", "\t$Rt, $addr", []>;
1604 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1605 "stlb", "\t$Rt, $addr", []>;
1606 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1607 "stlh", "\t$Rt, $addr", []>;
1609 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1610 // data/instruction access.
1611 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1612 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1613 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1615 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1617 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1618 Sched<[WritePreLd]> {
1619 let Inst{31-25} = 0b1111100;
1620 let Inst{24} = instr;
1623 let Inst{21} = write;
1625 let Inst{15-12} = 0b1111;
1628 let Inst{19-16} = addr{16-13}; // Rn
1629 let Inst{11-0} = addr{11-0}; // imm12
1631 let DecoderMethod = "DecodeT2LoadImm12";
1634 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1636 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1637 Sched<[WritePreLd]> {
1638 let Inst{31-25} = 0b1111100;
1639 let Inst{24} = instr;
1640 let Inst{23} = 0; // U = 0
1642 let Inst{21} = write;
1644 let Inst{15-12} = 0b1111;
1645 let Inst{11-8} = 0b1100;
1648 let Inst{19-16} = addr{12-9}; // Rn
1649 let Inst{7-0} = addr{7-0}; // imm8
1651 let DecoderMethod = "DecodeT2LoadImm8";
1654 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1656 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1657 Sched<[WritePreLd]> {
1658 let Inst{31-25} = 0b1111100;
1659 let Inst{24} = instr;
1660 let Inst{23} = 0; // add = TRUE for T1
1662 let Inst{21} = write;
1664 let Inst{15-12} = 0b1111;
1665 let Inst{11-6} = 0b000000;
1668 let Inst{19-16} = addr{9-6}; // Rn
1669 let Inst{3-0} = addr{5-2}; // Rm
1670 let Inst{5-4} = addr{1-0}; // imm2
1672 let DecoderMethod = "DecodeT2LoadShift";
1676 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1677 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1678 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1680 // pci variant is very similar to i12, but supports negative offsets
1681 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1682 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1683 IIC_Preload, opc, "\t$addr",
1684 [(ARMPreload (ARMWrapper tconstpool:$addr),
1685 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1686 let Inst{31-25} = 0b1111100;
1687 let Inst{24} = inst;
1688 let Inst{22-20} = 0b001;
1689 let Inst{19-16} = 0b1111;
1690 let Inst{15-12} = 0b1111;
1693 let Inst{23} = addr{12}; // add = (U == '1')
1694 let Inst{11-0} = addr{11-0}; // imm12
1696 let DecoderMethod = "DecodeT2LoadLabel";
1699 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1700 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1702 //===----------------------------------------------------------------------===//
1703 // Load / store multiple Instructions.
1706 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1707 InstrItinClass itin_upd, bit L_bit> {
1709 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1710 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1714 let Inst{31-27} = 0b11101;
1715 let Inst{26-25} = 0b00;
1716 let Inst{24-23} = 0b01; // Increment After
1718 let Inst{21} = 0; // No writeback
1719 let Inst{20} = L_bit;
1720 let Inst{19-16} = Rn;
1721 let Inst{15-0} = regs;
1724 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1725 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1729 let Inst{31-27} = 0b11101;
1730 let Inst{26-25} = 0b00;
1731 let Inst{24-23} = 0b01; // Increment After
1733 let Inst{21} = 1; // Writeback
1734 let Inst{20} = L_bit;
1735 let Inst{19-16} = Rn;
1736 let Inst{15-0} = regs;
1739 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1740 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1744 let Inst{31-27} = 0b11101;
1745 let Inst{26-25} = 0b00;
1746 let Inst{24-23} = 0b10; // Decrement Before
1748 let Inst{21} = 0; // No writeback
1749 let Inst{20} = L_bit;
1750 let Inst{19-16} = Rn;
1751 let Inst{15-0} = regs;
1754 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1755 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1759 let Inst{31-27} = 0b11101;
1760 let Inst{26-25} = 0b00;
1761 let Inst{24-23} = 0b10; // Decrement Before
1763 let Inst{21} = 1; // Writeback
1764 let Inst{20} = L_bit;
1765 let Inst{19-16} = Rn;
1766 let Inst{15-0} = regs;
1770 let hasSideEffects = 0 in {
1772 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1773 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1775 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1776 InstrItinClass itin_upd, bit L_bit> {
1778 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1779 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1783 let Inst{31-27} = 0b11101;
1784 let Inst{26-25} = 0b00;
1785 let Inst{24-23} = 0b01; // Increment After
1787 let Inst{21} = 0; // No writeback
1788 let Inst{20} = L_bit;
1789 let Inst{19-16} = Rn;
1791 let Inst{14} = regs{14};
1793 let Inst{12-0} = regs{12-0};
1796 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1797 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1801 let Inst{31-27} = 0b11101;
1802 let Inst{26-25} = 0b00;
1803 let Inst{24-23} = 0b01; // Increment After
1805 let Inst{21} = 1; // Writeback
1806 let Inst{20} = L_bit;
1807 let Inst{19-16} = Rn;
1809 let Inst{14} = regs{14};
1811 let Inst{12-0} = regs{12-0};
1814 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1815 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1819 let Inst{31-27} = 0b11101;
1820 let Inst{26-25} = 0b00;
1821 let Inst{24-23} = 0b10; // Decrement Before
1823 let Inst{21} = 0; // No writeback
1824 let Inst{20} = L_bit;
1825 let Inst{19-16} = Rn;
1827 let Inst{14} = regs{14};
1829 let Inst{12-0} = regs{12-0};
1832 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1833 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1837 let Inst{31-27} = 0b11101;
1838 let Inst{26-25} = 0b00;
1839 let Inst{24-23} = 0b10; // Decrement Before
1841 let Inst{21} = 1; // Writeback
1842 let Inst{20} = L_bit;
1843 let Inst{19-16} = Rn;
1845 let Inst{14} = regs{14};
1847 let Inst{12-0} = regs{12-0};
1852 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1853 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1858 //===----------------------------------------------------------------------===//
1859 // Move Instructions.
1862 let hasSideEffects = 0 in
1863 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1864 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1865 let Inst{31-27} = 0b11101;
1866 let Inst{26-25} = 0b01;
1867 let Inst{24-21} = 0b0010;
1868 let Inst{19-16} = 0b1111; // Rn
1869 let Inst{14-12} = 0b000;
1870 let Inst{7-4} = 0b0000;
1872 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1873 pred:$p, zero_reg)>;
1874 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1876 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1879 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1880 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1881 AddedComplexity = 1 in
1882 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1883 "mov", ".w\t$Rd, $imm",
1884 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1885 let Inst{31-27} = 0b11110;
1887 let Inst{24-21} = 0b0010;
1888 let Inst{19-16} = 0b1111; // Rn
1892 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1893 // Use aliases to get that to play nice here.
1894 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1896 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1899 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1900 pred:$p, zero_reg)>;
1901 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1902 pred:$p, zero_reg)>;
1904 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1905 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1906 "movw", "\t$Rd, $imm",
1907 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
1908 Requires<[IsThumb, HasV8MBaseline]> {
1909 let Inst{31-27} = 0b11110;
1911 let Inst{24-21} = 0b0010;
1912 let Inst{20} = 0; // The S bit.
1918 let Inst{11-8} = Rd;
1919 let Inst{19-16} = imm{15-12};
1920 let Inst{26} = imm{11};
1921 let Inst{14-12} = imm{10-8};
1922 let Inst{7-0} = imm{7-0};
1923 let DecoderMethod = "DecodeT2MOVTWInstruction";
1926 def : InstAlias<"mov${p} $Rd, $imm",
1927 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
1928 Requires<[IsThumb, HasV8MBaseline]>;
1930 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1931 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1933 let Constraints = "$src = $Rd" in {
1934 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1935 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1936 "movt", "\t$Rd, $imm",
1938 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1940 Requires<[IsThumb, HasV8MBaseline]> {
1941 let Inst{31-27} = 0b11110;
1943 let Inst{24-21} = 0b0110;
1944 let Inst{20} = 0; // The S bit.
1950 let Inst{11-8} = Rd;
1951 let Inst{19-16} = imm{15-12};
1952 let Inst{26} = imm{11};
1953 let Inst{14-12} = imm{10-8};
1954 let Inst{7-0} = imm{7-0};
1955 let DecoderMethod = "DecodeT2MOVTWInstruction";
1958 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1959 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1960 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
1963 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1965 //===----------------------------------------------------------------------===//
1966 // Extend Instructions.
1971 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1972 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1973 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1974 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1975 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1977 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1978 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1979 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1980 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1981 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1983 // A simple right-shift can also be used in most cases (the exception is the
1984 // SXTH operations with a rotate of 24: there the non-contiguous bits are
1986 def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
1987 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
1988 Requires<[HasT2ExtractPack, IsThumb2]>;
1989 def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
1990 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
1991 Requires<[HasT2ExtractPack, IsThumb2]>;
1995 let AddedComplexity = 16 in {
1996 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1997 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1998 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1999 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2000 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
2001 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2003 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2004 // The transformation should probably be done as a combiner action
2005 // instead so we can include a check for masking back in the upper
2006 // eight bits of the source into the lower eight bits of the result.
2007 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2008 // (t2UXTB16 rGPR:$Src, 3)>,
2009 // Requires<[HasT2ExtractPack, IsThumb2]>;
2010 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2011 (t2UXTB16 rGPR:$Src, 1)>,
2012 Requires<[HasT2ExtractPack, IsThumb2]>;
2014 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
2015 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2016 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
2017 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2018 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
2020 def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
2021 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
2022 Requires<[HasT2ExtractPack, IsThumb2]>;
2023 def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
2024 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
2025 Requires<[HasT2ExtractPack, IsThumb2]>;
2029 //===----------------------------------------------------------------------===//
2030 // Arithmetic Instructions.
2033 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
2034 defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
2036 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2038 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
2039 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
2040 // AdjustInstrPostInstrSelection where we determine whether or not to
2041 // set the "s" bit based on CPSR liveness.
2043 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2044 // support for an optional CPSR definition that corresponds to the DAG
2045 // node's second value. We can then eliminate the implicit def of CPSR.
2046 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;
2047 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;
2049 let hasPostISelHook = 1 in {
2050 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>;
2051 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>;
2055 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;
2057 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2058 // CPSR and the implicit def of CPSR is not needed.
2059 defm t2RSBS : T2I_rbin_s_is <ARMsubc>;
2061 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2062 // The assume-no-carry-in form uses the negation of the input since add/sub
2063 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2064 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2066 // The AddedComplexity preferences the first variant over the others since
2067 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2068 let AddedComplexity = 1 in
2069 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2070 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2071 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2072 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2073 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2074 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2075 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2076 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2078 let AddedComplexity = 1 in
2079 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2080 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2081 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2082 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2083 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2084 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2085 // The with-carry-in form matches bitwise not instead of the negation.
2086 // Effectively, the inverse interpretation of the carry flag already accounts
2087 // for part of the negation.
2088 let AddedComplexity = 1 in
2089 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2090 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2091 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2092 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2093 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2094 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2096 // Select Bytes -- for disassembly only
2098 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2099 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2100 Requires<[IsThumb2, HasDSP]> {
2101 let Inst{31-27} = 0b11111;
2102 let Inst{26-24} = 0b010;
2104 let Inst{22-20} = 0b010;
2105 let Inst{15-12} = 0b1111;
2107 let Inst{6-4} = 0b000;
2110 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2111 // And Miscellaneous operations -- for disassembly only
2112 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2113 list<dag> pat = [/* For disassembly only; pattern left blank */],
2114 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2115 string asm = "\t$Rd, $Rn, $Rm">
2116 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2117 Requires<[IsThumb2, HasDSP]> {
2118 let Inst{31-27} = 0b11111;
2119 let Inst{26-23} = 0b0101;
2120 let Inst{22-20} = op22_20;
2121 let Inst{15-12} = 0b1111;
2122 let Inst{7-4} = op7_4;
2128 let Inst{11-8} = Rd;
2129 let Inst{19-16} = Rn;
2133 // Saturating add/subtract -- for disassembly only
2135 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2136 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2137 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2138 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2139 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2140 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2141 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2142 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2143 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2144 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2145 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2146 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2147 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2148 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2149 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2150 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2151 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2152 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2153 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2154 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2155 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2156 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2158 // Signed/Unsigned add/subtract -- for disassembly only
2160 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2161 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2162 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2163 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2164 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2165 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2166 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2167 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2168 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2169 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2170 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2171 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2173 // Signed/Unsigned halving add/subtract -- for disassembly only
2175 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2176 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2177 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2178 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2179 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2180 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2181 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2182 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2183 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2184 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2185 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2186 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2188 // Helper class for disassembly only
2189 // A6.3.16 & A6.3.17
2190 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2191 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2192 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2193 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2194 let Inst{31-27} = 0b11111;
2195 let Inst{26-24} = 0b011;
2196 let Inst{23} = long;
2197 let Inst{22-20} = op22_20;
2198 let Inst{7-4} = op7_4;
2201 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2202 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2203 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2204 let Inst{31-27} = 0b11111;
2205 let Inst{26-24} = 0b011;
2206 let Inst{23} = long;
2207 let Inst{22-20} = op22_20;
2208 let Inst{7-4} = op7_4;
2211 // Unsigned Sum of Absolute Differences [and Accumulate].
2212 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2213 (ins rGPR:$Rn, rGPR:$Rm),
2214 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2215 Requires<[IsThumb2, HasDSP]> {
2216 let Inst{15-12} = 0b1111;
2218 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2219 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2220 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2221 Requires<[IsThumb2, HasDSP]>;
2223 // Signed/Unsigned saturate.
2224 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2225 string opc, string asm, list<dag> pattern>
2226 : T2I<oops, iops, itin, opc, asm, pattern> {
2232 let Inst{11-8} = Rd;
2233 let Inst{19-16} = Rn;
2234 let Inst{4-0} = sat_imm;
2235 let Inst{21} = sh{5};
2236 let Inst{14-12} = sh{4-2};
2237 let Inst{7-6} = sh{1-0};
2242 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2243 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
2244 Requires<[IsThumb2]> {
2245 let Inst{31-27} = 0b11110;
2246 let Inst{25-22} = 0b1100;
2252 def t2SSAT16: T2SatI<
2253 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2254 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2255 Requires<[IsThumb2, HasDSP]> {
2256 let Inst{31-27} = 0b11110;
2257 let Inst{25-22} = 0b1100;
2260 let Inst{21} = 1; // sh = '1'
2261 let Inst{14-12} = 0b000; // imm3 = '000'
2262 let Inst{7-6} = 0b00; // imm2 = '00'
2263 let Inst{5-4} = 0b00;
2268 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2269 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
2270 Requires<[IsThumb2]> {
2271 let Inst{31-27} = 0b11110;
2272 let Inst{25-22} = 0b1110;
2277 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2279 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2280 Requires<[IsThumb2, HasDSP]> {
2281 let Inst{31-22} = 0b1111001110;
2284 let Inst{21} = 1; // sh = '1'
2285 let Inst{14-12} = 0b000; // imm3 = '000'
2286 let Inst{7-6} = 0b00; // imm2 = '00'
2287 let Inst{5-4} = 0b00;
2290 def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos), (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
2291 def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos), (t2USAT imm0_31:$pos, GPR:$a, 0)>;
2292 def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
2293 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2295 //===----------------------------------------------------------------------===//
2296 // Shift and rotate Instructions.
2299 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31, shl>;
2300 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2301 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;
2302 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, rotr>;
2304 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2305 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2306 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2308 let Uses = [CPSR] in {
2309 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2310 "rrx", "\t$Rd, $Rm",
2311 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2312 let Inst{31-27} = 0b11101;
2313 let Inst{26-25} = 0b01;
2314 let Inst{24-21} = 0b0010;
2315 let Inst{19-16} = 0b1111; // Rn
2316 let Inst{14-12} = 0b000;
2317 let Inst{7-4} = 0b0011;
2321 let isCodeGenOnly = 1, Defs = [CPSR] in {
2322 def t2MOVsrl_flag : T2TwoRegShiftImm<
2323 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2324 "lsrs", ".w\t$Rd, $Rm, #1",
2325 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2327 let Inst{31-27} = 0b11101;
2328 let Inst{26-25} = 0b01;
2329 let Inst{24-21} = 0b0010;
2330 let Inst{20} = 1; // The S bit.
2331 let Inst{19-16} = 0b1111; // Rn
2332 let Inst{5-4} = 0b01; // Shift type.
2333 // Shift amount = Inst{14-12:7-6} = 1.
2334 let Inst{14-12} = 0b000;
2335 let Inst{7-6} = 0b01;
2337 def t2MOVsra_flag : T2TwoRegShiftImm<
2338 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2339 "asrs", ".w\t$Rd, $Rm, #1",
2340 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2342 let Inst{31-27} = 0b11101;
2343 let Inst{26-25} = 0b01;
2344 let Inst{24-21} = 0b0010;
2345 let Inst{20} = 1; // The S bit.
2346 let Inst{19-16} = 0b1111; // Rn
2347 let Inst{5-4} = 0b10; // Shift type.
2348 // Shift amount = Inst{14-12:7-6} = 1.
2349 let Inst{14-12} = 0b000;
2350 let Inst{7-6} = 0b01;
2354 //===----------------------------------------------------------------------===//
2355 // Bitwise Instructions.
2358 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2359 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>;
2360 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2361 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>;
2362 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2363 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>;
2365 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2366 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2367 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2369 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2370 string opc, string asm, list<dag> pattern>
2371 : T2I<oops, iops, itin, opc, asm, pattern> {
2376 let Inst{11-8} = Rd;
2377 let Inst{4-0} = msb{4-0};
2378 let Inst{14-12} = lsb{4-2};
2379 let Inst{7-6} = lsb{1-0};
2382 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2383 string opc, string asm, list<dag> pattern>
2384 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2387 let Inst{19-16} = Rn;
2390 let Constraints = "$src = $Rd" in
2391 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2392 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2393 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2394 let Inst{31-27} = 0b11110;
2395 let Inst{26} = 0; // should be 0.
2397 let Inst{24-20} = 0b10110;
2398 let Inst{19-16} = 0b1111; // Rn
2400 let Inst{5} = 0; // should be 0.
2403 let msb{4-0} = imm{9-5};
2404 let lsb{4-0} = imm{4-0};
2407 def t2SBFX: T2TwoRegBitFI<
2408 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2409 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2410 let Inst{31-27} = 0b11110;
2412 let Inst{24-20} = 0b10100;
2416 def t2UBFX: T2TwoRegBitFI<
2417 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2418 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2419 let Inst{31-27} = 0b11110;
2421 let Inst{24-20} = 0b11100;
2425 // A8.8.247 UDF - Undefined (Encoding T2)
2426 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2427 [(int_arm_undefined imm0_65535:$imm16)]> {
2429 let Inst{31-29} = 0b111;
2430 let Inst{28-27} = 0b10;
2431 let Inst{26-20} = 0b1111111;
2432 let Inst{19-16} = imm16{15-12};
2434 let Inst{14-12} = 0b010;
2435 let Inst{11-0} = imm16{11-0};
2438 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2439 let Constraints = "$src = $Rd" in {
2440 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2441 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2442 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2443 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2444 bf_inv_mask_imm:$imm))]> {
2445 let Inst{31-27} = 0b11110;
2446 let Inst{26} = 0; // should be 0.
2448 let Inst{24-20} = 0b10110;
2450 let Inst{5} = 0; // should be 0.
2453 let msb{4-0} = imm{9-5};
2454 let lsb{4-0} = imm{4-0};
2458 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2459 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2460 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2462 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2463 /// unary operation that produces a value. These are predicable and can be
2464 /// changed to modify CPSR.
2465 multiclass T2I_un_irs<bits<4> opcod, string opc,
2466 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2468 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2470 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2472 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2473 let isAsCheapAsAMove = Cheap;
2474 let isReMaterializable = ReMat;
2475 let isMoveImm = MoveImm;
2476 let Inst{31-27} = 0b11110;
2478 let Inst{24-21} = opcod;
2479 let Inst{19-16} = 0b1111; // Rn
2483 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2484 opc, ".w\t$Rd, $Rm",
2485 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2486 let Inst{31-27} = 0b11101;
2487 let Inst{26-25} = 0b01;
2488 let Inst{24-21} = opcod;
2489 let Inst{19-16} = 0b1111; // Rn
2490 let Inst{14-12} = 0b000; // imm3
2491 let Inst{7-6} = 0b00; // imm2
2492 let Inst{5-4} = 0b00; // type
2495 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2496 opc, ".w\t$Rd, $ShiftedRm",
2497 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2499 let Inst{31-27} = 0b11101;
2500 let Inst{26-25} = 0b01;
2501 let Inst{24-21} = opcod;
2502 let Inst{19-16} = 0b1111; // Rn
2506 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2507 let AddedComplexity = 1 in
2508 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2509 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2512 let AddedComplexity = 1 in
2513 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2514 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2516 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2517 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2518 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2521 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2522 // will match the extended, not the original bitWidth for $src.
2523 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2524 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2527 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2528 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2529 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2530 Requires<[IsThumb2]>;
2532 def : T2Pat<(t2_so_imm_not:$src),
2533 (t2MVNi t2_so_imm_not:$src)>;
2535 //===----------------------------------------------------------------------===//
2536 // Multiply Instructions.
2538 let isCommutable = 1 in
2539 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2540 "mul", "\t$Rd, $Rn, $Rm",
2541 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2542 let Inst{31-27} = 0b11111;
2543 let Inst{26-23} = 0b0110;
2544 let Inst{22-20} = 0b000;
2545 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2546 let Inst{7-4} = 0b0000; // Multiply
2549 def t2MLA: T2FourReg<
2550 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2551 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2552 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2553 Requires<[IsThumb2, UseMulOps]> {
2554 let Inst{31-27} = 0b11111;
2555 let Inst{26-23} = 0b0110;
2556 let Inst{22-20} = 0b000;
2557 let Inst{7-4} = 0b0000; // Multiply
2560 def t2MLS: T2FourReg<
2561 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2562 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2563 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2564 Requires<[IsThumb2, UseMulOps]> {
2565 let Inst{31-27} = 0b11111;
2566 let Inst{26-23} = 0b0110;
2567 let Inst{22-20} = 0b000;
2568 let Inst{7-4} = 0b0001; // Multiply and Subtract
2571 // Extra precision multiplies with low / high results
2572 let hasSideEffects = 0 in {
2573 let isCommutable = 1 in {
2574 def t2SMULL : T2MulLong<0b000, 0b0000,
2575 (outs rGPR:$RdLo, rGPR:$RdHi),
2576 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2577 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2579 def t2UMULL : T2MulLong<0b010, 0b0000,
2580 (outs rGPR:$RdLo, rGPR:$RdHi),
2581 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2582 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2585 // Multiply + accumulate
2586 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2587 (outs rGPR:$RdLo, rGPR:$RdHi),
2588 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2589 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2590 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2592 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2593 (outs rGPR:$RdLo, rGPR:$RdHi),
2594 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2595 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2596 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2598 def t2UMAAL : T2MulLong<0b110, 0b0110,
2599 (outs rGPR:$RdLo, rGPR:$RdHi),
2600 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2601 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2602 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
2603 Requires<[IsThumb2, HasDSP]>;
2606 // Rounding variants of the below included for disassembly only
2608 // Most significant word multiply
2609 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2610 "smmul", "\t$Rd, $Rn, $Rm",
2611 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2612 Requires<[IsThumb2, HasDSP]> {
2613 let Inst{31-27} = 0b11111;
2614 let Inst{26-23} = 0b0110;
2615 let Inst{22-20} = 0b101;
2616 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2617 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2620 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2621 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2622 Requires<[IsThumb2, HasDSP]> {
2623 let Inst{31-27} = 0b11111;
2624 let Inst{26-23} = 0b0110;
2625 let Inst{22-20} = 0b101;
2626 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2627 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2630 def t2SMMLA : T2FourReg<
2631 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2632 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2633 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2634 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2635 let Inst{31-27} = 0b11111;
2636 let Inst{26-23} = 0b0110;
2637 let Inst{22-20} = 0b101;
2638 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2641 def t2SMMLAR: T2FourReg<
2642 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2643 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2644 Requires<[IsThumb2, HasDSP]> {
2645 let Inst{31-27} = 0b11111;
2646 let Inst{26-23} = 0b0110;
2647 let Inst{22-20} = 0b101;
2648 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2651 def t2SMMLS: T2FourReg<
2652 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2653 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2654 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2655 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2656 let Inst{31-27} = 0b11111;
2657 let Inst{26-23} = 0b0110;
2658 let Inst{22-20} = 0b110;
2659 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2662 def t2SMMLSR:T2FourReg<
2663 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2664 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2665 Requires<[IsThumb2, HasDSP]> {
2666 let Inst{31-27} = 0b11111;
2667 let Inst{26-23} = 0b0110;
2668 let Inst{22-20} = 0b110;
2669 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2672 multiclass T2I_smul<string opc, SDNode opnode> {
2673 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2674 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2675 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2676 (sext_inreg rGPR:$Rm, i16)))]>,
2677 Requires<[IsThumb2, HasDSP]> {
2678 let Inst{31-27} = 0b11111;
2679 let Inst{26-23} = 0b0110;
2680 let Inst{22-20} = 0b001;
2681 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2682 let Inst{7-6} = 0b00;
2683 let Inst{5-4} = 0b00;
2686 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2687 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2688 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2689 (sra rGPR:$Rm, (i32 16))))]>,
2690 Requires<[IsThumb2, HasDSP]> {
2691 let Inst{31-27} = 0b11111;
2692 let Inst{26-23} = 0b0110;
2693 let Inst{22-20} = 0b001;
2694 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2695 let Inst{7-6} = 0b00;
2696 let Inst{5-4} = 0b01;
2699 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2700 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2701 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2702 (sext_inreg rGPR:$Rm, i16)))]>,
2703 Requires<[IsThumb2, HasDSP]> {
2704 let Inst{31-27} = 0b11111;
2705 let Inst{26-23} = 0b0110;
2706 let Inst{22-20} = 0b001;
2707 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2708 let Inst{7-6} = 0b00;
2709 let Inst{5-4} = 0b10;
2712 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2713 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2714 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2715 (sra rGPR:$Rm, (i32 16))))]>,
2716 Requires<[IsThumb2, HasDSP]> {
2717 let Inst{31-27} = 0b11111;
2718 let Inst{26-23} = 0b0110;
2719 let Inst{22-20} = 0b001;
2720 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2721 let Inst{7-6} = 0b00;
2722 let Inst{5-4} = 0b11;
2725 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2726 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2728 Requires<[IsThumb2, HasDSP]> {
2729 let Inst{31-27} = 0b11111;
2730 let Inst{26-23} = 0b0110;
2731 let Inst{22-20} = 0b011;
2732 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2733 let Inst{7-6} = 0b00;
2734 let Inst{5-4} = 0b00;
2737 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2738 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2740 Requires<[IsThumb2, HasDSP]> {
2741 let Inst{31-27} = 0b11111;
2742 let Inst{26-23} = 0b0110;
2743 let Inst{22-20} = 0b011;
2744 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2745 let Inst{7-6} = 0b00;
2746 let Inst{5-4} = 0b01;
2751 multiclass T2I_smla<string opc, SDNode opnode> {
2753 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2754 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2755 [(set rGPR:$Rd, (add rGPR:$Ra,
2756 (opnode (sext_inreg rGPR:$Rn, i16),
2757 (sext_inreg rGPR:$Rm, i16))))]>,
2758 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2759 let Inst{31-27} = 0b11111;
2760 let Inst{26-23} = 0b0110;
2761 let Inst{22-20} = 0b001;
2762 let Inst{7-6} = 0b00;
2763 let Inst{5-4} = 0b00;
2767 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2768 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2769 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2770 (sra rGPR:$Rm, (i32 16)))))]>,
2771 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2772 let Inst{31-27} = 0b11111;
2773 let Inst{26-23} = 0b0110;
2774 let Inst{22-20} = 0b001;
2775 let Inst{7-6} = 0b00;
2776 let Inst{5-4} = 0b01;
2780 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2781 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2782 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2783 (sext_inreg rGPR:$Rm, i16))))]>,
2784 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2785 let Inst{31-27} = 0b11111;
2786 let Inst{26-23} = 0b0110;
2787 let Inst{22-20} = 0b001;
2788 let Inst{7-6} = 0b00;
2789 let Inst{5-4} = 0b10;
2793 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2794 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2795 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2796 (sra rGPR:$Rm, (i32 16)))))]>,
2797 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2798 let Inst{31-27} = 0b11111;
2799 let Inst{26-23} = 0b0110;
2800 let Inst{22-20} = 0b001;
2801 let Inst{7-6} = 0b00;
2802 let Inst{5-4} = 0b11;
2806 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2807 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2809 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2810 let Inst{31-27} = 0b11111;
2811 let Inst{26-23} = 0b0110;
2812 let Inst{22-20} = 0b011;
2813 let Inst{7-6} = 0b00;
2814 let Inst{5-4} = 0b00;
2818 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2819 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2821 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2822 let Inst{31-27} = 0b11111;
2823 let Inst{26-23} = 0b0110;
2824 let Inst{22-20} = 0b011;
2825 let Inst{7-6} = 0b00;
2826 let Inst{5-4} = 0b01;
2830 defm t2SMUL : T2I_smul<"smul", mul>;
2831 defm t2SMLA : T2I_smla<"smla", mul>;
2833 // Halfword multiple accumulate long: SMLAL<x><y>
2834 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2835 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2836 [/* For disassembly only; pattern left blank */]>,
2837 Requires<[IsThumb2, HasDSP]>;
2838 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2839 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2840 [/* For disassembly only; pattern left blank */]>,
2841 Requires<[IsThumb2, HasDSP]>;
2842 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2843 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2844 [/* For disassembly only; pattern left blank */]>,
2845 Requires<[IsThumb2, HasDSP]>;
2846 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2847 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2848 [/* For disassembly only; pattern left blank */]>,
2849 Requires<[IsThumb2, HasDSP]>;
2851 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2852 def t2SMUAD: T2ThreeReg_mac<
2853 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2854 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2855 Requires<[IsThumb2, HasDSP]> {
2856 let Inst{15-12} = 0b1111;
2858 def t2SMUADX:T2ThreeReg_mac<
2859 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2860 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2861 Requires<[IsThumb2, HasDSP]> {
2862 let Inst{15-12} = 0b1111;
2864 def t2SMUSD: T2ThreeReg_mac<
2865 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2866 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2867 Requires<[IsThumb2, HasDSP]> {
2868 let Inst{15-12} = 0b1111;
2870 def t2SMUSDX:T2ThreeReg_mac<
2871 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2872 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2873 Requires<[IsThumb2, HasDSP]> {
2874 let Inst{15-12} = 0b1111;
2876 def t2SMLAD : T2FourReg_mac<
2877 0, 0b010, 0b0000, (outs rGPR:$Rd),
2878 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2879 "\t$Rd, $Rn, $Rm, $Ra", []>,
2880 Requires<[IsThumb2, HasDSP]>;
2881 def t2SMLADX : T2FourReg_mac<
2882 0, 0b010, 0b0001, (outs rGPR:$Rd),
2883 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2884 "\t$Rd, $Rn, $Rm, $Ra", []>,
2885 Requires<[IsThumb2, HasDSP]>;
2886 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2887 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2888 "\t$Rd, $Rn, $Rm, $Ra", []>,
2889 Requires<[IsThumb2, HasDSP]>;
2890 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2891 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2892 "\t$Rd, $Rn, $Rm, $Ra", []>,
2893 Requires<[IsThumb2, HasDSP]>;
2894 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2895 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2896 "\t$Ra, $Rd, $Rn, $Rm", []>,
2897 Requires<[IsThumb2, HasDSP]>;
2898 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2899 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2900 "\t$Ra, $Rd, $Rn, $Rm", []>,
2901 Requires<[IsThumb2, HasDSP]>;
2902 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2903 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2904 "\t$Ra, $Rd, $Rn, $Rm", []>,
2905 Requires<[IsThumb2, HasDSP]>;
2906 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2907 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2908 "\t$Ra, $Rd, $Rn, $Rm", []>,
2909 Requires<[IsThumb2, HasDSP]>;
2911 //===----------------------------------------------------------------------===//
2912 // Division Instructions.
2913 // Signed and unsigned division on v7-M
2915 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2916 "sdiv", "\t$Rd, $Rn, $Rm",
2917 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2918 Requires<[HasDivide, IsThumb, HasV8MBaseline]> {
2919 let Inst{31-27} = 0b11111;
2920 let Inst{26-21} = 0b011100;
2922 let Inst{15-12} = 0b1111;
2923 let Inst{7-4} = 0b1111;
2926 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2927 "udiv", "\t$Rd, $Rn, $Rm",
2928 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2929 Requires<[HasDivide, IsThumb, HasV8MBaseline]> {
2930 let Inst{31-27} = 0b11111;
2931 let Inst{26-21} = 0b011101;
2933 let Inst{15-12} = 0b1111;
2934 let Inst{7-4} = 0b1111;
2937 //===----------------------------------------------------------------------===//
2938 // Misc. Arithmetic Instructions.
2941 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2942 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2943 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2944 let Inst{31-27} = 0b11111;
2945 let Inst{26-22} = 0b01010;
2946 let Inst{21-20} = op1;
2947 let Inst{15-12} = 0b1111;
2948 let Inst{7-6} = 0b10;
2949 let Inst{5-4} = op2;
2953 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2954 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2957 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2958 "rbit", "\t$Rd, $Rm",
2959 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
2962 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2963 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2966 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2967 "rev16", ".w\t$Rd, $Rm",
2968 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2971 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2972 "revsh", ".w\t$Rd, $Rm",
2973 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2976 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2977 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2978 (t2REVSH rGPR:$Rm)>;
2980 def t2PKHBT : T2ThreeReg<
2981 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2982 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2983 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2984 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2986 Requires<[HasT2ExtractPack, IsThumb2]>,
2987 Sched<[WriteALUsi, ReadALU]> {
2988 let Inst{31-27} = 0b11101;
2989 let Inst{26-25} = 0b01;
2990 let Inst{24-20} = 0b01100;
2991 let Inst{5} = 0; // BT form
2995 let Inst{14-12} = sh{4-2};
2996 let Inst{7-6} = sh{1-0};
2999 // Alternate cases for PKHBT where identities eliminate some nodes.
3000 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
3001 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
3002 Requires<[HasT2ExtractPack, IsThumb2]>;
3003 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
3004 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3005 Requires<[HasT2ExtractPack, IsThumb2]>;
3007 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3008 // will match the pattern below.
3009 def t2PKHTB : T2ThreeReg<
3010 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
3011 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3012 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3013 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
3015 Requires<[HasT2ExtractPack, IsThumb2]>,
3016 Sched<[WriteALUsi, ReadALU]> {
3017 let Inst{31-27} = 0b11101;
3018 let Inst{26-25} = 0b01;
3019 let Inst{24-20} = 0b01100;
3020 let Inst{5} = 1; // TB form
3024 let Inst{14-12} = sh{4-2};
3025 let Inst{7-6} = sh{1-0};
3028 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3029 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3030 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
3031 // pkhtb src1, src2, asr (17..31).
3032 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
3033 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
3034 Requires<[HasT2ExtractPack, IsThumb2]>;
3035 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
3036 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3037 Requires<[HasT2ExtractPack, IsThumb2]>;
3038 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
3039 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
3040 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
3041 Requires<[HasT2ExtractPack, IsThumb2]>;
3043 //===----------------------------------------------------------------------===//
3044 // CRC32 Instructions
3047 // + CRC32{B,H,W} 0x04C11DB7
3048 // + CRC32C{B,H,W} 0x1EDC6F41
3051 class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
3052 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
3053 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
3054 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
3055 Requires<[IsThumb2, HasV8, HasCRC]> {
3056 let Inst{31-27} = 0b11111;
3057 let Inst{26-21} = 0b010110;
3059 let Inst{15-12} = 0b1111;
3060 let Inst{7-6} = 0b10;
3064 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3065 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3066 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3067 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3068 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
3069 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
3071 //===----------------------------------------------------------------------===//
3072 // Comparison Instructions...
3074 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
3075 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>;
3077 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
3078 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
3079 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
3080 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
3081 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
3082 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
3084 let isCompare = 1, Defs = [CPSR] in {
3086 def t2CMNri : T2OneRegCmpImm<
3087 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
3088 "cmn", ".w\t$Rn, $imm",
3089 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
3090 Sched<[WriteCMP, ReadALU]> {
3091 let Inst{31-27} = 0b11110;
3093 let Inst{24-21} = 0b1000;
3094 let Inst{20} = 1; // The S bit.
3096 let Inst{11-8} = 0b1111; // Rd
3099 def t2CMNzrr : T2TwoRegCmp<
3100 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
3101 "cmn", ".w\t$Rn, $Rm",
3102 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3103 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3104 let Inst{31-27} = 0b11101;
3105 let Inst{26-25} = 0b01;
3106 let Inst{24-21} = 0b1000;
3107 let Inst{20} = 1; // The S bit.
3108 let Inst{14-12} = 0b000; // imm3
3109 let Inst{11-8} = 0b1111; // Rd
3110 let Inst{7-6} = 0b00; // imm2
3111 let Inst{5-4} = 0b00; // type
3114 def t2CMNzrs : T2OneRegCmpShiftedReg<
3115 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3116 "cmn", ".w\t$Rn, $ShiftedRm",
3117 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3118 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3119 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3120 let Inst{31-27} = 0b11101;
3121 let Inst{26-25} = 0b01;
3122 let Inst{24-21} = 0b1000;
3123 let Inst{20} = 1; // The S bit.
3124 let Inst{11-8} = 0b1111; // Rd
3128 // Assembler aliases w/o the ".w" suffix.
3129 // No alias here for 'rr' version as not all instantiations of this multiclass
3130 // want one (CMP in particular, does not).
3131 def : t2InstAlias<"cmn${p} $Rn, $imm",
3132 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3133 def : t2InstAlias<"cmn${p} $Rn, $shift",
3134 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3136 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3137 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3139 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3140 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3142 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3143 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3144 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3145 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
3146 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3147 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3149 // Conditional moves
3150 let hasSideEffects = 0 in {
3152 let isCommutable = 1, isSelect = 1 in
3153 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3154 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
3156 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3158 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3160 let isMoveImm = 1 in
3162 : t2PseudoInst<(outs rGPR:$Rd),
3163 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3165 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3167 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3169 let isCodeGenOnly = 1 in {
3170 let isMoveImm = 1 in
3172 : t2PseudoInst<(outs rGPR:$Rd),
3173 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3175 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3177 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3179 let isMoveImm = 1 in
3181 : t2PseudoInst<(outs rGPR:$Rd),
3182 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3185 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3187 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3189 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3190 : t2PseudoInst<(outs rGPR:$Rd),
3191 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3193 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3194 (opnode rGPR:$Rm, (i32 ty:$imm)),
3196 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3198 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3199 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3200 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3201 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3203 let isMoveImm = 1 in
3205 : t2PseudoInst<(outs rGPR:$dst),
3206 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3208 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3210 RegConstraint<"$false = $dst">;
3211 } // isCodeGenOnly = 1
3215 //===----------------------------------------------------------------------===//
3216 // Atomic operations intrinsics
3219 // memory barriers protect the atomic sequences
3220 let hasSideEffects = 1 in {
3221 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3222 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
3223 Requires<[IsThumb, HasDB]> {
3225 let Inst{31-4} = 0xf3bf8f5;
3226 let Inst{3-0} = opt;
3229 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3230 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
3231 Requires<[IsThumb, HasDB]> {
3233 let Inst{31-4} = 0xf3bf8f4;
3234 let Inst{3-0} = opt;
3237 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3238 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
3239 Requires<[IsThumb, HasDB]> {
3241 let Inst{31-4} = 0xf3bf8f6;
3242 let Inst{3-0} = opt;
3246 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3247 InstrItinClass itin, string opc, string asm, string cstr,
3248 list<dag> pattern, bits<4> rt2 = 0b1111>
3249 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3250 let Inst{31-27} = 0b11101;
3251 let Inst{26-20} = 0b0001101;
3252 let Inst{11-8} = rt2;
3253 let Inst{7-4} = opcod;
3254 let Inst{3-0} = 0b1111;
3258 let Inst{19-16} = addr;
3259 let Inst{15-12} = Rt;
3261 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3262 InstrItinClass itin, string opc, string asm, string cstr,
3263 list<dag> pattern, bits<4> rt2 = 0b1111>
3264 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3265 let Inst{31-27} = 0b11101;
3266 let Inst{26-20} = 0b0001100;
3267 let Inst{11-8} = rt2;
3268 let Inst{7-4} = opcod;
3274 let Inst{19-16} = addr;
3275 let Inst{15-12} = Rt;
3278 let mayLoad = 1 in {
3279 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3280 AddrModeNone, 4, NoItinerary,
3281 "ldrexb", "\t$Rt, $addr", "",
3282 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>,
3283 Requires<[IsThumb, HasV8MBaseline]>;
3284 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3285 AddrModeNone, 4, NoItinerary,
3286 "ldrexh", "\t$Rt, $addr", "",
3287 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,
3288 Requires<[IsThumb, HasV8MBaseline]>;
3289 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3290 AddrModeNone, 4, NoItinerary,
3291 "ldrex", "\t$Rt, $addr", "",
3292 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,
3293 Requires<[IsThumb, HasV8MBaseline]> {
3296 let Inst{31-27} = 0b11101;
3297 let Inst{26-20} = 0b0000101;
3298 let Inst{19-16} = addr{11-8};
3299 let Inst{15-12} = Rt;
3300 let Inst{11-8} = 0b1111;
3301 let Inst{7-0} = addr{7-0};
3303 let hasExtraDefRegAllocReq = 1 in
3304 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3305 (ins addr_offset_none:$addr),
3306 AddrModeNone, 4, NoItinerary,
3307 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3309 Requires<[IsThumb2, IsNotMClass]> {
3311 let Inst{11-8} = Rt2;
3313 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3314 AddrModeNone, 4, NoItinerary,
3315 "ldaexb", "\t$Rt, $addr", "",
3316 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
3317 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3318 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3319 AddrModeNone, 4, NoItinerary,
3320 "ldaexh", "\t$Rt, $addr", "",
3321 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
3322 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3323 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3324 AddrModeNone, 4, NoItinerary,
3325 "ldaex", "\t$Rt, $addr", "",
3326 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
3327 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
3330 let Inst{31-27} = 0b11101;
3331 let Inst{26-20} = 0b0001101;
3332 let Inst{19-16} = addr;
3333 let Inst{15-12} = Rt;
3334 let Inst{11-8} = 0b1111;
3335 let Inst{7-0} = 0b11101111;
3337 let hasExtraDefRegAllocReq = 1 in
3338 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3339 (ins addr_offset_none:$addr),
3340 AddrModeNone, 4, NoItinerary,
3341 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3342 [], {?, ?, ?, ?}>, Requires<[IsThumb,
3343 HasAcquireRelease, HasV7Clrex, IsNotMClass]> {
3345 let Inst{11-8} = Rt2;
3351 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3352 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3353 (ins rGPR:$Rt, addr_offset_none:$addr),
3354 AddrModeNone, 4, NoItinerary,
3355 "strexb", "\t$Rd, $Rt, $addr", "",
3357 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3358 Requires<[IsThumb, HasV8MBaseline]>;
3359 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3360 (ins rGPR:$Rt, addr_offset_none:$addr),
3361 AddrModeNone, 4, NoItinerary,
3362 "strexh", "\t$Rd, $Rt, $addr", "",
3364 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3365 Requires<[IsThumb, HasV8MBaseline]>;
3367 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3368 t2addrmode_imm0_1020s4:$addr),
3369 AddrModeNone, 4, NoItinerary,
3370 "strex", "\t$Rd, $Rt, $addr", "",
3372 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,
3373 Requires<[IsThumb, HasV8MBaseline]> {
3377 let Inst{31-27} = 0b11101;
3378 let Inst{26-20} = 0b0000100;
3379 let Inst{19-16} = addr{11-8};
3380 let Inst{15-12} = Rt;
3381 let Inst{11-8} = Rd;
3382 let Inst{7-0} = addr{7-0};
3384 let hasExtraSrcRegAllocReq = 1 in
3385 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3386 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3387 AddrModeNone, 4, NoItinerary,
3388 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3390 Requires<[IsThumb2, IsNotMClass]> {
3392 let Inst{11-8} = Rt2;
3394 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3395 (ins rGPR:$Rt, addr_offset_none:$addr),
3396 AddrModeNone, 4, NoItinerary,
3397 "stlexb", "\t$Rd, $Rt, $addr", "",
3399 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3400 Requires<[IsThumb, HasAcquireRelease,
3403 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3404 (ins rGPR:$Rt, addr_offset_none:$addr),
3405 AddrModeNone, 4, NoItinerary,
3406 "stlexh", "\t$Rd, $Rt, $addr", "",
3408 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3409 Requires<[IsThumb, HasAcquireRelease,
3412 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3413 addr_offset_none:$addr),
3414 AddrModeNone, 4, NoItinerary,
3415 "stlex", "\t$Rd, $Rt, $addr", "",
3417 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
3418 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
3422 let Inst{31-27} = 0b11101;
3423 let Inst{26-20} = 0b0001100;
3424 let Inst{19-16} = addr;
3425 let Inst{15-12} = Rt;
3426 let Inst{11-4} = 0b11111110;
3429 let hasExtraSrcRegAllocReq = 1 in
3430 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3431 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3432 AddrModeNone, 4, NoItinerary,
3433 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3434 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,
3435 HasV7Clrex, IsNotMClass]> {
3437 let Inst{11-8} = Rt2;
3441 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3442 Requires<[IsThumb, HasV7Clrex]> {
3443 let Inst{31-16} = 0xf3bf;
3444 let Inst{15-14} = 0b10;
3447 let Inst{11-8} = 0b1111;
3448 let Inst{7-4} = 0b0010;
3449 let Inst{3-0} = 0b1111;
3452 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3453 (t2LDREXB addr_offset_none:$addr)>,
3454 Requires<[IsThumb, HasV8MBaseline]>;
3455 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3456 (t2LDREXH addr_offset_none:$addr)>,
3457 Requires<[IsThumb, HasV8MBaseline]>;
3458 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3459 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>,
3460 Requires<[IsThumb, HasV8MBaseline]>;
3461 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3462 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>,
3463 Requires<[IsThumb, HasV8MBaseline]>;
3465 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3466 (t2LDAEXB addr_offset_none:$addr)>,
3467 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3468 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3469 (t2LDAEXH addr_offset_none:$addr)>,
3470 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3471 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3472 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>,
3473 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3474 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3475 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>,
3476 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3478 //===----------------------------------------------------------------------===//
3479 // SJLJ Exception handling intrinsics
3480 // eh_sjlj_setjmp() is an instruction sequence to store the return
3481 // address and save #0 in R0 for the non-longjmp case.
3482 // Since by its nature we may be coming from some other function to get
3483 // here, and we're using the stack frame for the containing function to
3484 // save/restore registers, we can't keep anything live in regs across
3485 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3486 // when we get here from a longjmp(). We force everything out of registers
3487 // except for our own input by listing the relevant registers in Defs. By
3488 // doing so, we also cause the prologue/epilogue code to actively preserve
3489 // all of the callee-saved resgisters, which is exactly what we want.
3490 // $val is a scratch register for our use.
3492 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3493 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3494 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3495 usesCustomInserter = 1 in {
3496 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3497 AddrModeNone, 0, NoItinerary, "", "",
3498 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3499 Requires<[IsThumb2, HasVFP2]>;
3503 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3504 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3505 usesCustomInserter = 1 in {
3506 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3507 AddrModeNone, 0, NoItinerary, "", "",
3508 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3509 Requires<[IsThumb2, NoVFP]>;
3513 //===----------------------------------------------------------------------===//
3514 // Control-Flow Instructions
3517 // FIXME: remove when we have a way to marking a MI with these properties.
3518 // FIXME: Should pc be an implicit operand like PICADD, etc?
3519 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3520 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3521 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3522 reglist:$regs, variable_ops),
3523 4, IIC_iLoad_mBr, [],
3524 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3525 RegConstraint<"$Rn = $wb">;
3527 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3528 let isPredicable = 1 in
3529 def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br,
3531 [(br bb:$target)]>, Sched<[WriteBr]>,
3532 Requires<[IsThumb, HasV8MBaseline]> {
3533 let Inst{31-27} = 0b11110;
3534 let Inst{15-14} = 0b10;
3538 let Inst{26} = target{23};
3539 let Inst{13} = target{22};
3540 let Inst{11} = target{21};
3541 let Inst{25-16} = target{20-11};
3542 let Inst{10-0} = target{10-0};
3543 let DecoderMethod = "DecodeT2BInstruction";
3544 let AsmMatchConverter = "cvtThumbBranches";
3547 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
3548 def t2BR_JT : t2PseudoInst<(outs),
3549 (ins GPR:$target, GPR:$index, i32imm:$jt),
3551 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,
3554 // FIXME: Add a case that can be predicated.
3555 def t2TBB_JT : t2PseudoInst<(outs),
3556 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3559 def t2TBH_JT : t2PseudoInst<(outs),
3560 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3563 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3564 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3567 let Inst{31-20} = 0b111010001101;
3568 let Inst{19-16} = Rn;
3569 let Inst{15-5} = 0b11110000000;
3570 let Inst{4} = 0; // B form
3573 let DecoderMethod = "DecodeThumbTableBranch";
3576 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3577 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3580 let Inst{31-20} = 0b111010001101;
3581 let Inst{19-16} = Rn;
3582 let Inst{15-5} = 0b11110000000;
3583 let Inst{4} = 1; // H form
3586 let DecoderMethod = "DecodeThumbTableBranch";
3588 } // isNotDuplicable, isIndirectBranch
3590 } // isBranch, isTerminator, isBarrier
3592 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3593 // a two-value operand where a dag node expects ", "two operands. :(
3594 let isBranch = 1, isTerminator = 1 in
3595 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3597 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3598 let Inst{31-27} = 0b11110;
3599 let Inst{15-14} = 0b10;
3603 let Inst{25-22} = p;
3606 let Inst{26} = target{20};
3607 let Inst{11} = target{19};
3608 let Inst{13} = target{18};
3609 let Inst{21-16} = target{17-12};
3610 let Inst{10-0} = target{11-1};
3612 let DecoderMethod = "DecodeThumb2BCCInstruction";
3613 let AsmMatchConverter = "cvtThumbBranches";
3616 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
3618 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3621 def tTAILJMPd: tPseudoExpand<(outs),
3622 (ins thumb_br_target:$dst, pred:$p),
3624 (t2B thumb_br_target:$dst, pred:$p)>,
3625 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3629 let Defs = [ITSTATE] in
3630 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3631 AddrModeNone, 2, IIC_iALUx,
3632 "it$mask\t$cc", "", []>,
3633 ComplexDeprecationPredicate<"IT"> {
3634 // 16-bit instruction.
3635 let Inst{31-16} = 0x0000;
3636 let Inst{15-8} = 0b10111111;
3641 let Inst{3-0} = mask;
3643 let DecoderMethod = "DecodeIT";
3646 // Branch and Exchange Jazelle -- for disassembly only
3648 def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
3649 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
3651 let Inst{31-27} = 0b11110;
3653 let Inst{25-20} = 0b111100;
3654 let Inst{19-16} = func;
3655 let Inst{15-0} = 0b1000111100000000;
3658 // Compare and branch on zero / non-zero
3659 let isBranch = 1, isTerminator = 1 in {
3660 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3661 "cbz\t$Rn, $target", []>,
3662 T1Misc<{0,0,?,1,?,?,?}>,
3663 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3667 let Inst{9} = target{5};
3668 let Inst{7-3} = target{4-0};
3672 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3673 "cbnz\t$Rn, $target", []>,
3674 T1Misc<{1,0,?,1,?,?,?}>,
3675 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3679 let Inst{9} = target{5};
3680 let Inst{7-3} = target{4-0};
3686 // Change Processor State is a system instruction.
3687 // FIXME: Since the asm parser has currently no clean way to handle optional
3688 // operands, create 3 versions of the same instruction. Once there's a clean
3689 // framework to represent optional operands, change this behavior.
3690 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3691 !strconcat("cps", asm_op), []>,
3692 Requires<[IsThumb2, IsNotMClass]> {
3698 let Inst{31-11} = 0b111100111010111110000;
3699 let Inst{10-9} = imod;
3701 let Inst{7-5} = iflags;
3702 let Inst{4-0} = mode;
3703 let DecoderMethod = "DecodeT2CPSInstruction";
3707 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3708 "$imod\t$iflags, $mode">;
3709 let mode = 0, M = 0 in
3710 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3711 "$imod.w\t$iflags">;
3712 let imod = 0, iflags = 0, M = 1 in
3713 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3715 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3716 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3717 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3719 // A6.3.4 Branches and miscellaneous control
3720 // Table A6-14 Change Processor State, and hint instructions
3721 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
3722 [(int_arm_hint imm0_239:$imm)]> {
3724 let Inst{31-3} = 0b11110011101011111000000000000;
3725 let Inst{7-0} = imm;
3728 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
3729 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
3730 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
3731 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
3732 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
3733 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
3734 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
3735 let Predicates = [IsThumb2, HasV8];
3737 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
3738 let Predicates = [IsThumb2, HasRAS];
3740 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
3741 let Predicates = [IsThumb2, HasRAS];
3744 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
3745 [(int_arm_dbg imm0_15:$opt)]> {
3747 let Inst{31-20} = 0b111100111010;
3748 let Inst{19-16} = 0b1111;
3749 let Inst{15-8} = 0b10000000;
3750 let Inst{7-4} = 0b1111;
3751 let Inst{3-0} = opt;
3754 // Secure Monitor Call is a system instruction.
3755 // Option = Inst{19-16}
3756 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3757 []>, Requires<[IsThumb2, HasTrustZone]> {
3758 let Inst{31-27} = 0b11110;
3759 let Inst{26-20} = 0b1111111;
3760 let Inst{15-12} = 0b1000;
3763 let Inst{19-16} = opt;
3766 class T2DCPS<bits<2> opt, string opc>
3767 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3768 let Inst{31-27} = 0b11110;
3769 let Inst{26-20} = 0b1111000;
3770 let Inst{19-16} = 0b1111;
3771 let Inst{15-12} = 0b1000;
3772 let Inst{11-2} = 0b0000000000;
3773 let Inst{1-0} = opt;
3776 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
3777 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
3778 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
3780 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3781 string opc, string asm, list<dag> pattern>
3782 : T2I<oops, iops, itin, opc, asm, pattern>,
3783 Requires<[IsThumb2,IsNotMClass]> {
3785 let Inst{31-25} = 0b1110100;
3786 let Inst{24-23} = Op;
3789 let Inst{20-16} = 0b01101;
3790 let Inst{15-5} = 0b11000000000;
3791 let Inst{4-0} = mode{4-0};
3794 // Store Return State is a system instruction.
3795 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3796 "srsdb", "\tsp!, $mode", []>;
3797 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3798 "srsdb","\tsp, $mode", []>;
3799 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3800 "srsia","\tsp!, $mode", []>;
3801 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3802 "srsia","\tsp, $mode", []>;
3805 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3806 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3808 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3809 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3811 // Return From Exception is a system instruction.
3812 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3813 string opc, string asm, list<dag> pattern>
3814 : T2I<oops, iops, itin, opc, asm, pattern>,
3815 Requires<[IsThumb2,IsNotMClass]> {
3816 let Inst{31-20} = op31_20{11-0};
3819 let Inst{19-16} = Rn;
3820 let Inst{15-0} = 0xc000;
3823 def t2RFEDBW : T2RFE<0b111010000011,
3824 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3825 [/* For disassembly only; pattern left blank */]>;
3826 def t2RFEDB : T2RFE<0b111010000001,
3827 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3828 [/* For disassembly only; pattern left blank */]>;
3829 def t2RFEIAW : T2RFE<0b111010011011,
3830 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3831 [/* For disassembly only; pattern left blank */]>;
3832 def t2RFEIA : T2RFE<0b111010011001,
3833 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3834 [/* For disassembly only; pattern left blank */]>;
3836 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
3837 // Exception return instruction is "subs pc, lr, #imm".
3838 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3839 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
3840 "subs", "\tpc, lr, $imm",
3841 [(ARMintretflag imm0_255:$imm)]>,
3842 Requires<[IsThumb2,IsNotMClass]> {
3843 let Inst{31-8} = 0b111100111101111010001111;
3846 let Inst{7-0} = imm;
3849 // Hypervisor Call is a system instruction.
3851 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
3852 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
3854 let Inst{31-20} = 0b111101111110;
3855 let Inst{19-16} = imm16{15-12};
3856 let Inst{15-12} = 0b1000;
3857 let Inst{11-0} = imm16{11-0};
3861 // Alias for HVC without the ".w" optional width specifier
3862 def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
3864 // ERET - Return from exception in Hypervisor mode.
3865 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
3866 // includes virtualization extensions.
3867 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
3868 Requires<[IsThumb2, HasVirtualization]>;
3870 //===----------------------------------------------------------------------===//
3871 // Non-Instruction Patterns
3874 // 32-bit immediate using movw + movt.
3875 // This is a single pseudo instruction to make it re-materializable.
3876 // FIXME: Remove this when we can do generalized remat.
3877 let isReMaterializable = 1, isMoveImm = 1 in
3878 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3879 [(set rGPR:$dst, (i32 imm:$src))]>,
3880 Requires<[IsThumb, UseMovt]>;
3882 // Pseudo instruction that combines movw + movt + add pc (if pic).
3883 // It also makes it possible to rematerialize the instructions.
3884 // FIXME: Remove this when we can do generalized remat and when machine licm
3885 // can properly the instructions.
3886 let isReMaterializable = 1 in {
3887 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3889 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3890 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3894 def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst),
3895 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>,
3896 Requires<[IsThumb2, UseMovt]>;
3897 def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst),
3898 (t2MOVi32imm tglobaltlsaddr:$dst)>,
3899 Requires<[IsThumb2, UseMovt]>;
3901 // ConstantPool, GlobalAddress, and JumpTable
3902 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3903 def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>,
3904 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3905 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3906 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3908 def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;
3910 // Pseudo instruction that combines ldr from constpool and add pc. This should
3911 // be expanded into two instructions late to allow if-conversion and
3913 let canFoldAsLoad = 1, isReMaterializable = 1 in
3914 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3916 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3918 Requires<[IsThumb2]>;
3920 // Pseudo isntruction that combines movs + predicated rsbmi
3921 // to implement integer ABS
3922 let usesCustomInserter = 1, Defs = [CPSR] in {
3923 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3924 NoItinerary, []>, Requires<[IsThumb2]>;
3927 //===----------------------------------------------------------------------===//
3928 // Coprocessor load/store -- for disassembly only
3930 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern>
3931 : T2I<oops, iops, NoItinerary, opc, asm, pattern> {
3932 let Inst{31-28} = op31_28;
3933 let Inst{27-25} = 0b110;
3936 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> {
3937 def _OFFSET : T2CI<op31_28,
3938 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3939 asm, "\t$cop, $CRd, $addr", pattern> {
3943 let Inst{24} = 1; // P = 1
3944 let Inst{23} = addr{8};
3945 let Inst{22} = Dbit;
3946 let Inst{21} = 0; // W = 0
3947 let Inst{20} = load;
3948 let Inst{19-16} = addr{12-9};
3949 let Inst{15-12} = CRd;
3950 let Inst{11-8} = cop;
3951 let Inst{7-0} = addr{7-0};
3952 let DecoderMethod = "DecodeCopMemInstruction";
3954 def _PRE : T2CI<op31_28,
3955 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3956 asm, "\t$cop, $CRd, $addr!", []> {
3960 let Inst{24} = 1; // P = 1
3961 let Inst{23} = addr{8};
3962 let Inst{22} = Dbit;
3963 let Inst{21} = 1; // W = 1
3964 let Inst{20} = load;
3965 let Inst{19-16} = addr{12-9};
3966 let Inst{15-12} = CRd;
3967 let Inst{11-8} = cop;
3968 let Inst{7-0} = addr{7-0};
3969 let DecoderMethod = "DecodeCopMemInstruction";
3971 def _POST: T2CI<op31_28,
3972 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3973 postidx_imm8s4:$offset),
3974 asm, "\t$cop, $CRd, $addr, $offset", []> {
3979 let Inst{24} = 0; // P = 0
3980 let Inst{23} = offset{8};
3981 let Inst{22} = Dbit;
3982 let Inst{21} = 1; // W = 1
3983 let Inst{20} = load;
3984 let Inst{19-16} = addr;
3985 let Inst{15-12} = CRd;
3986 let Inst{11-8} = cop;
3987 let Inst{7-0} = offset{7-0};
3988 let DecoderMethod = "DecodeCopMemInstruction";
3990 def _OPTION : T2CI<op31_28, (outs),
3991 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3992 coproc_option_imm:$option),
3993 asm, "\t$cop, $CRd, $addr, $option", []> {
3998 let Inst{24} = 0; // P = 0
3999 let Inst{23} = 1; // U = 1
4000 let Inst{22} = Dbit;
4001 let Inst{21} = 0; // W = 0
4002 let Inst{20} = load;
4003 let Inst{19-16} = addr;
4004 let Inst{15-12} = CRd;
4005 let Inst{11-8} = cop;
4006 let Inst{7-0} = option;
4007 let DecoderMethod = "DecodeCopMemInstruction";
4011 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4012 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4013 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4014 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4016 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4017 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4018 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4019 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4022 //===----------------------------------------------------------------------===//
4023 // Move between special register and ARM core register -- for disassembly only
4025 // Move to ARM core register from Special Register
4029 // A/R class can only move from CPSR or SPSR.
4030 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
4031 []>, Requires<[IsThumb2,IsNotMClass]> {
4033 let Inst{31-12} = 0b11110011111011111000;
4034 let Inst{11-8} = Rd;
4035 let Inst{7-0} = 0b00000000;
4038 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
4040 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
4041 []>, Requires<[IsThumb2,IsNotMClass]> {
4043 let Inst{31-12} = 0b11110011111111111000;
4044 let Inst{11-8} = Rd;
4045 let Inst{7-0} = 0b00000000;
4048 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
4049 NoItinerary, "mrs", "\t$Rd, $banked", []>,
4050 Requires<[IsThumb, HasVirtualization]> {
4054 let Inst{31-21} = 0b11110011111;
4055 let Inst{20} = banked{5}; // R bit
4056 let Inst{19-16} = banked{3-0};
4057 let Inst{15-12} = 0b1000;
4058 let Inst{11-8} = Rd;
4059 let Inst{7-5} = 0b001;
4060 let Inst{4} = banked{4};
4061 let Inst{3-0} = 0b0000;
4067 // This MRS has a mask field in bits 7-0 and can take more values than
4068 // the A/R class (a full msr_mask).
4069 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
4070 "mrs", "\t$Rd, $SYSm", []>,
4071 Requires<[IsThumb,IsMClass]> {
4074 let Inst{31-12} = 0b11110011111011111000;
4075 let Inst{11-8} = Rd;
4076 let Inst{7-0} = SYSm;
4078 let Unpredictable{20-16} = 0b11111;
4079 let Unpredictable{13} = 0b1;
4083 // Move from ARM core register to Special Register
4087 // No need to have both system and application versions, the encodings are the
4088 // same and the assembly parser has no way to distinguish between them. The mask
4089 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4090 // the mask with the fields to be accessed in the special register.
4091 let Defs = [CPSR] in
4092 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
4093 NoItinerary, "msr", "\t$mask, $Rn", []>,
4094 Requires<[IsThumb2,IsNotMClass]> {
4097 let Inst{31-21} = 0b11110011100;
4098 let Inst{20} = mask{4}; // R Bit
4099 let Inst{19-16} = Rn;
4100 let Inst{15-12} = 0b1000;
4101 let Inst{11-8} = mask{3-0};
4105 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
4106 // separate encoding (distinguished by bit 5.
4107 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
4108 NoItinerary, "msr", "\t$banked, $Rn", []>,
4109 Requires<[IsThumb, HasVirtualization]> {
4113 let Inst{31-21} = 0b11110011100;
4114 let Inst{20} = banked{5}; // R bit
4115 let Inst{19-16} = Rn;
4116 let Inst{15-12} = 0b1000;
4117 let Inst{11-8} = banked{3-0};
4118 let Inst{7-5} = 0b001;
4119 let Inst{4} = banked{4};
4120 let Inst{3-0} = 0b0000;
4126 // Move from ARM core register to Special Register
4127 let Defs = [CPSR] in
4128 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
4129 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
4130 Requires<[IsThumb,IsMClass]> {
4133 let Inst{31-21} = 0b11110011100;
4135 let Inst{19-16} = Rn;
4136 let Inst{15-12} = 0b1000;
4137 let Inst{11-10} = SYSm{11-10};
4138 let Inst{9-8} = 0b00;
4139 let Inst{7-0} = SYSm{7-0};
4141 let Unpredictable{20} = 0b1;
4142 let Unpredictable{13} = 0b1;
4143 let Unpredictable{9-8} = 0b11;
4147 //===----------------------------------------------------------------------===//
4148 // Move between coprocessor and ARM core register
4151 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4153 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4155 let Inst{27-24} = 0b1110;
4156 let Inst{20} = direction;
4166 let Inst{15-12} = Rt;
4167 let Inst{11-8} = cop;
4168 let Inst{23-21} = opc1;
4169 let Inst{7-5} = opc2;
4170 let Inst{3-0} = CRm;
4171 let Inst{19-16} = CRn;
4174 class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4175 list<dag> pattern = []>
4176 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4177 let Inst{27-24} = 0b1100;
4178 let Inst{23-21} = 0b010;
4179 let Inst{20} = direction;
4187 let Inst{15-12} = Rt;
4188 let Inst{19-16} = Rt2;
4189 let Inst{11-8} = cop;
4190 let Inst{7-4} = opc1;
4191 let Inst{3-0} = CRm;
4194 /* from ARM core register to coprocessor */
4195 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4197 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4198 c_imm:$CRm, imm0_7:$opc2),
4199 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4200 imm:$CRm, imm:$opc2)]>,
4201 ComplexDeprecationPredicate<"MCR">;
4202 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4203 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4204 c_imm:$CRm, 0, pred:$p)>;
4205 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4206 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4207 c_imm:$CRm, imm0_7:$opc2),
4208 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4209 imm:$CRm, imm:$opc2)]> {
4210 let Predicates = [IsThumb2, PreV8];
4212 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4213 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4214 c_imm:$CRm, 0, pred:$p)>;
4216 /* from coprocessor to ARM core register */
4217 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4218 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4219 c_imm:$CRm, imm0_7:$opc2), []>;
4220 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4221 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4222 c_imm:$CRm, 0, pred:$p)>;
4224 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4225 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4226 c_imm:$CRm, imm0_7:$opc2), []> {
4227 let Predicates = [IsThumb2, PreV8];
4229 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4230 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4231 c_imm:$CRm, 0, pred:$p)>;
4233 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4234 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4236 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4237 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4240 /* from ARM core register to coprocessor */
4241 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),
4242 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4244 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4246 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),
4247 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4249 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
4250 GPR:$Rt2, imm:$CRm)]> {
4251 let Predicates = [IsThumb2, PreV8];
4254 /* from coprocessor to ARM core register */
4255 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4256 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>;
4258 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),
4259 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> {
4260 let Predicates = [IsThumb2, PreV8];
4263 //===----------------------------------------------------------------------===//
4264 // Other Coprocessor Instructions.
4267 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4268 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4269 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4270 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4271 imm:$CRm, imm:$opc2)]> {
4272 let Inst{27-24} = 0b1110;
4281 let Inst{3-0} = CRm;
4283 let Inst{7-5} = opc2;
4284 let Inst{11-8} = cop;
4285 let Inst{15-12} = CRd;
4286 let Inst{19-16} = CRn;
4287 let Inst{23-20} = opc1;
4289 let Predicates = [IsThumb2, PreV8];
4292 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4293 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4294 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4295 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4296 imm:$CRm, imm:$opc2)]> {
4297 let Inst{27-24} = 0b1110;
4306 let Inst{3-0} = CRm;
4308 let Inst{7-5} = opc2;
4309 let Inst{11-8} = cop;
4310 let Inst{15-12} = CRd;
4311 let Inst{19-16} = CRn;
4312 let Inst{23-20} = opc1;
4314 let Predicates = [IsThumb2, PreV8];
4319 //===----------------------------------------------------------------------===//
4320 // ARMv8.1 Privilege Access Never extension
4324 def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
4325 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4330 let Inst{2-0} = 0b000;
4332 let Unpredictable{4} = 0b1;
4333 let Unpredictable{2-0} = 0b111;
4336 //===----------------------------------------------------------------------===//
4337 // ARMv8-M Security Extensions instructions
4340 let hasSideEffects = 1 in
4341 def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
4342 Requires<[Has8MSecExt]> {
4343 let Inst = 0xe97fe97f;
4346 class T2TT<bits<2> at, string asm, list<dag> pattern>
4347 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
4352 let Inst{31-20} = 0b111010000100;
4353 let Inst{19-16} = Rn;
4354 let Inst{15-12} = 0b1111;
4355 let Inst{11-8} = Rt;
4357 let Inst{5-0} = 0b000000;
4359 let Unpredictable{5-0} = 0b111111;
4362 def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
4363 def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
4364 def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
4365 def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
4367 //===----------------------------------------------------------------------===//
4368 // Non-Instruction Patterns
4371 // SXT/UXT with no rotate
4372 let AddedComplexity = 16 in {
4373 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4374 Requires<[IsThumb2]>;
4375 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4376 Requires<[IsThumb2]>;
4377 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4378 Requires<[HasT2ExtractPack, IsThumb2]>;
4379 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4380 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4381 Requires<[HasT2ExtractPack, IsThumb2]>;
4382 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4383 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4384 Requires<[HasT2ExtractPack, IsThumb2]>;
4387 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4388 Requires<[IsThumb2]>;
4389 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4390 Requires<[IsThumb2]>;
4391 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4392 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4393 Requires<[HasT2ExtractPack, IsThumb2]>;
4394 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4395 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4396 Requires<[HasT2ExtractPack, IsThumb2]>;
4398 // Atomic load/store patterns
4399 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4400 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4401 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4402 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4403 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4404 (t2LDRBs t2addrmode_so_reg:$addr)>;
4405 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4406 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4407 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4408 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4409 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4410 (t2LDRHs t2addrmode_so_reg:$addr)>;
4411 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4412 (t2LDRi12 t2addrmode_imm12:$addr)>;
4413 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4414 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4415 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4416 (t2LDRs t2addrmode_so_reg:$addr)>;
4417 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4418 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4419 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4420 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4421 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4422 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4423 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4424 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4425 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4426 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4427 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4428 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4429 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4430 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4431 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4432 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4433 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4434 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4436 let AddedComplexity = 8 in {
4437 def : T2Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4438 def : T2Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4439 def : T2Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
4440 def : T2Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
4441 def : T2Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
4442 def : T2Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;
4446 //===----------------------------------------------------------------------===//
4447 // Assembler aliases
4450 // Aliases for ADC without the ".w" optional width specifier.
4451 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4452 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4453 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4454 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4455 pred:$p, cc_out:$s)>;
4457 // Aliases for SBC without the ".w" optional width specifier.
4458 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4459 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4460 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4461 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4462 pred:$p, cc_out:$s)>;
4464 // Aliases for ADD without the ".w" optional width specifier.
4465 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4466 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4468 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4469 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4470 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4471 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4472 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4473 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4474 pred:$p, cc_out:$s)>;
4475 // ... and with the destination and source register combined.
4476 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4477 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4478 def : t2InstAlias<"add${p} $Rdn, $imm",
4479 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4480 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4481 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4482 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4483 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4484 pred:$p, cc_out:$s)>;
4486 // add w/ negative immediates is just a sub.
4487 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4488 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4490 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4491 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4492 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4493 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4495 def : t2InstAlias<"add${p} $Rdn, $imm",
4496 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4498 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4499 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4501 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4502 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4503 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4504 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4506 def : t2InstAlias<"addw${p} $Rdn, $imm",
4507 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4510 // Aliases for SUB without the ".w" optional width specifier.
4511 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4512 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4513 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4514 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4515 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4516 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4517 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4518 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4519 pred:$p, cc_out:$s)>;
4520 // ... and with the destination and source register combined.
4521 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4522 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4523 def : t2InstAlias<"sub${p} $Rdn, $imm",
4524 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4525 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4526 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4527 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4528 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4529 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4530 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4531 pred:$p, cc_out:$s)>;
4533 // Alias for compares without the ".w" optional width specifier.
4534 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4535 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4536 def : t2InstAlias<"teq${p} $Rn, $Rm",
4537 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4538 def : t2InstAlias<"tst${p} $Rn, $Rm",
4539 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4542 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4543 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4544 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4546 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4548 def : t2InstAlias<"ldr${p} $Rt, $addr",
4549 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4550 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4551 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4552 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4553 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4554 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4555 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4556 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4557 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4559 def : t2InstAlias<"ldr${p} $Rt, $addr",
4560 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4561 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4562 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4563 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4564 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4565 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4566 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4567 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4568 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4570 def : t2InstAlias<"ldr${p} $Rt, $addr",
4571 (t2LDRpci GPRnopc:$Rt, t2ldrlabel:$addr, pred:$p)>;
4572 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4573 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4574 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4575 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4576 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4577 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4578 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4579 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4581 // Alias for MVN with(out) the ".w" optional width specifier.
4582 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4583 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4584 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4585 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4586 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4587 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4589 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
4590 // input operands swapped when the shift amount is zero (i.e., unspecified).
4591 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4592 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4593 Requires<[HasT2ExtractPack, IsThumb2]>;
4594 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4595 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
4596 Requires<[HasT2ExtractPack, IsThumb2]>;
4598 // PUSH/POP aliases for STM/LDM
4599 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4600 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4601 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4602 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4604 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4605 def : t2InstAlias<"stm${p} $Rn, $regs",
4606 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4607 def : t2InstAlias<"stm${p} $Rn!, $regs",
4608 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4610 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4611 def : t2InstAlias<"ldm${p} $Rn, $regs",
4612 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4613 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4614 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4616 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4617 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4618 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4619 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4620 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4622 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4623 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4624 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4625 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4626 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4628 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4629 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4630 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4631 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4634 // Alias for RSB without the ".w" optional width specifier, and with optional
4635 // implied destination register.
4636 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4637 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4638 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4639 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4640 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4641 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4642 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4643 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4646 // SSAT/USAT optional shift operand.
4647 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4648 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4649 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4650 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4652 // STM w/o the .w suffix.
4653 def : t2InstAlias<"stm${p} $Rn, $regs",
4654 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4656 // Alias for STR, STRB, and STRH without the ".w" optional
4658 def : t2InstAlias<"str${p} $Rt, $addr",
4659 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4660 def : t2InstAlias<"strb${p} $Rt, $addr",
4661 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4662 def : t2InstAlias<"strh${p} $Rt, $addr",
4663 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4665 def : t2InstAlias<"str${p} $Rt, $addr",
4666 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4667 def : t2InstAlias<"strb${p} $Rt, $addr",
4668 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4669 def : t2InstAlias<"strh${p} $Rt, $addr",
4670 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4672 // Extend instruction optional rotate operand.
4673 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4674 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4675 Requires<[HasT2ExtractPack, IsThumb2]>;
4676 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4677 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4678 Requires<[HasT2ExtractPack, IsThumb2]>;
4679 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4680 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4681 Requires<[HasT2ExtractPack, IsThumb2]>;
4682 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4683 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4684 Requires<[HasT2ExtractPack, IsThumb2]>;
4686 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4687 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4688 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4689 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4690 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4691 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4692 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4693 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4695 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4696 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4697 Requires<[HasT2ExtractPack, IsThumb2]>;
4698 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4699 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4700 Requires<[HasT2ExtractPack, IsThumb2]>;
4701 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4702 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4703 Requires<[HasT2ExtractPack, IsThumb2]>;
4704 def : InstAlias<"uxtb16${p} $Rd, $Rm",
4705 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4706 Requires<[HasT2ExtractPack, IsThumb2]>;
4708 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4709 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4710 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4711 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4712 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4713 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4714 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4715 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4717 // Extend instruction w/o the ".w" optional width specifier.
4718 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4719 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4720 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4721 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4722 Requires<[HasT2ExtractPack, IsThumb2]>;
4723 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4724 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4726 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4727 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4728 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4729 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4730 Requires<[HasT2ExtractPack, IsThumb2]>;
4731 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4732 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4735 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4737 def : t2InstAlias<"mov${p} $Rd, $imm",
4738 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4739 def : t2InstAlias<"mvn${p} $Rd, $imm",
4740 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4741 // Same for AND <--> BIC
4742 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4743 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4744 pred:$p, cc_out:$s)>;
4745 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4746 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4747 pred:$p, cc_out:$s)>;
4748 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4749 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4750 pred:$p, cc_out:$s)>;
4751 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4752 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4753 pred:$p, cc_out:$s)>;
4754 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4755 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4756 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4757 pred:$p, cc_out:$s)>;
4758 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4759 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4760 pred:$p, cc_out:$s)>;
4761 // Same for CMP <--> CMN via t2_so_imm_neg
4762 def : t2InstAlias<"cmp${p} $Rd, $imm",
4763 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4764 def : t2InstAlias<"cmn${p} $Rd, $imm",
4765 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4768 // Wide 'mul' encoding can be specified with only two operands.
4769 def : t2InstAlias<"mul${p} $Rn, $Rm",
4770 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4772 // "neg" is and alias for "rsb rd, rn, #0"
4773 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4774 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4776 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4777 // these, unfortunately.
4778 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4779 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4780 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4781 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4783 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4784 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4785 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4786 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4788 // ADR w/o the .w suffix
4789 def : t2InstAlias<"adr${p} $Rd, $addr",
4790 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4792 // LDR(literal) w/ alternate [pc, #imm] syntax.
4793 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4794 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4795 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4796 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4797 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4798 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4799 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4800 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4801 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4802 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4803 // Version w/ the .w suffix.
4804 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4805 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
4806 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4807 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4808 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4809 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4810 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4811 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4812 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4813 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4815 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4816 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4818 // Pseudo instruction ldr Rt, =immediate
4820 : t2AsmPseudo<"ldr${p} $Rt, $immediate",
4821 (ins GPRnopc:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
4823 // PLD/PLDW/PLI with alternate literal form.
4824 def : t2InstAlias<"pld${p} $addr",
4825 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4826 def : InstAlias<"pli${p} $addr",
4827 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
4828 Requires<[IsThumb2,HasV7]>;