1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower ARM MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
16 #include "ARMAsmPrinter.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/IR/Constants.h"
21 #include "llvm/IR/Mangler.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstBuilder.h"
26 #include "llvm/MC/MCStreamer.h"
30 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
31 const MCSymbol *Symbol) {
33 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext);
34 switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) {
36 llvm_unreachable("Unknown target flag on symbol operand");
37 case ARMII::MO_NO_FLAG:
41 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext);
42 Expr = ARMMCExpr::createLower16(Expr, OutContext);
46 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext);
47 Expr = ARMMCExpr::createUpper16(Expr, OutContext);
51 if (!MO.isJTI() && MO.getOffset())
52 Expr = MCBinaryExpr::createAdd(Expr,
53 MCConstantExpr::create(MO.getOffset(),
56 return MCOperand::createExpr(Expr);
60 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
62 switch (MO.getType()) {
63 default: llvm_unreachable("unknown operand type");
64 case MachineOperand::MO_Register:
65 // Ignore all non-CPSR implicit register operands.
66 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
68 assert(!MO.getSubReg() && "Subregs should be eliminated!");
69 MCOp = MCOperand::createReg(MO.getReg());
71 case MachineOperand::MO_Immediate:
72 MCOp = MCOperand::createImm(MO.getImm());
74 case MachineOperand::MO_MachineBasicBlock:
75 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
76 MO.getMBB()->getSymbol(), OutContext));
78 case MachineOperand::MO_GlobalAddress: {
79 MCOp = GetSymbolRef(MO,
80 GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
83 case MachineOperand::MO_ExternalSymbol:
84 MCOp = GetSymbolRef(MO,
85 GetExternalSymbolSymbol(MO.getSymbolName()));
87 case MachineOperand::MO_JumpTableIndex:
88 MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
90 case MachineOperand::MO_ConstantPoolIndex:
91 if (Subtarget->genExecuteOnly())
92 llvm_unreachable("execute-only should not generate constant pools");
93 MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
95 case MachineOperand::MO_BlockAddress:
96 MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
98 case MachineOperand::MO_FPImmediate: {
99 APFloat Val = MO.getFPImm()->getValueAPF();
101 Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored);
102 MCOp = MCOperand::createFPImm(Val.convertToDouble());
105 case MachineOperand::MO_RegisterMask:
106 // Ignore call clobbers.
112 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
114 OutMI.setOpcode(MI->getOpcode());
116 // In the MC layer, we keep modified immediates in their encoded form
117 bool EncodeImms = false;
118 switch (MI->getOpcode()) {
144 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
145 const MachineOperand &MO = MI->getOperand(i);
148 if (AP.lowerOperand(MO, MCOp)) {
149 if (MCOp.isImm() && EncodeImms) {
150 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
154 OutMI.addOperand(MCOp);
159 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
161 if (MI.getParent()->getParent()->getInfo<ARMFunctionInfo>()
164 MI.emitError("An attempt to perform XRay instrumentation for a"
165 " Thumb function (not supported). Detected when emitting a sled.");
168 static const int8_t NoopsInSledCount = 6;
169 // We want to emit the following pattern:
174 // ; 6 NOP instructions (24 bytes)
177 // We need the 24 bytes (6 instructions) because at runtime, we'd be patching
178 // over the full 28 bytes (7 instructions) with the following pattern:
181 // MOVW r0, #<lower 16 bits of function ID>
182 // MOVT r0, #<higher 16 bits of function ID>
183 // MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit>
184 // MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit>
188 OutStreamer->EmitCodeAlignment(4);
189 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
190 OutStreamer->EmitLabel(CurSled);
191 auto Target = OutContext.createTempSymbol();
193 // Emit "B #20" instruction, which jumps over the next 24 bytes (because
194 // register pc is 8 bytes ahead of the jump instruction by the moment CPU
196 // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|.
197 // It is not clear why |addReg(0)| is needed (the last operand).
198 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
199 .addImm(ARMCC::AL).addReg(0));
202 Subtarget->getInstrInfo()->getNoopForElfTarget(Noop);
203 for (int8_t I = 0; I < NoopsInSledCount; I++)
205 OutStreamer->EmitInstruction(Noop, getSubtargetInfo());
208 OutStreamer->EmitLabel(Target);
209 recordSled(CurSled, MI, Kind);
212 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
214 EmitSled(MI, SledKind::FUNCTION_ENTER);
217 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
219 EmitSled(MI, SledKind::FUNCTION_EXIT);
222 void ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
224 EmitSled(MI, SledKind::TAIL_CALL);