1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains code to lower ARM MachineInstrs to their corresponding
12 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "MCTargetDesc/ARMBaseInfo.h"
21 #include "MCTargetDesc/ARMMCExpr.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstBuilder.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/Support/ErrorHandling.h"
38 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
39 const MCSymbol *Symbol) {
40 MCSymbolRefExpr::VariantKind SymbolVariant = MCSymbolRefExpr::VK_None;
41 if (MO.getTargetFlags() & ARMII::MO_SBREL)
42 SymbolVariant = MCSymbolRefExpr::VK_ARM_SBREL;
45 MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
46 switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) {
48 llvm_unreachable("Unknown target flag on symbol operand");
49 case ARMII::MO_NO_FLAG:
53 MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
54 Expr = ARMMCExpr::createLower16(Expr, OutContext);
58 MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
59 Expr = ARMMCExpr::createUpper16(Expr, OutContext);
63 if (!MO.isJTI() && MO.getOffset())
64 Expr = MCBinaryExpr::createAdd(Expr,
65 MCConstantExpr::create(MO.getOffset(),
68 return MCOperand::createExpr(Expr);
72 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
74 switch (MO.getType()) {
75 default: llvm_unreachable("unknown operand type");
76 case MachineOperand::MO_Register:
77 // Ignore all non-CPSR implicit register operands.
78 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
80 assert(!MO.getSubReg() && "Subregs should be eliminated!");
81 MCOp = MCOperand::createReg(MO.getReg());
83 case MachineOperand::MO_Immediate:
84 MCOp = MCOperand::createImm(MO.getImm());
86 case MachineOperand::MO_MachineBasicBlock:
87 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
88 MO.getMBB()->getSymbol(), OutContext));
90 case MachineOperand::MO_GlobalAddress:
91 MCOp = GetSymbolRef(MO,
92 GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
94 case MachineOperand::MO_ExternalSymbol:
95 MCOp = GetSymbolRef(MO,
96 GetExternalSymbolSymbol(MO.getSymbolName()));
98 case MachineOperand::MO_JumpTableIndex:
99 MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
101 case MachineOperand::MO_ConstantPoolIndex:
102 if (Subtarget->genExecuteOnly())
103 llvm_unreachable("execute-only should not generate constant pools");
104 MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
106 case MachineOperand::MO_BlockAddress:
107 MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
109 case MachineOperand::MO_FPImmediate: {
110 APFloat Val = MO.getFPImm()->getValueAPF();
112 Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored);
113 MCOp = MCOperand::createFPImm(Val.convertToDouble());
116 case MachineOperand::MO_RegisterMask:
117 // Ignore call clobbers.
123 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
125 OutMI.setOpcode(MI->getOpcode());
127 // In the MC layer, we keep modified immediates in their encoded form
128 bool EncodeImms = false;
129 switch (MI->getOpcode()) {
155 for (const MachineOperand &MO : MI->operands()) {
157 if (AP.lowerOperand(MO, MCOp)) {
158 if (MCOp.isImm() && EncodeImms) {
159 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
163 OutMI.addOperand(MCOp);
168 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
170 if (MI.getParent()->getParent()->getInfo<ARMFunctionInfo>()
173 MI.emitError("An attempt to perform XRay instrumentation for a"
174 " Thumb function (not supported). Detected when emitting a sled.");
177 static const int8_t NoopsInSledCount = 6;
178 // We want to emit the following pattern:
183 // ; 6 NOP instructions (24 bytes)
186 // We need the 24 bytes (6 instructions) because at runtime, we'd be patching
187 // over the full 28 bytes (7 instructions) with the following pattern:
190 // MOVW r0, #<lower 16 bits of function ID>
191 // MOVT r0, #<higher 16 bits of function ID>
192 // MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit>
193 // MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit>
197 OutStreamer->EmitCodeAlignment(4);
198 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
199 OutStreamer->EmitLabel(CurSled);
200 auto Target = OutContext.createTempSymbol();
202 // Emit "B #20" instruction, which jumps over the next 24 bytes (because
203 // register pc is 8 bytes ahead of the jump instruction by the moment CPU
205 // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|.
206 // It is not clear why |addReg(0)| is needed (the last operand).
207 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
208 .addImm(ARMCC::AL).addReg(0));
211 Subtarget->getInstrInfo()->getNoop(Noop);
212 for (int8_t I = 0; I < NoopsInSledCount; I++)
213 OutStreamer->EmitInstruction(Noop, getSubtargetInfo());
215 OutStreamer->EmitLabel(Target);
216 recordSled(CurSled, MI, Kind);
219 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
221 EmitSled(MI, SledKind::FUNCTION_ENTER);
224 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
226 EmitSled(MI, SledKind::FUNCTION_EXIT);
229 void ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
231 EmitSled(MI, SledKind::TAIL_CALL);