1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower ARM MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
16 #include "ARMAsmPrinter.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "MCTargetDesc/ARMBaseInfo.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCInstBuilder.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ErrorHandling.h"
39 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
40 const MCSymbol *Symbol) {
41 MCSymbolRefExpr::VariantKind SymbolVariant = MCSymbolRefExpr::VK_None;
42 if (MO.getTargetFlags() & ARMII::MO_SBREL)
43 SymbolVariant = MCSymbolRefExpr::VK_ARM_SBREL;
46 MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
47 switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) {
49 llvm_unreachable("Unknown target flag on symbol operand");
50 case ARMII::MO_NO_FLAG:
54 MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
55 Expr = ARMMCExpr::createLower16(Expr, OutContext);
59 MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
60 Expr = ARMMCExpr::createUpper16(Expr, OutContext);
64 if (!MO.isJTI() && MO.getOffset())
65 Expr = MCBinaryExpr::createAdd(Expr,
66 MCConstantExpr::create(MO.getOffset(),
69 return MCOperand::createExpr(Expr);
73 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
75 switch (MO.getType()) {
76 default: llvm_unreachable("unknown operand type");
77 case MachineOperand::MO_Register:
78 // Ignore all non-CPSR implicit register operands.
79 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
81 assert(!MO.getSubReg() && "Subregs should be eliminated!");
82 MCOp = MCOperand::createReg(MO.getReg());
84 case MachineOperand::MO_Immediate:
85 MCOp = MCOperand::createImm(MO.getImm());
87 case MachineOperand::MO_MachineBasicBlock:
88 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
89 MO.getMBB()->getSymbol(), OutContext));
91 case MachineOperand::MO_GlobalAddress:
92 MCOp = GetSymbolRef(MO,
93 GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
95 case MachineOperand::MO_ExternalSymbol:
96 MCOp = GetSymbolRef(MO,
97 GetExternalSymbolSymbol(MO.getSymbolName()));
99 case MachineOperand::MO_JumpTableIndex:
100 MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
102 case MachineOperand::MO_ConstantPoolIndex:
103 if (Subtarget->genExecuteOnly())
104 llvm_unreachable("execute-only should not generate constant pools");
105 MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
107 case MachineOperand::MO_BlockAddress:
108 MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
110 case MachineOperand::MO_FPImmediate: {
111 APFloat Val = MO.getFPImm()->getValueAPF();
113 Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored);
114 MCOp = MCOperand::createFPImm(Val.convertToDouble());
117 case MachineOperand::MO_RegisterMask:
118 // Ignore call clobbers.
124 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
126 OutMI.setOpcode(MI->getOpcode());
128 // In the MC layer, we keep modified immediates in their encoded form
129 bool EncodeImms = false;
130 switch (MI->getOpcode()) {
156 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
157 const MachineOperand &MO = MI->getOperand(i);
160 if (AP.lowerOperand(MO, MCOp)) {
161 if (MCOp.isImm() && EncodeImms) {
162 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
166 OutMI.addOperand(MCOp);
171 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
173 if (MI.getParent()->getParent()->getInfo<ARMFunctionInfo>()
176 MI.emitError("An attempt to perform XRay instrumentation for a"
177 " Thumb function (not supported). Detected when emitting a sled.");
180 static const int8_t NoopsInSledCount = 6;
181 // We want to emit the following pattern:
186 // ; 6 NOP instructions (24 bytes)
189 // We need the 24 bytes (6 instructions) because at runtime, we'd be patching
190 // over the full 28 bytes (7 instructions) with the following pattern:
193 // MOVW r0, #<lower 16 bits of function ID>
194 // MOVT r0, #<higher 16 bits of function ID>
195 // MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit>
196 // MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit>
200 OutStreamer->EmitCodeAlignment(4);
201 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
202 OutStreamer->EmitLabel(CurSled);
203 auto Target = OutContext.createTempSymbol();
205 // Emit "B #20" instruction, which jumps over the next 24 bytes (because
206 // register pc is 8 bytes ahead of the jump instruction by the moment CPU
208 // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|.
209 // It is not clear why |addReg(0)| is needed (the last operand).
210 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
211 .addImm(ARMCC::AL).addReg(0));
214 Subtarget->getInstrInfo()->getNoop(Noop);
215 for (int8_t I = 0; I < NoopsInSledCount; I++)
216 OutStreamer->EmitInstruction(Noop, getSubtargetInfo());
218 OutStreamer->EmitLabel(Target);
219 recordSled(CurSled, MI, Kind);
222 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
224 EmitSled(MI, SledKind::FUNCTION_ENTER);
227 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
229 EmitSled(MI, SledKind::FUNCTION_EXIT);
232 void ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
234 EmitSled(MI, SledKind::TAIL_CALL);