1 //===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the targeting of the RegisterBankInfo class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #include "ARMRegisterBankInfo.h"
15 #include "ARMInstrInfo.h" // For the register classes
16 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
23 #ifndef LLVM_BUILD_GLOBAL_ISEL
24 #error "You shouldn't build this"
27 // FIXME: TableGen this.
28 // If it grows too much and TableGen still isn't ready to do the job, extract it
29 // into an ARMGenRegisterBankInfo.def (similar to AArch64).
32 const uint32_t GPRCoverageData[] = {
34 (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) |
35 (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) |
36 (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) |
37 (1u << ARM::GPRnopc_and_hGPRRegClassID) |
38 (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) |
39 (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) |
40 (1u << ARM::hGPR_and_tcGPRRegClassID),
45 // FIXME: Some of the entries below this point can be safely removed once
46 // this is tablegenerated. It's only needed because of the hardcoded
47 // register class limit.
58 RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
59 RegisterBank *RegBanks[] = {&GPRRegBank};
61 RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
63 RegisterBankInfo::ValueMapping ValueMappings[] = {
64 {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}};
65 } // end namespace arm
66 } // end namespace llvm
68 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
69 : RegisterBankInfo(ARM::RegBanks, ARM::NumRegisterBanks) {
70 static bool AlreadyInit = false;
71 // We have only one set of register banks, whatever the subtarget
72 // is. Therefore, the initialization of the RegBanks table should be
73 // done only once. Indeed the table of all register banks
74 // (ARM::RegBanks) is unique in the compiler. At some point, it
75 // will get tablegen'ed and the whole constructor becomes empty.
80 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
82 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
84 // Initialize the GPR bank.
85 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
86 "Subclass not added?");
87 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
88 "Subclass not added?");
89 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
90 "Subclass not added?");
91 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
92 "Subclass not added?");
93 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
94 "Subclass not added?");
95 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
96 "Subclass not added?");
97 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
98 "Subclass not added?");
99 assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
102 const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
103 const TargetRegisterClass &RC) const {
106 switch (RC.getID()) {
108 case tGPR_and_tcGPRRegClassID:
109 return getRegBank(ARM::GPRRegBankID);
111 llvm_unreachable("Unsupported register kind");
114 llvm_unreachable("Switch should handle all register classes");
117 RegisterBankInfo::InstructionMapping
118 ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
119 auto Opc = MI.getOpcode();
121 // Try the default logic for non-generic instructions that are either copies
122 // or already have some operands assigned to banks.
123 if (!isPreISelGenericOpcode(Opc)) {
124 InstructionMapping Mapping = getInstrMappingImpl(MI);
125 if (Mapping.isValid())
129 using namespace TargetOpcode;
131 unsigned NumOperands = MI.getNumOperands();
132 const ValueMapping *OperandsMapping = &ARM::ValueMappings[0];
137 // FIXME: We're abusing the fact that everything lives in a GPR for now; in
138 // the real world we would use different mappings.
139 OperandsMapping = &ARM::ValueMappings[0];
142 OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr});
145 return InstructionMapping{};
148 return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,