1 //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the RegisterBankInfo class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
21 class TargetRegisterInfo;
25 GPRRegBankID = 0, // General purpose registers
28 } // end namespace ARM
30 /// This class provides the information for the target register banks.
31 class ARMRegisterBankInfo final : public RegisterBankInfo {
33 ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
36 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
38 InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
40 } // End llvm namespace.