1 //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the RegisterBankInfo class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
19 #define GET_REGBANK_DECLARATIONS
20 #include "ARMGenRegisterBank.inc"
24 class TargetRegisterInfo;
26 class ARMGenRegisterBankInfo : public RegisterBankInfo {
27 #define GET_TARGET_REGBANK_CLASS
28 #include "ARMGenRegisterBank.inc"
31 /// This class provides the information for the target register banks.
32 class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo {
34 ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
37 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
39 InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
41 } // End llvm namespace.