1 //=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
11 // below is to define a generic SchedWriteRes for every combination of
12 // latency and microOps. The naming conventions is to use a prefix, one field
13 // for latency, and one or more microOp count/type designators.
16 // MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
18 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
19 // 11 micro-ops to be issued as follows: one to I pipe, six to S pipes and
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 // Define Generic 1 micro-op types
27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
32 let ResourceCycles = [17]; }
33 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
34 let ResourceCycles = [18]; }
35 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
36 let ResourceCycles = [19]; }
37 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
38 let ResourceCycles = [20]; }
39 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
40 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
41 def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2; }
42 def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; }
43 def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
44 def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; }
45 def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; }
46 def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
47 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
48 let ResourceCycles = [32]; }
49 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
50 let ResourceCycles = [32]; }
51 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
52 let ResourceCycles = [35]; }
53 def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
54 def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
55 def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
56 def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
58 // A57Write_3cyc_1L - A57Write_20cyc_1L
59 foreach Lat = 3-20 in {
60 def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
65 // A57Write_4cyc_1S - A57Write_16cyc_1S
66 foreach Lat = 4-16 in {
67 def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
72 def A57Write_4cyc_1M : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
73 def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
74 def A57Write_4cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 4; }
75 def A57Write_5cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 5; }
76 def A57Write_6cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 6; }
77 def A57Write_6cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 6; }
78 def A57Write_8cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 8; }
79 def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
80 def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
81 def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
84 //===----------------------------------------------------------------------===//
85 // Define Generic 2 micro-op types
87 def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
90 let ResourceCycles = [32, 32];
92 def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
97 def A57Write_6cyc_1V_1X : SchedWriteRes<[A57UnitV,
102 def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
107 def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,
112 def A57Write_9cyc_1L_1V : SchedWriteRes<[A57UnitL,
117 def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
121 def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
125 def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {
129 def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
133 def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
137 def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,
142 def A57Write_5cyc_1I_1M : SchedWriteRes<[A57UnitI,
147 def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
151 def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
155 def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
160 def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
164 def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,
169 def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,
174 def A57Write_1cyc_1S_1I : SchedWriteRes<[A57UnitS,
179 def A57Write_2cyc_1S_1I : SchedWriteRes<[A57UnitS,
184 def A57Write_3cyc_1S_1I : SchedWriteRes<[A57UnitS,
189 def A57Write_1cyc_1S_1M : SchedWriteRes<[A57UnitS,
194 def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,
199 def A57Write_3cyc_1B_1I : SchedWriteRes<[A57UnitB,
204 def A57Write_6cyc_1B_1L : SchedWriteRes<[A57UnitB,
209 def A57Write_2cyc_1I_1M : SchedWriteRes<[A57UnitI,
214 def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {
218 def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
222 def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
225 let ResourceCycles = [18, 18];
227 def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
232 def A57Write_4cyc_1I_1M : SchedWriteRes<[A57UnitI,
238 // A57Write_3cyc_1L_1I - A57Write_20cyc_1L_1I
239 foreach Lat = 3-20 in {
240 def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
241 let Latency = Lat; let NumMicroOps = 2;
245 def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
250 def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
255 def A57Write_4cyc_1S_1V : SchedWriteRes<[A57UnitS,
260 def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
265 // A57Write_4cyc_1S_1I - A57Write_16cyc_1S_1I
266 foreach Lat = 4-16 in {
267 def A57Write_#Lat#cyc_1S_1I : SchedWriteRes<[A57UnitS, A57UnitI]> {
268 let Latency = Lat; let NumMicroOps = 2;
272 def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
278 //===----------------------------------------------------------------------===//
279 // Define Generic 3 micro-op types
281 def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
285 def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,
286 A57UnitS, A57UnitS]> {
290 def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,
296 def A57Write_3cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,
302 def A57Write_4cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,
308 def A57Write_4cyc_1I_1L_1M : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitM]> {
312 def A57Write_8cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,
318 def A57Write_9cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,