contrib/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td

   1 //=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
  11 // below is to define a generic SchedWriteRes for every combination of
  12 // latency and microOps. The naming conventions is to use a prefix, one field
  13 // for latency, and one or more microOp count/type designators.
  14 //   Prefix: A57Write
  15 //   Latency: #cyc
  16 //   MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
  17 //
  18 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
  19 //      11 micro-ops to be issued as follows: one to I pipe, six to S pipes and
  20 //      four to V pipes.
  21 //
  22 //===----------------------------------------------------------------------===//
  23
  24 //===----------------------------------------------------------------------===//
  25 // Define Generic 1 micro-op types
  26
  27 def A57Write_5cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 5;  }
  28 def A57Write_5cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 5;  }
  29 def A57Write_5cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
  30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
  31 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
  32                                                     let ResourceCycles = [17]; }
  33 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
  34                                                     let ResourceCycles = [18]; }
  35 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
  36                                                     let ResourceCycles = [19]; }
  37 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
  38                                                     let ResourceCycles = [20]; }
  39 def A57Write_1cyc_1B  : SchedWriteRes<[A57UnitB]> { let Latency = 1;  }
  40 def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;  }
  41 def A57Write_2cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 2;  }
  42 def A57Write_3cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 3;  }
  43 def A57Write_1cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 1;  }
  44 def A57Write_2cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 2;  }
  45 def A57Write_3cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 3;  }
  46 def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;  }
  47 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
  48                                                     let ResourceCycles = [32]; }
  49 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
  50                                                     let ResourceCycles = [32]; }
  51 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
  52                                                     let ResourceCycles = [35]; }
  53 def A57Write_3cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 3;  }
  54 def A57Write_3cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 3;  }
  55 def A57Write_3cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 3;  }
  56 def A57Write_3cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 3;  }
  57
  58 // A57Write_3cyc_1L - A57Write_20cyc_1L
  59 foreach Lat = 3-20 in {
  60   def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
  61     let Latency = Lat;
  62   }
  63 }
  64
  65 // A57Write_4cyc_1S - A57Write_16cyc_1S
  66 foreach Lat = 4-16 in {
  67   def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
  68     let Latency = Lat;
  69   }
  70 }
  71
  72 def A57Write_4cyc_1M  : SchedWriteRes<[A57UnitL]> { let Latency = 4;  }
  73 def A57Write_4cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
  74 def A57Write_4cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 4;  }
  75 def A57Write_5cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 5;  }
  76 def A57Write_6cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 6;  }
  77 def A57Write_6cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 6;  }
  78 def A57Write_8cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 8;  }
  79 def A57Write_9cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
  80 def A57Write_6cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 6;  }
  81 def A57Write_6cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 6;  }
  82
  83
  84 //===----------------------------------------------------------------------===//
  85 // Define Generic 2 micro-op types
  86
  87 def A57Write_64cyc_2X    : SchedWriteRes<[A57UnitX, A57UnitX]> {
  88   let Latency     = 64;
  89   let NumMicroOps = 2;
  90   let ResourceCycles = [32, 32];
  91 }
  92 def A57Write_6cyc_1I_1L  : SchedWriteRes<[A57UnitI,
  93                                           A57UnitL]> {
  94   let Latency     = 6;
  95   let NumMicroOps = 2;
  96 }
  97 def A57Write_6cyc_1V_1X  : SchedWriteRes<[A57UnitV,
  98                                           A57UnitX]> {
  99   let Latency     = 6;
 100   let NumMicroOps = 2;
 101 }
 102 def A57Write_7cyc_1V_1X  : SchedWriteRes<[A57UnitV,
 103                                           A57UnitX]> {
 104   let Latency     = 7;
 105   let NumMicroOps = 2;
 106 }
 107 def A57Write_8cyc_1L_1V  : SchedWriteRes<[A57UnitL,
 108                                           A57UnitV]> {
 109   let Latency     = 8;
 110   let NumMicroOps = 2;
 111 }
 112 def A57Write_9cyc_1L_1V  : SchedWriteRes<[A57UnitL,
 113                                           A57UnitV]> {
 114   let Latency     = 9;
 115   let NumMicroOps = 2;
 116 }
 117 def A57Write_9cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 118   let Latency     = 9;
 119   let NumMicroOps = 2;
 120 }
 121 def A57Write_8cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
 122   let Latency     = 8;
 123   let NumMicroOps = 2;
 124 }
 125 def A57Write_6cyc_2L     : SchedWriteRes<[A57UnitL, A57UnitL]> {
 126   let Latency     = 6;
 127   let NumMicroOps = 2;
 128 }
 129 def A57Write_6cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 130   let Latency     = 6;
 131   let NumMicroOps = 2;
 132 }
 133 def A57Write_6cyc_2W     : SchedWriteRes<[A57UnitW, A57UnitW]> {
 134   let Latency     = 6;
 135   let NumMicroOps = 2;
 136 }
 137 def A57Write_5cyc_1I_1L  : SchedWriteRes<[A57UnitI,
 138                                           A57UnitL]> {
 139   let Latency     = 5;
 140   let NumMicroOps = 2;
 141 }
 142 def A57Write_5cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 143                                           A57UnitM]> {
 144   let Latency     = 5;
 145   let NumMicroOps = 2;
 146 }
 147 def A57Write_5cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 148   let Latency     = 5;
 149   let NumMicroOps = 2;
 150 }
 151 def A57Write_5cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
 152   let Latency     = 5;
 153   let NumMicroOps = 2;
 154 }
 155 def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
 156                                           A57UnitV]> {
 157   let Latency     = 10;
 158   let NumMicroOps = 2;
 159 }
 160 def A57Write_10cyc_2V    : SchedWriteRes<[A57UnitV, A57UnitV]> {
 161   let Latency     = 10;
 162   let NumMicroOps = 2;
 163 }
 164 def A57Write_1cyc_1B_1I  : SchedWriteRes<[A57UnitB,
 165                                           A57UnitI]> {
 166   let Latency     = 1;
 167   let NumMicroOps = 2;
 168 }
 169 def A57Write_1cyc_1I_1S  : SchedWriteRes<[A57UnitI,
 170                                           A57UnitS]> {
 171   let Latency     = 1;
 172   let NumMicroOps = 2;
 173 }
 174 def A57Write_1cyc_1S_1I  : SchedWriteRes<[A57UnitS,
 175                                           A57UnitI]> {
 176   let Latency     = 1;
 177   let NumMicroOps = 2;
 178 }
 179 def A57Write_2cyc_1S_1I  : SchedWriteRes<[A57UnitS,
 180                                           A57UnitI]> {
 181   let Latency     = 2;
 182   let NumMicroOps = 2;
 183 }
 184 def A57Write_3cyc_1S_1I  : SchedWriteRes<[A57UnitS,
 185                                           A57UnitI]> {
 186   let Latency     = 3;
 187   let NumMicroOps = 2;
 188 }
 189 def A57Write_1cyc_1S_1M  : SchedWriteRes<[A57UnitS,
 190                                           A57UnitM]> {
 191   let Latency     = 1;
 192   let NumMicroOps = 2;
 193 }
 194 def A57Write_2cyc_1B_1I  : SchedWriteRes<[A57UnitB,
 195                                           A57UnitI]> {
 196   let Latency     = 2;
 197   let NumMicroOps = 2;
 198 }
 199 def A57Write_3cyc_1B_1I  : SchedWriteRes<[A57UnitB,
 200                                           A57UnitI]> {
 201   let Latency     = 3;
 202   let NumMicroOps = 2;
 203 }
 204 def A57Write_6cyc_1B_1L  : SchedWriteRes<[A57UnitB,
 205                                           A57UnitI]> {
 206   let Latency     = 6;
 207   let NumMicroOps = 2;
 208 }
 209 def A57Write_2cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 210                                           A57UnitM]> {
 211   let Latency     = 2;
 212   let NumMicroOps = 2;
 213 }
 214 def A57Write_2cyc_2S     : SchedWriteRes<[A57UnitS, A57UnitS]> {
 215   let Latency     = 2;
 216   let NumMicroOps = 2;
 217 }
 218 def A57Write_2cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 219   let Latency     = 2;
 220   let NumMicroOps = 2;
 221 }
 222 def A57Write_36cyc_2X    : SchedWriteRes<[A57UnitX, A57UnitX]> {
 223   let Latency     = 36;
 224   let NumMicroOps = 2;
 225   let ResourceCycles = [18, 18];
 226 }
 227 def A57Write_3cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 228                                           A57UnitM]> {
 229   let Latency     = 3;
 230   let NumMicroOps = 2;
 231 }
 232 def A57Write_4cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 233                                           A57UnitM]> {
 234   let Latency     = 4;
 235   let NumMicroOps = 2;
 236 }
 237
 238 // A57Write_3cyc_1L_1I - A57Write_20cyc_1L_1I
 239 foreach Lat = 3-20 in {
 240   def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
 241     let Latency = Lat; let NumMicroOps = 2;
 242   }
 243 }
 244
 245 def A57Write_3cyc_1I_1S  : SchedWriteRes<[A57UnitI,
 246                                           A57UnitS]> {
 247   let Latency     = 3;
 248   let NumMicroOps = 2;
 249 }
 250 def A57Write_3cyc_1S_1V  : SchedWriteRes<[A57UnitS,
 251                                           A57UnitV]> {
 252   let Latency     = 3;
 253   let NumMicroOps = 2;
 254 }
 255 def A57Write_4cyc_1S_1V  : SchedWriteRes<[A57UnitS,
 256                                           A57UnitV]> {
 257   let Latency     = 4;
 258   let NumMicroOps = 2;
 259 }
 260 def A57Write_3cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 261   let Latency     = 3;
 262   let NumMicroOps = 2;
 263 }
 264
 265 // A57Write_4cyc_1S_1I - A57Write_16cyc_1S_1I
 266 foreach Lat = 4-16 in {
 267   def A57Write_#Lat#cyc_1S_1I : SchedWriteRes<[A57UnitS, A57UnitI]> {
 268     let Latency = Lat; let NumMicroOps = 2;
 269   }
 270 }
 271
 272 def A57Write_4cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
 273   let Latency     = 4;
 274   let NumMicroOps = 2;
 275 }
 276
 277
 278 //===----------------------------------------------------------------------===//
 279 // Define Generic 3 micro-op types
 280
 281 def A57Write_10cyc_3V       : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
 282   let Latency     = 10;
 283   let NumMicroOps = 3;
 284 }
 285 def A57Write_2cyc_1I_2S     : SchedWriteRes<[A57UnitI,
 286                                              A57UnitS, A57UnitS]> {
 287   let Latency     = 2;
 288   let NumMicroOps = 3;
 289 }
 290 def A57Write_3cyc_1I_1S_1V  : SchedWriteRes<[A57UnitI,
 291                                              A57UnitS,
 292                                              A57UnitV]> {
 293   let Latency     = 3;
 294   let NumMicroOps = 3;
 295 }
 296 def A57Write_3cyc_1S_1V_1I  : SchedWriteRes<[A57UnitS,
 297                                              A57UnitV,
 298                                              A57UnitI]> {
 299   let Latency     = 3;
 300   let NumMicroOps = 3;
 301 }
 302 def A57Write_4cyc_1S_1V_1I  : SchedWriteRes<[A57UnitS,
 303                                              A57UnitV,
 304                                              A57UnitI]> {
 305   let Latency     = 4;
 306   let NumMicroOps = 3;
 307 }
 308 def A57Write_4cyc_1I_1L_1M  : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitM]> {
 309   let Latency     = 4;
 310   let NumMicroOps = 3;
 311 }
 312 def A57Write_8cyc_1L_1V_1I  : SchedWriteRes<[A57UnitL,
 313                                              A57UnitV,
 314                                              A57UnitI]> {
 315   let Latency     = 8;
 316   let NumMicroOps = 3;
 317 }
 318 def A57Write_9cyc_1L_1V_1I  : SchedWriteRes<[A57UnitL,
 319                                              A57UnitV,
 320                                              A57UnitI]> {
 321   let Latency     = 9;
 322   let NumMicroOps = 3;
 323 }