1 //=- ARMScheduleSwift.td - Swift Scheduling Definitions -*- tablegen -*----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the Swift processor..
12 //===----------------------------------------------------------------------===//
14 // ===---------------------------------------------------------------------===//
15 // This section contains legacy support for itineraries. This is
16 // required until SD and PostRA schedulers are replaced by MachineScheduler.
18 def SW_DIS0 : FuncUnit;
19 def SW_DIS1 : FuncUnit;
20 def SW_DIS2 : FuncUnit;
22 def SW_ALU0 : FuncUnit;
23 def SW_ALU1 : FuncUnit;
25 def SW_IDIV : FuncUnit;
26 def SW_FDIV : FuncUnit;
28 // FIXME: Need bypasses.
29 // FIXME: Model the multiple stages of IIC_iMOVix2, IIC_iMOVix2addpc, and
30 // IIC_iMOVix2ld better.
31 // FIXME: Model the special immediate shifts that are not microcoded.
32 // FIXME: Do we need to model the fact that uses of r15 in a micro-op force it
33 // to issue on pipe 1?
34 // FIXME: Model the pipelined behavior of CMP / TST instructions.
35 // FIXME: Better model the microcode stages of multiply instructions, especially
36 // conditional variants.
37 // FIXME: Add preload instruction when it is documented.
38 // FIXME: Model non-pipelined nature of FP div / sqrt unit.
40 // Swift machine model for scheduling and other instruction cost heuristics.
41 def SwiftModel : SchedMachineModel {
42 let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
43 let MicroOpBufferSize = 45; // Based on NEON renamed registers.
45 let MispredictPenalty = 14; // A branch direction mispredict.
46 let CompleteModel = 0; // FIXME: Remove if all instructions are covered.
50 def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>;
52 // Swift resource mapping.
53 let SchedModel = SwiftModel in {
54 // Processor resources.
55 def SwiftUnitP01 : ProcResource<2>; // ALU unit.
56 def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit.
57 def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit.
58 def SwiftUnitP2 : ProcResource<1>; // LS unit.
59 def SwiftUnitDiv : ProcResource<1>;
61 // Generic resource requirements.
62 def SwiftWriteP0OneCycle : SchedWriteRes<[SwiftUnitP0]>;
63 def SwiftWriteP0TwoCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 2; }
64 def SwiftWriteP0FourCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 4; }
65 def SwiftWriteP0SixCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 6; }
66 def SwiftWriteP0P1FourCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> {
69 def SwiftWriteP0P1SixCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> {
72 def SwiftWriteP01OneCycle : SchedWriteRes<[SwiftUnitP01]>;
73 def SwiftWriteP1TwoCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 2; }
74 def SwiftWriteP1FourCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 4; }
75 def SwiftWriteP1SixCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 6; }
76 def SwiftWriteP1EightCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 8; }
77 def SwiftWriteP1TwelveCyc : SchedWriteRes<[SwiftUnitP1]> { let Latency = 12; }
78 def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>;
79 def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>;
80 def SwiftWriteP01TwoCycle : SchedWriteRes<[SwiftUnitP01]> { let Latency = 2; }
81 def SwiftWriteP01ThreeCycleTwoUops : SchedWriteRes<[SwiftUnitP01,
86 def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> {
89 let ResourceCycles = [3];
91 // Plain load without writeback.
92 def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> {
95 def SwiftWriteP2FourCycle : SchedWriteRes<[SwiftUnitP2]> {
98 // A store does not write to a register.
99 def SwiftWriteP2 : SchedWriteRes<[SwiftUnitP2]> {
102 foreach Num = 1-4 in {
103 def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>;
105 def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle,
106 SwiftWriteP01OneCycle,
107 SwiftWriteP2ThreeCycle]>;
108 // 4.2.4 Arithmetic and Logical.
109 // ALU operation register shifted by immediate variant.
110 def SwiftWriteALUsi : SchedWriteVariant<[
111 // lsl #2, lsl #1, or lsr #1.
112 SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01TwoCycle]>,
113 SchedVar<NoSchedPred, [WriteALU]>
115 def SwiftWriteALUsr : SchedWriteVariant<[
116 SchedVar<IsPredicatedPred, [SwiftWriteP01ThreeCycleTwoUops]>,
117 SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
119 def SwiftWriteALUSsr : SchedWriteVariant<[
120 SchedVar<IsPredicatedPred, [SwiftWriteP0ThreeCycleThreeUops]>,
121 SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
123 def SwiftReadAdvanceALUsr : SchedReadVariant<[
124 SchedVar<IsPredicatedPred, [SchedReadAdvance<2>]>,
125 SchedVar<NoSchedPred, [NoReadAdvance]>
127 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
128 // AND,BIC,EOR,ORN,ORR
129 // CLZ,RBIT,REV,REV16,REVSH,PKH
130 def : WriteRes<WriteALU, [SwiftUnitP01]>;
131 def : SchedAlias<WriteALUsi, SwiftWriteALUsi>;
132 def : SchedAlias<WriteALUsr, SwiftWriteALUsr>;
133 def : SchedAlias<WriteALUSsr, SwiftWriteALUSsr>;
134 def : ReadAdvance<ReadALU, 0>;
135 def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>;
136 def : SchedAlias<WriteLd, SwiftWriteP2ThreeCycle>;
137 def : SchedAlias<WriteST, SwiftWriteP2>;
140 def SwiftChooseShiftKindP01OneOrTwoCycle : SchedWriteVariant<[
141 SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01OneCycle]>,
142 SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
145 // 4.2.5 Integer comparison
146 def : WriteRes<WriteCMP, [SwiftUnitP01]>;
147 def : SchedAlias<WriteCMPsi, SwiftChooseShiftKindP01OneOrTwoCycle>;
148 def : SchedAlias<WriteCMPsr, SwiftWriteP01TwoCycle>;
153 // MOV(register-shiftedregister) MVN(register-shiftedregister)
157 // Sign/Zero extension
158 def : InstRW<[SwiftWriteP01OneCycle],
159 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
160 "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH",
162 // Pseudo instructions.
163 def : InstRW<[SwiftWriteP01OneCycle2x],
164 (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi32imm",
165 "t2MOVi32imm", "t2MOV_ga_dyn")>;
166 def : InstRW<[SwiftWriteP01OneCycle3x],
167 (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel")>;
168 def : InstRW<[SwiftWriteP01OneCycle2x_load],
169 (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>;
171 def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>;
173 def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[
174 SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCycleTwoUops ]>,
175 SchedVar<NoSchedPred, [ SwiftWriteP0OneCycle ]>
180 def : InstRW<[SwiftPredP0OneOrTwoCycle], (instregex "SEL", "t2SEL")>;
183 // BFI,BFC, SBFX,UBFX
184 def : InstRW< [SwiftWriteP01TwoCycle],
185 (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI",
186 "(t|t2)UBFX", "(t|t2)SBFX")>;
188 // 4.2.9 Saturating arithmetic
189 def : InstRW< [SwiftWriteP01TwoCycle],
190 (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT",
191 "USAT16", "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX",
192 "UQADD8", "UQADD16","UQSUB8","UQSUB16","UQASX","UQSAX", "t2QADD",
193 "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT",
194 "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX",
195 "t2UQADD8", "t2UQADD16","t2UQSUB8","t2UQSUB16","t2UQASX","t2UQSAX")>;
197 // 4.2.10 Parallel Arithmetic
199 def : InstRW< [SwiftWriteALUsr],
200 (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX",
201 "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8",
202 "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8",
203 "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX")>;
205 def : InstRW< [SwiftWriteP01TwoCycle],
206 (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX",
207 "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16",
208 "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16",
209 "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16",
210 "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX",
211 "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>;
213 // 4.2.11 Sum of Absolute Difference
214 def : InstRW< [SwiftWriteP0P1FourCycle], (instregex "USAD8") >;
215 def : InstRW<[SwiftWriteP0P1FourCycle, ReadALU, ReadALU, SchedReadAdvance<2>],
216 (instregex "USADA8")>;
218 // 4.2.12 Integer Multiply (32-bit result)
220 def : InstRW< [SwiftWriteP0FourCycle],
221 (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
222 "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL",
223 "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT",
224 "t2SMULWB", "t2SMULWT", "t2SMUSD")>;
226 def SwiftWriteP0P01FiveCycleTwoUops :
227 SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
231 def SwiftPredP0P01FourFiveCycle : SchedWriteVariant<[
232 SchedVar<IsPredicatedPred, [ SwiftWriteP0P01FiveCycleTwoUops ]>,
233 SchedVar<NoSchedPred, [ SwiftWriteP0FourCycle ]>
236 def SwiftReadAdvanceFourCyclesPred : SchedReadVariant<[
237 SchedVar<IsPredicatedPred, [SchedReadAdvance<4>]>,
238 SchedVar<NoSchedPred, [ReadALU]>
241 // Multiply accumulate, three sources
242 def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
243 SwiftReadAdvanceFourCyclesPred],
244 (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
245 "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS",
248 // 4.2.13 Integer Multiply (32-bit result, Q flag)
249 def : InstRW< [SwiftWriteP0FourCycle],
250 (instregex "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX")>;
251 def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
252 SwiftReadAdvanceFourCyclesPred],
253 (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX",
254 "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT",
255 "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT")>;
256 def : InstRW< [SwiftPredP0P01FourFiveCycle],
257 (instregex "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX")>;
259 def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
262 let ResourceCycles = [2, 1];
264 def SwiftWrite1Cycle : SchedWriteRes<[]> {
268 def SwiftWrite5Cycle : SchedWriteRes<[]> {
272 def SwiftWrite6Cycle : SchedWriteRes<[]> {
277 // 4.2.14 Integer Multiply, Long
278 def : InstRW< [SwiftP0P0P01FiveCycle, SwiftWrite5Cycle],
279 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
281 def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
284 let ResourceCycles = [2, 3];
287 // Aliasing sub-target specific WriteRes to generic ones
288 def : SchedAlias<WriteMUL16, SwiftWriteP0FourCycle>;
289 def : SchedAlias<WriteMUL32, SwiftWriteP0FourCycle>;
290 def : SchedAlias<WriteMUL64Lo, SwiftP0P0P01FiveCycle>;
291 def : SchedAlias<WriteMUL64Hi, SwiftWrite5Cycle>;
292 def : SchedAlias<WriteMAC16, SwiftPredP0P01FourFiveCycle>;
293 def : SchedAlias<WriteMAC32, SwiftPredP0P01FourFiveCycle>;
294 def : SchedAlias<WriteMAC64Lo, SwiftWrite5Cycle>;
295 def : SchedAlias<WriteMAC64Hi, Swift2P03P01FiveCycle>;
296 def : ReadAdvance<ReadMUL, 0>;
297 def : SchedAlias<ReadMAC, SwiftReadAdvanceFourCyclesPred>;
299 // 4.2.15 Integer Multiply Accumulate, Long
300 // 4.2.16 Integer Multiply Accumulate, Dual
301 // 4.2.17 Integer Multiply Accumulate Accumulate, Long
302 // We are being a bit inaccurate here.
303 def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU,
304 SchedReadAdvance<4>, SchedReadAdvance<3>],
305 (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
306 "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
307 "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", "t2SMLALBT",
308 "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX",
311 def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
314 let ResourceCycles = [1, 14];
316 // 4.2.18 Integer Divide
317 def : WriteRes<WriteDIV, [SwiftUnitDiv]>; // Workaround.
318 def : InstRW <[SwiftDiv],
319 (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
321 // 4.2.19 Integer Load Single Element
322 // 4.2.20 Integer Load Signextended
323 def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
327 def SwiftWriteP2P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
331 def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01,
336 def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> {
340 def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2,
345 def SwiftWrBackOne : SchedWriteRes<[]> {
349 def SwiftWriteLdFour : SchedWriteRes<[]> {
354 def : InstRW<[SwiftWriteP2ThreeCycle],
355 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
356 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
357 "tLDR(r|i|spi|pci|pciASM)")>;
358 def : InstRW<[SwiftWriteP2ThreeCycle],
359 (instregex "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>;
360 def : InstRW<[SwiftWriteP2P01FourCycle],
361 (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$",
362 "t2LDRpci_pic", "tLDRS(B|H)")>;
363 def : InstRW<[SwiftWriteP2P01ThreeCycle, SwiftWrBackOne],
364 (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
365 "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
366 "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>;
367 def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne],
368 (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
369 "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T")>;
371 // 4.2.21 Integer Dual Load
373 def : InstRW<[SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour],
374 (instregex "t2LDRDi8", "LDRD$")>;
375 def : InstRW<[SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne],
376 (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>;
378 // 4.2.22 Integer Load, Multiple
380 foreach Lat = 3-25 in {
381 def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> {
384 def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> {
390 foreach NumAddr = 1-16 in {
391 def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NumAddr>;
393 def SwiftWriteLDMAddrNoWB : SchedWriteRes<[SwiftUnitP01]> { let Latency = 0; }
394 def SwiftWriteLDMAddrWB : SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]>;
395 def SwiftWriteLM : SchedWriteVariant<[
396 SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy]>,
397 SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
399 SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
400 SwiftWriteLM5Cy, SwiftWriteLM6Cy]>,
401 SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
402 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
404 SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
405 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
406 SwiftWriteLM7Cy, SwiftWriteLM8Cy]>,
407 SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
408 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
409 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
411 SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
412 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
413 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
414 SwiftWriteLM9Cy, SwiftWriteLM10Cy]>,
415 SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
416 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
417 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
418 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
420 SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
421 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
422 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
423 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
424 SwiftWriteLM11Cy, SwiftWriteLM12Cy]>,
425 SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
426 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
427 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
428 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
429 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
431 SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
432 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
433 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
434 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
435 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
436 SwiftWriteLM13Cy, SwiftWriteLM14Cy]>,
437 SchedVar<SwiftLMAddr13Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
438 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
439 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
440 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
441 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
442 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
444 SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
445 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
446 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
447 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
448 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
449 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
450 SwiftWriteLM15Cy, SwiftWriteLM16Cy]>,
451 SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
452 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
453 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
454 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
455 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
456 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
457 SwiftWriteLM15Cy, SwiftWriteLM16Cy,
459 SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
460 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
461 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
462 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
463 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
464 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
465 SwiftWriteLM15Cy, SwiftWriteLM16Cy,
466 SwiftWriteLM17Cy, SwiftWriteLM18Cy]>,
467 // Unknow number of registers, just use resources for two registers.
468 SchedVar<NoSchedPred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
469 SwiftWriteLM5CyNo, SwiftWriteLM6CyNo,
470 SwiftWriteLM7CyNo, SwiftWriteLM8CyNo,
471 SwiftWriteLM9CyNo, SwiftWriteLM10CyNo,
472 SwiftWriteLM11CyNo, SwiftWriteLM12CyNo,
473 SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
474 SwiftWriteLM15CyNo, SwiftWriteLM16CyNo,
475 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo]>
477 ]> { let Variadic=1; }
479 def : InstRW<[SwiftWriteLM, SwiftWriteLDMAddrNoWB],
480 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
481 "(t|sys)LDM(IA|DA|DB|IB)$")>;
482 def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM],
483 (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/
484 "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
485 def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle],
486 (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>;
487 // 4.2.23 Integer Store, Single Element
488 def : InstRW<[SwiftWriteP2],
489 (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX",
490 "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
492 def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2],
493 (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)",
494 "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)",
495 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
496 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
498 // 4.2.24 Integer Store, Dual
499 def : InstRW<[SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle],
500 (instregex "STRD$", "t2STRDi8")>;
501 def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2, SwiftWriteP2,
502 SwiftWriteP01OneCycle],
503 (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>;
505 // 4.2.25 Integer Store, Multiple
506 def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
510 foreach NumAddr = 1-16 in {
511 def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>;
513 def SwiftWriteSTM : SchedWriteVariant<[
514 SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM2]>,
515 SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM3]>,
516 SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM4]>,
517 SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM5]>,
518 SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM6]>,
519 SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM7]>,
520 SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM8]>,
521 SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM9]>,
522 SchedVar<SwiftLMAddr10Pred,[SwiftWriteSTM10]>,
523 SchedVar<SwiftLMAddr11Pred,[SwiftWriteSTM11]>,
524 SchedVar<SwiftLMAddr12Pred,[SwiftWriteSTM12]>,
525 SchedVar<SwiftLMAddr13Pred,[SwiftWriteSTM13]>,
526 SchedVar<SwiftLMAddr14Pred,[SwiftWriteSTM14]>,
527 SchedVar<SwiftLMAddr15Pred,[SwiftWriteSTM15]>,
528 SchedVar<SwiftLMAddr16Pred,[SwiftWriteSTM16]>,
529 // Unknow number of registers, just use resources for two registers.
530 SchedVar<NoSchedPred, [SwiftWriteSTM2]>
532 def : InstRW<[SwiftWriteSTM],
533 (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
534 def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM],
535 (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
538 // LDRLIT pseudo instructions, they expand to LDR + PICADD
539 def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU],
540 (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>;
541 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
542 def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2ThreeCycle],
543 (instregex "LDRLIT_ga_pcrel_ldr")>;
546 def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; }
547 def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }
548 def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; }
551 def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
552 def : InstRW<[WriteNoop], (instregex "t2IT", "IT", "NOP")>;
554 // 4.2.28 Advanced SIMD, Integer, 2 cycle
555 def : InstRW<[SwiftWriteP0TwoCycle],
556 (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL",
557 "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi",
558 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
559 "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL", "VQSHLU", "VBIF",
560 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
562 def : InstRW<[SwiftWriteP1TwoCycle],
563 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
565 // 4.2.29 Advanced SIMD, Integer, 4 cycle
566 // 4.2.30 Advanced SIMD, Integer with Accumulate
567 def : InstRW<[SwiftWriteP0FourCycle],
568 (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
569 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
570 "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD",
572 def : InstRW<[SwiftWriteP1FourCycle],
573 (instregex "VRECPE", "VRSQRTE")>;
575 // 4.2.31 Advanced SIMD, Add and Shift with Narrow
576 def : InstRW<[SwiftWriteP0P1FourCycle],
577 (instregex "VADDHN", "VSUBHN", "VSHRN")>;
578 def : InstRW<[SwiftWriteP0P1SixCycle],
579 (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
580 "VQRSHRN", "VQRSHRUN")>;
582 // 4.2.32 Advanced SIMD, Vector Table Lookup
583 foreach Num = 1-4 in {
584 def SwiftWrite#Num#xP1TwoCycle : WriteSequence<[SwiftWriteP1TwoCycle], Num>;
586 def : InstRW<[SwiftWrite1xP1TwoCycle],
587 (instregex "VTB(L|X)1")>;
588 def : InstRW<[SwiftWrite2xP1TwoCycle],
589 (instregex "VTB(L|X)2")>;
590 def : InstRW<[SwiftWrite3xP1TwoCycle],
591 (instregex "VTB(L|X)3")>;
592 def : InstRW<[SwiftWrite4xP1TwoCycle],
593 (instregex "VTB(L|X)4")>;
595 // 4.2.33 Advanced SIMD, Transpose
596 def : InstRW<[SwiftWriteP1FourCycle, SwiftWriteP1FourCycle,
597 SwiftWriteP1TwoCycle/*RsrcOnly*/, SchedReadAdvance<2>],
598 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
600 // 4.2.34 Advanced SIMD and VFP, Floating Point
601 def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VABS(S|D)$", "VNEG(S|D)$")>;
602 def : InstRW<[SwiftWriteP0FourCycle],
603 (instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)")>;
604 def : InstRW<[SwiftWriteP0FourCycle],
605 (instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX",
607 def : InstRW<[SwiftWriteP0SixCycle], (instregex "VADDD$", "VSUBD$")>;
608 def : InstRW<[SwiftWriteP1EightCycle], (instregex "VRECPS", "VRSQRTS")>;
610 // 4.2.35 Advanced SIMD and VFP, Multiply
611 def : InstRW<[SwiftWriteP1FourCycle],
612 (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
613 "VMULL", "VQDMULL")>;
614 def : InstRW<[SwiftWriteP1FourCycle],
615 (instregex "VMLA", "VMLS", "VNMLA", "VNMLS", "VFMA(S|D)", "VFMS(S|D)",
616 "VFNMA", "VFNMS", "VMLAL", "VMLSL","VQDMLAL", "VQDMLSL")>;
617 def : InstRW<[SwiftWriteP1EightCycle], (instregex "VFMAfd", "VFMSfd")>;
618 def : InstRW<[SwiftWriteP1TwelveCyc], (instregex "VFMAfq", "VFMSfq")>;
620 // 4.2.36 Advanced SIMD and VFP, Convert
621 def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
623 // 4.2.37 Advanced SIMD and VFP, Move
624 def : InstRW<[SwiftWriteP0TwoCycle],
625 (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc",
626 "VMVNv", "VMVN(d|q)", "VMVN(S|D)cc",
628 def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>;
629 def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>],
630 (instregex "VQMOVN")>;
631 def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN", "VDUPf")>;
632 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>],
633 (instregex "VDUP(8|16|32)")>;
634 def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>;
635 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>],
636 (instregex "VMOVSR$", "VSETLN")>;
637 def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle],
638 (instregex "VMOVRR(D|S)$")>;
639 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
640 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>,
641 WriteSequence<[SwiftWrite1Cycle, SwiftWriteP2FourCycle,
642 SwiftWriteP1TwoCycle]>],
643 (instregex "VMOVSRR$")>;
644 def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle]>],
645 (instregex "VGETLN(u|i)")>;
646 def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle,
647 SwiftWriteP01OneCycle]>],
648 (instregex "VGETLNs")>;
650 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
651 // Serializing instructions.
652 def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
654 let ResourceCycles = [15];
656 def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
658 let ResourceCycles = [15];
660 def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
662 let ResourceCycles = [15];
664 def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
666 def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
669 def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>;
671 // 4.2.39 Advanced SIMD and VFP, Load Single Element
672 def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>;
674 // 4.2.40 Advanced SIMD and VFP, Store Single Element
675 def : InstRW<[SwiftWriteLM4Cy], (instregex "VSTRD$", "VSTRS$")>;
677 // 4.2.41 Advanced SIMD and VFP, Load Multiple
678 // 4.2.42 Advanced SIMD and VFP, Store Multiple
680 // Resource requirement for permuting, just reserves the resources.
681 foreach Num = 1-28 in {
682 def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
684 let NumMicroOps = Num;
685 let ResourceCycles = [Num];
689 // Pre RA pseudos - load/store to a Q register as a D register pair.
690 def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDMQIA$", "VSTMQIA$")>;
692 // Post RA not modelled accurately. We assume that register use of width 64
693 // bit maps to a D register, 128 maps to a Q register. Not all different kinds
694 // are accurately represented.
695 def SwiftWriteVLDM : SchedWriteVariant<[
696 // Load of one S register.
697 SchedVar<SwiftLMAddr1Pred, [SwiftWriteLM4Cy]>,
698 // Load of one D register.
699 SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo]>,
700 // Load of 3 S register.
701 SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
702 SwiftWriteLM13CyNo, SwiftWriteP01OneCycle,
704 // Load of a Q register (not necessarily true). We should not be mapping to
705 // 4 S registers, either.
706 SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo,
707 SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>,
708 // Load of 5 S registers.
709 SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
710 SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
711 SwiftWriteLM17CyNo, SwiftWriteP01OneCycle,
713 // Load of 3 D registers. (Must also be able to handle s register list -
714 // though, not accurate)
715 SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
716 SwiftWriteLM10Cy, SwiftWriteLM14CyNo,
717 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
718 SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
719 // Load of 7 S registers.
720 SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
721 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
722 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
723 SwiftWriteLM21CyNo, SwiftWriteP01OneCycle,
725 // Load of two Q registers.
726 SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
727 SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
728 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
729 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
730 SwiftWriteP01OneCycle, SwiftVLDMPerm2]>,
731 // Load of 9 S registers.
732 SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
733 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
734 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
735 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
736 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
738 // Load of 5 D registers.
739 SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
740 SwiftWriteLM10Cy, SwiftWriteLM14Cy,
741 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
742 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
743 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
744 SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
745 // Inaccurate: reuse describtion from 9 S registers.
746 SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
747 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
748 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
749 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
750 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
751 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
753 // Load of three Q registers.
754 SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
755 SwiftWriteLM11Cy, SwiftWriteLM11Cy,
756 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
757 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
758 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
759 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
760 SwiftWriteP01OneCycle, SwiftVLDMPerm3]>,
761 // Inaccurate: reuse describtion from 9 S registers.
762 SchedVar<SwiftLMAddr13Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
763 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
764 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
765 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
766 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
767 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
768 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
770 // Load of 7 D registers inaccurate.
771 SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
772 SwiftWriteLM10Cy, SwiftWriteLM14Cy,
773 SwiftWriteLM14Cy, SwiftWriteLM14CyNo,
774 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
775 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
776 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
777 SwiftWriteP01OneCycle, SwiftVLDMPerm7]>,
778 SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
779 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
780 SwiftWriteLM17Cy, SwiftWriteLM18CyNo,
781 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
782 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
783 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
784 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
785 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
787 // Load of 4 Q registers.
788 SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM7Cy, SwiftWriteLM10Cy,
789 SwiftWriteLM11Cy, SwiftWriteLM14Cy,
790 SwiftWriteLM15Cy, SwiftWriteLM18CyNo,
791 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
792 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
793 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
794 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
795 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
796 SwiftWriteP01OneCycle, SwiftVLDMPerm4]>,
797 // Unknow number of registers, just use resources for two registers.
798 SchedVar<NoSchedPred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
799 SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
800 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
801 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
802 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
803 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
804 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
805 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
806 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
807 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
808 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
809 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
810 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
811 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
812 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
813 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
814 SwiftWriteP01OneCycle, SwiftVLDMPerm2]>
815 ]> { let Variadic = 1; }
817 def : InstRW<[SwiftWriteVLDM], (instregex "VLDM[SD](IA|DB)$")>;
819 def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVLDM],
820 (instregex "VLDM[SD](IA|DB)_UPD$")>;
822 def SwiftWriteVSTM : SchedWriteVariant<[
824 SchedVar<SwiftLMAddr1Pred, [SwiftWriteSTM1]>,
826 SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM1]>,
827 // Three S registers.
828 SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM4]>,
829 // Assume one Q register.
830 SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM1]>,
831 SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM6]>,
832 // Assume three D registers.
833 SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM4]>,
834 SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM8]>,
835 // Assume two Q registers.
836 SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM3]>,
837 SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM10]>,
838 // Assume 5 D registers.
839 SchedVar<SwiftLMAddr10Pred, [SwiftWriteSTM6]>,
840 SchedVar<SwiftLMAddr11Pred, [SwiftWriteSTM12]>,
841 // Assume three Q registers.
842 SchedVar<SwiftLMAddr12Pred, [SwiftWriteSTM4]>,
843 SchedVar<SwiftLMAddr13Pred, [SwiftWriteSTM14]>,
844 // Assume 7 D registers.
845 SchedVar<SwiftLMAddr14Pred, [SwiftWriteSTM8]>,
846 SchedVar<SwiftLMAddr15Pred, [SwiftWriteSTM16]>,
847 // Assume four Q registers.
848 SchedVar<SwiftLMAddr16Pred, [SwiftWriteSTM5]>,
849 // Asumme two Q registers.
850 SchedVar<NoSchedPred, [SwiftWriteSTM3]>
851 ]> { let Variadic = 1; }
853 def : InstRW<[SwiftWriteVSTM], (instregex "VSTM[SD](IA|DB)$")>;
855 def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVSTM],
856 (instregex "VSTM[SD](IA|DB)_UPD")>;
858 // 4.2.43 Advanced SIMD, Element or Structure Load and Store
859 def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
861 let ResourceCycles = [2];
863 def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
865 let ResourceCycles = [3];
867 foreach Num = 1-2 in {
868 def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
870 let NumMicroOps = Num;
871 let ResourceCycles = [Num];
875 // Multiple structures.
876 // Single element structure loads.
877 // We assume aligned.
878 // Single/two register.
879 def : InstRW<[SwiftWriteLM4Cy], (instregex "VLD1(d|q)(8|16|32|64)$")>;
880 def : InstRW<[SwiftWriteLM4Cy, SwiftWriteP01OneCycle],
881 (instregex "VLD1(d|q)(8|16|32|64)wb")>;
883 def : InstRW<[SwiftWrite3xP2FourCy],
884 (instregex "VLD1(d|q)(8|16|32|64)T$", "VLD1d64TPseudo")>;
885 def : InstRW<[SwiftWrite3xP2FourCy, SwiftWriteP01OneCycle],
886 (instregex "VLD1(d|q)(8|16|32|64)Twb")>;
888 def : InstRW<[SwiftWrite2xP2FourCy],
889 (instregex "VLD1(d|q)(8|16|32|64)Q$", "VLD1d64QPseudo")>;
890 def : InstRW<[SwiftWrite2xP2FourCy, SwiftWriteP01OneCycle],
891 (instregex "VLD1(d|q)(8|16|32|64)Qwb")>;
892 // Two element structure loads.
893 // Two/four register.
894 def : InstRW<[SwiftWriteLM9Cy, SwiftExt2xP0, SwiftVLDMPerm2],
895 (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;
896 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
898 (instregex "VLD2(d|q|b)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB")>;
899 // Three element structure.
900 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
901 SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
902 (instregex "VLD3(d|q)(8|16|32)$")>;
903 def : InstRW<[SwiftWriteLM9Cy, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
904 (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$")>;
906 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
907 SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
908 (instregex "VLD3(d|q)(8|16|32)_UPD$")>;
909 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm3,
910 SwiftWrite3xP2FourCy],
911 (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
912 // Four element structure loads.
913 def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
914 SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4,
915 SwiftWrite3xP2FourCy],
916 (instregex "VLD4(d|q)(8|16|32)$")>;
917 def : InstRW<[SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4,
918 SwiftWrite3xP2FourCy],
919 (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$")>;
920 def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
921 SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
922 SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
923 (instregex "VLD4(d|q)(8|16|32)_UPD")>;
924 def : InstRW<[SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
925 SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
926 (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
928 // Single all/lane loads.
929 // One element structure.
930 def : InstRW<[SwiftWriteLM6Cy, SwiftVLDMPerm2],
931 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
932 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm2],
933 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)",
934 "VLD1LNq(8|16|32)Pseudo_UPD")>;
935 // Two element structure.
936 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2],
937 (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",
938 "VLD2LN(d|q)(8|16|32)Pseudo$")>;
939 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftWriteP01OneCycle,
940 SwiftExt1xP0, SwiftVLDMPerm2],
941 (instregex "VLD2LN(d|q)(8|16|32)_UPD$")>;
942 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
943 SwiftExt1xP0, SwiftVLDMPerm2],
944 (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb")>;
945 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
946 SwiftExt1xP0, SwiftVLDMPerm2],
947 (instregex "VLD2LN(d|q)(8|16|32)Pseudo_UPD")>;
948 // Three element structure.
949 def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0,
951 (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$",
952 "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
953 def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy,
954 SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm3],
955 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>;
956 def : InstRW<[SwiftWriteLM7Cy, SwiftWriteP01OneCycle, SwiftWriteLM8Cy,
957 SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3],
958 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>;
959 // Four element struture.
960 def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
961 SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5],
962 (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$",
963 "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
964 def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
965 SwiftWriteLM10CyNo, SwiftWriteP01OneCycle, SwiftExt1xP0,
967 (instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD")>;
968 def : InstRW<[SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftWriteLM9Cy,
969 SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0,
971 (instregex "VLD4(DUP|LN)(d|q)(8|16|32)Pseudo_UPD")>;
973 // Multiple structures.
974 // Single element structure store.
975 def : InstRW<[SwiftWrite1xP2], (instregex "VST1d(8|16|32|64)$")>;
976 def : InstRW<[SwiftWrite2xP2], (instregex "VST1q(8|16|32|64)$")>;
977 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2],
978 (instregex "VST1d(8|16|32|64)wb")>;
979 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2],
980 (instregex "VST1q(8|16|32|64)wb")>;
981 def : InstRW<[SwiftWrite3xP2],
982 (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$")>;
983 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite3xP2],
984 (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB")>;
985 def : InstRW<[SwiftWrite4xP2],
986 (instregex "VST1d(8|16|32|64)(Q|QPseudo)$")>;
987 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2],
988 (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)")>;
989 // Two element structure store.
990 def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
991 (instregex "VST2(d|b)(8|16|32)$")>;
992 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
993 (instregex "VST2(b|d)(8|16|32)wb")>;
994 def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
995 (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;
996 def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
997 (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB")>;
998 // Three element structure store.
999 def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
1000 (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$")>;
1001 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
1002 (instregex "VST3(d|q)(8|16|32)_UPD",
1003 "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
1004 // Four element structure store.
1005 def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
1006 (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$")>;
1007 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm4],
1008 (instregex "VST4(d|q)(8|16|32)_UPD",
1009 "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
1010 // Single/all lane store.
1011 // One element structure.
1012 def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
1013 (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;
1014 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
1015 (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD")>;
1016 // Two element structure.
1017 def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm2],
1018 (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;
1019 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm2],
1020 (instregex "VST2LN(d|q)(8|16|32)_UPD",
1021 "VST2LN(d|q)(8|16|32)Pseudo_UPD")>;
1022 // Three element structure.
1023 def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
1024 (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;
1025 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
1026 (instregex "VST3LN(d|q)(8|16|32)_UPD",
1027 "VST3LN(d|q)(8|16|32)Pseudo_UPD")>;
1028 // Four element structure.
1029 def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
1030 (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$")>;
1031 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2],
1032 (instregex "VST4LN(d|q)(8|16|32)_UPD",
1033 "VST4LN(d|q)(8|16|32)Pseudo_UPD")>;
1035 // 4.2.44 VFP, Divide and Square Root
1036 def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
1037 let NumMicroOps = 1;
1039 let ResourceCycles = [1, 15];
1041 def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
1042 let NumMicroOps = 1;
1044 let ResourceCycles = [1, 30];
1046 def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
1047 def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
1049 // ===---------------------------------------------------------------------===//
1050 // Floating-point. Map target defined SchedReadWrite to processor specific ones
1052 def : SchedAlias<WriteFPCVT, SwiftWriteP1FourCycle>;
1053 def : SchedAlias<WriteFPMOV, SwiftWriteP2ThreeCycle>;
1055 def : SchedAlias<WriteFPALU32, SwiftWriteP0FourCycle>;
1056 def : SchedAlias<WriteFPALU64, SwiftWriteP0SixCycle>;
1058 def : SchedAlias<WriteFPMUL32, SwiftWriteP1FourCycle>;
1059 def : SchedAlias<WriteFPMUL64, SwiftWriteP1SixCycle>;
1061 def : SchedAlias<WriteFPMAC32, SwiftWriteP1FourCycle>;
1062 def : SchedAlias<WriteFPMAC64, SwiftWriteP1FourCycle>;
1064 def : SchedAlias<WriteFPDIV32, SwiftDiv17>;
1065 def : SchedAlias<WriteFPSQRT32, SwiftDiv17>;
1067 def : SchedAlias<WriteFPDIV64, SwiftDiv32>;
1068 def : SchedAlias<WriteFPSQRT64, SwiftDiv32>;
1070 def : ReadAdvance<ReadFPMUL, 0>;
1071 def : ReadAdvance<ReadFPMAC, 0>;
1073 // Overriden via InstRW for this processor.
1074 def : WriteRes<WriteVLD1, []>;
1075 def : WriteRes<WriteVLD2, []>;
1076 def : WriteRes<WriteVLD3, []>;
1077 def : WriteRes<WriteVLD4, []>;
1078 def : WriteRes<WriteVST1, []>;
1079 def : WriteRes<WriteVST2, []>;
1080 def : WriteRes<WriteVST3, []>;
1081 def : WriteRes<WriteVST4, []>;
1084 def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
1086 def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
1087 let ResourceCycles = [0];