1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
16 #include "ARMCallLowering.h"
17 #include "ARMLegalizerInfo.h"
18 #include "ARMRegisterBankInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMInstrInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "MCTargetDesc/ARMMCTargetDesc.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb1InstrInfo.h"
27 #include "Thumb2InstrInfo.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCTargetOptions.h"
37 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/TargetParser.h"
40 #include "llvm/Target/TargetOptions.h"
44 #define DEBUG_TYPE "arm-subtarget"
46 #define GET_SUBTARGETINFO_TARGET_DESC
47 #define GET_SUBTARGETINFO_CTOR
48 #include "ARMGenSubtargetInfo.inc"
51 UseFusedMulOps("arm-use-mulops",
52 cl::init(true), cl::Hidden);
60 static cl::opt<ITMode>
61 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
63 cl::values(clEnumValN(DefaultIT, "arm-default-it",
64 "Generate IT block based on arch"),
65 clEnumValN(RestrictedIT, "arm-restrict-it",
66 "Disallow deprecated IT based on ARMv8"),
67 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
68 "Allow IT blocks based on ARMv7")));
70 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
71 /// currently supported (for testing only).
73 ForceFastISel("arm-force-fast-isel",
74 cl::init(false), cl::Hidden);
76 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
77 /// so that we can use initializer lists for subtarget initialization.
78 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
80 initializeEnvironment();
81 initSubtargetFeatures(CPU, FS);
85 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
87 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
88 if (STI.isThumb1Only())
89 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
91 return new ARMFrameLowering(STI);
94 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
95 const std::string &FS,
96 const ARMBaseTargetMachine &TM, bool IsLittle)
97 : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
98 CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
99 TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
100 // At this point initializeSubtargetDependencies has been called so
101 // we can query directly.
102 InstrInfo(isThumb1Only()
103 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
105 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
106 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
109 CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
110 Legalizer.reset(new ARMLegalizerInfo(*this));
112 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
114 // FIXME: At this point, we can't rely on Subtarget having RBI.
115 // It's awkward to mix passing RBI and the Subtarget; should we pass
117 InstSelector.reset(createARMInstructionSelector(
118 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
120 RegBankInfo.reset(RBI);
123 const CallLowering *ARMSubtarget::getCallLowering() const {
124 return CallLoweringInfo.get();
127 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
128 return InstSelector.get();
131 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
132 return Legalizer.get();
135 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
136 return RegBankInfo.get();
139 bool ARMSubtarget::isXRaySupported() const {
140 // We don't currently suppport Thumb, but Windows requires Thumb.
141 return hasV6Ops() && hasARMOps() && !isTargetWindows();
144 void ARMSubtarget::initializeEnvironment() {
145 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
146 // directly from it, but we can try to make sure they're consistent when both
148 UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
149 Options.ExceptionModel == ExceptionHandling::None) ||
150 Options.ExceptionModel == ExceptionHandling::SjLj;
151 assert((!TM.getMCAsmInfo() ||
152 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
153 ExceptionHandling::SjLj) == UseSjLjEH) &&
154 "inconsistent sjlj choice between CodeGen and MC");
157 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
158 if (CPUString.empty()) {
159 CPUString = "generic";
161 if (isTargetDarwin()) {
162 StringRef ArchName = TargetTriple.getArchName();
163 ARM::ArchKind AK = ARM::parseArch(ArchName);
164 if (AK == ARM::ArchKind::ARMV7S)
165 // Default to the Swift CPU when targeting armv7s/thumbv7s.
167 else if (AK == ARM::ArchKind::ARMV7K)
168 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
169 // ARMv7k does not use SjLj exception handling.
170 CPUString = "cortex-a7";
174 // Insert the architecture feature derived from the target triple into the
175 // feature string. This is important for setting features that are implied
176 // based on the architecture version.
177 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
180 ArchFS = (Twine(ArchFS) + "," + FS).str();
184 ParseSubtargetFeatures(CPUString, ArchFS);
186 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
187 // Assert this for now to make the change obvious.
188 assert(hasV6T2Ops() || !hasThumb2());
190 // Execute only support requires movt support
191 if (genExecuteOnly())
192 assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
194 // Keep a pointer to static instruction cost data for the specified CPU.
195 SchedModel = getSchedModelForCPU(CPUString);
197 // Initialize scheduling itinerary for the specified CPU.
198 InstrItins = getInstrItineraryForCPU(CPUString);
200 // FIXME: this is invalid for WindowsCE
201 if (isTargetWindows())
206 if (isTargetNaCl() || isAAPCS16_ABI())
209 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
210 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
211 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
212 // support in the assembler and linker to be used. This would need to be
213 // fixed to fully support tail calls in Thumb1.
215 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
216 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
217 // means if we need to reload LR, it takes extra instructions, which outweighs
218 // the value of the tail call; but here we don't know yet whether LR is going
219 // to be used. We take the optimistic approach of generating the tail call and
220 // perhaps taking a hit if we need to restore the LR.
222 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
223 // but we need to make sure there are enough registers; the only valid
224 // registers are the 4 used for parameters. We don't currently do this
227 SupportsTailCall = !isThumb() || hasV8MBaselineOps();
229 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
230 SupportsTailCall = false;
234 RestrictIT = hasV8Ops();
244 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
245 const FeatureBitset &Bits = getFeatureBits();
246 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
247 (Options.UnsafeFPMath || isTargetDarwin()))
248 UseNEONForSinglePrecisionFP = true;
253 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
254 switch (ARMProcFamily) {
259 LdStMultipleTiming = DoubleIssue;
262 LdStMultipleTiming = DoubleIssue;
265 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
266 PreISelOperandLatencyAdjustment = 1;
271 MaxInterleaveFactor = 2;
272 PreISelOperandLatencyAdjustment = 1;
273 PartialUpdateClearance = 12;
294 PreISelOperandLatencyAdjustment = 1;
297 MaxInterleaveFactor = 2;
298 LdStMultipleTiming = SingleIssuePlusExtras;
299 PreISelOperandLatencyAdjustment = 1;
300 PartialUpdateClearance = 12;
305 bool ARMSubtarget::isAPCS_ABI() const {
306 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
307 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
309 bool ARMSubtarget::isAAPCS_ABI() const {
310 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
311 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
312 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
314 bool ARMSubtarget::isAAPCS16_ABI() const {
315 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
316 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
319 bool ARMSubtarget::isROPI() const {
320 return TM.getRelocationModel() == Reloc::ROPI ||
321 TM.getRelocationModel() == Reloc::ROPI_RWPI;
323 bool ARMSubtarget::isRWPI() const {
324 return TM.getRelocationModel() == Reloc::RWPI ||
325 TM.getRelocationModel() == Reloc::ROPI_RWPI;
328 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
329 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
332 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
333 // the section that is being relocated. This means we have to use o load even
334 // for GVs that are known to be local to the dso.
335 if (isTargetMachO() && TM.isPositionIndependent() &&
336 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
342 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
343 return isTargetELF() && TM.isPositionIndependent() &&
344 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
347 unsigned ARMSubtarget::getMispredictionPenalty() const {
348 return SchedModel.MispredictPenalty;
351 bool ARMSubtarget::enableMachineScheduler() const {
352 // Enable the MachineScheduler before register allocation for subtargets
353 // with the use-misched feature.
354 return useMachineScheduler();
357 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
358 bool ARMSubtarget::enablePostRAScheduler() const {
359 if (disablePostRAScheduler())
361 // Don't reschedule potential IT blocks.
362 return !isThumb1Only();
365 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
367 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
368 // For general targets, the prologue can grow when VFPs are allocated with
369 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
370 // format which it's more important to get right.
371 return isTargetWatchABI() || (isSwift() && !MF.getFunction().optForMinSize());
374 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
375 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
376 // immediates as it is inherently position independent, and may be out of
378 return !NoMovt && hasV8MBaselineOps() &&
379 (isTargetWindows() || !MF.getFunction().optForMinSize() || genExecuteOnly());
382 bool ARMSubtarget::useFastISel() const {
383 // Enable fast-isel for any target, for testing only.
387 // Limit fast-isel to the targets that are or have been tested.
391 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
392 return TM.Options.EnableFastISel &&
393 ((isTargetMachO() && !isThumb1Only()) ||
394 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));