1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMSubtarget.h"
18 #include "ARMTargetMachine.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "Thumb1FrameLowering.h"
21 #include "Thumb1InstrInfo.h"
22 #include "Thumb2InstrInfo.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCTargetOptions.h"
31 #include "llvm/Support/CodeGen.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/TargetParser.h"
34 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "arm-subtarget"
42 #define GET_SUBTARGETINFO_TARGET_DESC
43 #define GET_SUBTARGETINFO_CTOR
44 #include "ARMGenSubtargetInfo.inc"
47 UseFusedMulOps("arm-use-mulops",
48 cl::init(true), cl::Hidden);
56 static cl::opt<ITMode>
57 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
59 cl::values(clEnumValN(DefaultIT, "arm-default-it",
60 "Generate IT block based on arch"),
61 clEnumValN(RestrictedIT, "arm-restrict-it",
62 "Disallow deprecated IT based on ARMv8"),
63 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
64 "Allow IT blocks based on ARMv7")));
66 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
67 /// currently supported (for testing only).
69 ForceFastISel("arm-force-fast-isel",
70 cl::init(false), cl::Hidden);
72 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
73 /// so that we can use initializer lists for subtarget initialization.
74 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
76 initializeEnvironment();
77 initSubtargetFeatures(CPU, FS);
81 /// EnableExecuteOnly - Enables the generation of execute-only code on supported
84 EnableExecuteOnly("arm-execute-only");
86 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
88 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
89 if (STI.isThumb1Only())
90 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
92 return new ARMFrameLowering(STI);
95 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
96 const std::string &FS,
97 const ARMBaseTargetMachine &TM, bool IsLittle)
98 : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
99 GenExecuteOnly(EnableExecuteOnly), CPUString(CPU), IsLittle(IsLittle),
100 TargetTriple(TT), Options(TM.Options), TM(TM),
101 FrameLowering(initializeFrameLowering(CPU, FS)),
102 // At this point initializeSubtargetDependencies has been called so
103 // we can query directly.
104 InstrInfo(isThumb1Only()
105 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
107 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
108 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
111 const CallLowering *ARMSubtarget::getCallLowering() const {
112 assert(GISel && "Access to GlobalISel APIs not set");
113 return GISel->getCallLowering();
116 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
117 assert(GISel && "Access to GlobalISel APIs not set");
118 return GISel->getInstructionSelector();
121 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
122 assert(GISel && "Access to GlobalISel APIs not set");
123 return GISel->getLegalizerInfo();
126 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
127 assert(GISel && "Access to GlobalISel APIs not set");
128 return GISel->getRegBankInfo();
131 bool ARMSubtarget::isXRaySupported() const {
132 // We don't currently suppport Thumb, but Windows requires Thumb.
133 return hasV6Ops() && hasARMOps() && !isTargetWindows();
136 void ARMSubtarget::initializeEnvironment() {
137 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
138 // directly from it, but we can try to make sure they're consistent when both
140 UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
141 assert((!TM.getMCAsmInfo() ||
142 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
143 ExceptionHandling::SjLj) == UseSjLjEH) &&
144 "inconsistent sjlj choice between CodeGen and MC");
147 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
148 if (CPUString.empty()) {
149 CPUString = "generic";
151 if (isTargetDarwin()) {
152 StringRef ArchName = TargetTriple.getArchName();
153 unsigned ArchKind = ARM::parseArch(ArchName);
154 if (ArchKind == ARM::AK_ARMV7S)
155 // Default to the Swift CPU when targeting armv7s/thumbv7s.
157 else if (ArchKind == ARM::AK_ARMV7K)
158 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
159 // ARMv7k does not use SjLj exception handling.
160 CPUString = "cortex-a7";
164 // Insert the architecture feature derived from the target triple into the
165 // feature string. This is important for setting features that are implied
166 // based on the architecture version.
167 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
170 ArchFS = (Twine(ArchFS) + "," + FS).str();
174 ParseSubtargetFeatures(CPUString, ArchFS);
176 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
177 // Assert this for now to make the change obvious.
178 assert(hasV6T2Ops() || !hasThumb2());
180 // Execute only support requires movt support
181 if (genExecuteOnly())
182 assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
184 // Keep a pointer to static instruction cost data for the specified CPU.
185 SchedModel = getSchedModelForCPU(CPUString);
187 // Initialize scheduling itinerary for the specified CPU.
188 InstrItins = getInstrItineraryForCPU(CPUString);
190 // FIXME: this is invalid for WindowsCE
191 if (isTargetWindows())
196 if (isTargetNaCl() || isAAPCS16_ABI())
199 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
200 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
201 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
202 // support in the assembler and linker to be used. This would need to be
203 // fixed to fully support tail calls in Thumb1.
205 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
206 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
207 // means if we need to reload LR, it takes extra instructions, which outweighs
208 // the value of the tail call; but here we don't know yet whether LR is going
209 // to be used. We generate the tail call here and turn it back into CALL/RET
210 // in emitEpilogue if LR is used.
212 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
213 // but we need to make sure there are enough registers; the only valid
214 // registers are the 4 used for parameters. We don't currently do this
217 SupportsTailCall = !isThumb() || hasV8MBaselineOps();
219 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
220 SupportsTailCall = false;
224 RestrictIT = hasV8Ops();
234 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
235 const FeatureBitset &Bits = getFeatureBits();
236 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
237 (Options.UnsafeFPMath || isTargetDarwin()))
238 UseNEONForSinglePrecisionFP = true;
243 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
244 switch (ARMProcFamily) {
249 LdStMultipleTiming = DoubleIssue;
252 LdStMultipleTiming = DoubleIssue;
255 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
256 PreISelOperandLatencyAdjustment = 1;
261 MaxInterleaveFactor = 2;
262 PreISelOperandLatencyAdjustment = 1;
263 PartialUpdateClearance = 12;
282 PreISelOperandLatencyAdjustment = 1;
285 MaxInterleaveFactor = 2;
286 LdStMultipleTiming = SingleIssuePlusExtras;
287 PreISelOperandLatencyAdjustment = 1;
288 PartialUpdateClearance = 12;
293 bool ARMSubtarget::isAPCS_ABI() const {
294 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
295 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
297 bool ARMSubtarget::isAAPCS_ABI() const {
298 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
299 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
300 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
302 bool ARMSubtarget::isAAPCS16_ABI() const {
303 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
304 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
307 bool ARMSubtarget::isROPI() const {
308 return TM.getRelocationModel() == Reloc::ROPI ||
309 TM.getRelocationModel() == Reloc::ROPI_RWPI;
311 bool ARMSubtarget::isRWPI() const {
312 return TM.getRelocationModel() == Reloc::RWPI ||
313 TM.getRelocationModel() == Reloc::ROPI_RWPI;
316 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
317 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
320 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
321 // the section that is being relocated. This means we have to use o load even
322 // for GVs that are known to be local to the dso.
323 if (isTargetMachO() && TM.isPositionIndependent() &&
324 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
330 unsigned ARMSubtarget::getMispredictionPenalty() const {
331 return SchedModel.MispredictPenalty;
334 bool ARMSubtarget::hasSinCos() const {
335 return isTargetWatchOS() ||
336 (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
339 bool ARMSubtarget::enableMachineScheduler() const {
340 // Enable the MachineScheduler before register allocation for out-of-order
341 // architectures where we do not use the PostRA scheduler anymore (for now
342 // restricted to swift).
343 return getSchedModel().isOutOfOrder() && isSwift();
346 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
347 bool ARMSubtarget::enablePostRAScheduler() const {
348 // No need for PostRA scheduling on out of order CPUs (for now restricted to
350 if (getSchedModel().isOutOfOrder() && isSwift())
352 return (!isThumb() || hasThumb2());
355 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
357 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
358 // For general targets, the prologue can grow when VFPs are allocated with
359 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
360 // format which it's more important to get right.
361 return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
364 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
365 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
366 // immediates as it is inherently position independent, and may be out of
368 return !NoMovt && hasV8MBaselineOps() &&
369 (isTargetWindows() || !MF.getFunction()->optForMinSize() || genExecuteOnly());
372 bool ARMSubtarget::useFastISel() const {
373 // Enable fast-isel for any target, for testing only.
377 // Limit fast-isel to the targets that are or have been tested.
381 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
382 return TM.Options.EnableFastISel &&
383 ((isTargetMachO() && !isThumb1Only()) ||
384 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));