1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Support/TargetParser.h"
38 #define DEBUG_TYPE "arm-subtarget"
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
45 UseFusedMulOps("arm-use-mulops",
46 cl::init(true), cl::Hidden);
54 static cl::opt<ITMode>
55 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
57 cl::values(clEnumValN(DefaultIT, "arm-default-it",
58 "Generate IT block based on arch"),
59 clEnumValN(RestrictedIT, "arm-restrict-it",
60 "Disallow deprecated IT based on ARMv8"),
61 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
62 "Allow IT blocks based on ARMv7")));
64 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65 /// currently supported (for testing only).
67 ForceFastISel("arm-force-fast-isel",
68 cl::init(false), cl::Hidden);
70 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
71 /// so that we can use initializer lists for subtarget initialization.
72 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
74 initializeEnvironment();
75 initSubtargetFeatures(CPU, FS);
79 /// EnableExecuteOnly - Enables the generation of execute-only code on supported
82 EnableExecuteOnly("arm-execute-only");
84 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
86 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
87 if (STI.isThumb1Only())
88 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
90 return new ARMFrameLowering(STI);
93 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
94 const std::string &FS,
95 const ARMBaseTargetMachine &TM, bool IsLittle)
96 : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
97 GenExecuteOnly(EnableExecuteOnly), CPUString(CPU), IsLittle(IsLittle),
98 TargetTriple(TT), Options(TM.Options), TM(TM),
99 FrameLowering(initializeFrameLowering(CPU, FS)),
100 // At this point initializeSubtargetDependencies has been called so
101 // we can query directly.
102 InstrInfo(isThumb1Only()
103 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
105 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
106 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
107 TLInfo(TM, *this), GISel() {}
109 const CallLowering *ARMSubtarget::getCallLowering() const {
110 assert(GISel && "Access to GlobalISel APIs not set");
111 return GISel->getCallLowering();
114 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
115 assert(GISel && "Access to GlobalISel APIs not set");
116 return GISel->getInstructionSelector();
119 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
120 assert(GISel && "Access to GlobalISel APIs not set");
121 return GISel->getLegalizerInfo();
124 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
125 assert(GISel && "Access to GlobalISel APIs not set");
126 return GISel->getRegBankInfo();
129 bool ARMSubtarget::isXRaySupported() const {
130 // We don't currently suppport Thumb, but Windows requires Thumb.
131 return hasV6Ops() && hasARMOps() && !isTargetWindows();
134 void ARMSubtarget::initializeEnvironment() {
135 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
136 // directly from it, but we can try to make sure they're consistent when both
138 UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
139 assert((!TM.getMCAsmInfo() ||
140 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
141 ExceptionHandling::SjLj) == UseSjLjEH) &&
142 "inconsistent sjlj choice between CodeGen and MC");
145 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
146 if (CPUString.empty()) {
147 CPUString = "generic";
149 if (isTargetDarwin()) {
150 StringRef ArchName = TargetTriple.getArchName();
151 unsigned ArchKind = llvm::ARM::parseArch(ArchName);
152 if (ArchKind == llvm::ARM::AK_ARMV7S)
153 // Default to the Swift CPU when targeting armv7s/thumbv7s.
155 else if (ArchKind == llvm::ARM::AK_ARMV7K)
156 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
157 // ARMv7k does not use SjLj exception handling.
158 CPUString = "cortex-a7";
162 // Insert the architecture feature derived from the target triple into the
163 // feature string. This is important for setting features that are implied
164 // based on the architecture version.
165 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
168 ArchFS = (Twine(ArchFS) + "," + FS).str();
172 ParseSubtargetFeatures(CPUString, ArchFS);
174 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
175 // Assert this for now to make the change obvious.
176 assert(hasV6T2Ops() || !hasThumb2());
178 // Execute only support requires movt support
179 if (genExecuteOnly())
180 assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
182 // Keep a pointer to static instruction cost data for the specified CPU.
183 SchedModel = getSchedModelForCPU(CPUString);
185 // Initialize scheduling itinerary for the specified CPU.
186 InstrItins = getInstrItineraryForCPU(CPUString);
188 // FIXME: this is invalid for WindowsCE
189 if (isTargetWindows())
194 if (isTargetNaCl() || isAAPCS16_ABI())
197 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
198 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
199 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
200 // support in the assembler and linker to be used. This would need to be
201 // fixed to fully support tail calls in Thumb1.
203 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
204 // LR. This means if we need to reload LR, it takes an extra instructions,
205 // which outweighs the value of the tail call; but here we don't know yet
206 // whether LR is going to be used. Probably the right approach is to
207 // generate the tail call here and turn it back into CALL/RET in
208 // emitEpilogue if LR is used.
210 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
211 // but we need to make sure there are enough registers; the only valid
212 // registers are the 4 used for parameters. We don't currently do this
215 SupportsTailCall = !isThumb() || hasV8MBaselineOps();
217 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
218 SupportsTailCall = false;
222 RestrictIT = hasV8Ops();
232 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
233 const FeatureBitset &Bits = getFeatureBits();
234 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
235 (Options.UnsafeFPMath || isTargetDarwin()))
236 UseNEONForSinglePrecisionFP = true;
241 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
242 switch (ARMProcFamily) {
247 LdStMultipleTiming = DoubleIssue;
250 LdStMultipleTiming = DoubleIssue;
253 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
254 PreISelOperandLatencyAdjustment = 1;
259 MaxInterleaveFactor = 2;
260 PreISelOperandLatencyAdjustment = 1;
261 PartialUpdateClearance = 12;
279 PreISelOperandLatencyAdjustment = 1;
282 MaxInterleaveFactor = 2;
283 LdStMultipleTiming = SingleIssuePlusExtras;
284 PreISelOperandLatencyAdjustment = 1;
285 PartialUpdateClearance = 12;
290 bool ARMSubtarget::isAPCS_ABI() const {
291 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
292 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
294 bool ARMSubtarget::isAAPCS_ABI() const {
295 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
296 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
297 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
299 bool ARMSubtarget::isAAPCS16_ABI() const {
300 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
301 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
304 bool ARMSubtarget::isROPI() const {
305 return TM.getRelocationModel() == Reloc::ROPI ||
306 TM.getRelocationModel() == Reloc::ROPI_RWPI;
308 bool ARMSubtarget::isRWPI() const {
309 return TM.getRelocationModel() == Reloc::RWPI ||
310 TM.getRelocationModel() == Reloc::ROPI_RWPI;
313 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
314 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
317 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
318 // the section that is being relocated. This means we have to use o load even
319 // for GVs that are known to be local to the dso.
320 if (isTargetMachO() && TM.isPositionIndependent() &&
321 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
327 unsigned ARMSubtarget::getMispredictionPenalty() const {
328 return SchedModel.MispredictPenalty;
331 bool ARMSubtarget::hasSinCos() const {
332 return isTargetWatchOS() ||
333 (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
336 bool ARMSubtarget::enableMachineScheduler() const {
337 // Enable the MachineScheduler before register allocation for out-of-order
338 // architectures where we do not use the PostRA scheduler anymore (for now
339 // restricted to swift).
340 return getSchedModel().isOutOfOrder() && isSwift();
343 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
344 bool ARMSubtarget::enablePostRAScheduler() const {
345 // No need for PostRA scheduling on out of order CPUs (for now restricted to
347 if (getSchedModel().isOutOfOrder() && isSwift())
349 return (!isThumb() || hasThumb2());
352 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
354 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
355 // For general targets, the prologue can grow when VFPs are allocated with
356 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
357 // format which it's more important to get right.
358 return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
361 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
362 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
363 // immediates as it is inherently position independent, and may be out of
365 return !NoMovt && hasV8MBaselineOps() &&
366 (isTargetWindows() || !MF.getFunction()->optForMinSize() || genExecuteOnly());
369 bool ARMSubtarget::useFastISel() const {
370 // Enable fast-isel for any target, for testing only.
374 // Limit fast-isel to the targets that are or have been tested.
378 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
379 return TM.Options.EnableFastISel &&
380 ((isTargetMachO() && !isThumb1Only()) ||
381 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));