1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCInstrItineraries.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
33 #define GET_SUBTARGETINFO_HEADER
34 #include "ARMGenSubtargetInfo.inc"
40 class ARMBaseTargetMachine;
42 class ARMSubtarget : public ARMGenSubtargetInfo {
44 enum ARMProcFamilyEnum {
45 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
46 CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3,
47 CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,
48 Krait, Swift, ExynosM1
50 enum ARMProcClassEnum {
51 None, AClass, RClass, MClass
54 ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
55 ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
56 ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline
60 /// What kind of timing do load multiple/store multiple instructions have.
61 enum ARMLdStMultipleTiming {
62 /// Can load/store 2 registers/cycle.
64 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
65 /// is not 64-bit aligned.
66 DoubleIssueCheckUnalignedAccess,
67 /// Can load/store 1 register/cycle.
69 /// Can load/store 1 register/cycle, but needs an extra cycle for address
70 /// computation and potentially also for register writeback.
71 SingleIssuePlusExtras,
75 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
76 ARMProcFamilyEnum ARMProcFamily = Others;
78 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
79 ARMProcClassEnum ARMProcClass = None;
81 /// ARMArch - ARM architecture
82 ARMArchEnum ARMArch = ARMv4t;
84 /// HasV4TOps, HasV5TOps, HasV5TEOps,
85 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
86 /// Specify whether target support specific ARM ISA variants.
87 bool HasV4TOps = false;
88 bool HasV5TOps = false;
89 bool HasV5TEOps = false;
90 bool HasV6Ops = false;
91 bool HasV6MOps = false;
92 bool HasV6KOps = false;
93 bool HasV6T2Ops = false;
94 bool HasV7Ops = false;
95 bool HasV8Ops = false;
96 bool HasV8_1aOps = false;
97 bool HasV8_2aOps = false;
98 bool HasV8MBaselineOps = false;
99 bool HasV8MMainlineOps = false;
101 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
102 /// floating point ISAs are supported.
103 bool HasVFPv2 = false;
104 bool HasVFPv3 = false;
105 bool HasVFPv4 = false;
106 bool HasFPARMv8 = false;
107 bool HasNEON = false;
109 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
110 /// specified. Use the method useNEONForSinglePrecisionFP() to
111 /// determine if NEON should actually be used.
112 bool UseNEONForSinglePrecisionFP = false;
114 /// UseMulOps - True if non-microcoded fused integer multiply-add and
115 /// multiply-subtract instructions should be used.
116 bool UseMulOps = false;
118 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
119 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
120 bool SlowFPVMLx = false;
122 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
123 /// forwarding to allow mul + mla being issued back to back.
124 bool HasVMLxForwarding = false;
126 /// SlowFPBrcc - True if floating point compare + branch is slow.
127 bool SlowFPBrcc = false;
129 /// InThumbMode - True if compiling for Thumb, false for ARM.
130 bool InThumbMode = false;
132 /// UseSoftFloat - True if we're using software floating point features.
133 bool UseSoftFloat = false;
135 /// HasThumb2 - True if Thumb2 instructions are supported.
136 bool HasThumb2 = false;
138 /// NoARM - True if subtarget does not support ARM mode execution.
141 /// ReserveR9 - True if R9 is not available as a general purpose register.
142 bool ReserveR9 = false;
144 /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
145 /// 32-bit imms (including global addresses).
148 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
149 /// must be able to synthesize call stubs for interworking between ARM and
151 bool SupportsTailCall = false;
153 /// HasFP16 - True if subtarget supports half-precision FP conversions
154 bool HasFP16 = false;
156 /// HasFullFP16 - True if subtarget supports half-precision FP operations
157 bool HasFullFP16 = false;
159 /// HasD16 - True if subtarget is limited to 16 double precision
160 /// FP registers for VFPv3.
163 /// HasHardwareDivide - True if subtarget supports [su]div
164 bool HasHardwareDivide = false;
166 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
167 bool HasHardwareDivideInARM = false;
169 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
171 bool HasT2ExtractPack = false;
173 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
175 bool HasDataBarrier = false;
177 /// HasV7Clrex - True if the subtarget supports CLREX instructions
178 bool HasV7Clrex = false;
180 /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
182 bool HasAcquireRelease = false;
184 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
185 /// over 16-bit ones.
186 bool Pref32BitThumb = false;
188 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
189 /// that partially update CPSR and add false dependency on the previous
190 /// CPSR setting instruction.
191 bool AvoidCPSRPartialUpdate = false;
193 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
194 /// movs with shifter operand (i.e. asr, lsl, lsr).
195 bool AvoidMOVsShifterOperand = false;
197 /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
198 /// avoid issue "normal" call instructions to callees which do not return.
199 bool HasRetAddrStack = false;
201 /// HasMPExtension - True if the subtarget supports Multiprocessing
202 /// extension (ARMv7 only).
203 bool HasMPExtension = false;
205 /// HasVirtualization - True if the subtarget supports the Virtualization
207 bool HasVirtualization = false;
209 /// FPOnlySP - If true, the floating point unit only supports single
211 bool FPOnlySP = false;
213 /// If true, the processor supports the Performance Monitor Extensions. These
214 /// include a generic cycle-counter as well as more fine-grained (often
215 /// implementation-specific) events.
216 bool HasPerfMon = false;
218 /// HasTrustZone - if true, processor supports TrustZone security extensions
219 bool HasTrustZone = false;
221 /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
222 bool Has8MSecExt = false;
224 /// HasCrypto - if true, processor supports Cryptography extensions
225 bool HasCrypto = false;
227 /// HasCRC - if true, processor supports CRC instructions
230 /// HasRAS - if true, the processor supports RAS extensions
233 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
234 /// particularly effective at zeroing a VFP register.
235 bool HasZeroCycleZeroing = false;
237 /// If true, if conversion may decide to leave some instructions unpredicated.
238 bool IsProfitableToUnpredicate = false;
240 /// If true, VMOV will be favored over VGETLNi32.
241 bool HasSlowVGETLNi32 = false;
243 /// If true, VMOV will be favored over VDUP.
244 bool HasSlowVDUP32 = false;
246 /// If true, VMOVSR will be favored over VMOVDRR.
247 bool PreferVMOVSR = false;
249 /// If true, ISHST barriers will be used for Release semantics.
250 bool PreferISHST = false;
252 /// If true, a VLDM/VSTM starting with an odd register number is considered to
253 /// take more microops than single VLDRS/VSTRS.
254 bool SlowOddRegister = false;
256 /// If true, loading into a D subregister will be penalized.
257 bool SlowLoadDSubregister = false;
259 /// If true, the AGU and NEON/FPU units are multiplexed.
260 bool HasMuxedUnits = false;
262 /// If true, VMOVS will never be widened to VMOVD
263 bool DontWidenVMOVS = false;
265 /// If true, run the MLx expansion pass.
266 bool ExpandMLx = false;
268 /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
269 bool HasVMLxHazards = false;
271 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
272 bool UseNEONForFPMovs = false;
274 /// If true, VLDn instructions take an extra cycle for unaligned accesses.
275 bool CheckVLDnAlign = false;
277 /// If true, VFP instructions are not pipelined.
278 bool NonpipelinedVFP = false;
280 /// StrictAlign - If true, the subtarget disallows unaligned memory
281 /// accesses for some types. For details, see
282 /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
283 bool StrictAlign = false;
285 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
286 /// blocks to conform to ARMv8 rule.
287 bool RestrictIT = false;
289 /// HasDSP - If true, the subtarget supports the DSP (saturating arith
290 /// and such) instructions.
293 /// NaCl TRAP instruction is generated instead of the regular TRAP.
294 bool UseNaClTrap = false;
296 /// Generate calls via indirect call instructions.
297 bool GenLongCalls = false;
299 /// Target machine allowed unsafe FP math (such as use of NEON fp)
300 bool UnsafeFPMath = false;
302 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
303 bool UseSjLjEH = false;
305 /// stackAlignment - The minimum alignment known to hold of the stack frame on
306 /// entry to the function and which must be maintained by every function.
307 unsigned stackAlignment = 4;
309 /// CPUString - String name of used CPU.
310 std::string CPUString;
312 unsigned MaxInterleaveFactor = 1;
314 /// Clearance before partial register updates (in number of instructions)
315 unsigned PartialUpdateClearance = 0;
317 /// What kind of timing do load multiple/store multiple have (double issue,
318 /// single issue etc).
319 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
321 /// The adjustment that we need to apply to get the operand latency from the
322 /// operand cycle returned by the itinerary data for pre-ISel operands.
323 int PreISelOperandLatencyAdjustment = 2;
325 /// IsLittle - The target is Little Endian
328 /// TargetTriple - What processor and OS we're targeting.
331 /// SchedModel - Processor specific instruction costs.
332 MCSchedModel SchedModel;
334 /// Selected instruction itineraries (one entry per itinerary class.)
335 InstrItineraryData InstrItins;
337 /// Options passed via command line that could influence the target
338 const TargetOptions &Options;
340 const ARMBaseTargetMachine &TM;
343 /// This constructor initializes the data members to match that
344 /// of the specified triple.
346 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
347 const ARMBaseTargetMachine &TM, bool IsLittle);
349 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
350 /// that still makes it profitable to inline the call.
351 unsigned getMaxInlineSizeThreshold() const {
354 /// ParseSubtargetFeatures - Parses features string setting specified
355 /// subtarget options. Definition of function is auto generated by tblgen.
356 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
358 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
359 /// so that we can use initializer lists for subtarget initialization.
360 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
362 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
365 const ARMBaseInstrInfo *getInstrInfo() const override {
366 return InstrInfo.get();
368 const ARMTargetLowering *getTargetLowering() const override {
371 const ARMFrameLowering *getFrameLowering() const override {
372 return FrameLowering.get();
374 const ARMBaseRegisterInfo *getRegisterInfo() const override {
375 return &InstrInfo->getRegisterInfo();
379 ARMSelectionDAGInfo TSInfo;
380 // Either Thumb1FrameLowering or ARMFrameLowering.
381 std::unique_ptr<ARMFrameLowering> FrameLowering;
382 // Either Thumb1InstrInfo or Thumb2InstrInfo.
383 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
384 ARMTargetLowering TLInfo;
386 void initializeEnvironment();
387 void initSubtargetFeatures(StringRef CPU, StringRef FS);
388 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
391 void computeIssueWidth();
393 bool hasV4TOps() const { return HasV4TOps; }
394 bool hasV5TOps() const { return HasV5TOps; }
395 bool hasV5TEOps() const { return HasV5TEOps; }
396 bool hasV6Ops() const { return HasV6Ops; }
397 bool hasV6MOps() const { return HasV6MOps; }
398 bool hasV6KOps() const { return HasV6KOps; }
399 bool hasV6T2Ops() const { return HasV6T2Ops; }
400 bool hasV7Ops() const { return HasV7Ops; }
401 bool hasV8Ops() const { return HasV8Ops; }
402 bool hasV8_1aOps() const { return HasV8_1aOps; }
403 bool hasV8_2aOps() const { return HasV8_2aOps; }
404 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
405 bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
408 /// These functions are obsolete, please consider adding subtarget features
409 /// or properties instead of calling them.
410 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
411 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
412 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
413 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
414 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
415 bool isSwift() const { return ARMProcFamily == Swift; }
416 bool isCortexM3() const { return ARMProcFamily == CortexM3; }
417 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
418 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
419 bool isKrait() const { return ARMProcFamily == Krait; }
422 bool hasARMOps() const { return !NoARM; }
424 bool hasVFP2() const { return HasVFPv2; }
425 bool hasVFP3() const { return HasVFPv3; }
426 bool hasVFP4() const { return HasVFPv4; }
427 bool hasFPARMv8() const { return HasFPARMv8; }
428 bool hasNEON() const { return HasNEON; }
429 bool hasCrypto() const { return HasCrypto; }
430 bool hasCRC() const { return HasCRC; }
431 bool hasRAS() const { return HasRAS; }
432 bool hasVirtualization() const { return HasVirtualization; }
433 bool useNEONForSinglePrecisionFP() const {
434 return hasNEON() && UseNEONForSinglePrecisionFP;
437 bool hasDivide() const { return HasHardwareDivide; }
438 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
439 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
440 bool hasDataBarrier() const { return HasDataBarrier; }
441 bool hasV7Clrex() const { return HasV7Clrex; }
442 bool hasAcquireRelease() const { return HasAcquireRelease; }
443 bool hasAnyDataBarrier() const {
444 return HasDataBarrier || (hasV6Ops() && !isThumb());
446 bool useMulOps() const { return UseMulOps; }
447 bool useFPVMLx() const { return !SlowFPVMLx; }
448 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
449 bool isFPBrccSlow() const { return SlowFPBrcc; }
450 bool isFPOnlySP() const { return FPOnlySP; }
451 bool hasPerfMon() const { return HasPerfMon; }
452 bool hasTrustZone() const { return HasTrustZone; }
453 bool has8MSecExt() const { return Has8MSecExt; }
454 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
455 bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
456 bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
457 bool hasSlowVDUP32() const { return HasSlowVDUP32; }
458 bool preferVMOVSR() const { return PreferVMOVSR; }
459 bool preferISHSTBarriers() const { return PreferISHST; }
460 bool expandMLx() const { return ExpandMLx; }
461 bool hasVMLxHazards() const { return HasVMLxHazards; }
462 bool hasSlowOddRegister() const { return SlowOddRegister; }
463 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
464 bool hasMuxedUnits() const { return HasMuxedUnits; }
465 bool dontWidenVMOVS() const { return DontWidenVMOVS; }
466 bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
467 bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
468 bool nonpipelinedVFP() const { return NonpipelinedVFP; }
469 bool prefers32BitThumb() const { return Pref32BitThumb; }
470 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
471 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
472 bool hasRetAddrStack() const { return HasRetAddrStack; }
473 bool hasMPExtension() const { return HasMPExtension; }
474 bool hasDSP() const { return HasDSP; }
475 bool useNaClTrap() const { return UseNaClTrap; }
476 bool useSjLjEH() const { return UseSjLjEH; }
477 bool genLongCalls() const { return GenLongCalls; }
479 bool hasFP16() const { return HasFP16; }
480 bool hasD16() const { return HasD16; }
481 bool hasFullFP16() const { return HasFullFP16; }
483 const Triple &getTargetTriple() const { return TargetTriple; }
485 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
486 bool isTargetIOS() const { return TargetTriple.isiOS(); }
487 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
488 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
489 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
490 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
491 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
492 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
494 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
495 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
496 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
498 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
499 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
500 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
501 // even for GNUEABI, so we can make a distinction here and still conform to
502 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
503 // FIXME: The Darwin exception is temporary, while we move users to
504 // "*-*-*-macho" triples as quickly as possible.
505 bool isTargetAEABI() const {
506 return (TargetTriple.getEnvironment() == Triple::EABI ||
507 TargetTriple.getEnvironment() == Triple::EABIHF) &&
508 !isTargetDarwin() && !isTargetWindows();
510 bool isTargetGNUAEABI() const {
511 return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
512 TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
513 !isTargetDarwin() && !isTargetWindows();
515 bool isTargetMuslAEABI() const {
516 return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
517 TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
518 !isTargetDarwin() && !isTargetWindows();
521 // ARM Targets that support EHABI exception handling standard
522 // Darwin uses SjLj. Other targets might need more checks.
523 bool isTargetEHABICompatible() const {
524 return (TargetTriple.getEnvironment() == Triple::EABI ||
525 TargetTriple.getEnvironment() == Triple::GNUEABI ||
526 TargetTriple.getEnvironment() == Triple::MuslEABI ||
527 TargetTriple.getEnvironment() == Triple::EABIHF ||
528 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
529 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
530 isTargetAndroid()) &&
531 !isTargetDarwin() && !isTargetWindows();
534 bool isTargetHardFloat() const {
535 // FIXME: this is invalid for WindowsCE
536 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
537 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
538 TargetTriple.getEnvironment() == Triple::EABIHF ||
539 isTargetWindows() || isAAPCS16_ABI();
541 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
543 bool isAPCS_ABI() const;
544 bool isAAPCS_ABI() const;
545 bool isAAPCS16_ABI() const;
547 bool useSoftFloat() const { return UseSoftFloat; }
548 bool isThumb() const { return InThumbMode; }
549 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
550 bool isThumb2() const { return InThumbMode && HasThumb2; }
551 bool hasThumb2() const { return HasThumb2; }
552 bool isMClass() const { return ARMProcClass == MClass; }
553 bool isRClass() const { return ARMProcClass == RClass; }
554 bool isAClass() const { return ARMProcClass == AClass; }
556 bool isR9Reserved() const {
557 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
560 /// Returns true if the frame setup is split into two separate pushes (first
561 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
563 bool splitFramePushPop() const {
564 return isTargetMachO();
567 bool useStride4VFPs(const MachineFunction &MF) const;
569 bool useMovt(const MachineFunction &MF) const;
571 bool supportsTailCall() const { return SupportsTailCall; }
573 bool allowsUnalignedMem() const { return !StrictAlign; }
575 bool restrictIT() const { return RestrictIT; }
577 const std::string & getCPUString() const { return CPUString; }
579 bool isLittle() const { return IsLittle; }
581 unsigned getMispredictionPenalty() const;
583 /// This function returns true if the target has sincos() routine in its
584 /// compiler runtime or math libraries.
585 bool hasSinCos() const;
587 /// Returns true if machine scheduler should be enabled.
588 bool enableMachineScheduler() const override;
590 /// True for some subtargets at > -O0.
591 bool enablePostRAScheduler() const override;
593 // enableAtomicExpand- True if we need to expand our atomics.
594 bool enableAtomicExpand() const override;
596 /// getInstrItins - Return the instruction itineraries based on subtarget
598 const InstrItineraryData *getInstrItineraryData() const override {
602 /// getStackAlignment - Returns the minimum alignment known to hold of the
603 /// stack frame on entry to the function and which must be maintained by every
604 /// function for this subtarget.
605 unsigned getStackAlignment() const { return stackAlignment; }
607 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
609 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
611 ARMLdStMultipleTiming getLdStMultipleTiming() const {
612 return LdStMultipleTiming;
615 int getPreISelOperandLatencyAdjustment() const {
616 return PreISelOperandLatencyAdjustment;
619 /// True if the GV will be accessed via an indirect symbol.
620 bool isGVIndirectSymbol(const GlobalValue *GV) const;
622 /// True if fast-isel is used.
623 bool useFastISel() const;
625 } // End llvm namespace
627 #endif // ARMSUBTARGET_H