1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBaseRegisterInfo.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMISelLowering.h"
22 #include "ARMSelectionDAGInfo.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
25 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
26 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
27 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/TargetSubtargetInfo.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/MC/MCSchedule.h"
32 #include "llvm/Target/TargetOptions.h"
36 #define GET_SUBTARGETINFO_HEADER
37 #include "ARMGenSubtargetInfo.inc"
41 class ARMBaseTargetMachine;
45 class ARMSubtarget : public ARMGenSubtargetInfo {
47 enum ARMProcFamilyEnum {
76 enum ARMProcClassEnum {
115 /// What kind of timing do load multiple/store multiple instructions have.
116 enum ARMLdStMultipleTiming {
117 /// Can load/store 2 registers/cycle.
119 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
120 /// is not 64-bit aligned.
121 DoubleIssueCheckUnalignedAccess,
122 /// Can load/store 1 register/cycle.
124 /// Can load/store 1 register/cycle, but needs an extra cycle for address
125 /// computation and potentially also for register writeback.
126 SingleIssuePlusExtras,
130 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
131 ARMProcFamilyEnum ARMProcFamily = Others;
133 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
134 ARMProcClassEnum ARMProcClass = None;
136 /// ARMArch - ARM architecture
137 ARMArchEnum ARMArch = ARMv4t;
139 /// HasV4TOps, HasV5TOps, HasV5TEOps,
140 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
141 /// Specify whether target support specific ARM ISA variants.
142 bool HasV4TOps = false;
143 bool HasV5TOps = false;
144 bool HasV5TEOps = false;
145 bool HasV6Ops = false;
146 bool HasV6MOps = false;
147 bool HasV6KOps = false;
148 bool HasV6T2Ops = false;
149 bool HasV7Ops = false;
150 bool HasV8Ops = false;
151 bool HasV8_1aOps = false;
152 bool HasV8_2aOps = false;
153 bool HasV8_3aOps = false;
154 bool HasV8MBaselineOps = false;
155 bool HasV8MMainlineOps = false;
157 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
158 /// floating point ISAs are supported.
159 bool HasVFPv2 = false;
160 bool HasVFPv3 = false;
161 bool HasVFPv4 = false;
162 bool HasFPARMv8 = false;
163 bool HasNEON = false;
165 /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
166 bool HasDotProd = false;
168 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
169 /// specified. Use the method useNEONForSinglePrecisionFP() to
170 /// determine if NEON should actually be used.
171 bool UseNEONForSinglePrecisionFP = false;
173 /// UseMulOps - True if non-microcoded fused integer multiply-add and
174 /// multiply-subtract instructions should be used.
175 bool UseMulOps = false;
177 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
178 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
179 bool SlowFPVMLx = false;
181 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
182 /// forwarding to allow mul + mla being issued back to back.
183 bool HasVMLxForwarding = false;
185 /// SlowFPBrcc - True if floating point compare + branch is slow.
186 bool SlowFPBrcc = false;
188 /// InThumbMode - True if compiling for Thumb, false for ARM.
189 bool InThumbMode = false;
191 /// UseSoftFloat - True if we're using software floating point features.
192 bool UseSoftFloat = false;
194 /// UseMISched - True if MachineScheduler should be used for this subtarget.
195 bool UseMISched = false;
197 /// DisablePostRAScheduler - False if scheduling should happen again after
198 /// register allocation.
199 bool DisablePostRAScheduler = false;
201 /// HasThumb2 - True if Thumb2 instructions are supported.
202 bool HasThumb2 = false;
204 /// NoARM - True if subtarget does not support ARM mode execution.
207 /// ReserveR9 - True if R9 is not available as a general purpose register.
208 bool ReserveR9 = false;
210 /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
211 /// 32-bit imms (including global addresses).
214 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
215 /// must be able to synthesize call stubs for interworking between ARM and
217 bool SupportsTailCall = false;
219 /// HasFP16 - True if subtarget supports half-precision FP conversions
220 bool HasFP16 = false;
222 /// HasFullFP16 - True if subtarget supports half-precision FP operations
223 bool HasFullFP16 = false;
225 /// HasD16 - True if subtarget is limited to 16 double precision
226 /// FP registers for VFPv3.
229 /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
230 bool HasHardwareDivideInThumb = false;
232 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
233 bool HasHardwareDivideInARM = false;
235 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
237 bool HasDataBarrier = false;
239 /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
241 bool HasFullDataBarrier = false;
243 /// HasV7Clrex - True if the subtarget supports CLREX instructions
244 bool HasV7Clrex = false;
246 /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
248 bool HasAcquireRelease = false;
250 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
251 /// over 16-bit ones.
252 bool Pref32BitThumb = false;
254 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
255 /// that partially update CPSR and add false dependency on the previous
256 /// CPSR setting instruction.
257 bool AvoidCPSRPartialUpdate = false;
259 /// CheapPredicableCPSRDef - If true, disable +1 predication cost
260 /// for instructions updating CPSR. Enabled for Cortex-A57.
261 bool CheapPredicableCPSRDef = false;
263 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
264 /// movs with shifter operand (i.e. asr, lsl, lsr).
265 bool AvoidMOVsShifterOperand = false;
267 /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
268 /// avoid issue "normal" call instructions to callees which do not return.
269 bool HasRetAddrStack = false;
271 /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
272 /// a branch predictor or not changes the expected cost of taking a branch
273 /// which affects the choice of whether to use predicated instructions.
274 bool HasBranchPredictor = true;
276 /// HasMPExtension - True if the subtarget supports Multiprocessing
277 /// extension (ARMv7 only).
278 bool HasMPExtension = false;
280 /// HasVirtualization - True if the subtarget supports the Virtualization
282 bool HasVirtualization = false;
284 /// FPOnlySP - If true, the floating point unit only supports single
286 bool FPOnlySP = false;
288 /// If true, the processor supports the Performance Monitor Extensions. These
289 /// include a generic cycle-counter as well as more fine-grained (often
290 /// implementation-specific) events.
291 bool HasPerfMon = false;
293 /// HasTrustZone - if true, processor supports TrustZone security extensions
294 bool HasTrustZone = false;
296 /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
297 bool Has8MSecExt = false;
299 /// HasCrypto - if true, processor supports Cryptography extensions
300 bool HasCrypto = false;
302 /// HasCRC - if true, processor supports CRC instructions
305 /// HasRAS - if true, the processor supports RAS extensions
308 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
309 /// particularly effective at zeroing a VFP register.
310 bool HasZeroCycleZeroing = false;
312 /// HasFPAO - if true, processor does positive address offset computation faster
313 bool HasFPAO = false;
315 /// HasFuseAES - if true, processor executes back to back AES instruction
317 bool HasFuseAES = false;
319 /// If true, if conversion may decide to leave some instructions unpredicated.
320 bool IsProfitableToUnpredicate = false;
322 /// If true, VMOV will be favored over VGETLNi32.
323 bool HasSlowVGETLNi32 = false;
325 /// If true, VMOV will be favored over VDUP.
326 bool HasSlowVDUP32 = false;
328 /// If true, VMOVSR will be favored over VMOVDRR.
329 bool PreferVMOVSR = false;
331 /// If true, ISHST barriers will be used for Release semantics.
332 bool PreferISHST = false;
334 /// If true, a VLDM/VSTM starting with an odd register number is considered to
335 /// take more microops than single VLDRS/VSTRS.
336 bool SlowOddRegister = false;
338 /// If true, loading into a D subregister will be penalized.
339 bool SlowLoadDSubregister = false;
341 /// If true, the AGU and NEON/FPU units are multiplexed.
342 bool HasMuxedUnits = false;
344 /// If true, VMOVS will never be widened to VMOVD
345 bool DontWidenVMOVS = false;
347 /// If true, run the MLx expansion pass.
348 bool ExpandMLx = false;
350 /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
351 bool HasVMLxHazards = false;
353 // If true, read thread pointer from coprocessor register.
354 bool ReadTPHard = false;
356 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
357 bool UseNEONForFPMovs = false;
359 /// If true, VLDn instructions take an extra cycle for unaligned accesses.
360 bool CheckVLDnAlign = false;
362 /// If true, VFP instructions are not pipelined.
363 bool NonpipelinedVFP = false;
365 /// StrictAlign - If true, the subtarget disallows unaligned memory
366 /// accesses for some types. For details, see
367 /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
368 bool StrictAlign = false;
370 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
371 /// blocks to conform to ARMv8 rule.
372 bool RestrictIT = false;
374 /// HasDSP - If true, the subtarget supports the DSP (saturating arith
375 /// and such) instructions.
378 /// NaCl TRAP instruction is generated instead of the regular TRAP.
379 bool UseNaClTrap = false;
381 /// Generate calls via indirect call instructions.
382 bool GenLongCalls = false;
384 /// Generate code that does not contain data access to code sections.
385 bool GenExecuteOnly = false;
387 /// Target machine allowed unsafe FP math (such as use of NEON fp)
388 bool UnsafeFPMath = false;
390 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
391 bool UseSjLjEH = false;
393 /// Implicitly convert an instruction to a different one if its immediates
394 /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
395 bool NegativeImmediates = true;
397 /// stackAlignment - The minimum alignment known to hold of the stack frame on
398 /// entry to the function and which must be maintained by every function.
399 unsigned stackAlignment = 4;
401 /// CPUString - String name of used CPU.
402 std::string CPUString;
404 unsigned MaxInterleaveFactor = 1;
406 /// Clearance before partial register updates (in number of instructions)
407 unsigned PartialUpdateClearance = 0;
409 /// What kind of timing do load multiple/store multiple have (double issue,
410 /// single issue etc).
411 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
413 /// The adjustment that we need to apply to get the operand latency from the
414 /// operand cycle returned by the itinerary data for pre-ISel operands.
415 int PreISelOperandLatencyAdjustment = 2;
417 /// IsLittle - The target is Little Endian
420 /// TargetTriple - What processor and OS we're targeting.
423 /// SchedModel - Processor specific instruction costs.
424 MCSchedModel SchedModel;
426 /// Selected instruction itineraries (one entry per itinerary class.)
427 InstrItineraryData InstrItins;
429 /// Options passed via command line that could influence the target
430 const TargetOptions &Options;
432 const ARMBaseTargetMachine &TM;
435 /// This constructor initializes the data members to match that
436 /// of the specified triple.
438 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
439 const ARMBaseTargetMachine &TM, bool IsLittle);
441 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
442 /// that still makes it profitable to inline the call.
443 unsigned getMaxInlineSizeThreshold() const {
447 /// ParseSubtargetFeatures - Parses features string setting specified
448 /// subtarget options. Definition of function is auto generated by tblgen.
449 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
451 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
452 /// so that we can use initializer lists for subtarget initialization.
453 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
455 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
459 const ARMBaseInstrInfo *getInstrInfo() const override {
460 return InstrInfo.get();
463 const ARMTargetLowering *getTargetLowering() const override {
467 const ARMFrameLowering *getFrameLowering() const override {
468 return FrameLowering.get();
471 const ARMBaseRegisterInfo *getRegisterInfo() const override {
472 return &InstrInfo->getRegisterInfo();
475 const CallLowering *getCallLowering() const override;
476 const InstructionSelector *getInstructionSelector() const override;
477 const LegalizerInfo *getLegalizerInfo() const override;
478 const RegisterBankInfo *getRegBankInfo() const override;
481 ARMSelectionDAGInfo TSInfo;
482 // Either Thumb1FrameLowering or ARMFrameLowering.
483 std::unique_ptr<ARMFrameLowering> FrameLowering;
484 // Either Thumb1InstrInfo or Thumb2InstrInfo.
485 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
486 ARMTargetLowering TLInfo;
488 /// GlobalISel related APIs.
489 std::unique_ptr<CallLowering> CallLoweringInfo;
490 std::unique_ptr<InstructionSelector> InstSelector;
491 std::unique_ptr<LegalizerInfo> Legalizer;
492 std::unique_ptr<RegisterBankInfo> RegBankInfo;
494 void initializeEnvironment();
495 void initSubtargetFeatures(StringRef CPU, StringRef FS);
496 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
499 void computeIssueWidth();
501 bool hasV4TOps() const { return HasV4TOps; }
502 bool hasV5TOps() const { return HasV5TOps; }
503 bool hasV5TEOps() const { return HasV5TEOps; }
504 bool hasV6Ops() const { return HasV6Ops; }
505 bool hasV6MOps() const { return HasV6MOps; }
506 bool hasV6KOps() const { return HasV6KOps; }
507 bool hasV6T2Ops() const { return HasV6T2Ops; }
508 bool hasV7Ops() const { return HasV7Ops; }
509 bool hasV8Ops() const { return HasV8Ops; }
510 bool hasV8_1aOps() const { return HasV8_1aOps; }
511 bool hasV8_2aOps() const { return HasV8_2aOps; }
512 bool hasV8_3aOps() const { return HasV8_3aOps; }
513 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
514 bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
517 /// These functions are obsolete, please consider adding subtarget features
518 /// or properties instead of calling them.
519 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
520 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
521 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
522 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
523 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
524 bool isSwift() const { return ARMProcFamily == Swift; }
525 bool isCortexM3() const { return ARMProcFamily == CortexM3; }
526 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
527 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
528 bool isKrait() const { return ARMProcFamily == Krait; }
531 bool hasARMOps() const { return !NoARM; }
533 bool hasVFP2() const { return HasVFPv2; }
534 bool hasVFP3() const { return HasVFPv3; }
535 bool hasVFP4() const { return HasVFPv4; }
536 bool hasFPARMv8() const { return HasFPARMv8; }
537 bool hasNEON() const { return HasNEON; }
538 bool hasCrypto() const { return HasCrypto; }
539 bool hasDotProd() const { return HasDotProd; }
540 bool hasCRC() const { return HasCRC; }
541 bool hasRAS() const { return HasRAS; }
542 bool hasVirtualization() const { return HasVirtualization; }
544 bool useNEONForSinglePrecisionFP() const {
545 return hasNEON() && UseNEONForSinglePrecisionFP;
548 bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
549 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
550 bool hasDataBarrier() const { return HasDataBarrier; }
551 bool hasFullDataBarrier() const { return HasFullDataBarrier; }
552 bool hasV7Clrex() const { return HasV7Clrex; }
553 bool hasAcquireRelease() const { return HasAcquireRelease; }
555 bool hasAnyDataBarrier() const {
556 return HasDataBarrier || (hasV6Ops() && !isThumb());
559 bool useMulOps() const { return UseMulOps; }
560 bool useFPVMLx() const { return !SlowFPVMLx; }
561 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
562 bool isFPBrccSlow() const { return SlowFPBrcc; }
563 bool isFPOnlySP() const { return FPOnlySP; }
564 bool hasPerfMon() const { return HasPerfMon; }
565 bool hasTrustZone() const { return HasTrustZone; }
566 bool has8MSecExt() const { return Has8MSecExt; }
567 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
568 bool hasFPAO() const { return HasFPAO; }
569 bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
570 bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
571 bool hasSlowVDUP32() const { return HasSlowVDUP32; }
572 bool preferVMOVSR() const { return PreferVMOVSR; }
573 bool preferISHSTBarriers() const { return PreferISHST; }
574 bool expandMLx() const { return ExpandMLx; }
575 bool hasVMLxHazards() const { return HasVMLxHazards; }
576 bool hasSlowOddRegister() const { return SlowOddRegister; }
577 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
578 bool hasMuxedUnits() const { return HasMuxedUnits; }
579 bool dontWidenVMOVS() const { return DontWidenVMOVS; }
580 bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
581 bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
582 bool nonpipelinedVFP() const { return NonpipelinedVFP; }
583 bool prefers32BitThumb() const { return Pref32BitThumb; }
584 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
585 bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
586 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
587 bool hasRetAddrStack() const { return HasRetAddrStack; }
588 bool hasBranchPredictor() const { return HasBranchPredictor; }
589 bool hasMPExtension() const { return HasMPExtension; }
590 bool hasDSP() const { return HasDSP; }
591 bool useNaClTrap() const { return UseNaClTrap; }
592 bool useSjLjEH() const { return UseSjLjEH; }
593 bool genLongCalls() const { return GenLongCalls; }
594 bool genExecuteOnly() const { return GenExecuteOnly; }
596 bool hasFP16() const { return HasFP16; }
597 bool hasD16() const { return HasD16; }
598 bool hasFullFP16() const { return HasFullFP16; }
600 bool hasFuseAES() const { return HasFuseAES; }
601 /// \brief Return true if the CPU supports any kind of instruction fusion.
602 bool hasFusion() const { return hasFuseAES(); }
604 const Triple &getTargetTriple() const { return TargetTriple; }
606 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
607 bool isTargetIOS() const { return TargetTriple.isiOS(); }
608 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
609 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
610 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
611 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
612 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
613 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
615 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
616 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
617 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
619 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
620 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
621 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
622 // even for GNUEABI, so we can make a distinction here and still conform to
623 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
624 // FIXME: The Darwin exception is temporary, while we move users to
625 // "*-*-*-macho" triples as quickly as possible.
626 bool isTargetAEABI() const {
627 return (TargetTriple.getEnvironment() == Triple::EABI ||
628 TargetTriple.getEnvironment() == Triple::EABIHF) &&
629 !isTargetDarwin() && !isTargetWindows();
631 bool isTargetGNUAEABI() const {
632 return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
633 TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
634 !isTargetDarwin() && !isTargetWindows();
636 bool isTargetMuslAEABI() const {
637 return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
638 TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
639 !isTargetDarwin() && !isTargetWindows();
642 // ARM Targets that support EHABI exception handling standard
643 // Darwin uses SjLj. Other targets might need more checks.
644 bool isTargetEHABICompatible() const {
645 return (TargetTriple.getEnvironment() == Triple::EABI ||
646 TargetTriple.getEnvironment() == Triple::GNUEABI ||
647 TargetTriple.getEnvironment() == Triple::MuslEABI ||
648 TargetTriple.getEnvironment() == Triple::EABIHF ||
649 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
650 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
651 isTargetAndroid()) &&
652 !isTargetDarwin() && !isTargetWindows();
655 bool isTargetHardFloat() const {
656 // FIXME: this is invalid for WindowsCE
657 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
658 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
659 TargetTriple.getEnvironment() == Triple::EABIHF ||
660 isTargetWindows() || isAAPCS16_ABI();
663 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
665 bool isXRaySupported() const override;
667 bool isAPCS_ABI() const;
668 bool isAAPCS_ABI() const;
669 bool isAAPCS16_ABI() const;
674 bool useMachineScheduler() const { return UseMISched; }
675 bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
676 bool useSoftFloat() const { return UseSoftFloat; }
677 bool isThumb() const { return InThumbMode; }
678 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
679 bool isThumb2() const { return InThumbMode && HasThumb2; }
680 bool hasThumb2() const { return HasThumb2; }
681 bool isMClass() const { return ARMProcClass == MClass; }
682 bool isRClass() const { return ARMProcClass == RClass; }
683 bool isAClass() const { return ARMProcClass == AClass; }
684 bool isReadTPHard() const { return ReadTPHard; }
686 bool isR9Reserved() const {
687 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
690 bool useR7AsFramePointer() const {
691 return isTargetDarwin() || (!isTargetWindows() && isThumb());
694 /// Returns true if the frame setup is split into two separate pushes (first
695 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
696 /// to lr. This is always required on Thumb1-only targets, as the push and
697 /// pop instructions can't access the high registers.
698 bool splitFramePushPop(const MachineFunction &MF) const {
699 return (useR7AsFramePointer() &&
700 MF.getTarget().Options.DisableFramePointerElim(MF)) ||
704 bool useStride4VFPs(const MachineFunction &MF) const;
706 bool useMovt(const MachineFunction &MF) const;
708 bool supportsTailCall() const { return SupportsTailCall; }
710 bool allowsUnalignedMem() const { return !StrictAlign; }
712 bool restrictIT() const { return RestrictIT; }
714 const std::string & getCPUString() const { return CPUString; }
716 bool isLittle() const { return IsLittle; }
718 unsigned getMispredictionPenalty() const;
720 /// Returns true if machine scheduler should be enabled.
721 bool enableMachineScheduler() const override;
723 /// True for some subtargets at > -O0.
724 bool enablePostRAScheduler() const override;
726 // enableAtomicExpand- True if we need to expand our atomics.
727 bool enableAtomicExpand() const override;
729 /// getInstrItins - Return the instruction itineraries based on subtarget
731 const InstrItineraryData *getInstrItineraryData() const override {
735 /// getStackAlignment - Returns the minimum alignment known to hold of the
736 /// stack frame on entry to the function and which must be maintained by every
737 /// function for this subtarget.
738 unsigned getStackAlignment() const { return stackAlignment; }
740 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
742 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
744 ARMLdStMultipleTiming getLdStMultipleTiming() const {
745 return LdStMultipleTiming;
748 int getPreISelOperandLatencyAdjustment() const {
749 return PreISelOperandLatencyAdjustment;
752 /// True if the GV will be accessed via an indirect symbol.
753 bool isGVIndirectSymbol(const GlobalValue *GV) const;
755 /// Returns the constant pool modifier needed to access the GV.
756 bool isGVInGOT(const GlobalValue *GV) const;
758 /// True if fast-isel is used.
759 bool useFastISel() const;
761 /// Returns the correct return opcode for the current feature set.
762 /// Use BX if available to allow mixing thumb/arm code, but fall back
763 /// to plain mov pc,lr on ARMv4.
764 unsigned getReturnOpcode() const {
772 /// Allow movt+movw for PIC global address calculation.
773 /// ELF does not have GOT relocations for movt+movw.
774 /// ROPI does not use GOT.
775 bool allowPositionIndependentMovt() const {
776 return isROPI() || !isTargetELF();
780 } // end namespace llvm
782 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H