1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/Target/TargetSubtargetInfo.h"
34 #define GET_SUBTARGETINFO_HEADER
35 #include "ARMGenSubtargetInfo.inc"
41 class ARMBaseTargetMachine;
43 class ARMSubtarget : public ARMGenSubtargetInfo {
45 enum ARMProcFamilyEnum {
46 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
47 CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexR52, CortexM3,
48 CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,
49 Krait, Swift, ExynosM1
51 enum ARMProcClassEnum {
52 None, AClass, RClass, MClass
55 ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
56 ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
57 ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline,
62 /// What kind of timing do load multiple/store multiple instructions have.
63 enum ARMLdStMultipleTiming {
64 /// Can load/store 2 registers/cycle.
66 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
67 /// is not 64-bit aligned.
68 DoubleIssueCheckUnalignedAccess,
69 /// Can load/store 1 register/cycle.
71 /// Can load/store 1 register/cycle, but needs an extra cycle for address
72 /// computation and potentially also for register writeback.
73 SingleIssuePlusExtras,
77 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
78 ARMProcFamilyEnum ARMProcFamily = Others;
80 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
81 ARMProcClassEnum ARMProcClass = None;
83 /// ARMArch - ARM architecture
84 ARMArchEnum ARMArch = ARMv4t;
86 /// HasV4TOps, HasV5TOps, HasV5TEOps,
87 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
88 /// Specify whether target support specific ARM ISA variants.
89 bool HasV4TOps = false;
90 bool HasV5TOps = false;
91 bool HasV5TEOps = false;
92 bool HasV6Ops = false;
93 bool HasV6MOps = false;
94 bool HasV6KOps = false;
95 bool HasV6T2Ops = false;
96 bool HasV7Ops = false;
97 bool HasV8Ops = false;
98 bool HasV8_1aOps = false;
99 bool HasV8_2aOps = false;
100 bool HasV8MBaselineOps = false;
101 bool HasV8MMainlineOps = false;
103 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
104 /// floating point ISAs are supported.
105 bool HasVFPv2 = false;
106 bool HasVFPv3 = false;
107 bool HasVFPv4 = false;
108 bool HasFPARMv8 = false;
109 bool HasNEON = false;
111 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
112 /// specified. Use the method useNEONForSinglePrecisionFP() to
113 /// determine if NEON should actually be used.
114 bool UseNEONForSinglePrecisionFP = false;
116 /// UseMulOps - True if non-microcoded fused integer multiply-add and
117 /// multiply-subtract instructions should be used.
118 bool UseMulOps = false;
120 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
121 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
122 bool SlowFPVMLx = false;
124 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
125 /// forwarding to allow mul + mla being issued back to back.
126 bool HasVMLxForwarding = false;
128 /// SlowFPBrcc - True if floating point compare + branch is slow.
129 bool SlowFPBrcc = false;
131 /// InThumbMode - True if compiling for Thumb, false for ARM.
132 bool InThumbMode = false;
134 /// UseSoftFloat - True if we're using software floating point features.
135 bool UseSoftFloat = false;
137 /// HasThumb2 - True if Thumb2 instructions are supported.
138 bool HasThumb2 = false;
140 /// NoARM - True if subtarget does not support ARM mode execution.
143 /// ReserveR9 - True if R9 is not available as a general purpose register.
144 bool ReserveR9 = false;
146 /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
147 /// 32-bit imms (including global addresses).
150 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
151 /// must be able to synthesize call stubs for interworking between ARM and
153 bool SupportsTailCall = false;
155 /// HasFP16 - True if subtarget supports half-precision FP conversions
156 bool HasFP16 = false;
158 /// HasFullFP16 - True if subtarget supports half-precision FP operations
159 bool HasFullFP16 = false;
161 /// HasD16 - True if subtarget is limited to 16 double precision
162 /// FP registers for VFPv3.
165 /// HasHardwareDivide - True if subtarget supports [su]div
166 bool HasHardwareDivide = false;
168 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
169 bool HasHardwareDivideInARM = false;
171 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
173 bool HasT2ExtractPack = false;
175 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
177 bool HasDataBarrier = false;
179 /// HasV7Clrex - True if the subtarget supports CLREX instructions
180 bool HasV7Clrex = false;
182 /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
184 bool HasAcquireRelease = false;
186 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
187 /// over 16-bit ones.
188 bool Pref32BitThumb = false;
190 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
191 /// that partially update CPSR and add false dependency on the previous
192 /// CPSR setting instruction.
193 bool AvoidCPSRPartialUpdate = false;
195 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
196 /// movs with shifter operand (i.e. asr, lsl, lsr).
197 bool AvoidMOVsShifterOperand = false;
199 /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
200 /// avoid issue "normal" call instructions to callees which do not return.
201 bool HasRetAddrStack = false;
203 /// HasMPExtension - True if the subtarget supports Multiprocessing
204 /// extension (ARMv7 only).
205 bool HasMPExtension = false;
207 /// HasVirtualization - True if the subtarget supports the Virtualization
209 bool HasVirtualization = false;
211 /// FPOnlySP - If true, the floating point unit only supports single
213 bool FPOnlySP = false;
215 /// If true, the processor supports the Performance Monitor Extensions. These
216 /// include a generic cycle-counter as well as more fine-grained (often
217 /// implementation-specific) events.
218 bool HasPerfMon = false;
220 /// HasTrustZone - if true, processor supports TrustZone security extensions
221 bool HasTrustZone = false;
223 /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
224 bool Has8MSecExt = false;
226 /// HasCrypto - if true, processor supports Cryptography extensions
227 bool HasCrypto = false;
229 /// HasCRC - if true, processor supports CRC instructions
232 /// HasRAS - if true, the processor supports RAS extensions
235 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
236 /// particularly effective at zeroing a VFP register.
237 bool HasZeroCycleZeroing = false;
239 /// HasFPAO - if true, processor does positive address offset computation faster
240 bool HasFPAO = false;
242 /// If true, if conversion may decide to leave some instructions unpredicated.
243 bool IsProfitableToUnpredicate = false;
245 /// If true, VMOV will be favored over VGETLNi32.
246 bool HasSlowVGETLNi32 = false;
248 /// If true, VMOV will be favored over VDUP.
249 bool HasSlowVDUP32 = false;
251 /// If true, VMOVSR will be favored over VMOVDRR.
252 bool PreferVMOVSR = false;
254 /// If true, ISHST barriers will be used for Release semantics.
255 bool PreferISHST = false;
257 /// If true, a VLDM/VSTM starting with an odd register number is considered to
258 /// take more microops than single VLDRS/VSTRS.
259 bool SlowOddRegister = false;
261 /// If true, loading into a D subregister will be penalized.
262 bool SlowLoadDSubregister = false;
264 /// If true, the AGU and NEON/FPU units are multiplexed.
265 bool HasMuxedUnits = false;
267 /// If true, VMOVS will never be widened to VMOVD
268 bool DontWidenVMOVS = false;
270 /// If true, run the MLx expansion pass.
271 bool ExpandMLx = false;
273 /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
274 bool HasVMLxHazards = false;
276 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
277 bool UseNEONForFPMovs = false;
279 /// If true, VLDn instructions take an extra cycle for unaligned accesses.
280 bool CheckVLDnAlign = false;
282 /// If true, VFP instructions are not pipelined.
283 bool NonpipelinedVFP = false;
285 /// StrictAlign - If true, the subtarget disallows unaligned memory
286 /// accesses for some types. For details, see
287 /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
288 bool StrictAlign = false;
290 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
291 /// blocks to conform to ARMv8 rule.
292 bool RestrictIT = false;
294 /// HasDSP - If true, the subtarget supports the DSP (saturating arith
295 /// and such) instructions.
298 /// NaCl TRAP instruction is generated instead of the regular TRAP.
299 bool UseNaClTrap = false;
301 /// Generate calls via indirect call instructions.
302 bool GenLongCalls = false;
304 /// Generate code that does not contain data access to code sections.
305 bool GenExecuteOnly = false;
307 /// Target machine allowed unsafe FP math (such as use of NEON fp)
308 bool UnsafeFPMath = false;
310 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
311 bool UseSjLjEH = false;
313 /// stackAlignment - The minimum alignment known to hold of the stack frame on
314 /// entry to the function and which must be maintained by every function.
315 unsigned stackAlignment = 4;
317 /// CPUString - String name of used CPU.
318 std::string CPUString;
320 unsigned MaxInterleaveFactor = 1;
322 /// Clearance before partial register updates (in number of instructions)
323 unsigned PartialUpdateClearance = 0;
325 /// What kind of timing do load multiple/store multiple have (double issue,
326 /// single issue etc).
327 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
329 /// The adjustment that we need to apply to get the operand latency from the
330 /// operand cycle returned by the itinerary data for pre-ISel operands.
331 int PreISelOperandLatencyAdjustment = 2;
333 /// IsLittle - The target is Little Endian
336 /// TargetTriple - What processor and OS we're targeting.
339 /// SchedModel - Processor specific instruction costs.
340 MCSchedModel SchedModel;
342 /// Selected instruction itineraries (one entry per itinerary class.)
343 InstrItineraryData InstrItins;
345 /// Options passed via command line that could influence the target
346 const TargetOptions &Options;
348 const ARMBaseTargetMachine &TM;
351 /// This constructor initializes the data members to match that
352 /// of the specified triple.
354 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
355 const ARMBaseTargetMachine &TM, bool IsLittle);
357 /// This object will take onwership of \p GISelAccessor.
358 void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); }
360 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
361 /// that still makes it profitable to inline the call.
362 unsigned getMaxInlineSizeThreshold() const {
365 /// ParseSubtargetFeatures - Parses features string setting specified
366 /// subtarget options. Definition of function is auto generated by tblgen.
367 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
369 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
370 /// so that we can use initializer lists for subtarget initialization.
371 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
373 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
376 const ARMBaseInstrInfo *getInstrInfo() const override {
377 return InstrInfo.get();
379 const ARMTargetLowering *getTargetLowering() const override {
382 const ARMFrameLowering *getFrameLowering() const override {
383 return FrameLowering.get();
385 const ARMBaseRegisterInfo *getRegisterInfo() const override {
386 return &InstrInfo->getRegisterInfo();
389 const CallLowering *getCallLowering() const override;
390 const InstructionSelector *getInstructionSelector() const override;
391 const LegalizerInfo *getLegalizerInfo() const override;
392 const RegisterBankInfo *getRegBankInfo() const override;
395 ARMSelectionDAGInfo TSInfo;
396 // Either Thumb1FrameLowering or ARMFrameLowering.
397 std::unique_ptr<ARMFrameLowering> FrameLowering;
398 // Either Thumb1InstrInfo or Thumb2InstrInfo.
399 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
400 ARMTargetLowering TLInfo;
402 /// Gather the accessor points to GlobalISel-related APIs.
403 /// This is used to avoid ifndefs spreading around while GISel is
404 /// an optional library.
405 std::unique_ptr<GISelAccessor> GISel;
407 void initializeEnvironment();
408 void initSubtargetFeatures(StringRef CPU, StringRef FS);
409 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
412 void computeIssueWidth();
414 bool hasV4TOps() const { return HasV4TOps; }
415 bool hasV5TOps() const { return HasV5TOps; }
416 bool hasV5TEOps() const { return HasV5TEOps; }
417 bool hasV6Ops() const { return HasV6Ops; }
418 bool hasV6MOps() const { return HasV6MOps; }
419 bool hasV6KOps() const { return HasV6KOps; }
420 bool hasV6T2Ops() const { return HasV6T2Ops; }
421 bool hasV7Ops() const { return HasV7Ops; }
422 bool hasV8Ops() const { return HasV8Ops; }
423 bool hasV8_1aOps() const { return HasV8_1aOps; }
424 bool hasV8_2aOps() const { return HasV8_2aOps; }
425 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
426 bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
429 /// These functions are obsolete, please consider adding subtarget features
430 /// or properties instead of calling them.
431 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
432 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
433 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
434 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
435 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
436 bool isSwift() const { return ARMProcFamily == Swift; }
437 bool isCortexM3() const { return ARMProcFamily == CortexM3; }
438 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
439 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
440 bool isKrait() const { return ARMProcFamily == Krait; }
443 bool hasARMOps() const { return !NoARM; }
445 bool hasVFP2() const { return HasVFPv2; }
446 bool hasVFP3() const { return HasVFPv3; }
447 bool hasVFP4() const { return HasVFPv4; }
448 bool hasFPARMv8() const { return HasFPARMv8; }
449 bool hasNEON() const { return HasNEON; }
450 bool hasCrypto() const { return HasCrypto; }
451 bool hasCRC() const { return HasCRC; }
452 bool hasRAS() const { return HasRAS; }
453 bool hasVirtualization() const { return HasVirtualization; }
454 bool useNEONForSinglePrecisionFP() const {
455 return hasNEON() && UseNEONForSinglePrecisionFP;
458 bool hasDivide() const { return HasHardwareDivide; }
459 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
460 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
461 bool hasDataBarrier() const { return HasDataBarrier; }
462 bool hasV7Clrex() const { return HasV7Clrex; }
463 bool hasAcquireRelease() const { return HasAcquireRelease; }
464 bool hasAnyDataBarrier() const {
465 return HasDataBarrier || (hasV6Ops() && !isThumb());
467 bool useMulOps() const { return UseMulOps; }
468 bool useFPVMLx() const { return !SlowFPVMLx; }
469 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
470 bool isFPBrccSlow() const { return SlowFPBrcc; }
471 bool isFPOnlySP() const { return FPOnlySP; }
472 bool hasPerfMon() const { return HasPerfMon; }
473 bool hasTrustZone() const { return HasTrustZone; }
474 bool has8MSecExt() const { return Has8MSecExt; }
475 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
476 bool hasFPAO() const { return HasFPAO; }
477 bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
478 bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
479 bool hasSlowVDUP32() const { return HasSlowVDUP32; }
480 bool preferVMOVSR() const { return PreferVMOVSR; }
481 bool preferISHSTBarriers() const { return PreferISHST; }
482 bool expandMLx() const { return ExpandMLx; }
483 bool hasVMLxHazards() const { return HasVMLxHazards; }
484 bool hasSlowOddRegister() const { return SlowOddRegister; }
485 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
486 bool hasMuxedUnits() const { return HasMuxedUnits; }
487 bool dontWidenVMOVS() const { return DontWidenVMOVS; }
488 bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
489 bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
490 bool nonpipelinedVFP() const { return NonpipelinedVFP; }
491 bool prefers32BitThumb() const { return Pref32BitThumb; }
492 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
493 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
494 bool hasRetAddrStack() const { return HasRetAddrStack; }
495 bool hasMPExtension() const { return HasMPExtension; }
496 bool hasDSP() const { return HasDSP; }
497 bool useNaClTrap() const { return UseNaClTrap; }
498 bool useSjLjEH() const { return UseSjLjEH; }
499 bool genLongCalls() const { return GenLongCalls; }
500 bool genExecuteOnly() const { return GenExecuteOnly; }
502 bool hasFP16() const { return HasFP16; }
503 bool hasD16() const { return HasD16; }
504 bool hasFullFP16() const { return HasFullFP16; }
506 const Triple &getTargetTriple() const { return TargetTriple; }
508 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
509 bool isTargetIOS() const { return TargetTriple.isiOS(); }
510 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
511 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
512 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
513 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
514 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
515 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
517 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
518 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
519 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
521 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
522 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
523 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
524 // even for GNUEABI, so we can make a distinction here and still conform to
525 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
526 // FIXME: The Darwin exception is temporary, while we move users to
527 // "*-*-*-macho" triples as quickly as possible.
528 bool isTargetAEABI() const {
529 return (TargetTriple.getEnvironment() == Triple::EABI ||
530 TargetTriple.getEnvironment() == Triple::EABIHF) &&
531 !isTargetDarwin() && !isTargetWindows();
533 bool isTargetGNUAEABI() const {
534 return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
535 TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
536 !isTargetDarwin() && !isTargetWindows();
538 bool isTargetMuslAEABI() const {
539 return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
540 TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
541 !isTargetDarwin() && !isTargetWindows();
544 // ARM Targets that support EHABI exception handling standard
545 // Darwin uses SjLj. Other targets might need more checks.
546 bool isTargetEHABICompatible() const {
547 return (TargetTriple.getEnvironment() == Triple::EABI ||
548 TargetTriple.getEnvironment() == Triple::GNUEABI ||
549 TargetTriple.getEnvironment() == Triple::MuslEABI ||
550 TargetTriple.getEnvironment() == Triple::EABIHF ||
551 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
552 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
553 isTargetAndroid()) &&
554 !isTargetDarwin() && !isTargetWindows();
557 bool isTargetHardFloat() const {
558 // FIXME: this is invalid for WindowsCE
559 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
560 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
561 TargetTriple.getEnvironment() == Triple::EABIHF ||
562 isTargetWindows() || isAAPCS16_ABI();
564 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
566 virtual bool isXRaySupported() const override;
568 bool isAPCS_ABI() const;
569 bool isAAPCS_ABI() const;
570 bool isAAPCS16_ABI() const;
575 bool useSoftFloat() const { return UseSoftFloat; }
576 bool isThumb() const { return InThumbMode; }
577 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
578 bool isThumb2() const { return InThumbMode && HasThumb2; }
579 bool hasThumb2() const { return HasThumb2; }
580 bool isMClass() const { return ARMProcClass == MClass; }
581 bool isRClass() const { return ARMProcClass == RClass; }
582 bool isAClass() const { return ARMProcClass == AClass; }
584 bool isR9Reserved() const {
585 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
588 bool useR7AsFramePointer() const {
589 return isTargetDarwin() || (!isTargetWindows() && isThumb());
591 /// Returns true if the frame setup is split into two separate pushes (first
592 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
593 /// to lr. This is always required on Thumb1-only targets, as the push and
594 /// pop instructions can't access the high registers.
595 bool splitFramePushPop(const MachineFunction &MF) const {
596 return (useR7AsFramePointer() &&
597 MF.getTarget().Options.DisableFramePointerElim(MF)) ||
601 bool useStride4VFPs(const MachineFunction &MF) const;
603 bool useMovt(const MachineFunction &MF) const;
605 bool supportsTailCall() const { return SupportsTailCall; }
607 bool allowsUnalignedMem() const { return !StrictAlign; }
609 bool restrictIT() const { return RestrictIT; }
611 const std::string & getCPUString() const { return CPUString; }
613 bool isLittle() const { return IsLittle; }
615 unsigned getMispredictionPenalty() const;
617 /// This function returns true if the target has sincos() routine in its
618 /// compiler runtime or math libraries.
619 bool hasSinCos() const;
621 /// Returns true if machine scheduler should be enabled.
622 bool enableMachineScheduler() const override;
624 /// True for some subtargets at > -O0.
625 bool enablePostRAScheduler() const override;
627 // enableAtomicExpand- True if we need to expand our atomics.
628 bool enableAtomicExpand() const override;
630 /// getInstrItins - Return the instruction itineraries based on subtarget
632 const InstrItineraryData *getInstrItineraryData() const override {
636 /// getStackAlignment - Returns the minimum alignment known to hold of the
637 /// stack frame on entry to the function and which must be maintained by every
638 /// function for this subtarget.
639 unsigned getStackAlignment() const { return stackAlignment; }
641 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
643 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
645 ARMLdStMultipleTiming getLdStMultipleTiming() const {
646 return LdStMultipleTiming;
649 int getPreISelOperandLatencyAdjustment() const {
650 return PreISelOperandLatencyAdjustment;
653 /// True if the GV will be accessed via an indirect symbol.
654 bool isGVIndirectSymbol(const GlobalValue *GV) const;
656 /// True if fast-isel is used.
657 bool useFastISel() const;
659 } // End llvm namespace
661 #endif // ARMSUBTARGET_H