1 //===-- ARMSystemRegister.td - ARM Register defs -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 include "llvm/TableGen/SearchableTable.td"
12 //===----------------------------------------------------------------------===//
13 // Declarations that describe the ARM system-registers
14 //===----------------------------------------------------------------------===//
16 // M-Class System Registers.
17 // 'Mask' bits create unique keys for searches.
19 class MClassSysReg<bits<1> UniqMask1,
23 string name> : SearchableTable {
24 let SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
26 bits<13> M1Encoding12;
27 bits<10> M2M3Encoding8;
31 let EnumValueField = "M1Encoding12";
32 let EnumValueField = "M2M3Encoding8";
33 let EnumValueField = "Encoding";
35 let M1Encoding12{12} = UniqMask1;
36 let M1Encoding12{11-00} = Enc12;
39 let M2M3Encoding8{9} = UniqMask2;
40 let M2M3Encoding8{8} = UniqMask3;
41 let M2M3Encoding8{7-0} = Enc12{7-0};
42 code Requires = [{ {} }];
45 // [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr.
46 // Mask1 Mask2 Mask3 Enc12, Name
47 let Requires = [{ {ARM::FeatureDSP} }] in {
48 def : MClassSysReg<0, 0, 0, 0x400, "apsr_g">;
49 def : MClassSysReg<0, 1, 1, 0xc00, "apsr_nzcvqg">;
50 def : MClassSysReg<0, 0, 0, 0x401, "iapsr_g">;
51 def : MClassSysReg<0, 1, 1, 0xc01, "iapsr_nzcvqg">;
52 def : MClassSysReg<0, 0, 0, 0x402, "eapsr_g">;
53 def : MClassSysReg<0, 1, 1, 0xc02, "eapsr_nzcvqg">;
54 def : MClassSysReg<0, 0, 0, 0x403, "xpsr_g">;
55 def : MClassSysReg<0, 1, 1, 0xc03, "xpsr_nzcvqg">;
58 def : MClassSysReg<0, 0, 1, 0x800, "apsr">;
59 def : MClassSysReg<1, 1, 0, 0x800, "apsr_nzcvq">;
60 def : MClassSysReg<0, 0, 1, 0x801, "iapsr">;
61 def : MClassSysReg<1, 1, 0, 0x801, "iapsr_nzcvq">;
62 def : MClassSysReg<0, 0, 1, 0x802, "eapsr">;
63 def : MClassSysReg<1, 1, 0, 0x802, "eapsr_nzcvq">;
64 def : MClassSysReg<0, 0, 1, 0x803, "xpsr">;
65 def : MClassSysReg<1, 1, 0, 0x803, "xpsr_nzcvq">;
67 def : MClassSysReg<0, 0, 1, 0x805, "ipsr">;
68 def : MClassSysReg<0, 0, 1, 0x806, "epsr">;
69 def : MClassSysReg<0, 0, 1, 0x807, "iepsr">;
70 def : MClassSysReg<0, 0, 1, 0x808, "msp">;
71 def : MClassSysReg<0, 0, 1, 0x809, "psp">;
73 let Requires = [{ {ARM::HasV8MBaselineOps} }] in {
74 def : MClassSysReg<0, 0, 1, 0x80a, "msplim">;
75 def : MClassSysReg<0, 0, 1, 0x80b, "psplim">;
78 def : MClassSysReg<0, 0, 1, 0x810, "primask">;
80 let Requires = [{ {ARM::HasV7Ops} }] in {
81 def : MClassSysReg<0, 0, 1, 0x811, "basepri">;
82 def : MClassSysReg<0, 0, 1, 0x812, "basepri_max">;
83 def : MClassSysReg<0, 0, 1, 0x813, "faultmask">;
86 def : MClassSysReg<0, 0, 1, 0x814, "control">;
88 let Requires = [{ {ARM::Feature8MSecExt} }] in {
89 def : MClassSysReg<0, 0, 1, 0x888, "msp_ns">;
90 def : MClassSysReg<0, 0, 1, 0x889, "psp_ns">;
93 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in {
94 def : MClassSysReg<0, 0, 1, 0x88a, "msplim_ns">;
95 def : MClassSysReg<0, 0, 1, 0x88b, "psplim_ns">;
98 def : MClassSysReg<0, 0, 1, 0x890, "primask_ns">;
100 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in {
101 def : MClassSysReg<0, 0, 1, 0x891, "basepri_ns">;
102 def : MClassSysReg<0, 0, 1, 0x893, "faultmask_ns">;
105 let Requires = [{ {ARM::Feature8MSecExt} }] in {
106 def : MClassSysReg<0, 0, 1, 0x894, "control_ns">;
107 def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">;
113 class BankedReg<string name, bits<8> enc>
119 let SearchableFields = ["Name", "Encoding"];
122 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
124 def : BankedReg<"r8_usr", 0x00>;
125 def : BankedReg<"r9_usr", 0x01>;
126 def : BankedReg<"r10_usr", 0x02>;
127 def : BankedReg<"r11_usr", 0x03>;
128 def : BankedReg<"r12_usr", 0x04>;
129 def : BankedReg<"sp_usr", 0x05>;
130 def : BankedReg<"lr_usr", 0x06>;
131 def : BankedReg<"r8_fiq", 0x08>;
132 def : BankedReg<"r9_fiq", 0x09>;
133 def : BankedReg<"r10_fiq", 0x0a>;
134 def : BankedReg<"r11_fiq", 0x0b>;
135 def : BankedReg<"r12_fiq", 0x0c>;
136 def : BankedReg<"sp_fiq", 0x0d>;
137 def : BankedReg<"lr_fiq", 0x0e>;
138 def : BankedReg<"lr_irq", 0x10>;
139 def : BankedReg<"sp_irq", 0x11>;
140 def : BankedReg<"lr_svc", 0x12>;
141 def : BankedReg<"sp_svc", 0x13>;
142 def : BankedReg<"lr_abt", 0x14>;
143 def : BankedReg<"sp_abt", 0x15>;
144 def : BankedReg<"lr_und", 0x16>;
145 def : BankedReg<"sp_und", 0x17>;
146 def : BankedReg<"lr_mon", 0x1c>;
147 def : BankedReg<"sp_mon", 0x1d>;
148 def : BankedReg<"elr_hyp", 0x1e>;
149 def : BankedReg<"sp_hyp", 0x1f>;
150 def : BankedReg<"spsr_fiq", 0x2e>;
151 def : BankedReg<"spsr_irq", 0x30>;
152 def : BankedReg<"spsr_svc", 0x32>;
153 def : BankedReg<"spsr_abt", 0x34>;
154 def : BankedReg<"spsr_und", 0x36>;
155 def : BankedReg<"spsr_mon", 0x3c>;
156 def : BankedReg<"spsr_hyp", 0x3e>;