1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMSubtarget.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/StringMap.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/Analysis/TargetTransformInfo.h"
22 #include "llvm/Support/CodeGen.h"
23 #include "llvm/Target/TargetMachine.h"
28 class ARMBaseTargetMachine : public LLVMTargetMachine {
33 ARM_ABI_AAPCS, // ARM EABI
38 std::unique_ptr<TargetLoweringObjectFile> TLOF;
39 ARMSubtarget Subtarget;
41 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
44 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
45 StringRef FS, const TargetOptions &Options,
46 Optional<Reloc::Model> RM, CodeModel::Model CM,
47 CodeGenOpt::Level OL, bool isLittle);
48 ~ARMBaseTargetMachine() override;
50 const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
51 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
52 bool isLittleEndian() const { return isLittle; }
54 /// \brief Get the TargetIRAnalysis for this target.
55 TargetIRAnalysis getTargetIRAnalysis() override;
57 // Pass Pipeline Configuration
58 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
60 TargetLoweringObjectFile *getObjFileLowering() const override {
65 /// ARM target machine.
67 class ARMTargetMachine : public ARMBaseTargetMachine {
68 virtual void anchor();
71 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
72 StringRef FS, const TargetOptions &Options,
73 Optional<Reloc::Model> RM, CodeModel::Model CM,
74 CodeGenOpt::Level OL, bool isLittle);
77 /// ARM little endian target machine.
79 class ARMLETargetMachine : public ARMTargetMachine {
80 void anchor() override;
83 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
84 StringRef FS, const TargetOptions &Options,
85 Optional<Reloc::Model> RM, CodeModel::Model CM,
86 CodeGenOpt::Level OL);
89 /// ARM big endian target machine.
91 class ARMBETargetMachine : public ARMTargetMachine {
92 void anchor() override;
95 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
96 StringRef FS, const TargetOptions &Options,
97 Optional<Reloc::Model> RM, CodeModel::Model CM,
98 CodeGenOpt::Level OL);
101 /// Thumb target machine.
102 /// Due to the way architectures are handled, this represents both
103 /// Thumb-1 and Thumb-2.
105 class ThumbTargetMachine : public ARMBaseTargetMachine {
106 virtual void anchor();
109 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
110 StringRef FS, const TargetOptions &Options,
111 Optional<Reloc::Model> RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL, bool isLittle);
115 /// Thumb little endian target machine.
117 class ThumbLETargetMachine : public ThumbTargetMachine {
118 void anchor() override;
121 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
122 StringRef FS, const TargetOptions &Options,
123 Optional<Reloc::Model> RM, CodeModel::Model CM,
124 CodeGenOpt::Level OL);
127 /// Thumb big endian target machine.
129 class ThumbBETargetMachine : public ThumbTargetMachine {
130 void anchor() override;
133 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
134 StringRef FS, const TargetOptions &Options,
135 Optional<Reloc::Model> RM, CodeModel::Model CM,
136 CodeGenOpt::Level OL);
139 } // end namespace llvm
141 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H