1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
29 ARM_ABI_AAPCS, // ARM EABI
34 std::unique_ptr<TargetLoweringObjectFile> TLOF;
35 ARMSubtarget Subtarget;
37 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
40 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
41 StringRef FS, const TargetOptions &Options,
42 Optional<Reloc::Model> RM, CodeModel::Model CM,
43 CodeGenOpt::Level OL, bool isLittle);
44 ~ARMBaseTargetMachine() override;
46 const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
47 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
48 bool isLittleEndian() const { return isLittle; }
50 /// \brief Get the TargetIRAnalysis for this target.
51 TargetIRAnalysis getTargetIRAnalysis() override;
53 // Pass Pipeline Configuration
54 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
56 TargetLoweringObjectFile *getObjFileLowering() const override {
61 /// ARM target machine.
63 class ARMTargetMachine : public ARMBaseTargetMachine {
64 virtual void anchor();
66 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
67 StringRef FS, const TargetOptions &Options,
68 Optional<Reloc::Model> RM, CodeModel::Model CM,
69 CodeGenOpt::Level OL, bool isLittle);
72 /// ARM little endian target machine.
74 class ARMLETargetMachine : public ARMTargetMachine {
75 void anchor() override;
77 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
78 StringRef FS, const TargetOptions &Options,
79 Optional<Reloc::Model> RM, CodeModel::Model CM,
80 CodeGenOpt::Level OL);
83 /// ARM big endian target machine.
85 class ARMBETargetMachine : public ARMTargetMachine {
86 void anchor() override;
88 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
89 StringRef FS, const TargetOptions &Options,
90 Optional<Reloc::Model> RM, CodeModel::Model CM,
91 CodeGenOpt::Level OL);
94 /// Thumb target machine.
95 /// Due to the way architectures are handled, this represents both
96 /// Thumb-1 and Thumb-2.
98 class ThumbTargetMachine : public ARMBaseTargetMachine {
99 virtual void anchor();
101 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
102 StringRef FS, const TargetOptions &Options,
103 Optional<Reloc::Model> RM, CodeModel::Model CM,
104 CodeGenOpt::Level OL, bool isLittle);
107 /// Thumb little endian target machine.
109 class ThumbLETargetMachine : public ThumbTargetMachine {
110 void anchor() override;
112 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
113 StringRef FS, const TargetOptions &Options,
114 Optional<Reloc::Model> RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL);
118 /// Thumb big endian target machine.
120 class ThumbBETargetMachine : public ThumbTargetMachine {
121 void anchor() override;
123 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
124 StringRef FS, const TargetOptions &Options,
125 Optional<Reloc::Model> RM, CodeModel::Model CM,
126 CodeGenOpt::Level OL);
129 } // end namespace llvm