1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMTargetTransformInfo.h"
11 #include "llvm/Support/Debug.h"
12 #include "llvm/Target/CostTable.h"
13 #include "llvm/Target/TargetLowering.h"
16 #define DEBUG_TYPE "armtti"
18 bool ARMTTIImpl::areInlineCompatible(const Function *Caller,
19 const Function *Callee) const {
20 const TargetMachine &TM = getTLI()->getTargetMachine();
21 const FeatureBitset &CallerBits =
22 TM.getSubtargetImpl(*Caller)->getFeatureBits();
23 const FeatureBitset &CalleeBits =
24 TM.getSubtargetImpl(*Callee)->getFeatureBits();
26 // To inline a callee, all features not in the whitelist must match exactly.
27 bool MatchExact = (CallerBits & ~InlineFeatureWhitelist) ==
28 (CalleeBits & ~InlineFeatureWhitelist);
29 // For features in the whitelist, the callee's features must be a subset of
31 bool MatchSubset = ((CallerBits & CalleeBits) & InlineFeatureWhitelist) ==
32 (CalleeBits & InlineFeatureWhitelist);
33 return MatchExact && MatchSubset;
36 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
37 assert(Ty->isIntegerTy());
39 unsigned Bits = Ty->getPrimitiveSizeInBits();
40 if (Bits == 0 || Imm.getActiveBits() >= 64)
43 int64_t SImmVal = Imm.getSExtValue();
44 uint64_t ZImmVal = Imm.getZExtValue();
46 if ((SImmVal >= 0 && SImmVal < 65536) ||
47 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
48 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
50 return ST->hasV6T2Ops() ? 2 : 3;
53 if ((SImmVal >= 0 && SImmVal < 65536) ||
54 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
55 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
57 return ST->hasV6T2Ops() ? 2 : 3;
60 if (SImmVal >= 0 && SImmVal < 256)
62 if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
64 // Load from constantpool.
69 // Constants smaller than 256 fit in the immediate field of
70 // Thumb1 instructions so we return a zero cost and 1 otherwise.
71 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
72 const APInt &Imm, Type *Ty) {
73 if (Imm.isNonNegative() && Imm.getLimitedValue() < 256)
79 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
81 // Division by a constant can be turned into multiplication, but only if we
82 // know it's constant. So it's not so much that the immediate is cheap (it's
83 // not), but that the alternative is worse.
84 // FIXME: this is probably unneeded with GlobalISel.
85 if ((Opcode == Instruction::SDiv || Opcode == Instruction::UDiv ||
86 Opcode == Instruction::SRem || Opcode == Instruction::URem) &&
90 if (Opcode == Instruction::And)
91 // Conversion to BIC is free, and means we can use ~Imm instead.
92 return std::min(getIntImmCost(Imm, Ty), getIntImmCost(~Imm, Ty));
94 if (Opcode == Instruction::Add)
95 // Conversion to SUB is free, and means we can use -Imm instead.
96 return std::min(getIntImmCost(Imm, Ty), getIntImmCost(-Imm, Ty));
98 if (Opcode == Instruction::ICmp && Imm.isNegative() &&
99 Ty->getIntegerBitWidth() == 32) {
100 int64_t NegImm = -Imm.getSExtValue();
101 if (ST->isThumb2() && NegImm < 1<<12)
102 // icmp X, #-C -> cmn X, #C
104 if (ST->isThumb() && NegImm < 1<<8)
105 // icmp X, #-C -> adds X, #C
109 return getIntImmCost(Imm, Ty);
113 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
114 const Instruction *I) {
115 int ISD = TLI->InstructionOpcodeToISD(Opcode);
116 assert(ISD && "Invalid opcode");
118 // Single to/from double precision conversions.
119 static const CostTblEntry NEONFltDblTbl[] = {
120 // Vector fptrunc/fpext conversions.
121 { ISD::FP_ROUND, MVT::v2f64, 2 },
122 { ISD::FP_EXTEND, MVT::v2f32, 2 },
123 { ISD::FP_EXTEND, MVT::v4f32, 4 }
126 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
127 ISD == ISD::FP_EXTEND)) {
128 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
129 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second))
130 return LT.first * Entry->Cost;
133 EVT SrcTy = TLI->getValueType(DL, Src);
134 EVT DstTy = TLI->getValueType(DL, Dst);
136 if (!SrcTy.isSimple() || !DstTy.isSimple())
137 return BaseT::getCastInstrCost(Opcode, Dst, Src);
139 // Some arithmetic, load and store operations have specific instructions
140 // to cast up/down their types automatically at no extra cost.
141 // TODO: Get these tables to know at least what the related operations are.
142 static const TypeConversionCostTblEntry NEONVectorConversionTbl[] = {
143 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
144 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
145 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
146 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
147 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
148 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
150 // The number of vmovl instructions for the extension.
151 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
152 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
153 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
154 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
155 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
156 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
157 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
158 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
159 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
160 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
162 // Operations that we legalize using splitting.
163 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
164 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
166 // Vector float <-> i32 conversions.
167 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
168 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
170 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
171 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
172 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
173 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
174 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
175 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
176 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
177 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
178 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
179 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
180 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
181 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
182 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
183 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
184 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
185 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
186 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
187 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
188 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
189 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
191 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
192 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
193 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
194 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
195 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
196 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
198 // Vector double <-> i32 conversions.
199 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
200 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
202 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
203 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
204 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
205 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
206 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
207 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
209 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
210 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
211 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
212 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
213 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
214 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
217 if (SrcTy.isVector() && ST->hasNEON()) {
218 if (const auto *Entry = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
220 SrcTy.getSimpleVT()))
224 // Scalar float to integer conversions.
225 static const TypeConversionCostTblEntry NEONFloatConversionTbl[] = {
226 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
227 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
228 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
229 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
230 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
231 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
232 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
233 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
234 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
235 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
236 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
237 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
238 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
239 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
240 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
241 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
242 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
243 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
244 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
245 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
247 if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
248 if (const auto *Entry = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
250 SrcTy.getSimpleVT()))
254 // Scalar integer to float conversions.
255 static const TypeConversionCostTblEntry NEONIntegerConversionTbl[] = {
256 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
257 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
258 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
259 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
260 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
261 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
262 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
263 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
264 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
265 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
266 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
267 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
268 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
269 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
270 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
271 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
272 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
273 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
274 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
275 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
278 if (SrcTy.isInteger() && ST->hasNEON()) {
279 if (const auto *Entry = ConvertCostTableLookup(NEONIntegerConversionTbl,
280 ISD, DstTy.getSimpleVT(),
281 SrcTy.getSimpleVT()))
285 // Scalar integer conversion costs.
286 static const TypeConversionCostTblEntry ARMIntegerConversionTbl[] = {
287 // i16 -> i64 requires two dependent operations.
288 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
290 // Truncates on i64 are assumed to be free.
291 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
292 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
293 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
294 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
297 if (SrcTy.isInteger()) {
298 if (const auto *Entry = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
300 SrcTy.getSimpleVT()))
304 return BaseT::getCastInstrCost(Opcode, Dst, Src);
307 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
309 // Penalize inserting into an D-subregister. We end up with a three times
310 // lower estimated throughput on swift.
311 if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement &&
312 ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32)
315 if ((Opcode == Instruction::InsertElement ||
316 Opcode == Instruction::ExtractElement)) {
317 // Cross-class copies are expensive on many microarchitectures,
318 // so assume they are expensive by default.
319 if (ValTy->getVectorElementType()->isIntegerTy())
322 // Even if it's not a cross class copy, this likely leads to mixing
323 // of NEON and VFP code and should be therefore penalized.
324 if (ValTy->isVectorTy() &&
325 ValTy->getScalarSizeInBits() <= 32)
326 return std::max(BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U);
329 return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
332 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
333 const Instruction *I) {
335 int ISD = TLI->InstructionOpcodeToISD(Opcode);
336 // On NEON a a vector select gets lowered to vbsl.
337 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
338 // Lowering of some vector selects is currently far from perfect.
339 static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = {
340 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
341 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
342 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
345 EVT SelCondTy = TLI->getValueType(DL, CondTy);
346 EVT SelValTy = TLI->getValueType(DL, ValTy);
347 if (SelCondTy.isSimple() && SelValTy.isSimple()) {
348 if (const auto *Entry = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
349 SelCondTy.getSimpleVT(),
350 SelValTy.getSimpleVT()))
354 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
358 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
361 int ARMTTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
363 // Address computations in vectorized code with non-consecutive addresses will
364 // likely result in more instructions compared to scalar code where the
365 // computation can more often be merged into the index mode. The resulting
366 // extra micro-ops can significantly decrease throughput.
367 unsigned NumVectorInstToHideOverhead = 10;
368 int MaxMergeDistance = 64;
370 if (Ty->isVectorTy() && SE &&
371 !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1))
372 return NumVectorInstToHideOverhead;
374 // In many cases the address computation is not merged into the instruction
379 int ARMTTIImpl::getFPOpCost(Type *Ty) {
380 // Use similar logic that's in ARMISelLowering:
381 // Any ARM CPU with VFP2 has floating point, but Thumb1 didn't have access
384 if (ST->hasVFP2() && !ST->isThumb1Only()) {
385 if (Ty->isFloatTy()) {
386 return TargetTransformInfo::TCC_Basic;
389 if (Ty->isDoubleTy()) {
390 return ST->isFPOnlySP() ? TargetTransformInfo::TCC_Expensive :
391 TargetTransformInfo::TCC_Basic;
395 return TargetTransformInfo::TCC_Expensive;
398 int ARMTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
400 // We only handle costs of reverse and alternate shuffles for now.
401 if (Kind != TTI::SK_Reverse && Kind != TTI::SK_Alternate)
402 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
404 if (Kind == TTI::SK_Reverse) {
405 static const CostTblEntry NEONShuffleTbl[] = {
406 // Reverse shuffle cost one instruction if we are shuffling within a
407 // double word (vrev) or two if we shuffle a quad word (vrev, vext).
408 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
409 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
410 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
411 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
413 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
414 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
415 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 2},
416 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}};
418 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
420 if (const auto *Entry = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE,
422 return LT.first * Entry->Cost;
424 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
426 if (Kind == TTI::SK_Alternate) {
427 static const CostTblEntry NEONAltShuffleTbl[] = {
428 // Alt shuffle cost table for ARM. Cost is the number of instructions
429 // required to create the shuffled vector.
431 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
432 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
433 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
434 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
436 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
437 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
438 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2},
440 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 16},
442 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}};
444 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
445 if (const auto *Entry = CostTableLookup(NEONAltShuffleTbl,
446 ISD::VECTOR_SHUFFLE, LT.second))
447 return LT.first * Entry->Cost;
448 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
450 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
453 int ARMTTIImpl::getArithmeticInstrCost(
454 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
455 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
456 TTI::OperandValueProperties Opd2PropInfo,
457 ArrayRef<const Value *> Args) {
459 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
460 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
462 const unsigned FunctionCallDivCost = 20;
463 const unsigned ReciprocalDivCost = 10;
464 static const CostTblEntry CostTbl[] = {
466 // These costs are somewhat random. Choose a cost of 20 to indicate that
467 // vectorizing devision (added function call) is going to be very expensive.
468 // Double registers types.
469 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
470 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
471 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
472 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
473 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
474 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
475 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
476 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
477 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
478 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
479 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
480 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
481 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
482 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
483 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
484 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
485 // Quad register types.
486 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
487 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
488 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
489 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
490 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
491 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
492 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
493 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
494 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
495 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
496 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
497 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
498 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
499 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
500 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
501 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
506 if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second))
507 return LT.first * Entry->Cost;
509 int Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
510 Opd1PropInfo, Opd2PropInfo);
512 // This is somewhat of a hack. The problem that we are facing is that SROA
513 // creates a sequence of shift, and, or instructions to construct values.
514 // These sequences are recognized by the ISel and have zero-cost. Not so for
515 // the vectorized code. Because we have support for v2i64 but not i64 those
516 // sequences look particularly beneficial to vectorize.
517 // To work around this we increase the cost of v2i64 operations to make them
518 // seem less beneficial.
519 if (LT.second == MVT::v2i64 &&
520 Op2Info == TargetTransformInfo::OK_UniformConstantValue)
526 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
527 unsigned AddressSpace, const Instruction *I) {
528 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
530 if (Src->isVectorTy() && Alignment != 16 &&
531 Src->getVectorElementType()->isDoubleTy()) {
532 // Unaligned loads/stores are extremely inefficient.
533 // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.
539 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
541 ArrayRef<unsigned> Indices,
543 unsigned AddressSpace) {
544 assert(Factor >= 2 && "Invalid interleave factor");
545 assert(isa<VectorType>(VecTy) && "Expect a vector type");
547 // vldN/vstN doesn't support vector types of i64/f64 element.
548 bool EltIs64Bits = DL.getTypeSizeInBits(VecTy->getScalarType()) == 64;
550 if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits) {
551 unsigned NumElts = VecTy->getVectorNumElements();
552 auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
554 // vldN/vstN only support legal vector types of size 64 or 128 in bits.
555 // Accesses having vector types that are a multiple of 128 bits can be
556 // matched to more than one vldN/vstN instruction.
557 if (NumElts % Factor == 0 &&
558 TLI->isLegalInterleavedAccessType(SubVecTy, DL))
559 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL);
562 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
563 Alignment, AddressSpace);