1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMAddressingModes.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMMCTargetDesc.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
15 #include "llvm/MC/MCFixedLenDisassembler.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/SubtargetFeature.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "arm-disassembler"
34 typedef MCDisassembler::DecodeStatus DecodeStatus;
38 // Handles the condition code status of instructions in IT blocks
42 // Returns the condition code for instruction in IT block
44 unsigned CC = ARMCC::AL;
50 // Advances the IT block state to the next T or E
51 void advanceITState() {
55 // Returns true if the current instruction is in an IT block
56 bool instrInITBlock() {
57 return !ITStates.empty();
60 // Returns true if current instruction is the last instruction in an IT block
61 bool instrLastInITBlock() {
62 return ITStates.size() == 1;
65 // Called when decoding an IT instruction. Sets the IT state for the following
66 // instructions that for the IT block. Firstcond and Mask correspond to the
67 // fields in the IT instruction encoding.
68 void setITState(char Firstcond, char Mask) {
69 // (3 - the number of trailing zeros) is the number of then / else.
70 unsigned CondBit0 = Firstcond & 1;
71 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
72 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
73 assert(NumTZ <= 3 && "Invalid IT mask!");
74 // push condition codes onto the stack the correct order for the pops
75 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
76 bool T = ((Mask >> Pos) & 1) == CondBit0;
78 ITStates.push_back(CCBits);
80 ITStates.push_back(CCBits ^ 1);
82 ITStates.push_back(CCBits);
86 std::vector<unsigned char> ITStates;
89 /// ARM disassembler for all ARM platforms.
90 class ARMDisassembler : public MCDisassembler {
92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
93 MCDisassembler(STI, Ctx) {
96 ~ARMDisassembler() override = default;
98 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
99 ArrayRef<uint8_t> Bytes, uint64_t Address,
100 raw_ostream &VStream,
101 raw_ostream &CStream) const override;
104 /// Thumb disassembler for all Thumb platforms.
105 class ThumbDisassembler : public MCDisassembler {
107 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
108 MCDisassembler(STI, Ctx) {
111 ~ThumbDisassembler() override = default;
113 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
114 ArrayRef<uint8_t> Bytes, uint64_t Address,
115 raw_ostream &VStream,
116 raw_ostream &CStream) const override;
119 mutable ITStatus ITBlock;
120 DecodeStatus AddThumbPredicate(MCInst&) const;
121 void UpdateThumbVFPPredicate(MCInst&) const;
124 } // end anonymous namespace
126 static bool Check(DecodeStatus &Out, DecodeStatus In) {
128 case MCDisassembler::Success:
129 // Out stays the same.
131 case MCDisassembler::SoftFail:
134 case MCDisassembler::Fail:
138 llvm_unreachable("Invalid DecodeStatus!");
141 // Forward declare these because the autogenerated code will reference them.
142 // Definitions are further down.
143 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
144 uint64_t Address, const void *Decoder);
145 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
146 unsigned RegNo, uint64_t Address,
147 const void *Decoder);
148 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
149 unsigned RegNo, uint64_t Address,
150 const void *Decoder);
151 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
164 uint64_t Address, const void *Decoder);
165 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
168 const void *Decoder);
169 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
172 uint64_t Address, const void *Decoder);
173 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
174 unsigned RegNo, uint64_t Address,
175 const void *Decoder);
177 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
186 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
195 const void *Decoder);
196 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
203 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
316 uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
318 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
320 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
322 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
345 uint64_t Address, const void* Decoder);
346 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
347 uint64_t Address, const void* Decoder);
348 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
349 uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
398 uint64_t Address, const void *Decoder);
399 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
400 uint64_t Address, const void *Decoder);
402 #include "ARMGenDisassemblerTables.inc"
404 static MCDisassembler *createARMDisassembler(const Target &T,
405 const MCSubtargetInfo &STI,
407 return new ARMDisassembler(STI, Ctx);
410 static MCDisassembler *createThumbDisassembler(const Target &T,
411 const MCSubtargetInfo &STI,
413 return new ThumbDisassembler(STI, Ctx);
416 // Post-decoding checks
417 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
418 uint64_t Address, raw_ostream &OS,
421 DecodeStatus Result) {
422 switch (MI.getOpcode()) {
424 // HVC is undefined if condition = 0xf otherwise upredictable
425 // if condition != 0xe
426 uint32_t Cond = (Insn >> 28) & 0xF;
428 return MCDisassembler::Fail;
430 return MCDisassembler::SoftFail;
433 default: return Result;
437 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
438 ArrayRef<uint8_t> Bytes,
439 uint64_t Address, raw_ostream &OS,
440 raw_ostream &CS) const {
443 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
444 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
447 // We want to read exactly 4 bytes of data.
448 if (Bytes.size() < 4) {
450 return MCDisassembler::Fail;
453 // Encoded as a small-endian 32-bit word in the stream.
455 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
457 // Calling the auto-generated decoder function.
458 DecodeStatus Result =
459 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
460 if (Result != MCDisassembler::Fail) {
462 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
470 const DecodeTable Tables[] = {
471 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
472 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
473 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
474 {DecoderTablev8Crypto32, false},
477 for (auto Table : Tables) {
478 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
479 if (Result != MCDisassembler::Fail) {
481 // Add a fake predicate operand, because we share these instruction
482 // definitions with Thumb2 where these instructions are predicable.
483 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
484 return MCDisassembler::Fail;
490 return MCDisassembler::Fail;
495 extern const MCInstrDesc ARMInsts[];
497 } // end namespace llvm
499 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
500 /// immediate Value in the MCInst. The immediate Value has had any PC
501 /// adjustment made by the caller. If the instruction is a branch instruction
502 /// then isBranch is true, else false. If the getOpInfo() function was set as
503 /// part of the setupForSymbolicDisassembly() call then that function is called
504 /// to get any symbolic information at the Address for this instruction. If
505 /// that returns non-zero then the symbolic information it returns is used to
506 /// create an MCExpr and that is added as an operand to the MCInst. If
507 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
508 /// Value is done and if a symbol is found an MCExpr is created with that, else
509 /// an MCExpr with Value is created. This function returns true if it adds an
510 /// operand to the MCInst and false otherwise.
511 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
512 bool isBranch, uint64_t InstSize,
513 MCInst &MI, const void *Decoder) {
514 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
515 // FIXME: Does it make sense for value to be negative?
516 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
517 /* Offset */ 0, InstSize);
520 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
521 /// referenced by a load instruction with the base register that is the Pc.
522 /// These can often be values in a literal pool near the Address of the
523 /// instruction. The Address of the instruction and its immediate Value are
524 /// used as a possible literal pool entry. The SymbolLookUp call back will
525 /// return the name of a symbol referenced by the literal pool's entry if
526 /// the referenced address is that of a symbol. Or it will return a pointer to
527 /// a literal 'C' string if the referenced address of the literal pool's entry
528 /// is an address into a section with 'C' string literals.
529 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
530 const void *Decoder) {
531 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
532 Dis->tryAddingPcLoadReferenceComment(Value, Address);
535 // Thumb1 instructions don't have explicit S bits. Rather, they
536 // implicitly set CPSR. Since it's not represented in the encoding, the
537 // auto-generated decoder won't inject the CPSR operand. We need to fix
538 // that as a post-pass.
539 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
540 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
541 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
542 MCInst::iterator I = MI.begin();
543 for (unsigned i = 0; i < NumOps; ++i, ++I) {
544 if (I == MI.end()) break;
545 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
546 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
547 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
552 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
555 // Most Thumb instructions don't have explicit predicates in the
556 // encoding, but rather get their predicates from IT context. We need
557 // to fix up the predicate operands using this context information as a
559 MCDisassembler::DecodeStatus
560 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
561 MCDisassembler::DecodeStatus S = Success;
563 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
565 // A few instructions actually have predicates encoded in them. Don't
566 // try to overwrite it if we're seeing one of those.
567 switch (MI.getOpcode()) {
578 // Some instructions (mostly conditional branches) are not
579 // allowed in IT blocks.
580 if (ITBlock.instrInITBlock())
586 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
593 // Some instructions (mostly unconditional branches) can
594 // only appears at the end of, or outside of, an IT.
595 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
602 // If we're in an IT block, base the predicate on that. Otherwise,
603 // assume a predicate of AL.
605 CC = ITBlock.getITCC();
608 if (ITBlock.instrInITBlock())
609 ITBlock.advanceITState();
611 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
612 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
613 MCInst::iterator I = MI.begin();
614 for (unsigned i = 0; i < NumOps; ++i, ++I) {
615 if (I == MI.end()) break;
616 if (OpInfo[i].isPredicate()) {
617 I = MI.insert(I, MCOperand::createImm(CC));
620 MI.insert(I, MCOperand::createReg(0));
622 MI.insert(I, MCOperand::createReg(ARM::CPSR));
627 I = MI.insert(I, MCOperand::createImm(CC));
630 MI.insert(I, MCOperand::createReg(0));
632 MI.insert(I, MCOperand::createReg(ARM::CPSR));
637 // Thumb VFP instructions are a special case. Because we share their
638 // encodings between ARM and Thumb modes, and they are predicable in ARM
639 // mode, the auto-generated decoder will give them an (incorrect)
640 // predicate operand. We need to rewrite these operands based on the IT
641 // context as a post-pass.
642 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
644 CC = ITBlock.getITCC();
645 if (ITBlock.instrInITBlock())
646 ITBlock.advanceITState();
648 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
649 MCInst::iterator I = MI.begin();
650 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
651 for (unsigned i = 0; i < NumOps; ++i, ++I) {
652 if (OpInfo[i].isPredicate() ) {
658 I->setReg(ARM::CPSR);
664 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
665 ArrayRef<uint8_t> Bytes,
668 raw_ostream &CS) const {
671 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
672 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
674 // We want to read exactly 2 bytes of data.
675 if (Bytes.size() < 2) {
677 return MCDisassembler::Fail;
680 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
681 DecodeStatus Result =
682 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
683 if (Result != MCDisassembler::Fail) {
685 Check(Result, AddThumbPredicate(MI));
689 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
693 bool InITBlock = ITBlock.instrInITBlock();
694 Check(Result, AddThumbPredicate(MI));
695 AddThumb1SBit(MI, InITBlock);
700 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
701 if (Result != MCDisassembler::Fail) {
704 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
705 // the Thumb predicate.
706 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
707 Result = MCDisassembler::SoftFail;
709 Check(Result, AddThumbPredicate(MI));
711 // If we find an IT instruction, we need to parse its condition
712 // code and mask operands so that we can apply them correctly
713 // to the subsequent instructions.
714 if (MI.getOpcode() == ARM::t2IT) {
716 unsigned Firstcond = MI.getOperand(0).getImm();
717 unsigned Mask = MI.getOperand(1).getImm();
718 ITBlock.setITState(Firstcond, Mask);
724 // We want to read exactly 4 bytes of data.
725 if (Bytes.size() < 4) {
727 return MCDisassembler::Fail;
731 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
733 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
734 if (Result != MCDisassembler::Fail) {
736 bool InITBlock = ITBlock.instrInITBlock();
737 Check(Result, AddThumbPredicate(MI));
738 AddThumb1SBit(MI, InITBlock);
743 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
744 if (Result != MCDisassembler::Fail) {
746 Check(Result, AddThumbPredicate(MI));
750 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
752 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
753 if (Result != MCDisassembler::Fail) {
755 UpdateThumbVFPPredicate(MI);
761 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
762 if (Result != MCDisassembler::Fail) {
767 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
768 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
770 if (Result != MCDisassembler::Fail) {
772 Check(Result, AddThumbPredicate(MI));
777 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
778 uint32_t NEONLdStInsn = Insn32;
779 NEONLdStInsn &= 0xF0FFFFFF;
780 NEONLdStInsn |= 0x04000000;
781 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
783 if (Result != MCDisassembler::Fail) {
785 Check(Result, AddThumbPredicate(MI));
790 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
791 uint32_t NEONDataInsn = Insn32;
792 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
793 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
794 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
795 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
797 if (Result != MCDisassembler::Fail) {
799 Check(Result, AddThumbPredicate(MI));
803 uint32_t NEONCryptoInsn = Insn32;
804 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
805 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
806 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
807 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
809 if (Result != MCDisassembler::Fail) {
814 uint32_t NEONv8Insn = Insn32;
815 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
816 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
818 if (Result != MCDisassembler::Fail) {
825 return MCDisassembler::Fail;
828 extern "C" void LLVMInitializeARMDisassembler() {
829 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
830 createARMDisassembler);
831 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
832 createARMDisassembler);
833 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
834 createThumbDisassembler);
835 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
836 createThumbDisassembler);
839 static const uint16_t GPRDecoderTable[] = {
840 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
841 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
842 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
843 ARM::R12, ARM::SP, ARM::LR, ARM::PC
846 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
847 uint64_t Address, const void *Decoder) {
849 return MCDisassembler::Fail;
851 unsigned Register = GPRDecoderTable[RegNo];
852 Inst.addOperand(MCOperand::createReg(Register));
853 return MCDisassembler::Success;
857 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
858 uint64_t Address, const void *Decoder) {
859 DecodeStatus S = MCDisassembler::Success;
862 S = MCDisassembler::SoftFail;
864 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
870 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
871 uint64_t Address, const void *Decoder) {
872 DecodeStatus S = MCDisassembler::Success;
876 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
877 return MCDisassembler::Success;
880 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
884 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
885 uint64_t Address, const void *Decoder) {
887 return MCDisassembler::Fail;
888 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
891 static const uint16_t GPRPairDecoderTable[] = {
892 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
893 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
896 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
897 uint64_t Address, const void *Decoder) {
898 DecodeStatus S = MCDisassembler::Success;
901 return MCDisassembler::Fail;
903 if ((RegNo & 1) || RegNo == 0xe)
904 S = MCDisassembler::SoftFail;
906 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
907 Inst.addOperand(MCOperand::createReg(RegisterPair));
911 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
912 uint64_t Address, const void *Decoder) {
913 unsigned Register = 0;
934 return MCDisassembler::Fail;
937 Inst.addOperand(MCOperand::createReg(Register));
938 return MCDisassembler::Success;
941 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
942 uint64_t Address, const void *Decoder) {
943 DecodeStatus S = MCDisassembler::Success;
945 const FeatureBitset &featureBits =
946 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
948 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
949 S = MCDisassembler::SoftFail;
951 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
955 static const uint16_t SPRDecoderTable[] = {
956 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
957 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
958 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
959 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
960 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
961 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
962 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
963 ARM::S28, ARM::S29, ARM::S30, ARM::S31
966 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
967 uint64_t Address, const void *Decoder) {
969 return MCDisassembler::Fail;
971 unsigned Register = SPRDecoderTable[RegNo];
972 Inst.addOperand(MCOperand::createReg(Register));
973 return MCDisassembler::Success;
976 static const uint16_t DPRDecoderTable[] = {
977 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
978 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
979 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
980 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
981 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
982 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
983 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
984 ARM::D28, ARM::D29, ARM::D30, ARM::D31
987 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
988 uint64_t Address, const void *Decoder) {
989 const FeatureBitset &featureBits =
990 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
992 bool hasD16 = featureBits[ARM::FeatureD16];
994 if (RegNo > 31 || (hasD16 && RegNo > 15))
995 return MCDisassembler::Fail;
997 unsigned Register = DPRDecoderTable[RegNo];
998 Inst.addOperand(MCOperand::createReg(Register));
999 return MCDisassembler::Success;
1002 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1003 uint64_t Address, const void *Decoder) {
1005 return MCDisassembler::Fail;
1006 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1010 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1011 uint64_t Address, const void *Decoder) {
1013 return MCDisassembler::Fail;
1014 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1017 static const uint16_t QPRDecoderTable[] = {
1018 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1019 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1020 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1021 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1024 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1025 uint64_t Address, const void *Decoder) {
1026 if (RegNo > 31 || (RegNo & 1) != 0)
1027 return MCDisassembler::Fail;
1030 unsigned Register = QPRDecoderTable[RegNo];
1031 Inst.addOperand(MCOperand::createReg(Register));
1032 return MCDisassembler::Success;
1035 static const uint16_t DPairDecoderTable[] = {
1036 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1037 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1038 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1039 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1040 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1044 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1045 uint64_t Address, const void *Decoder) {
1047 return MCDisassembler::Fail;
1049 unsigned Register = DPairDecoderTable[RegNo];
1050 Inst.addOperand(MCOperand::createReg(Register));
1051 return MCDisassembler::Success;
1054 static const uint16_t DPairSpacedDecoderTable[] = {
1055 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1056 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1057 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1058 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1059 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1060 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1061 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1062 ARM::D28_D30, ARM::D29_D31
1065 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1068 const void *Decoder) {
1070 return MCDisassembler::Fail;
1072 unsigned Register = DPairSpacedDecoderTable[RegNo];
1073 Inst.addOperand(MCOperand::createReg(Register));
1074 return MCDisassembler::Success;
1077 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1078 uint64_t Address, const void *Decoder) {
1079 if (Val == 0xF) return MCDisassembler::Fail;
1080 // AL predicate is not allowed on Thumb1 branches.
1081 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1082 return MCDisassembler::Fail;
1083 Inst.addOperand(MCOperand::createImm(Val));
1084 if (Val == ARMCC::AL) {
1085 Inst.addOperand(MCOperand::createReg(0));
1087 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1088 return MCDisassembler::Success;
1091 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1092 uint64_t Address, const void *Decoder) {
1094 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1096 Inst.addOperand(MCOperand::createReg(0));
1097 return MCDisassembler::Success;
1100 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1101 uint64_t Address, const void *Decoder) {
1102 DecodeStatus S = MCDisassembler::Success;
1104 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1105 unsigned type = fieldFromInstruction(Val, 5, 2);
1106 unsigned imm = fieldFromInstruction(Val, 7, 5);
1108 // Register-immediate
1109 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1110 return MCDisassembler::Fail;
1112 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1115 Shift = ARM_AM::lsl;
1118 Shift = ARM_AM::lsr;
1121 Shift = ARM_AM::asr;
1124 Shift = ARM_AM::ror;
1128 if (Shift == ARM_AM::ror && imm == 0)
1129 Shift = ARM_AM::rrx;
1131 unsigned Op = Shift | (imm << 3);
1132 Inst.addOperand(MCOperand::createImm(Op));
1137 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1138 uint64_t Address, const void *Decoder) {
1139 DecodeStatus S = MCDisassembler::Success;
1141 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1142 unsigned type = fieldFromInstruction(Val, 5, 2);
1143 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1145 // Register-register
1146 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1147 return MCDisassembler::Fail;
1148 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1149 return MCDisassembler::Fail;
1151 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1154 Shift = ARM_AM::lsl;
1157 Shift = ARM_AM::lsr;
1160 Shift = ARM_AM::asr;
1163 Shift = ARM_AM::ror;
1167 Inst.addOperand(MCOperand::createImm(Shift));
1172 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1173 uint64_t Address, const void *Decoder) {
1174 DecodeStatus S = MCDisassembler::Success;
1176 bool NeedDisjointWriteback = false;
1177 unsigned WritebackReg = 0;
1178 switch (Inst.getOpcode()) {
1181 case ARM::LDMIA_UPD:
1182 case ARM::LDMDB_UPD:
1183 case ARM::LDMIB_UPD:
1184 case ARM::LDMDA_UPD:
1185 case ARM::t2LDMIA_UPD:
1186 case ARM::t2LDMDB_UPD:
1187 case ARM::t2STMIA_UPD:
1188 case ARM::t2STMDB_UPD:
1189 NeedDisjointWriteback = true;
1190 WritebackReg = Inst.getOperand(0).getReg();
1194 // Empty register lists are not allowed.
1195 if (Val == 0) return MCDisassembler::Fail;
1196 for (unsigned i = 0; i < 16; ++i) {
1197 if (Val & (1 << i)) {
1198 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1199 return MCDisassembler::Fail;
1200 // Writeback not allowed if Rn is in the target list.
1201 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1202 Check(S, MCDisassembler::SoftFail);
1209 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1210 uint64_t Address, const void *Decoder) {
1211 DecodeStatus S = MCDisassembler::Success;
1213 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1214 unsigned regs = fieldFromInstruction(Val, 0, 8);
1216 // In case of unpredictable encoding, tweak the operands.
1217 if (regs == 0 || (Vd + regs) > 32) {
1218 regs = Vd + regs > 32 ? 32 - Vd : regs;
1219 regs = std::max( 1u, regs);
1220 S = MCDisassembler::SoftFail;
1223 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1224 return MCDisassembler::Fail;
1225 for (unsigned i = 0; i < (regs - 1); ++i) {
1226 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1227 return MCDisassembler::Fail;
1233 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1234 uint64_t Address, const void *Decoder) {
1235 DecodeStatus S = MCDisassembler::Success;
1237 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1238 unsigned regs = fieldFromInstruction(Val, 1, 7);
1240 // In case of unpredictable encoding, tweak the operands.
1241 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1242 regs = Vd + regs > 32 ? 32 - Vd : regs;
1243 regs = std::max( 1u, regs);
1244 regs = std::min(16u, regs);
1245 S = MCDisassembler::SoftFail;
1248 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1249 return MCDisassembler::Fail;
1250 for (unsigned i = 0; i < (regs - 1); ++i) {
1251 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1252 return MCDisassembler::Fail;
1258 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1259 uint64_t Address, const void *Decoder) {
1260 // This operand encodes a mask of contiguous zeros between a specified MSB
1261 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1262 // the mask of all bits LSB-and-lower, and then xor them to create
1263 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1264 // create the final mask.
1265 unsigned msb = fieldFromInstruction(Val, 5, 5);
1266 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1268 DecodeStatus S = MCDisassembler::Success;
1270 Check(S, MCDisassembler::SoftFail);
1271 // The check above will cause the warning for the "potentially undefined
1272 // instruction encoding" but we can't build a bad MCOperand value here
1273 // with a lsb > msb or else printing the MCInst will cause a crash.
1277 uint32_t msb_mask = 0xFFFFFFFF;
1278 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1279 uint32_t lsb_mask = (1U << lsb) - 1;
1281 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1285 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1286 uint64_t Address, const void *Decoder) {
1287 DecodeStatus S = MCDisassembler::Success;
1289 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1290 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1291 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1292 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1293 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1294 unsigned U = fieldFromInstruction(Insn, 23, 1);
1296 switch (Inst.getOpcode()) {
1297 case ARM::LDC_OFFSET:
1300 case ARM::LDC_OPTION:
1301 case ARM::LDCL_OFFSET:
1303 case ARM::LDCL_POST:
1304 case ARM::LDCL_OPTION:
1305 case ARM::STC_OFFSET:
1308 case ARM::STC_OPTION:
1309 case ARM::STCL_OFFSET:
1311 case ARM::STCL_POST:
1312 case ARM::STCL_OPTION:
1313 case ARM::t2LDC_OFFSET:
1314 case ARM::t2LDC_PRE:
1315 case ARM::t2LDC_POST:
1316 case ARM::t2LDC_OPTION:
1317 case ARM::t2LDCL_OFFSET:
1318 case ARM::t2LDCL_PRE:
1319 case ARM::t2LDCL_POST:
1320 case ARM::t2LDCL_OPTION:
1321 case ARM::t2STC_OFFSET:
1322 case ARM::t2STC_PRE:
1323 case ARM::t2STC_POST:
1324 case ARM::t2STC_OPTION:
1325 case ARM::t2STCL_OFFSET:
1326 case ARM::t2STCL_PRE:
1327 case ARM::t2STCL_POST:
1328 case ARM::t2STCL_OPTION:
1329 if (coproc == 0xA || coproc == 0xB)
1330 return MCDisassembler::Fail;
1336 const FeatureBitset &featureBits =
1337 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1338 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1339 return MCDisassembler::Fail;
1341 Inst.addOperand(MCOperand::createImm(coproc));
1342 Inst.addOperand(MCOperand::createImm(CRd));
1343 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1344 return MCDisassembler::Fail;
1346 switch (Inst.getOpcode()) {
1347 case ARM::t2LDC2_OFFSET:
1348 case ARM::t2LDC2L_OFFSET:
1349 case ARM::t2LDC2_PRE:
1350 case ARM::t2LDC2L_PRE:
1351 case ARM::t2STC2_OFFSET:
1352 case ARM::t2STC2L_OFFSET:
1353 case ARM::t2STC2_PRE:
1354 case ARM::t2STC2L_PRE:
1355 case ARM::LDC2_OFFSET:
1356 case ARM::LDC2L_OFFSET:
1358 case ARM::LDC2L_PRE:
1359 case ARM::STC2_OFFSET:
1360 case ARM::STC2L_OFFSET:
1362 case ARM::STC2L_PRE:
1363 case ARM::t2LDC_OFFSET:
1364 case ARM::t2LDCL_OFFSET:
1365 case ARM::t2LDC_PRE:
1366 case ARM::t2LDCL_PRE:
1367 case ARM::t2STC_OFFSET:
1368 case ARM::t2STCL_OFFSET:
1369 case ARM::t2STC_PRE:
1370 case ARM::t2STCL_PRE:
1371 case ARM::LDC_OFFSET:
1372 case ARM::LDCL_OFFSET:
1375 case ARM::STC_OFFSET:
1376 case ARM::STCL_OFFSET:
1379 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1380 Inst.addOperand(MCOperand::createImm(imm));
1382 case ARM::t2LDC2_POST:
1383 case ARM::t2LDC2L_POST:
1384 case ARM::t2STC2_POST:
1385 case ARM::t2STC2L_POST:
1386 case ARM::LDC2_POST:
1387 case ARM::LDC2L_POST:
1388 case ARM::STC2_POST:
1389 case ARM::STC2L_POST:
1390 case ARM::t2LDC_POST:
1391 case ARM::t2LDCL_POST:
1392 case ARM::t2STC_POST:
1393 case ARM::t2STCL_POST:
1395 case ARM::LDCL_POST:
1397 case ARM::STCL_POST:
1401 // The 'option' variant doesn't encode 'U' in the immediate since
1402 // the immediate is unsigned [0,255].
1403 Inst.addOperand(MCOperand::createImm(imm));
1407 switch (Inst.getOpcode()) {
1408 case ARM::LDC_OFFSET:
1411 case ARM::LDC_OPTION:
1412 case ARM::LDCL_OFFSET:
1414 case ARM::LDCL_POST:
1415 case ARM::LDCL_OPTION:
1416 case ARM::STC_OFFSET:
1419 case ARM::STC_OPTION:
1420 case ARM::STCL_OFFSET:
1422 case ARM::STCL_POST:
1423 case ARM::STCL_OPTION:
1424 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1425 return MCDisassembler::Fail;
1435 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1436 uint64_t Address, const void *Decoder) {
1437 DecodeStatus S = MCDisassembler::Success;
1439 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1440 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1441 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1442 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1443 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1444 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1445 unsigned P = fieldFromInstruction(Insn, 24, 1);
1446 unsigned W = fieldFromInstruction(Insn, 21, 1);
1448 // On stores, the writeback operand precedes Rt.
1449 switch (Inst.getOpcode()) {
1450 case ARM::STR_POST_IMM:
1451 case ARM::STR_POST_REG:
1452 case ARM::STRB_POST_IMM:
1453 case ARM::STRB_POST_REG:
1454 case ARM::STRT_POST_REG:
1455 case ARM::STRT_POST_IMM:
1456 case ARM::STRBT_POST_REG:
1457 case ARM::STRBT_POST_IMM:
1458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1459 return MCDisassembler::Fail;
1465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1466 return MCDisassembler::Fail;
1468 // On loads, the writeback operand comes after Rt.
1469 switch (Inst.getOpcode()) {
1470 case ARM::LDR_POST_IMM:
1471 case ARM::LDR_POST_REG:
1472 case ARM::LDRB_POST_IMM:
1473 case ARM::LDRB_POST_REG:
1474 case ARM::LDRBT_POST_REG:
1475 case ARM::LDRBT_POST_IMM:
1476 case ARM::LDRT_POST_REG:
1477 case ARM::LDRT_POST_IMM:
1478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1479 return MCDisassembler::Fail;
1485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1486 return MCDisassembler::Fail;
1488 ARM_AM::AddrOpc Op = ARM_AM::add;
1489 if (!fieldFromInstruction(Insn, 23, 1))
1492 bool writeback = (P == 0) || (W == 1);
1493 unsigned idx_mode = 0;
1495 idx_mode = ARMII::IndexModePre;
1496 else if (!P && writeback)
1497 idx_mode = ARMII::IndexModePost;
1499 if (writeback && (Rn == 15 || Rn == Rt))
1500 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1503 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1504 return MCDisassembler::Fail;
1505 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1506 switch( fieldFromInstruction(Insn, 5, 2)) {
1520 return MCDisassembler::Fail;
1522 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1523 if (Opc == ARM_AM::ror && amt == 0)
1525 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1527 Inst.addOperand(MCOperand::createImm(imm));
1529 Inst.addOperand(MCOperand::createReg(0));
1530 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1531 Inst.addOperand(MCOperand::createImm(tmp));
1534 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1535 return MCDisassembler::Fail;
1540 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1541 uint64_t Address, const void *Decoder) {
1542 DecodeStatus S = MCDisassembler::Success;
1544 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1545 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1546 unsigned type = fieldFromInstruction(Val, 5, 2);
1547 unsigned imm = fieldFromInstruction(Val, 7, 5);
1548 unsigned U = fieldFromInstruction(Val, 12, 1);
1550 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1566 if (ShOp == ARM_AM::ror && imm == 0)
1569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1570 return MCDisassembler::Fail;
1571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1572 return MCDisassembler::Fail;
1575 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1577 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1578 Inst.addOperand(MCOperand::createImm(shift));
1584 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1585 uint64_t Address, const void *Decoder) {
1586 DecodeStatus S = MCDisassembler::Success;
1588 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1589 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1590 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1591 unsigned type = fieldFromInstruction(Insn, 22, 1);
1592 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1593 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1594 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1595 unsigned W = fieldFromInstruction(Insn, 21, 1);
1596 unsigned P = fieldFromInstruction(Insn, 24, 1);
1597 unsigned Rt2 = Rt + 1;
1599 bool writeback = (W == 1) | (P == 0);
1601 // For {LD,ST}RD, Rt must be even, else undefined.
1602 switch (Inst.getOpcode()) {
1605 case ARM::STRD_POST:
1608 case ARM::LDRD_POST:
1609 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1614 switch (Inst.getOpcode()) {
1617 case ARM::STRD_POST:
1618 if (P == 0 && W == 1)
1619 S = MCDisassembler::SoftFail;
1621 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1622 S = MCDisassembler::SoftFail;
1623 if (type && Rm == 15)
1624 S = MCDisassembler::SoftFail;
1626 S = MCDisassembler::SoftFail;
1627 if (!type && fieldFromInstruction(Insn, 8, 4))
1628 S = MCDisassembler::SoftFail;
1632 case ARM::STRH_POST:
1634 S = MCDisassembler::SoftFail;
1635 if (writeback && (Rn == 15 || Rn == Rt))
1636 S = MCDisassembler::SoftFail;
1637 if (!type && Rm == 15)
1638 S = MCDisassembler::SoftFail;
1642 case ARM::LDRD_POST:
1643 if (type && Rn == 15) {
1645 S = MCDisassembler::SoftFail;
1648 if (P == 0 && W == 1)
1649 S = MCDisassembler::SoftFail;
1650 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1651 S = MCDisassembler::SoftFail;
1652 if (!type && writeback && Rn == 15)
1653 S = MCDisassembler::SoftFail;
1654 if (writeback && (Rn == Rt || Rn == Rt2))
1655 S = MCDisassembler::SoftFail;
1659 case ARM::LDRH_POST:
1660 if (type && Rn == 15) {
1662 S = MCDisassembler::SoftFail;
1666 S = MCDisassembler::SoftFail;
1667 if (!type && Rm == 15)
1668 S = MCDisassembler::SoftFail;
1669 if (!type && writeback && (Rn == 15 || Rn == Rt))
1670 S = MCDisassembler::SoftFail;
1673 case ARM::LDRSH_PRE:
1674 case ARM::LDRSH_POST:
1676 case ARM::LDRSB_PRE:
1677 case ARM::LDRSB_POST:
1678 if (type && Rn == 15) {
1680 S = MCDisassembler::SoftFail;
1683 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1684 S = MCDisassembler::SoftFail;
1685 if (!type && (Rt == 15 || Rm == 15))
1686 S = MCDisassembler::SoftFail;
1687 if (!type && writeback && (Rn == 15 || Rn == Rt))
1688 S = MCDisassembler::SoftFail;
1694 if (writeback) { // Writeback
1696 U |= ARMII::IndexModePre << 9;
1698 U |= ARMII::IndexModePost << 9;
1700 // On stores, the writeback operand precedes Rt.
1701 switch (Inst.getOpcode()) {
1704 case ARM::STRD_POST:
1707 case ARM::STRH_POST:
1708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1709 return MCDisassembler::Fail;
1716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1717 return MCDisassembler::Fail;
1718 switch (Inst.getOpcode()) {
1721 case ARM::STRD_POST:
1724 case ARM::LDRD_POST:
1725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1726 return MCDisassembler::Fail;
1733 // On loads, the writeback operand comes after Rt.
1734 switch (Inst.getOpcode()) {
1737 case ARM::LDRD_POST:
1740 case ARM::LDRH_POST:
1742 case ARM::LDRSH_PRE:
1743 case ARM::LDRSH_POST:
1745 case ARM::LDRSB_PRE:
1746 case ARM::LDRSB_POST:
1749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1750 return MCDisassembler::Fail;
1757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1758 return MCDisassembler::Fail;
1761 Inst.addOperand(MCOperand::createReg(0));
1762 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1765 return MCDisassembler::Fail;
1766 Inst.addOperand(MCOperand::createImm(U));
1769 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1770 return MCDisassembler::Fail;
1775 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1776 uint64_t Address, const void *Decoder) {
1777 DecodeStatus S = MCDisassembler::Success;
1779 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1780 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1797 Inst.addOperand(MCOperand::createImm(mode));
1798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1799 return MCDisassembler::Fail;
1804 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1805 uint64_t Address, const void *Decoder) {
1806 DecodeStatus S = MCDisassembler::Success;
1808 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1809 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1810 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1811 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1814 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1816 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1817 return MCDisassembler::Fail;
1818 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1819 return MCDisassembler::Fail;
1820 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1821 return MCDisassembler::Fail;
1822 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1823 return MCDisassembler::Fail;
1827 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1829 uint64_t Address, const void *Decoder) {
1830 DecodeStatus S = MCDisassembler::Success;
1832 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1833 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1834 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1837 // Ambiguous with RFE and SRS
1838 switch (Inst.getOpcode()) {
1840 Inst.setOpcode(ARM::RFEDA);
1842 case ARM::LDMDA_UPD:
1843 Inst.setOpcode(ARM::RFEDA_UPD);
1846 Inst.setOpcode(ARM::RFEDB);
1848 case ARM::LDMDB_UPD:
1849 Inst.setOpcode(ARM::RFEDB_UPD);
1852 Inst.setOpcode(ARM::RFEIA);
1854 case ARM::LDMIA_UPD:
1855 Inst.setOpcode(ARM::RFEIA_UPD);
1858 Inst.setOpcode(ARM::RFEIB);
1860 case ARM::LDMIB_UPD:
1861 Inst.setOpcode(ARM::RFEIB_UPD);
1864 Inst.setOpcode(ARM::SRSDA);
1866 case ARM::STMDA_UPD:
1867 Inst.setOpcode(ARM::SRSDA_UPD);
1870 Inst.setOpcode(ARM::SRSDB);
1872 case ARM::STMDB_UPD:
1873 Inst.setOpcode(ARM::SRSDB_UPD);
1876 Inst.setOpcode(ARM::SRSIA);
1878 case ARM::STMIA_UPD:
1879 Inst.setOpcode(ARM::SRSIA_UPD);
1882 Inst.setOpcode(ARM::SRSIB);
1884 case ARM::STMIB_UPD:
1885 Inst.setOpcode(ARM::SRSIB_UPD);
1888 return MCDisassembler::Fail;
1891 // For stores (which become SRS's, the only operand is the mode.
1892 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1893 // Check SRS encoding constraints
1894 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1895 fieldFromInstruction(Insn, 20, 1) == 0))
1896 return MCDisassembler::Fail;
1899 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1903 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1907 return MCDisassembler::Fail;
1908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1909 return MCDisassembler::Fail; // Tied
1910 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1911 return MCDisassembler::Fail;
1912 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1913 return MCDisassembler::Fail;
1918 // Check for UNPREDICTABLE predicated ESB instruction
1919 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1920 uint64_t Address, const void *Decoder) {
1921 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1922 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1923 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1924 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1926 DecodeStatus S = MCDisassembler::Success;
1928 Inst.addOperand(MCOperand::createImm(imm8));
1930 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1931 return MCDisassembler::Fail;
1933 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1934 // so all predicates should be allowed.
1935 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1936 S = MCDisassembler::SoftFail;
1941 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1942 uint64_t Address, const void *Decoder) {
1943 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1944 unsigned M = fieldFromInstruction(Insn, 17, 1);
1945 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1946 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1948 DecodeStatus S = MCDisassembler::Success;
1950 // This decoder is called from multiple location that do not check
1951 // the full encoding is valid before they do.
1952 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1953 fieldFromInstruction(Insn, 16, 1) != 0 ||
1954 fieldFromInstruction(Insn, 20, 8) != 0x10)
1955 return MCDisassembler::Fail;
1957 // imod == '01' --> UNPREDICTABLE
1958 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1959 // return failure here. The '01' imod value is unprintable, so there's
1960 // nothing useful we could do even if we returned UNPREDICTABLE.
1962 if (imod == 1) return MCDisassembler::Fail;
1965 Inst.setOpcode(ARM::CPS3p);
1966 Inst.addOperand(MCOperand::createImm(imod));
1967 Inst.addOperand(MCOperand::createImm(iflags));
1968 Inst.addOperand(MCOperand::createImm(mode));
1969 } else if (imod && !M) {
1970 Inst.setOpcode(ARM::CPS2p);
1971 Inst.addOperand(MCOperand::createImm(imod));
1972 Inst.addOperand(MCOperand::createImm(iflags));
1973 if (mode) S = MCDisassembler::SoftFail;
1974 } else if (!imod && M) {
1975 Inst.setOpcode(ARM::CPS1p);
1976 Inst.addOperand(MCOperand::createImm(mode));
1977 if (iflags) S = MCDisassembler::SoftFail;
1979 // imod == '00' && M == '0' --> UNPREDICTABLE
1980 Inst.setOpcode(ARM::CPS1p);
1981 Inst.addOperand(MCOperand::createImm(mode));
1982 S = MCDisassembler::SoftFail;
1988 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1989 uint64_t Address, const void *Decoder) {
1990 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1991 unsigned M = fieldFromInstruction(Insn, 8, 1);
1992 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1993 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1995 DecodeStatus S = MCDisassembler::Success;
1997 // imod == '01' --> UNPREDICTABLE
1998 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1999 // return failure here. The '01' imod value is unprintable, so there's
2000 // nothing useful we could do even if we returned UNPREDICTABLE.
2002 if (imod == 1) return MCDisassembler::Fail;
2005 Inst.setOpcode(ARM::t2CPS3p);
2006 Inst.addOperand(MCOperand::createImm(imod));
2007 Inst.addOperand(MCOperand::createImm(iflags));
2008 Inst.addOperand(MCOperand::createImm(mode));
2009 } else if (imod && !M) {
2010 Inst.setOpcode(ARM::t2CPS2p);
2011 Inst.addOperand(MCOperand::createImm(imod));
2012 Inst.addOperand(MCOperand::createImm(iflags));
2013 if (mode) S = MCDisassembler::SoftFail;
2014 } else if (!imod && M) {
2015 Inst.setOpcode(ARM::t2CPS1p);
2016 Inst.addOperand(MCOperand::createImm(mode));
2017 if (iflags) S = MCDisassembler::SoftFail;
2019 // imod == '00' && M == '0' --> this is a HINT instruction
2020 int imm = fieldFromInstruction(Insn, 0, 8);
2021 // HINT are defined only for immediate in [0..4]
2022 if(imm > 4) return MCDisassembler::Fail;
2023 Inst.setOpcode(ARM::t2HINT);
2024 Inst.addOperand(MCOperand::createImm(imm));
2030 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2031 uint64_t Address, const void *Decoder) {
2032 DecodeStatus S = MCDisassembler::Success;
2034 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2037 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2038 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2039 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2040 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2042 if (Inst.getOpcode() == ARM::t2MOVTi16)
2043 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2044 return MCDisassembler::Fail;
2045 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2046 return MCDisassembler::Fail;
2048 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2049 Inst.addOperand(MCOperand::createImm(imm));
2054 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2055 uint64_t Address, const void *Decoder) {
2056 DecodeStatus S = MCDisassembler::Success;
2058 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2059 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2062 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2063 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2065 if (Inst.getOpcode() == ARM::MOVTi16)
2066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2067 return MCDisassembler::Fail;
2069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2070 return MCDisassembler::Fail;
2072 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2073 Inst.addOperand(MCOperand::createImm(imm));
2075 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2076 return MCDisassembler::Fail;
2081 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2082 uint64_t Address, const void *Decoder) {
2083 DecodeStatus S = MCDisassembler::Success;
2085 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2086 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2087 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2088 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2089 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2092 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2094 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2095 return MCDisassembler::Fail;
2096 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2097 return MCDisassembler::Fail;
2098 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2099 return MCDisassembler::Fail;
2100 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2101 return MCDisassembler::Fail;
2103 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2104 return MCDisassembler::Fail;
2109 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2110 uint64_t Address, const void *Decoder) {
2111 DecodeStatus S = MCDisassembler::Success;
2113 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2114 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2115 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2118 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2121 return MCDisassembler::Fail;
2122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2123 return MCDisassembler::Fail;
2124 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2125 return MCDisassembler::Fail;
2130 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2131 uint64_t Address, const void *Decoder) {
2132 DecodeStatus S = MCDisassembler::Success;
2134 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2136 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2137 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2139 if (!FeatureBits[ARM::HasV8_1aOps] ||
2140 !FeatureBits[ARM::HasV8Ops])
2141 return MCDisassembler::Fail;
2143 // Decoder can be called from DecodeTST, which does not check the full
2144 // encoding is valid.
2145 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2146 fieldFromInstruction(Insn, 4,4) != 0)
2147 return MCDisassembler::Fail;
2148 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2149 fieldFromInstruction(Insn, 0,4) != 0)
2150 S = MCDisassembler::SoftFail;
2152 Inst.setOpcode(ARM::SETPAN);
2153 Inst.addOperand(MCOperand::createImm(Imm));
2158 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2159 uint64_t Address, const void *Decoder) {
2160 DecodeStatus S = MCDisassembler::Success;
2162 unsigned add = fieldFromInstruction(Val, 12, 1);
2163 unsigned imm = fieldFromInstruction(Val, 0, 12);
2164 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2167 return MCDisassembler::Fail;
2169 if (!add) imm *= -1;
2170 if (imm == 0 && !add) imm = INT32_MIN;
2171 Inst.addOperand(MCOperand::createImm(imm));
2173 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2178 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2179 uint64_t Address, const void *Decoder) {
2180 DecodeStatus S = MCDisassembler::Success;
2182 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2183 // U == 1 to add imm, 0 to subtract it.
2184 unsigned U = fieldFromInstruction(Val, 8, 1);
2185 unsigned imm = fieldFromInstruction(Val, 0, 8);
2187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2188 return MCDisassembler::Fail;
2191 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2193 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2198 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2199 uint64_t Address, const void *Decoder) {
2200 DecodeStatus S = MCDisassembler::Success;
2202 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2203 // U == 1 to add imm, 0 to subtract it.
2204 unsigned U = fieldFromInstruction(Val, 8, 1);
2205 unsigned imm = fieldFromInstruction(Val, 0, 8);
2207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2208 return MCDisassembler::Fail;
2211 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2213 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2218 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2219 uint64_t Address, const void *Decoder) {
2220 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2224 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2225 uint64_t Address, const void *Decoder) {
2226 DecodeStatus Status = MCDisassembler::Success;
2228 // Note the J1 and J2 values are from the encoded instruction. So here
2229 // change them to I1 and I2 values via as documented:
2230 // I1 = NOT(J1 EOR S);
2231 // I2 = NOT(J2 EOR S);
2232 // and build the imm32 with one trailing zero as documented:
2233 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2234 unsigned S = fieldFromInstruction(Insn, 26, 1);
2235 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2236 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2237 unsigned I1 = !(J1 ^ S);
2238 unsigned I2 = !(J2 ^ S);
2239 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2240 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2241 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2242 int imm32 = SignExtend32<25>(tmp << 1);
2243 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2244 true, 4, Inst, Decoder))
2245 Inst.addOperand(MCOperand::createImm(imm32));
2251 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2252 uint64_t Address, const void *Decoder) {
2253 DecodeStatus S = MCDisassembler::Success;
2255 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2256 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2259 Inst.setOpcode(ARM::BLXi);
2260 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2261 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2262 true, 4, Inst, Decoder))
2263 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2267 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2268 true, 4, Inst, Decoder))
2269 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2270 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2271 return MCDisassembler::Fail;
2276 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2277 uint64_t Address, const void *Decoder) {
2278 DecodeStatus S = MCDisassembler::Success;
2280 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2281 unsigned align = fieldFromInstruction(Val, 4, 2);
2283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2284 return MCDisassembler::Fail;
2286 Inst.addOperand(MCOperand::createImm(0));
2288 Inst.addOperand(MCOperand::createImm(4 << align));
2293 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2294 uint64_t Address, const void *Decoder) {
2295 DecodeStatus S = MCDisassembler::Success;
2297 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2298 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2299 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2300 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2301 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2302 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2304 // First output register
2305 switch (Inst.getOpcode()) {
2306 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2307 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2308 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2309 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2310 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2311 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2312 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2313 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2314 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2315 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2316 return MCDisassembler::Fail;
2321 case ARM::VLD2b16wb_fixed:
2322 case ARM::VLD2b16wb_register:
2323 case ARM::VLD2b32wb_fixed:
2324 case ARM::VLD2b32wb_register:
2325 case ARM::VLD2b8wb_fixed:
2326 case ARM::VLD2b8wb_register:
2327 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2328 return MCDisassembler::Fail;
2331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2332 return MCDisassembler::Fail;
2335 // Second output register
2336 switch (Inst.getOpcode()) {
2340 case ARM::VLD3d8_UPD:
2341 case ARM::VLD3d16_UPD:
2342 case ARM::VLD3d32_UPD:
2346 case ARM::VLD4d8_UPD:
2347 case ARM::VLD4d16_UPD:
2348 case ARM::VLD4d32_UPD:
2349 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2350 return MCDisassembler::Fail;
2355 case ARM::VLD3q8_UPD:
2356 case ARM::VLD3q16_UPD:
2357 case ARM::VLD3q32_UPD:
2361 case ARM::VLD4q8_UPD:
2362 case ARM::VLD4q16_UPD:
2363 case ARM::VLD4q32_UPD:
2364 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2365 return MCDisassembler::Fail;
2370 // Third output register
2371 switch(Inst.getOpcode()) {
2375 case ARM::VLD3d8_UPD:
2376 case ARM::VLD3d16_UPD:
2377 case ARM::VLD3d32_UPD:
2381 case ARM::VLD4d8_UPD:
2382 case ARM::VLD4d16_UPD:
2383 case ARM::VLD4d32_UPD:
2384 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2385 return MCDisassembler::Fail;
2390 case ARM::VLD3q8_UPD:
2391 case ARM::VLD3q16_UPD:
2392 case ARM::VLD3q32_UPD:
2396 case ARM::VLD4q8_UPD:
2397 case ARM::VLD4q16_UPD:
2398 case ARM::VLD4q32_UPD:
2399 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2400 return MCDisassembler::Fail;
2406 // Fourth output register
2407 switch (Inst.getOpcode()) {
2411 case ARM::VLD4d8_UPD:
2412 case ARM::VLD4d16_UPD:
2413 case ARM::VLD4d32_UPD:
2414 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2415 return MCDisassembler::Fail;
2420 case ARM::VLD4q8_UPD:
2421 case ARM::VLD4q16_UPD:
2422 case ARM::VLD4q32_UPD:
2423 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2424 return MCDisassembler::Fail;
2430 // Writeback operand
2431 switch (Inst.getOpcode()) {
2432 case ARM::VLD1d8wb_fixed:
2433 case ARM::VLD1d16wb_fixed:
2434 case ARM::VLD1d32wb_fixed:
2435 case ARM::VLD1d64wb_fixed:
2436 case ARM::VLD1d8wb_register:
2437 case ARM::VLD1d16wb_register:
2438 case ARM::VLD1d32wb_register:
2439 case ARM::VLD1d64wb_register:
2440 case ARM::VLD1q8wb_fixed:
2441 case ARM::VLD1q16wb_fixed:
2442 case ARM::VLD1q32wb_fixed:
2443 case ARM::VLD1q64wb_fixed:
2444 case ARM::VLD1q8wb_register:
2445 case ARM::VLD1q16wb_register:
2446 case ARM::VLD1q32wb_register:
2447 case ARM::VLD1q64wb_register:
2448 case ARM::VLD1d8Twb_fixed:
2449 case ARM::VLD1d8Twb_register:
2450 case ARM::VLD1d16Twb_fixed:
2451 case ARM::VLD1d16Twb_register:
2452 case ARM::VLD1d32Twb_fixed:
2453 case ARM::VLD1d32Twb_register:
2454 case ARM::VLD1d64Twb_fixed:
2455 case ARM::VLD1d64Twb_register:
2456 case ARM::VLD1d8Qwb_fixed:
2457 case ARM::VLD1d8Qwb_register:
2458 case ARM::VLD1d16Qwb_fixed:
2459 case ARM::VLD1d16Qwb_register:
2460 case ARM::VLD1d32Qwb_fixed:
2461 case ARM::VLD1d32Qwb_register:
2462 case ARM::VLD1d64Qwb_fixed:
2463 case ARM::VLD1d64Qwb_register:
2464 case ARM::VLD2d8wb_fixed:
2465 case ARM::VLD2d16wb_fixed:
2466 case ARM::VLD2d32wb_fixed:
2467 case ARM::VLD2q8wb_fixed:
2468 case ARM::VLD2q16wb_fixed:
2469 case ARM::VLD2q32wb_fixed:
2470 case ARM::VLD2d8wb_register:
2471 case ARM::VLD2d16wb_register:
2472 case ARM::VLD2d32wb_register:
2473 case ARM::VLD2q8wb_register:
2474 case ARM::VLD2q16wb_register:
2475 case ARM::VLD2q32wb_register:
2476 case ARM::VLD2b8wb_fixed:
2477 case ARM::VLD2b16wb_fixed:
2478 case ARM::VLD2b32wb_fixed:
2479 case ARM::VLD2b8wb_register:
2480 case ARM::VLD2b16wb_register:
2481 case ARM::VLD2b32wb_register:
2482 Inst.addOperand(MCOperand::createImm(0));
2484 case ARM::VLD3d8_UPD:
2485 case ARM::VLD3d16_UPD:
2486 case ARM::VLD3d32_UPD:
2487 case ARM::VLD3q8_UPD:
2488 case ARM::VLD3q16_UPD:
2489 case ARM::VLD3q32_UPD:
2490 case ARM::VLD4d8_UPD:
2491 case ARM::VLD4d16_UPD:
2492 case ARM::VLD4d32_UPD:
2493 case ARM::VLD4q8_UPD:
2494 case ARM::VLD4q16_UPD:
2495 case ARM::VLD4q32_UPD:
2496 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2497 return MCDisassembler::Fail;
2503 // AddrMode6 Base (register+alignment)
2504 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2505 return MCDisassembler::Fail;
2507 // AddrMode6 Offset (register)
2508 switch (Inst.getOpcode()) {
2510 // The below have been updated to have explicit am6offset split
2511 // between fixed and register offset. For those instructions not
2512 // yet updated, we need to add an additional reg0 operand for the
2515 // The fixed offset encodes as Rm == 0xd, so we check for that.
2517 Inst.addOperand(MCOperand::createReg(0));
2520 // Fall through to handle the register offset variant.
2522 case ARM::VLD1d8wb_fixed:
2523 case ARM::VLD1d16wb_fixed:
2524 case ARM::VLD1d32wb_fixed:
2525 case ARM::VLD1d64wb_fixed:
2526 case ARM::VLD1d8Twb_fixed:
2527 case ARM::VLD1d16Twb_fixed:
2528 case ARM::VLD1d32Twb_fixed:
2529 case ARM::VLD1d64Twb_fixed:
2530 case ARM::VLD1d8Qwb_fixed:
2531 case ARM::VLD1d16Qwb_fixed:
2532 case ARM::VLD1d32Qwb_fixed:
2533 case ARM::VLD1d64Qwb_fixed:
2534 case ARM::VLD1d8wb_register:
2535 case ARM::VLD1d16wb_register:
2536 case ARM::VLD1d32wb_register:
2537 case ARM::VLD1d64wb_register:
2538 case ARM::VLD1q8wb_fixed:
2539 case ARM::VLD1q16wb_fixed:
2540 case ARM::VLD1q32wb_fixed:
2541 case ARM::VLD1q64wb_fixed:
2542 case ARM::VLD1q8wb_register:
2543 case ARM::VLD1q16wb_register:
2544 case ARM::VLD1q32wb_register:
2545 case ARM::VLD1q64wb_register:
2546 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2547 // variant encodes Rm == 0xf. Anything else is a register offset post-
2548 // increment and we need to add the register operand to the instruction.
2549 if (Rm != 0xD && Rm != 0xF &&
2550 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2551 return MCDisassembler::Fail;
2553 case ARM::VLD2d8wb_fixed:
2554 case ARM::VLD2d16wb_fixed:
2555 case ARM::VLD2d32wb_fixed:
2556 case ARM::VLD2b8wb_fixed:
2557 case ARM::VLD2b16wb_fixed:
2558 case ARM::VLD2b32wb_fixed:
2559 case ARM::VLD2q8wb_fixed:
2560 case ARM::VLD2q16wb_fixed:
2561 case ARM::VLD2q32wb_fixed:
2568 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2569 uint64_t Address, const void *Decoder) {
2570 unsigned type = fieldFromInstruction(Insn, 8, 4);
2571 unsigned align = fieldFromInstruction(Insn, 4, 2);
2572 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2573 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2574 if (type == 10 && align == 3) return MCDisassembler::Fail;
2576 unsigned load = fieldFromInstruction(Insn, 21, 1);
2577 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2578 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2581 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2582 uint64_t Address, const void *Decoder) {
2583 unsigned size = fieldFromInstruction(Insn, 6, 2);
2584 if (size == 3) return MCDisassembler::Fail;
2586 unsigned type = fieldFromInstruction(Insn, 8, 4);
2587 unsigned align = fieldFromInstruction(Insn, 4, 2);
2588 if (type == 8 && align == 3) return MCDisassembler::Fail;
2589 if (type == 9 && align == 3) return MCDisassembler::Fail;
2591 unsigned load = fieldFromInstruction(Insn, 21, 1);
2592 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2593 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2596 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2597 uint64_t Address, const void *Decoder) {
2598 unsigned size = fieldFromInstruction(Insn, 6, 2);
2599 if (size == 3) return MCDisassembler::Fail;
2601 unsigned align = fieldFromInstruction(Insn, 4, 2);
2602 if (align & 2) return MCDisassembler::Fail;
2604 unsigned load = fieldFromInstruction(Insn, 21, 1);
2605 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2606 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2609 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2610 uint64_t Address, const void *Decoder) {
2611 unsigned size = fieldFromInstruction(Insn, 6, 2);
2612 if (size == 3) return MCDisassembler::Fail;
2614 unsigned load = fieldFromInstruction(Insn, 21, 1);
2615 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2616 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2619 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2620 uint64_t Address, const void *Decoder) {
2621 DecodeStatus S = MCDisassembler::Success;
2623 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2624 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2625 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2626 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2627 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2628 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2630 // Writeback Operand
2631 switch (Inst.getOpcode()) {
2632 case ARM::VST1d8wb_fixed:
2633 case ARM::VST1d16wb_fixed:
2634 case ARM::VST1d32wb_fixed:
2635 case ARM::VST1d64wb_fixed:
2636 case ARM::VST1d8wb_register:
2637 case ARM::VST1d16wb_register:
2638 case ARM::VST1d32wb_register:
2639 case ARM::VST1d64wb_register:
2640 case ARM::VST1q8wb_fixed:
2641 case ARM::VST1q16wb_fixed:
2642 case ARM::VST1q32wb_fixed:
2643 case ARM::VST1q64wb_fixed:
2644 case ARM::VST1q8wb_register:
2645 case ARM::VST1q16wb_register:
2646 case ARM::VST1q32wb_register:
2647 case ARM::VST1q64wb_register:
2648 case ARM::VST1d8Twb_fixed:
2649 case ARM::VST1d16Twb_fixed:
2650 case ARM::VST1d32Twb_fixed:
2651 case ARM::VST1d64Twb_fixed:
2652 case ARM::VST1d8Twb_register:
2653 case ARM::VST1d16Twb_register:
2654 case ARM::VST1d32Twb_register:
2655 case ARM::VST1d64Twb_register:
2656 case ARM::VST1d8Qwb_fixed:
2657 case ARM::VST1d16Qwb_fixed:
2658 case ARM::VST1d32Qwb_fixed:
2659 case ARM::VST1d64Qwb_fixed:
2660 case ARM::VST1d8Qwb_register:
2661 case ARM::VST1d16Qwb_register:
2662 case ARM::VST1d32Qwb_register:
2663 case ARM::VST1d64Qwb_register:
2664 case ARM::VST2d8wb_fixed:
2665 case ARM::VST2d16wb_fixed:
2666 case ARM::VST2d32wb_fixed:
2667 case ARM::VST2d8wb_register:
2668 case ARM::VST2d16wb_register:
2669 case ARM::VST2d32wb_register:
2670 case ARM::VST2q8wb_fixed:
2671 case ARM::VST2q16wb_fixed:
2672 case ARM::VST2q32wb_fixed:
2673 case ARM::VST2q8wb_register:
2674 case ARM::VST2q16wb_register:
2675 case ARM::VST2q32wb_register:
2676 case ARM::VST2b8wb_fixed:
2677 case ARM::VST2b16wb_fixed:
2678 case ARM::VST2b32wb_fixed:
2679 case ARM::VST2b8wb_register:
2680 case ARM::VST2b16wb_register:
2681 case ARM::VST2b32wb_register:
2683 return MCDisassembler::Fail;
2684 Inst.addOperand(MCOperand::createImm(0));
2686 case ARM::VST3d8_UPD:
2687 case ARM::VST3d16_UPD:
2688 case ARM::VST3d32_UPD:
2689 case ARM::VST3q8_UPD:
2690 case ARM::VST3q16_UPD:
2691 case ARM::VST3q32_UPD:
2692 case ARM::VST4d8_UPD:
2693 case ARM::VST4d16_UPD:
2694 case ARM::VST4d32_UPD:
2695 case ARM::VST4q8_UPD:
2696 case ARM::VST4q16_UPD:
2697 case ARM::VST4q32_UPD:
2698 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2699 return MCDisassembler::Fail;
2705 // AddrMode6 Base (register+alignment)
2706 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2707 return MCDisassembler::Fail;
2709 // AddrMode6 Offset (register)
2710 switch (Inst.getOpcode()) {
2713 Inst.addOperand(MCOperand::createReg(0));
2714 else if (Rm != 0xF) {
2715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2716 return MCDisassembler::Fail;
2719 case ARM::VST1d8wb_fixed:
2720 case ARM::VST1d16wb_fixed:
2721 case ARM::VST1d32wb_fixed:
2722 case ARM::VST1d64wb_fixed:
2723 case ARM::VST1q8wb_fixed:
2724 case ARM::VST1q16wb_fixed:
2725 case ARM::VST1q32wb_fixed:
2726 case ARM::VST1q64wb_fixed:
2727 case ARM::VST1d8Twb_fixed:
2728 case ARM::VST1d16Twb_fixed:
2729 case ARM::VST1d32Twb_fixed:
2730 case ARM::VST1d64Twb_fixed:
2731 case ARM::VST1d8Qwb_fixed:
2732 case ARM::VST1d16Qwb_fixed:
2733 case ARM::VST1d32Qwb_fixed:
2734 case ARM::VST1d64Qwb_fixed:
2735 case ARM::VST2d8wb_fixed:
2736 case ARM::VST2d16wb_fixed:
2737 case ARM::VST2d32wb_fixed:
2738 case ARM::VST2q8wb_fixed:
2739 case ARM::VST2q16wb_fixed:
2740 case ARM::VST2q32wb_fixed:
2741 case ARM::VST2b8wb_fixed:
2742 case ARM::VST2b16wb_fixed:
2743 case ARM::VST2b32wb_fixed:
2748 // First input register
2749 switch (Inst.getOpcode()) {
2754 case ARM::VST1q16wb_fixed:
2755 case ARM::VST1q16wb_register:
2756 case ARM::VST1q32wb_fixed:
2757 case ARM::VST1q32wb_register:
2758 case ARM::VST1q64wb_fixed:
2759 case ARM::VST1q64wb_register:
2760 case ARM::VST1q8wb_fixed:
2761 case ARM::VST1q8wb_register:
2765 case ARM::VST2d16wb_fixed:
2766 case ARM::VST2d16wb_register:
2767 case ARM::VST2d32wb_fixed:
2768 case ARM::VST2d32wb_register:
2769 case ARM::VST2d8wb_fixed:
2770 case ARM::VST2d8wb_register:
2771 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2772 return MCDisassembler::Fail;
2777 case ARM::VST2b16wb_fixed:
2778 case ARM::VST2b16wb_register:
2779 case ARM::VST2b32wb_fixed:
2780 case ARM::VST2b32wb_register:
2781 case ARM::VST2b8wb_fixed:
2782 case ARM::VST2b8wb_register:
2783 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2784 return MCDisassembler::Fail;
2787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2788 return MCDisassembler::Fail;
2791 // Second input register
2792 switch (Inst.getOpcode()) {
2796 case ARM::VST3d8_UPD:
2797 case ARM::VST3d16_UPD:
2798 case ARM::VST3d32_UPD:
2802 case ARM::VST4d8_UPD:
2803 case ARM::VST4d16_UPD:
2804 case ARM::VST4d32_UPD:
2805 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2806 return MCDisassembler::Fail;
2811 case ARM::VST3q8_UPD:
2812 case ARM::VST3q16_UPD:
2813 case ARM::VST3q32_UPD:
2817 case ARM::VST4q8_UPD:
2818 case ARM::VST4q16_UPD:
2819 case ARM::VST4q32_UPD:
2820 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2821 return MCDisassembler::Fail;
2827 // Third input register
2828 switch (Inst.getOpcode()) {
2832 case ARM::VST3d8_UPD:
2833 case ARM::VST3d16_UPD:
2834 case ARM::VST3d32_UPD:
2838 case ARM::VST4d8_UPD:
2839 case ARM::VST4d16_UPD:
2840 case ARM::VST4d32_UPD:
2841 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2842 return MCDisassembler::Fail;
2847 case ARM::VST3q8_UPD:
2848 case ARM::VST3q16_UPD:
2849 case ARM::VST3q32_UPD:
2853 case ARM::VST4q8_UPD:
2854 case ARM::VST4q16_UPD:
2855 case ARM::VST4q32_UPD:
2856 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2857 return MCDisassembler::Fail;
2863 // Fourth input register
2864 switch (Inst.getOpcode()) {
2868 case ARM::VST4d8_UPD:
2869 case ARM::VST4d16_UPD:
2870 case ARM::VST4d32_UPD:
2871 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2872 return MCDisassembler::Fail;
2877 case ARM::VST4q8_UPD:
2878 case ARM::VST4q16_UPD:
2879 case ARM::VST4q32_UPD:
2880 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2881 return MCDisassembler::Fail;
2890 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2891 uint64_t Address, const void *Decoder) {
2892 DecodeStatus S = MCDisassembler::Success;
2894 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2895 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2896 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2897 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2898 unsigned align = fieldFromInstruction(Insn, 4, 1);
2899 unsigned size = fieldFromInstruction(Insn, 6, 2);
2901 if (size == 0 && align == 1)
2902 return MCDisassembler::Fail;
2903 align *= (1 << size);
2905 switch (Inst.getOpcode()) {
2906 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2907 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2908 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2909 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2910 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2911 return MCDisassembler::Fail;
2914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2915 return MCDisassembler::Fail;
2919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2920 return MCDisassembler::Fail;
2923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2924 return MCDisassembler::Fail;
2925 Inst.addOperand(MCOperand::createImm(align));
2927 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2928 // variant encodes Rm == 0xf. Anything else is a register offset post-
2929 // increment and we need to add the register operand to the instruction.
2930 if (Rm != 0xD && Rm != 0xF &&
2931 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2932 return MCDisassembler::Fail;
2937 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2938 uint64_t Address, const void *Decoder) {
2939 DecodeStatus S = MCDisassembler::Success;
2941 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2942 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2943 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2944 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2945 unsigned align = fieldFromInstruction(Insn, 4, 1);
2946 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2949 switch (Inst.getOpcode()) {
2950 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2951 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2952 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2953 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2954 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2955 return MCDisassembler::Fail;
2957 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2958 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2959 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2960 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2961 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2962 return MCDisassembler::Fail;
2965 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2966 return MCDisassembler::Fail;
2971 Inst.addOperand(MCOperand::createImm(0));
2973 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2974 return MCDisassembler::Fail;
2975 Inst.addOperand(MCOperand::createImm(align));
2977 if (Rm != 0xD && Rm != 0xF) {
2978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2979 return MCDisassembler::Fail;
2985 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2986 uint64_t Address, const void *Decoder) {
2987 DecodeStatus S = MCDisassembler::Success;
2989 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2990 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2991 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2992 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2993 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2995 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2996 return MCDisassembler::Fail;
2997 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2998 return MCDisassembler::Fail;
2999 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3000 return MCDisassembler::Fail;
3002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3003 return MCDisassembler::Fail;
3006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3007 return MCDisassembler::Fail;
3008 Inst.addOperand(MCOperand::createImm(0));
3011 Inst.addOperand(MCOperand::createReg(0));
3012 else if (Rm != 0xF) {
3013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3014 return MCDisassembler::Fail;
3020 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3021 uint64_t Address, const void *Decoder) {
3022 DecodeStatus S = MCDisassembler::Success;
3024 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3025 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3026 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3027 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3028 unsigned size = fieldFromInstruction(Insn, 6, 2);
3029 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3030 unsigned align = fieldFromInstruction(Insn, 4, 1);
3034 return MCDisassembler::Fail;
3045 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3046 return MCDisassembler::Fail;
3047 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3048 return MCDisassembler::Fail;
3049 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3050 return MCDisassembler::Fail;
3051 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3052 return MCDisassembler::Fail;
3054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3055 return MCDisassembler::Fail;
3058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3059 return MCDisassembler::Fail;
3060 Inst.addOperand(MCOperand::createImm(align));
3063 Inst.addOperand(MCOperand::createReg(0));
3064 else if (Rm != 0xF) {
3065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3066 return MCDisassembler::Fail;
3073 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3074 uint64_t Address, const void *Decoder) {
3075 DecodeStatus S = MCDisassembler::Success;
3077 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3078 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3079 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3080 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3081 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3082 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3083 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3084 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3087 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3088 return MCDisassembler::Fail;
3090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3091 return MCDisassembler::Fail;
3094 Inst.addOperand(MCOperand::createImm(imm));
3096 switch (Inst.getOpcode()) {
3097 case ARM::VORRiv4i16:
3098 case ARM::VORRiv2i32:
3099 case ARM::VBICiv4i16:
3100 case ARM::VBICiv2i32:
3101 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3102 return MCDisassembler::Fail;
3104 case ARM::VORRiv8i16:
3105 case ARM::VORRiv4i32:
3106 case ARM::VBICiv8i16:
3107 case ARM::VBICiv4i32:
3108 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3109 return MCDisassembler::Fail;
3118 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3119 uint64_t Address, const void *Decoder) {
3120 DecodeStatus S = MCDisassembler::Success;
3122 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3123 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3124 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3125 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3126 unsigned size = fieldFromInstruction(Insn, 18, 2);
3128 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3129 return MCDisassembler::Fail;
3130 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3131 return MCDisassembler::Fail;
3132 Inst.addOperand(MCOperand::createImm(8 << size));
3137 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3138 uint64_t Address, const void *Decoder) {
3139 Inst.addOperand(MCOperand::createImm(8 - Val));
3140 return MCDisassembler::Success;
3143 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3144 uint64_t Address, const void *Decoder) {
3145 Inst.addOperand(MCOperand::createImm(16 - Val));
3146 return MCDisassembler::Success;
3149 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3150 uint64_t Address, const void *Decoder) {
3151 Inst.addOperand(MCOperand::createImm(32 - Val));
3152 return MCDisassembler::Success;
3155 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3156 uint64_t Address, const void *Decoder) {
3157 Inst.addOperand(MCOperand::createImm(64 - Val));
3158 return MCDisassembler::Success;
3161 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3162 uint64_t Address, const void *Decoder) {
3163 DecodeStatus S = MCDisassembler::Success;
3165 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3166 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3167 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3168 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3169 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3170 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3171 unsigned op = fieldFromInstruction(Insn, 6, 1);
3173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3174 return MCDisassembler::Fail;
3176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3177 return MCDisassembler::Fail; // Writeback
3180 switch (Inst.getOpcode()) {
3183 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3184 return MCDisassembler::Fail;
3187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3188 return MCDisassembler::Fail;
3191 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3192 return MCDisassembler::Fail;
3197 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3198 uint64_t Address, const void *Decoder) {
3199 DecodeStatus S = MCDisassembler::Success;
3201 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3202 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3204 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3205 return MCDisassembler::Fail;
3207 switch(Inst.getOpcode()) {
3209 return MCDisassembler::Fail;
3211 break; // tADR does not explicitly represent the PC as an operand.
3213 Inst.addOperand(MCOperand::createReg(ARM::SP));
3217 Inst.addOperand(MCOperand::createImm(imm));
3221 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3222 uint64_t Address, const void *Decoder) {
3223 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3224 true, 2, Inst, Decoder))
3225 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3226 return MCDisassembler::Success;
3229 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3230 uint64_t Address, const void *Decoder) {
3231 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3232 true, 4, Inst, Decoder))
3233 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3234 return MCDisassembler::Success;
3237 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3238 uint64_t Address, const void *Decoder) {
3239 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3240 true, 2, Inst, Decoder))
3241 Inst.addOperand(MCOperand::createImm(Val << 1));
3242 return MCDisassembler::Success;
3245 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3246 uint64_t Address, const void *Decoder) {
3247 DecodeStatus S = MCDisassembler::Success;
3249 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3250 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3252 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3253 return MCDisassembler::Fail;
3254 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3255 return MCDisassembler::Fail;
3260 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3261 uint64_t Address, const void *Decoder) {
3262 DecodeStatus S = MCDisassembler::Success;
3264 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3265 unsigned imm = fieldFromInstruction(Val, 3, 5);
3267 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3268 return MCDisassembler::Fail;
3269 Inst.addOperand(MCOperand::createImm(imm));
3274 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3275 uint64_t Address, const void *Decoder) {
3276 unsigned imm = Val << 2;
3278 Inst.addOperand(MCOperand::createImm(imm));
3279 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3281 return MCDisassembler::Success;
3284 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3285 uint64_t Address, const void *Decoder) {
3286 Inst.addOperand(MCOperand::createReg(ARM::SP));
3287 Inst.addOperand(MCOperand::createImm(Val));
3289 return MCDisassembler::Success;
3292 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3293 uint64_t Address, const void *Decoder) {
3294 DecodeStatus S = MCDisassembler::Success;
3296 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3297 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3298 unsigned imm = fieldFromInstruction(Val, 0, 2);
3300 // Thumb stores cannot use PC as dest register.
3301 switch (Inst.getOpcode()) {
3306 return MCDisassembler::Fail;
3311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3312 return MCDisassembler::Fail;
3313 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3314 return MCDisassembler::Fail;
3315 Inst.addOperand(MCOperand::createImm(imm));
3320 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3321 uint64_t Address, const void *Decoder) {
3322 DecodeStatus S = MCDisassembler::Success;
3324 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3325 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3327 const FeatureBitset &featureBits =
3328 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3330 bool hasMP = featureBits[ARM::FeatureMP];
3331 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3334 switch (Inst.getOpcode()) {
3336 Inst.setOpcode(ARM::t2LDRBpci);
3339 Inst.setOpcode(ARM::t2LDRHpci);
3342 Inst.setOpcode(ARM::t2LDRSHpci);
3345 Inst.setOpcode(ARM::t2LDRSBpci);
3348 Inst.setOpcode(ARM::t2LDRpci);
3351 Inst.setOpcode(ARM::t2PLDpci);
3354 Inst.setOpcode(ARM::t2PLIpci);
3357 return MCDisassembler::Fail;
3360 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3364 switch (Inst.getOpcode()) {
3366 return MCDisassembler::Fail;
3368 Inst.setOpcode(ARM::t2PLDWs);
3371 Inst.setOpcode(ARM::t2PLIs);
3377 switch (Inst.getOpcode()) {
3382 return MCDisassembler::Fail;
3385 if (!hasV7Ops || !hasMP)
3386 return MCDisassembler::Fail;
3389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3390 return MCDisassembler::Fail;
3393 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3394 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3395 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3396 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3397 return MCDisassembler::Fail;
3402 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3403 uint64_t Address, const void* Decoder) {
3404 DecodeStatus S = MCDisassembler::Success;
3406 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3407 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3408 unsigned U = fieldFromInstruction(Insn, 9, 1);
3409 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3412 unsigned add = fieldFromInstruction(Insn, 9, 1);
3414 const FeatureBitset &featureBits =
3415 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3417 bool hasMP = featureBits[ARM::FeatureMP];
3418 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3421 switch (Inst.getOpcode()) {
3423 Inst.setOpcode(ARM::t2LDRpci);
3426 Inst.setOpcode(ARM::t2LDRBpci);
3428 case ARM::t2LDRSBi8:
3429 Inst.setOpcode(ARM::t2LDRSBpci);
3432 Inst.setOpcode(ARM::t2LDRHpci);
3434 case ARM::t2LDRSHi8:
3435 Inst.setOpcode(ARM::t2LDRSHpci);
3438 Inst.setOpcode(ARM::t2PLDpci);
3441 Inst.setOpcode(ARM::t2PLIpci);
3444 return MCDisassembler::Fail;
3446 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3450 switch (Inst.getOpcode()) {
3451 case ARM::t2LDRSHi8:
3452 return MCDisassembler::Fail;
3455 Inst.setOpcode(ARM::t2PLDWi8);
3457 case ARM::t2LDRSBi8:
3458 Inst.setOpcode(ARM::t2PLIi8);
3465 switch (Inst.getOpcode()) {
3470 return MCDisassembler::Fail;
3473 if (!hasV7Ops || !hasMP)
3474 return MCDisassembler::Fail;
3477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3478 return MCDisassembler::Fail;
3481 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3482 return MCDisassembler::Fail;
3486 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3487 uint64_t Address, const void* Decoder) {
3488 DecodeStatus S = MCDisassembler::Success;
3490 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3491 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3492 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3495 const FeatureBitset &featureBits =
3496 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3498 bool hasMP = featureBits[ARM::FeatureMP];
3499 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3502 switch (Inst.getOpcode()) {
3504 Inst.setOpcode(ARM::t2LDRpci);
3506 case ARM::t2LDRHi12:
3507 Inst.setOpcode(ARM::t2LDRHpci);
3509 case ARM::t2LDRSHi12:
3510 Inst.setOpcode(ARM::t2LDRSHpci);
3512 case ARM::t2LDRBi12:
3513 Inst.setOpcode(ARM::t2LDRBpci);
3515 case ARM::t2LDRSBi12:
3516 Inst.setOpcode(ARM::t2LDRSBpci);
3519 Inst.setOpcode(ARM::t2PLDpci);
3522 Inst.setOpcode(ARM::t2PLIpci);
3525 return MCDisassembler::Fail;
3527 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3531 switch (Inst.getOpcode()) {
3532 case ARM::t2LDRSHi12:
3533 return MCDisassembler::Fail;
3534 case ARM::t2LDRHi12:
3535 Inst.setOpcode(ARM::t2PLDWi12);
3537 case ARM::t2LDRSBi12:
3538 Inst.setOpcode(ARM::t2PLIi12);
3545 switch (Inst.getOpcode()) {
3550 return MCDisassembler::Fail;
3552 case ARM::t2PLDWi12:
3553 if (!hasV7Ops || !hasMP)
3554 return MCDisassembler::Fail;
3557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3558 return MCDisassembler::Fail;
3561 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3562 return MCDisassembler::Fail;
3566 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3567 uint64_t Address, const void* Decoder) {
3568 DecodeStatus S = MCDisassembler::Success;
3570 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3571 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3572 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3576 switch (Inst.getOpcode()) {
3578 Inst.setOpcode(ARM::t2LDRpci);
3581 Inst.setOpcode(ARM::t2LDRBpci);
3584 Inst.setOpcode(ARM::t2LDRHpci);
3587 Inst.setOpcode(ARM::t2LDRSBpci);
3590 Inst.setOpcode(ARM::t2LDRSHpci);
3593 return MCDisassembler::Fail;
3595 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3598 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3599 return MCDisassembler::Fail;
3600 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3601 return MCDisassembler::Fail;
3605 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3606 uint64_t Address, const void* Decoder) {
3607 DecodeStatus S = MCDisassembler::Success;
3609 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3610 unsigned U = fieldFromInstruction(Insn, 23, 1);
3611 int imm = fieldFromInstruction(Insn, 0, 12);
3613 const FeatureBitset &featureBits =
3614 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3616 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3619 switch (Inst.getOpcode()) {
3620 case ARM::t2LDRBpci:
3621 case ARM::t2LDRHpci:
3622 Inst.setOpcode(ARM::t2PLDpci);
3624 case ARM::t2LDRSBpci:
3625 Inst.setOpcode(ARM::t2PLIpci);
3627 case ARM::t2LDRSHpci:
3628 return MCDisassembler::Fail;
3634 switch(Inst.getOpcode()) {
3639 return MCDisassembler::Fail;
3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3643 return MCDisassembler::Fail;
3647 // Special case for #-0.
3653 Inst.addOperand(MCOperand::createImm(imm));
3658 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3659 uint64_t Address, const void *Decoder) {
3661 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3663 int imm = Val & 0xFF;
3665 if (!(Val & 0x100)) imm *= -1;
3666 Inst.addOperand(MCOperand::createImm(imm * 4));
3669 return MCDisassembler::Success;
3672 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3673 uint64_t Address, const void *Decoder) {
3674 DecodeStatus S = MCDisassembler::Success;
3676 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3677 unsigned imm = fieldFromInstruction(Val, 0, 9);
3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3680 return MCDisassembler::Fail;
3681 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3682 return MCDisassembler::Fail;
3687 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3688 uint64_t Address, const void *Decoder) {
3689 DecodeStatus S = MCDisassembler::Success;
3691 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3692 unsigned imm = fieldFromInstruction(Val, 0, 8);
3694 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3695 return MCDisassembler::Fail;
3697 Inst.addOperand(MCOperand::createImm(imm));
3702 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3703 uint64_t Address, const void *Decoder) {
3704 int imm = Val & 0xFF;
3707 else if (!(Val & 0x100))
3709 Inst.addOperand(MCOperand::createImm(imm));
3711 return MCDisassembler::Success;
3714 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3715 uint64_t Address, const void *Decoder) {
3716 DecodeStatus S = MCDisassembler::Success;
3718 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3719 unsigned imm = fieldFromInstruction(Val, 0, 9);
3721 // Thumb stores cannot use PC as dest register.
3722 switch (Inst.getOpcode()) {
3730 return MCDisassembler::Fail;
3736 // Some instructions always use an additive offset.
3737 switch (Inst.getOpcode()) {
3752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3753 return MCDisassembler::Fail;
3754 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3755 return MCDisassembler::Fail;
3760 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3761 uint64_t Address, const void *Decoder) {
3762 DecodeStatus S = MCDisassembler::Success;
3764 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3765 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3766 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3767 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3769 unsigned load = fieldFromInstruction(Insn, 20, 1);
3772 switch (Inst.getOpcode()) {
3773 case ARM::t2LDR_PRE:
3774 case ARM::t2LDR_POST:
3775 Inst.setOpcode(ARM::t2LDRpci);
3777 case ARM::t2LDRB_PRE:
3778 case ARM::t2LDRB_POST:
3779 Inst.setOpcode(ARM::t2LDRBpci);
3781 case ARM::t2LDRH_PRE:
3782 case ARM::t2LDRH_POST:
3783 Inst.setOpcode(ARM::t2LDRHpci);
3785 case ARM::t2LDRSB_PRE:
3786 case ARM::t2LDRSB_POST:
3788 Inst.setOpcode(ARM::t2PLIpci);
3790 Inst.setOpcode(ARM::t2LDRSBpci);
3792 case ARM::t2LDRSH_PRE:
3793 case ARM::t2LDRSH_POST:
3794 Inst.setOpcode(ARM::t2LDRSHpci);
3797 return MCDisassembler::Fail;
3799 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3804 return MCDisassembler::Fail;
3807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3808 return MCDisassembler::Fail;
3811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3812 return MCDisassembler::Fail;
3815 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3816 return MCDisassembler::Fail;
3821 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3822 uint64_t Address, const void *Decoder) {
3823 DecodeStatus S = MCDisassembler::Success;
3825 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3826 unsigned imm = fieldFromInstruction(Val, 0, 12);
3828 // Thumb stores cannot use PC as dest register.
3829 switch (Inst.getOpcode()) {
3831 case ARM::t2STRBi12:
3832 case ARM::t2STRHi12:
3834 return MCDisassembler::Fail;
3839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3840 return MCDisassembler::Fail;
3841 Inst.addOperand(MCOperand::createImm(imm));
3847 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3848 uint64_t Address, const void *Decoder) {
3849 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3851 Inst.addOperand(MCOperand::createReg(ARM::SP));
3852 Inst.addOperand(MCOperand::createReg(ARM::SP));
3853 Inst.addOperand(MCOperand::createImm(imm));
3855 return MCDisassembler::Success;
3858 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3859 uint64_t Address, const void *Decoder) {
3860 DecodeStatus S = MCDisassembler::Success;
3862 if (Inst.getOpcode() == ARM::tADDrSP) {
3863 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3864 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3867 return MCDisassembler::Fail;
3868 Inst.addOperand(MCOperand::createReg(ARM::SP));
3869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3870 return MCDisassembler::Fail;
3871 } else if (Inst.getOpcode() == ARM::tADDspr) {
3872 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3874 Inst.addOperand(MCOperand::createReg(ARM::SP));
3875 Inst.addOperand(MCOperand::createReg(ARM::SP));
3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3877 return MCDisassembler::Fail;
3883 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3884 uint64_t Address, const void *Decoder) {
3885 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3886 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3888 Inst.addOperand(MCOperand::createImm(imod));
3889 Inst.addOperand(MCOperand::createImm(flags));
3891 return MCDisassembler::Success;
3894 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3895 uint64_t Address, const void *Decoder) {
3896 DecodeStatus S = MCDisassembler::Success;
3897 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3898 unsigned add = fieldFromInstruction(Insn, 4, 1);
3900 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3901 return MCDisassembler::Fail;
3902 Inst.addOperand(MCOperand::createImm(add));
3907 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3908 uint64_t Address, const void *Decoder) {
3909 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3910 // Note only one trailing zero not two. Also the J1 and J2 values are from
3911 // the encoded instruction. So here change to I1 and I2 values via:
3912 // I1 = NOT(J1 EOR S);
3913 // I2 = NOT(J2 EOR S);
3914 // and build the imm32 with two trailing zeros as documented:
3915 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3916 unsigned S = (Val >> 23) & 1;
3917 unsigned J1 = (Val >> 22) & 1;
3918 unsigned J2 = (Val >> 21) & 1;
3919 unsigned I1 = !(J1 ^ S);
3920 unsigned I2 = !(J2 ^ S);
3921 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3922 int imm32 = SignExtend32<25>(tmp << 1);
3924 if (!tryAddingSymbolicOperand(Address,
3925 (Address & ~2u) + imm32 + 4,
3926 true, 4, Inst, Decoder))
3927 Inst.addOperand(MCOperand::createImm(imm32));
3928 return MCDisassembler::Success;
3931 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3932 uint64_t Address, const void *Decoder) {
3933 if (Val == 0xA || Val == 0xB)
3934 return MCDisassembler::Fail;
3936 const FeatureBitset &featureBits =
3937 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3939 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3940 return MCDisassembler::Fail;
3942 Inst.addOperand(MCOperand::createImm(Val));
3943 return MCDisassembler::Success;
3947 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3948 uint64_t Address, const void *Decoder) {
3949 DecodeStatus S = MCDisassembler::Success;
3951 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3952 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3954 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3956 return MCDisassembler::Fail;
3957 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3958 return MCDisassembler::Fail;
3963 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3964 uint64_t Address, const void *Decoder) {
3965 DecodeStatus S = MCDisassembler::Success;
3967 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3968 if (pred == 0xE || pred == 0xF) {
3969 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3972 return MCDisassembler::Fail;
3974 Inst.setOpcode(ARM::t2DSB);
3977 Inst.setOpcode(ARM::t2DMB);
3980 Inst.setOpcode(ARM::t2ISB);
3984 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3985 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3988 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3989 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3990 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3991 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3992 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3994 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3995 return MCDisassembler::Fail;
3996 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3997 return MCDisassembler::Fail;
4002 // Decode a shifted immediate operand. These basically consist
4003 // of an 8-bit value, and a 4-bit directive that specifies either
4004 // a splat operation or a rotation.
4005 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4006 uint64_t Address, const void *Decoder) {
4007 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4009 unsigned byte = fieldFromInstruction(Val, 8, 2);
4010 unsigned imm = fieldFromInstruction(Val, 0, 8);
4013 Inst.addOperand(MCOperand::createImm(imm));
4016 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4019 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4022 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4027 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4028 unsigned rot = fieldFromInstruction(Val, 7, 5);
4029 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4030 Inst.addOperand(MCOperand::createImm(imm));
4033 return MCDisassembler::Success;
4037 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4038 uint64_t Address, const void *Decoder) {
4039 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4040 true, 2, Inst, Decoder))
4041 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4042 return MCDisassembler::Success;
4045 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4047 const void *Decoder) {
4048 // Val is passed in as S:J1:J2:imm10:imm11
4049 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4050 // the encoded instruction. So here change to I1 and I2 values via:
4051 // I1 = NOT(J1 EOR S);
4052 // I2 = NOT(J2 EOR S);
4053 // and build the imm32 with one trailing zero as documented:
4054 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4055 unsigned S = (Val >> 23) & 1;
4056 unsigned J1 = (Val >> 22) & 1;
4057 unsigned J2 = (Val >> 21) & 1;
4058 unsigned I1 = !(J1 ^ S);
4059 unsigned I2 = !(J2 ^ S);
4060 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4061 int imm32 = SignExtend32<25>(tmp << 1);
4063 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4064 true, 4, Inst, Decoder))
4065 Inst.addOperand(MCOperand::createImm(imm32));
4066 return MCDisassembler::Success;
4069 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4070 uint64_t Address, const void *Decoder) {
4072 return MCDisassembler::Fail;
4074 Inst.addOperand(MCOperand::createImm(Val));
4075 return MCDisassembler::Success;
4078 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4079 uint64_t Address, const void *Decoder) {
4081 return MCDisassembler::Fail;
4083 Inst.addOperand(MCOperand::createImm(Val));
4084 return MCDisassembler::Success;
4087 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4088 uint64_t Address, const void *Decoder) {
4089 DecodeStatus S = MCDisassembler::Success;
4090 const FeatureBitset &FeatureBits =
4091 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4093 if (FeatureBits[ARM::FeatureMClass]) {
4094 unsigned ValLow = Val & 0xff;
4096 // Validate the SYSm value first.
4111 case 18: // basepri_max
4112 case 19: // faultmask
4113 if (!(FeatureBits[ARM::HasV7Ops]))
4114 // Values basepri, basepri_max and faultmask are only valid for v7m.
4115 return MCDisassembler::Fail;
4117 case 0x8a: // msplim_ns
4118 case 0x8b: // psplim_ns
4119 case 0x91: // basepri_ns
4120 case 0x92: // basepri_max_ns
4121 case 0x93: // faultmask_ns
4122 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4123 return MCDisassembler::Fail;
4127 case 0x88: // msp_ns
4128 case 0x89: // psp_ns
4129 case 0x90: // primask_ns
4130 case 0x94: // control_ns
4132 if (!(FeatureBits[ARM::Feature8MSecExt]))
4133 return MCDisassembler::Fail;
4136 return MCDisassembler::Fail;
4139 if (Inst.getOpcode() == ARM::t2MSR_M) {
4140 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4141 if (!(FeatureBits[ARM::HasV7Ops])) {
4142 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4145 S = MCDisassembler::SoftFail;
4148 // The ARMv7-M architecture stores an additional 2-bit mask value in
4149 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4150 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4151 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4152 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4153 // only if the processor includes the DSP extension.
4154 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4155 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4156 S = MCDisassembler::SoftFail;
4162 return MCDisassembler::Fail;
4164 Inst.addOperand(MCOperand::createImm(Val));
4168 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4169 uint64_t Address, const void *Decoder) {
4171 unsigned R = fieldFromInstruction(Val, 5, 1);
4172 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4174 // The table of encodings for these banked registers comes from B9.2.3 of the
4175 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4176 // neater. So by fiat, these values are UNPREDICTABLE:
4178 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4179 SysM == 0x1a || SysM == 0x1b)
4180 return MCDisassembler::SoftFail;
4182 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4183 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4184 return MCDisassembler::SoftFail;
4187 Inst.addOperand(MCOperand::createImm(Val));
4188 return MCDisassembler::Success;
4191 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4192 uint64_t Address, const void *Decoder) {
4193 DecodeStatus S = MCDisassembler::Success;
4195 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4196 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4197 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4200 S = MCDisassembler::SoftFail;
4202 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4203 return MCDisassembler::Fail;
4204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4205 return MCDisassembler::Fail;
4206 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4207 return MCDisassembler::Fail;
4212 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4214 const void *Decoder) {
4215 DecodeStatus S = MCDisassembler::Success;
4217 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4218 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4219 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4220 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4222 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4223 return MCDisassembler::Fail;
4225 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4226 S = MCDisassembler::SoftFail;
4228 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4229 return MCDisassembler::Fail;
4230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4233 return MCDisassembler::Fail;
4238 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4239 uint64_t Address, const void *Decoder) {
4240 DecodeStatus S = MCDisassembler::Success;
4242 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4243 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4244 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4245 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4246 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4247 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4249 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4252 return MCDisassembler::Fail;
4253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4254 return MCDisassembler::Fail;
4255 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4256 return MCDisassembler::Fail;
4257 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4258 return MCDisassembler::Fail;
4263 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4264 uint64_t Address, const void *Decoder) {
4265 DecodeStatus S = MCDisassembler::Success;
4267 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4268 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4269 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4270 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4271 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4272 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4273 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4275 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4276 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4278 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4279 return MCDisassembler::Fail;
4280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4281 return MCDisassembler::Fail;
4282 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4283 return MCDisassembler::Fail;
4284 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4285 return MCDisassembler::Fail;
4290 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4291 uint64_t Address, const void *Decoder) {
4292 DecodeStatus S = MCDisassembler::Success;
4294 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4295 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4296 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4297 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4298 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4299 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4301 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4304 return MCDisassembler::Fail;
4305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4306 return MCDisassembler::Fail;
4307 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4308 return MCDisassembler::Fail;
4309 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4310 return MCDisassembler::Fail;
4315 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4316 uint64_t Address, const void *Decoder) {
4317 DecodeStatus S = MCDisassembler::Success;
4319 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4320 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4321 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4322 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4323 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4324 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4326 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4329 return MCDisassembler::Fail;
4330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4331 return MCDisassembler::Fail;
4332 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4333 return MCDisassembler::Fail;
4334 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4335 return MCDisassembler::Fail;
4340 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4341 uint64_t Address, const void *Decoder) {
4342 DecodeStatus S = MCDisassembler::Success;
4344 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4345 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4346 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4347 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4348 unsigned size = fieldFromInstruction(Insn, 10, 2);
4354 return MCDisassembler::Fail;
4356 if (fieldFromInstruction(Insn, 4, 1))
4357 return MCDisassembler::Fail; // UNDEFINED
4358 index = fieldFromInstruction(Insn, 5, 3);
4361 if (fieldFromInstruction(Insn, 5, 1))
4362 return MCDisassembler::Fail; // UNDEFINED
4363 index = fieldFromInstruction(Insn, 6, 2);
4364 if (fieldFromInstruction(Insn, 4, 1))
4368 if (fieldFromInstruction(Insn, 6, 1))
4369 return MCDisassembler::Fail; // UNDEFINED
4370 index = fieldFromInstruction(Insn, 7, 1);
4372 switch (fieldFromInstruction(Insn, 4, 2)) {
4378 return MCDisassembler::Fail;
4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4384 return MCDisassembler::Fail;
4385 if (Rm != 0xF) { // Writeback
4386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4387 return MCDisassembler::Fail;
4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4390 return MCDisassembler::Fail;
4391 Inst.addOperand(MCOperand::createImm(align));
4394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4395 return MCDisassembler::Fail;
4397 Inst.addOperand(MCOperand::createReg(0));
4400 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4401 return MCDisassembler::Fail;
4402 Inst.addOperand(MCOperand::createImm(index));
4407 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4408 uint64_t Address, const void *Decoder) {
4409 DecodeStatus S = MCDisassembler::Success;
4411 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4412 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4413 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4414 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4415 unsigned size = fieldFromInstruction(Insn, 10, 2);
4421 return MCDisassembler::Fail;
4423 if (fieldFromInstruction(Insn, 4, 1))
4424 return MCDisassembler::Fail; // UNDEFINED
4425 index = fieldFromInstruction(Insn, 5, 3);
4428 if (fieldFromInstruction(Insn, 5, 1))
4429 return MCDisassembler::Fail; // UNDEFINED
4430 index = fieldFromInstruction(Insn, 6, 2);
4431 if (fieldFromInstruction(Insn, 4, 1))
4435 if (fieldFromInstruction(Insn, 6, 1))
4436 return MCDisassembler::Fail; // UNDEFINED
4437 index = fieldFromInstruction(Insn, 7, 1);
4439 switch (fieldFromInstruction(Insn, 4, 2)) {
4445 return MCDisassembler::Fail;
4450 if (Rm != 0xF) { // Writeback
4451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4452 return MCDisassembler::Fail;
4454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4455 return MCDisassembler::Fail;
4456 Inst.addOperand(MCOperand::createImm(align));
4459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4460 return MCDisassembler::Fail;
4462 Inst.addOperand(MCOperand::createReg(0));
4465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4466 return MCDisassembler::Fail;
4467 Inst.addOperand(MCOperand::createImm(index));
4472 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4473 uint64_t Address, const void *Decoder) {
4474 DecodeStatus S = MCDisassembler::Success;
4476 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4477 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4478 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4479 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4480 unsigned size = fieldFromInstruction(Insn, 10, 2);
4487 return MCDisassembler::Fail;
4489 index = fieldFromInstruction(Insn, 5, 3);
4490 if (fieldFromInstruction(Insn, 4, 1))
4494 index = fieldFromInstruction(Insn, 6, 2);
4495 if (fieldFromInstruction(Insn, 4, 1))
4497 if (fieldFromInstruction(Insn, 5, 1))
4501 if (fieldFromInstruction(Insn, 5, 1))
4502 return MCDisassembler::Fail; // UNDEFINED
4503 index = fieldFromInstruction(Insn, 7, 1);
4504 if (fieldFromInstruction(Insn, 4, 1) != 0)
4506 if (fieldFromInstruction(Insn, 6, 1))
4511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4512 return MCDisassembler::Fail;
4513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4514 return MCDisassembler::Fail;
4515 if (Rm != 0xF) { // Writeback
4516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4517 return MCDisassembler::Fail;
4519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4520 return MCDisassembler::Fail;
4521 Inst.addOperand(MCOperand::createImm(align));
4524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4525 return MCDisassembler::Fail;
4527 Inst.addOperand(MCOperand::createReg(0));
4530 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4531 return MCDisassembler::Fail;
4532 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4533 return MCDisassembler::Fail;
4534 Inst.addOperand(MCOperand::createImm(index));
4539 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4540 uint64_t Address, const void *Decoder) {
4541 DecodeStatus S = MCDisassembler::Success;
4543 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4544 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4545 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4546 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4547 unsigned size = fieldFromInstruction(Insn, 10, 2);
4554 return MCDisassembler::Fail;
4556 index = fieldFromInstruction(Insn, 5, 3);
4557 if (fieldFromInstruction(Insn, 4, 1))
4561 index = fieldFromInstruction(Insn, 6, 2);
4562 if (fieldFromInstruction(Insn, 4, 1))
4564 if (fieldFromInstruction(Insn, 5, 1))
4568 if (fieldFromInstruction(Insn, 5, 1))
4569 return MCDisassembler::Fail; // UNDEFINED
4570 index = fieldFromInstruction(Insn, 7, 1);
4571 if (fieldFromInstruction(Insn, 4, 1) != 0)
4573 if (fieldFromInstruction(Insn, 6, 1))
4578 if (Rm != 0xF) { // Writeback
4579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4580 return MCDisassembler::Fail;
4582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4583 return MCDisassembler::Fail;
4584 Inst.addOperand(MCOperand::createImm(align));
4587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4588 return MCDisassembler::Fail;
4590 Inst.addOperand(MCOperand::createReg(0));
4593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4594 return MCDisassembler::Fail;
4595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4596 return MCDisassembler::Fail;
4597 Inst.addOperand(MCOperand::createImm(index));
4602 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4603 uint64_t Address, const void *Decoder) {
4604 DecodeStatus S = MCDisassembler::Success;
4606 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4607 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4608 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4609 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4610 unsigned size = fieldFromInstruction(Insn, 10, 2);
4617 return MCDisassembler::Fail;
4619 if (fieldFromInstruction(Insn, 4, 1))
4620 return MCDisassembler::Fail; // UNDEFINED
4621 index = fieldFromInstruction(Insn, 5, 3);
4624 if (fieldFromInstruction(Insn, 4, 1))
4625 return MCDisassembler::Fail; // UNDEFINED
4626 index = fieldFromInstruction(Insn, 6, 2);
4627 if (fieldFromInstruction(Insn, 5, 1))
4631 if (fieldFromInstruction(Insn, 4, 2))
4632 return MCDisassembler::Fail; // UNDEFINED
4633 index = fieldFromInstruction(Insn, 7, 1);
4634 if (fieldFromInstruction(Insn, 6, 1))
4639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4640 return MCDisassembler::Fail;
4641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4642 return MCDisassembler::Fail;
4643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4644 return MCDisassembler::Fail;
4646 if (Rm != 0xF) { // Writeback
4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4648 return MCDisassembler::Fail;
4650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4651 return MCDisassembler::Fail;
4652 Inst.addOperand(MCOperand::createImm(align));
4655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4656 return MCDisassembler::Fail;
4658 Inst.addOperand(MCOperand::createReg(0));
4661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4662 return MCDisassembler::Fail;
4663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4664 return MCDisassembler::Fail;
4665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4666 return MCDisassembler::Fail;
4667 Inst.addOperand(MCOperand::createImm(index));
4672 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4673 uint64_t Address, const void *Decoder) {
4674 DecodeStatus S = MCDisassembler::Success;
4676 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4677 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4678 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4679 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4680 unsigned size = fieldFromInstruction(Insn, 10, 2);
4687 return MCDisassembler::Fail;
4689 if (fieldFromInstruction(Insn, 4, 1))
4690 return MCDisassembler::Fail; // UNDEFINED
4691 index = fieldFromInstruction(Insn, 5, 3);
4694 if (fieldFromInstruction(Insn, 4, 1))
4695 return MCDisassembler::Fail; // UNDEFINED
4696 index = fieldFromInstruction(Insn, 6, 2);
4697 if (fieldFromInstruction(Insn, 5, 1))
4701 if (fieldFromInstruction(Insn, 4, 2))
4702 return MCDisassembler::Fail; // UNDEFINED
4703 index = fieldFromInstruction(Insn, 7, 1);
4704 if (fieldFromInstruction(Insn, 6, 1))
4709 if (Rm != 0xF) { // Writeback
4710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4711 return MCDisassembler::Fail;
4713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4714 return MCDisassembler::Fail;
4715 Inst.addOperand(MCOperand::createImm(align));
4718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4719 return MCDisassembler::Fail;
4721 Inst.addOperand(MCOperand::createReg(0));
4724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4725 return MCDisassembler::Fail;
4726 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4727 return MCDisassembler::Fail;
4728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4729 return MCDisassembler::Fail;
4730 Inst.addOperand(MCOperand::createImm(index));
4735 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4736 uint64_t Address, const void *Decoder) {
4737 DecodeStatus S = MCDisassembler::Success;
4739 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4740 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4741 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4742 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4743 unsigned size = fieldFromInstruction(Insn, 10, 2);
4750 return MCDisassembler::Fail;
4752 if (fieldFromInstruction(Insn, 4, 1))
4754 index = fieldFromInstruction(Insn, 5, 3);
4757 if (fieldFromInstruction(Insn, 4, 1))
4759 index = fieldFromInstruction(Insn, 6, 2);
4760 if (fieldFromInstruction(Insn, 5, 1))
4764 switch (fieldFromInstruction(Insn, 4, 2)) {
4768 return MCDisassembler::Fail;
4770 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4773 index = fieldFromInstruction(Insn, 7, 1);
4774 if (fieldFromInstruction(Insn, 6, 1))
4779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4780 return MCDisassembler::Fail;
4781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4782 return MCDisassembler::Fail;
4783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4784 return MCDisassembler::Fail;
4785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4786 return MCDisassembler::Fail;
4788 if (Rm != 0xF) { // Writeback
4789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4790 return MCDisassembler::Fail;
4792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4793 return MCDisassembler::Fail;
4794 Inst.addOperand(MCOperand::createImm(align));
4797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4798 return MCDisassembler::Fail;
4800 Inst.addOperand(MCOperand::createReg(0));
4803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4804 return MCDisassembler::Fail;
4805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4806 return MCDisassembler::Fail;
4807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4808 return MCDisassembler::Fail;
4809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4810 return MCDisassembler::Fail;
4811 Inst.addOperand(MCOperand::createImm(index));
4816 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4817 uint64_t Address, const void *Decoder) {
4818 DecodeStatus S = MCDisassembler::Success;
4820 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4821 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4822 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4823 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4824 unsigned size = fieldFromInstruction(Insn, 10, 2);
4831 return MCDisassembler::Fail;
4833 if (fieldFromInstruction(Insn, 4, 1))
4835 index = fieldFromInstruction(Insn, 5, 3);
4838 if (fieldFromInstruction(Insn, 4, 1))
4840 index = fieldFromInstruction(Insn, 6, 2);
4841 if (fieldFromInstruction(Insn, 5, 1))
4845 switch (fieldFromInstruction(Insn, 4, 2)) {
4849 return MCDisassembler::Fail;
4851 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4854 index = fieldFromInstruction(Insn, 7, 1);
4855 if (fieldFromInstruction(Insn, 6, 1))
4860 if (Rm != 0xF) { // Writeback
4861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4862 return MCDisassembler::Fail;
4864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4865 return MCDisassembler::Fail;
4866 Inst.addOperand(MCOperand::createImm(align));
4869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4870 return MCDisassembler::Fail;
4872 Inst.addOperand(MCOperand::createReg(0));
4875 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4876 return MCDisassembler::Fail;
4877 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4878 return MCDisassembler::Fail;
4879 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4880 return MCDisassembler::Fail;
4881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4882 return MCDisassembler::Fail;
4883 Inst.addOperand(MCOperand::createImm(index));
4888 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4889 uint64_t Address, const void *Decoder) {
4890 DecodeStatus S = MCDisassembler::Success;
4891 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4892 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4893 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4894 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4895 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4897 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4898 S = MCDisassembler::SoftFail;
4900 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4901 return MCDisassembler::Fail;
4902 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4903 return MCDisassembler::Fail;
4904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4905 return MCDisassembler::Fail;
4906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4907 return MCDisassembler::Fail;
4908 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4909 return MCDisassembler::Fail;
4914 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4915 uint64_t Address, const void *Decoder) {
4916 DecodeStatus S = MCDisassembler::Success;
4917 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4918 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4919 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4920 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4921 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4923 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4924 S = MCDisassembler::SoftFail;
4926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4927 return MCDisassembler::Fail;
4928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4929 return MCDisassembler::Fail;
4930 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4931 return MCDisassembler::Fail;
4932 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4933 return MCDisassembler::Fail;
4934 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4935 return MCDisassembler::Fail;
4940 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4941 uint64_t Address, const void *Decoder) {
4942 DecodeStatus S = MCDisassembler::Success;
4943 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4944 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4948 S = MCDisassembler::SoftFail;
4952 return MCDisassembler::Fail;
4954 Inst.addOperand(MCOperand::createImm(pred));
4955 Inst.addOperand(MCOperand::createImm(mask));
4960 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4961 uint64_t Address, const void *Decoder) {
4962 DecodeStatus S = MCDisassembler::Success;
4964 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4965 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4966 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4967 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4968 unsigned W = fieldFromInstruction(Insn, 21, 1);
4969 unsigned U = fieldFromInstruction(Insn, 23, 1);
4970 unsigned P = fieldFromInstruction(Insn, 24, 1);
4971 bool writeback = (W == 1) | (P == 0);
4973 addr |= (U << 8) | (Rn << 9);
4975 if (writeback && (Rn == Rt || Rn == Rt2))
4976 Check(S, MCDisassembler::SoftFail);
4978 Check(S, MCDisassembler::SoftFail);
4981 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4982 return MCDisassembler::Fail;
4984 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4985 return MCDisassembler::Fail;
4986 // Writeback operand
4987 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4988 return MCDisassembler::Fail;
4990 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4991 return MCDisassembler::Fail;
4997 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4998 uint64_t Address, const void *Decoder) {
4999 DecodeStatus S = MCDisassembler::Success;
5001 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5002 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5003 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5004 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5005 unsigned W = fieldFromInstruction(Insn, 21, 1);
5006 unsigned U = fieldFromInstruction(Insn, 23, 1);
5007 unsigned P = fieldFromInstruction(Insn, 24, 1);
5008 bool writeback = (W == 1) | (P == 0);
5010 addr |= (U << 8) | (Rn << 9);
5012 if (writeback && (Rn == Rt || Rn == Rt2))
5013 Check(S, MCDisassembler::SoftFail);
5015 // Writeback operand
5016 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5017 return MCDisassembler::Fail;
5019 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5020 return MCDisassembler::Fail;
5022 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5023 return MCDisassembler::Fail;
5025 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5026 return MCDisassembler::Fail;
5031 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5032 uint64_t Address, const void *Decoder) {
5033 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5034 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5035 if (sign1 != sign2) return MCDisassembler::Fail;
5037 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5038 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5039 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5041 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5043 return MCDisassembler::Success;
5046 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5048 const void *Decoder) {
5049 DecodeStatus S = MCDisassembler::Success;
5051 // Shift of "asr #32" is not allowed in Thumb2 mode.
5052 if (Val == 0x20) S = MCDisassembler::Fail;
5053 Inst.addOperand(MCOperand::createImm(Val));
5057 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5058 uint64_t Address, const void *Decoder) {
5059 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5060 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5061 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5062 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5065 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5067 DecodeStatus S = MCDisassembler::Success;
5069 if (Rt == Rn || Rn == Rt2)
5070 S = MCDisassembler::SoftFail;
5072 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5073 return MCDisassembler::Fail;
5074 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5075 return MCDisassembler::Fail;
5076 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5077 return MCDisassembler::Fail;
5078 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5079 return MCDisassembler::Fail;
5084 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5085 uint64_t Address, const void *Decoder) {
5086 const FeatureBitset &featureBits =
5087 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5088 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5090 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5091 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5092 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5093 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5094 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5095 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5096 unsigned op = fieldFromInstruction(Insn, 5, 1);
5098 DecodeStatus S = MCDisassembler::Success;
5100 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5101 if (!(imm & 0x38)) {
5103 if (op == 1) return MCDisassembler::Fail;
5104 Inst.setOpcode(ARM::VMOVv2f32);
5109 Inst.setOpcode(ARM::VMOVv1i64);
5111 Inst.setOpcode(ARM::VMOVv8i8);
5116 Inst.setOpcode(ARM::VMVNv2i32);
5118 Inst.setOpcode(ARM::VMOVv2i32);
5123 Inst.setOpcode(ARM::VMVNv2i32);
5125 Inst.setOpcode(ARM::VMOVv2i32);
5129 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5132 if (!(imm & 0x20)) return MCDisassembler::Fail;
5134 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5135 return MCDisassembler::Fail;
5136 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5137 return MCDisassembler::Fail;
5138 Inst.addOperand(MCOperand::createImm(64 - imm));
5143 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5144 uint64_t Address, const void *Decoder) {
5145 const FeatureBitset &featureBits =
5146 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5147 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5149 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5150 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5151 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5152 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5153 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5154 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5155 unsigned op = fieldFromInstruction(Insn, 5, 1);
5157 DecodeStatus S = MCDisassembler::Success;
5159 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5160 if (!(imm & 0x38)) {
5162 if (op == 1) return MCDisassembler::Fail;
5163 Inst.setOpcode(ARM::VMOVv4f32);
5168 Inst.setOpcode(ARM::VMOVv2i64);
5170 Inst.setOpcode(ARM::VMOVv16i8);
5175 Inst.setOpcode(ARM::VMVNv4i32);
5177 Inst.setOpcode(ARM::VMOVv4i32);
5182 Inst.setOpcode(ARM::VMVNv4i32);
5184 Inst.setOpcode(ARM::VMOVv4i32);
5188 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5191 if (!(imm & 0x20)) return MCDisassembler::Fail;
5193 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5194 return MCDisassembler::Fail;
5195 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5196 return MCDisassembler::Fail;
5197 Inst.addOperand(MCOperand::createImm(64 - imm));
5202 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5203 uint64_t Address, const void *Decoder) {
5204 DecodeStatus S = MCDisassembler::Success;
5206 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5207 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5208 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5209 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5210 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5212 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5213 S = MCDisassembler::SoftFail;
5215 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5216 return MCDisassembler::Fail;
5217 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5218 return MCDisassembler::Fail;
5219 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5220 return MCDisassembler::Fail;
5221 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5222 return MCDisassembler::Fail;
5223 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5224 return MCDisassembler::Fail;
5229 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5230 uint64_t Address, const void *Decoder) {
5231 DecodeStatus S = MCDisassembler::Success;
5233 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5234 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5235 unsigned cop = fieldFromInstruction(Val, 8, 4);
5236 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5237 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5239 if ((cop & ~0x1) == 0xa)
5240 return MCDisassembler::Fail;
5243 S = MCDisassembler::SoftFail;
5245 // We have to check if the instruction is MRRC2
5246 // or MCRR2 when constructing the operands for
5247 // Inst. Reason is because MRRC2 stores to two
5248 // registers so it's tablegen desc has has two
5249 // outputs whereas MCRR doesn't store to any
5250 // registers so all of it's operands are listed
5251 // as inputs, therefore the operand order for
5252 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5253 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5255 if (Inst.getOpcode() == ARM::MRRC2) {
5256 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5257 return MCDisassembler::Fail;
5258 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5259 return MCDisassembler::Fail;
5261 Inst.addOperand(MCOperand::createImm(cop));
5262 Inst.addOperand(MCOperand::createImm(opc1));
5263 if (Inst.getOpcode() == ARM::MCRR2) {
5264 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5265 return MCDisassembler::Fail;
5266 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5267 return MCDisassembler::Fail;
5269 Inst.addOperand(MCOperand::createImm(CRm));