1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMAddressingModes.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMMCTargetDesc.h"
13 #include "Utils/ARMBaseInfo.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/SubtargetFeature.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
33 #define DEBUG_TYPE "arm-disassembler"
35 using DecodeStatus = MCDisassembler::DecodeStatus;
39 // Handles the condition code status of instructions in IT blocks
43 // Returns the condition code for instruction in IT block
45 unsigned CC = ARMCC::AL;
51 // Advances the IT block state to the next T or E
52 void advanceITState() {
56 // Returns true if the current instruction is in an IT block
57 bool instrInITBlock() {
58 return !ITStates.empty();
61 // Returns true if current instruction is the last instruction in an IT block
62 bool instrLastInITBlock() {
63 return ITStates.size() == 1;
66 // Called when decoding an IT instruction. Sets the IT state for the following
67 // instructions that for the IT block. Firstcond and Mask correspond to the
68 // fields in the IT instruction encoding.
69 void setITState(char Firstcond, char Mask) {
70 // (3 - the number of trailing zeros) is the number of then / else.
71 unsigned CondBit0 = Firstcond & 1;
72 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
73 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
74 assert(NumTZ <= 3 && "Invalid IT mask!");
75 // push condition codes onto the stack the correct order for the pops
76 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
77 bool T = ((Mask >> Pos) & 1) == CondBit0;
79 ITStates.push_back(CCBits);
81 ITStates.push_back(CCBits ^ 1);
83 ITStates.push_back(CCBits);
87 std::vector<unsigned char> ITStates;
90 /// ARM disassembler for all ARM platforms.
91 class ARMDisassembler : public MCDisassembler {
93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94 MCDisassembler(STI, Ctx) {
97 ~ARMDisassembler() override = default;
99 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
100 ArrayRef<uint8_t> Bytes, uint64_t Address,
101 raw_ostream &VStream,
102 raw_ostream &CStream) const override;
105 /// Thumb disassembler for all Thumb platforms.
106 class ThumbDisassembler : public MCDisassembler {
108 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
109 MCDisassembler(STI, Ctx) {
112 ~ThumbDisassembler() override = default;
114 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
115 ArrayRef<uint8_t> Bytes, uint64_t Address,
116 raw_ostream &VStream,
117 raw_ostream &CStream) const override;
120 mutable ITStatus ITBlock;
122 DecodeStatus AddThumbPredicate(MCInst&) const;
123 void UpdateThumbVFPPredicate(MCInst&) const;
126 } // end anonymous namespace
128 static bool Check(DecodeStatus &Out, DecodeStatus In) {
130 case MCDisassembler::Success:
131 // Out stays the same.
133 case MCDisassembler::SoftFail:
136 case MCDisassembler::Fail:
140 llvm_unreachable("Invalid DecodeStatus!");
143 // Forward declare these because the autogenerated code will reference them.
144 // Definitions are further down.
145 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
146 uint64_t Address, const void *Decoder);
147 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
148 unsigned RegNo, uint64_t Address,
149 const void *Decoder);
150 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
151 unsigned RegNo, uint64_t Address,
152 const void *Decoder);
153 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
164 uint64_t Address, const void *Decoder);
165 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
166 uint64_t Address, const void *Decoder);
167 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
170 const void *Decoder);
171 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
172 uint64_t Address, const void *Decoder);
173 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
174 uint64_t Address, const void *Decoder);
175 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
176 unsigned RegNo, uint64_t Address,
177 const void *Decoder);
179 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
186 uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
188 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
197 const void *Decoder);
198 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
205 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
210 const void *Decoder);
211 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
316 uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
318 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
320 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
322 uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
324 uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
328 const void *Decoder);
330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void* Decoder);
356 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void* Decoder);
358 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
398 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
399 uint64_t Address, const void *Decoder);
400 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
401 uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
404 uint64_t Address, const void *Decoder);
405 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
406 uint64_t Address, const void *Decoder);
407 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
408 uint64_t Address, const void *Decoder);
410 #include "ARMGenDisassemblerTables.inc"
412 static MCDisassembler *createARMDisassembler(const Target &T,
413 const MCSubtargetInfo &STI,
415 return new ARMDisassembler(STI, Ctx);
418 static MCDisassembler *createThumbDisassembler(const Target &T,
419 const MCSubtargetInfo &STI,
421 return new ThumbDisassembler(STI, Ctx);
424 // Post-decoding checks
425 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
426 uint64_t Address, raw_ostream &OS,
429 DecodeStatus Result) {
430 switch (MI.getOpcode()) {
432 // HVC is undefined if condition = 0xf otherwise upredictable
433 // if condition != 0xe
434 uint32_t Cond = (Insn >> 28) & 0xF;
436 return MCDisassembler::Fail;
438 return MCDisassembler::SoftFail;
441 default: return Result;
445 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
446 ArrayRef<uint8_t> Bytes,
447 uint64_t Address, raw_ostream &OS,
448 raw_ostream &CS) const {
451 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
452 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
455 // We want to read exactly 4 bytes of data.
456 if (Bytes.size() < 4) {
458 return MCDisassembler::Fail;
461 // Encoded as a small-endian 32-bit word in the stream.
463 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
465 // Calling the auto-generated decoder function.
466 DecodeStatus Result =
467 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
468 if (Result != MCDisassembler::Fail) {
470 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
478 const DecodeTable Tables[] = {
479 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
480 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
481 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
482 {DecoderTablev8Crypto32, false},
485 for (auto Table : Tables) {
486 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
487 if (Result != MCDisassembler::Fail) {
489 // Add a fake predicate operand, because we share these instruction
490 // definitions with Thumb2 where these instructions are predicable.
491 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
492 return MCDisassembler::Fail;
498 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
499 if (Result != MCDisassembler::Fail) {
501 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
505 return MCDisassembler::Fail;
510 extern const MCInstrDesc ARMInsts[];
512 } // end namespace llvm
514 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
515 /// immediate Value in the MCInst. The immediate Value has had any PC
516 /// adjustment made by the caller. If the instruction is a branch instruction
517 /// then isBranch is true, else false. If the getOpInfo() function was set as
518 /// part of the setupForSymbolicDisassembly() call then that function is called
519 /// to get any symbolic information at the Address for this instruction. If
520 /// that returns non-zero then the symbolic information it returns is used to
521 /// create an MCExpr and that is added as an operand to the MCInst. If
522 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
523 /// Value is done and if a symbol is found an MCExpr is created with that, else
524 /// an MCExpr with Value is created. This function returns true if it adds an
525 /// operand to the MCInst and false otherwise.
526 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
527 bool isBranch, uint64_t InstSize,
528 MCInst &MI, const void *Decoder) {
529 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
530 // FIXME: Does it make sense for value to be negative?
531 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
532 /* Offset */ 0, InstSize);
535 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
536 /// referenced by a load instruction with the base register that is the Pc.
537 /// These can often be values in a literal pool near the Address of the
538 /// instruction. The Address of the instruction and its immediate Value are
539 /// used as a possible literal pool entry. The SymbolLookUp call back will
540 /// return the name of a symbol referenced by the literal pool's entry if
541 /// the referenced address is that of a symbol. Or it will return a pointer to
542 /// a literal 'C' string if the referenced address of the literal pool's entry
543 /// is an address into a section with 'C' string literals.
544 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
545 const void *Decoder) {
546 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
547 Dis->tryAddingPcLoadReferenceComment(Value, Address);
550 // Thumb1 instructions don't have explicit S bits. Rather, they
551 // implicitly set CPSR. Since it's not represented in the encoding, the
552 // auto-generated decoder won't inject the CPSR operand. We need to fix
553 // that as a post-pass.
554 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
555 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
556 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
557 MCInst::iterator I = MI.begin();
558 for (unsigned i = 0; i < NumOps; ++i, ++I) {
559 if (I == MI.end()) break;
560 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
561 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
562 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
567 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
570 // Most Thumb instructions don't have explicit predicates in the
571 // encoding, but rather get their predicates from IT context. We need
572 // to fix up the predicate operands using this context information as a
574 MCDisassembler::DecodeStatus
575 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
576 MCDisassembler::DecodeStatus S = Success;
578 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
580 // A few instructions actually have predicates encoded in them. Don't
581 // try to overwrite it if we're seeing one of those.
582 switch (MI.getOpcode()) {
593 // Some instructions (mostly conditional branches) are not
594 // allowed in IT blocks.
595 if (ITBlock.instrInITBlock())
601 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
608 // Some instructions (mostly unconditional branches) can
609 // only appears at the end of, or outside of, an IT.
610 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
617 // If we're in an IT block, base the predicate on that. Otherwise,
618 // assume a predicate of AL.
620 CC = ITBlock.getITCC();
623 if (ITBlock.instrInITBlock())
624 ITBlock.advanceITState();
626 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
627 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
628 MCInst::iterator I = MI.begin();
629 for (unsigned i = 0; i < NumOps; ++i, ++I) {
630 if (I == MI.end()) break;
631 if (OpInfo[i].isPredicate()) {
632 I = MI.insert(I, MCOperand::createImm(CC));
635 MI.insert(I, MCOperand::createReg(0));
637 MI.insert(I, MCOperand::createReg(ARM::CPSR));
642 I = MI.insert(I, MCOperand::createImm(CC));
645 MI.insert(I, MCOperand::createReg(0));
647 MI.insert(I, MCOperand::createReg(ARM::CPSR));
652 // Thumb VFP instructions are a special case. Because we share their
653 // encodings between ARM and Thumb modes, and they are predicable in ARM
654 // mode, the auto-generated decoder will give them an (incorrect)
655 // predicate operand. We need to rewrite these operands based on the IT
656 // context as a post-pass.
657 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
659 CC = ITBlock.getITCC();
660 if (ITBlock.instrInITBlock())
661 ITBlock.advanceITState();
663 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
664 MCInst::iterator I = MI.begin();
665 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
666 for (unsigned i = 0; i < NumOps; ++i, ++I) {
667 if (OpInfo[i].isPredicate() ) {
673 I->setReg(ARM::CPSR);
679 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
680 ArrayRef<uint8_t> Bytes,
683 raw_ostream &CS) const {
686 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
687 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
689 // We want to read exactly 2 bytes of data.
690 if (Bytes.size() < 2) {
692 return MCDisassembler::Fail;
695 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
696 DecodeStatus Result =
697 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
698 if (Result != MCDisassembler::Fail) {
700 Check(Result, AddThumbPredicate(MI));
704 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
708 bool InITBlock = ITBlock.instrInITBlock();
709 Check(Result, AddThumbPredicate(MI));
710 AddThumb1SBit(MI, InITBlock);
715 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
716 if (Result != MCDisassembler::Fail) {
719 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
720 // the Thumb predicate.
721 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
722 Result = MCDisassembler::SoftFail;
724 Check(Result, AddThumbPredicate(MI));
726 // If we find an IT instruction, we need to parse its condition
727 // code and mask operands so that we can apply them correctly
728 // to the subsequent instructions.
729 if (MI.getOpcode() == ARM::t2IT) {
731 unsigned Firstcond = MI.getOperand(0).getImm();
732 unsigned Mask = MI.getOperand(1).getImm();
733 ITBlock.setITState(Firstcond, Mask);
739 // We want to read exactly 4 bytes of data.
740 if (Bytes.size() < 4) {
742 return MCDisassembler::Fail;
746 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
748 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
749 if (Result != MCDisassembler::Fail) {
751 bool InITBlock = ITBlock.instrInITBlock();
752 Check(Result, AddThumbPredicate(MI));
753 AddThumb1SBit(MI, InITBlock);
758 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
759 if (Result != MCDisassembler::Fail) {
761 Check(Result, AddThumbPredicate(MI));
765 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
767 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
768 if (Result != MCDisassembler::Fail) {
770 UpdateThumbVFPPredicate(MI);
776 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
777 if (Result != MCDisassembler::Fail) {
782 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
783 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
785 if (Result != MCDisassembler::Fail) {
787 Check(Result, AddThumbPredicate(MI));
792 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
793 uint32_t NEONLdStInsn = Insn32;
794 NEONLdStInsn &= 0xF0FFFFFF;
795 NEONLdStInsn |= 0x04000000;
796 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
798 if (Result != MCDisassembler::Fail) {
800 Check(Result, AddThumbPredicate(MI));
805 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
806 uint32_t NEONDataInsn = Insn32;
807 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
808 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
809 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
810 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
812 if (Result != MCDisassembler::Fail) {
814 Check(Result, AddThumbPredicate(MI));
818 uint32_t NEONCryptoInsn = Insn32;
819 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
820 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
821 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
822 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
824 if (Result != MCDisassembler::Fail) {
829 uint32_t NEONv8Insn = Insn32;
830 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
831 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
833 if (Result != MCDisassembler::Fail) {
840 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
841 if (Result != MCDisassembler::Fail) {
843 Check(Result, AddThumbPredicate(MI));
848 return MCDisassembler::Fail;
851 extern "C" void LLVMInitializeARMDisassembler() {
852 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
853 createARMDisassembler);
854 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
855 createARMDisassembler);
856 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
857 createThumbDisassembler);
858 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
859 createThumbDisassembler);
862 static const uint16_t GPRDecoderTable[] = {
863 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
864 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
865 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
866 ARM::R12, ARM::SP, ARM::LR, ARM::PC
869 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
870 uint64_t Address, const void *Decoder) {
872 return MCDisassembler::Fail;
874 unsigned Register = GPRDecoderTable[RegNo];
875 Inst.addOperand(MCOperand::createReg(Register));
876 return MCDisassembler::Success;
880 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
881 uint64_t Address, const void *Decoder) {
882 DecodeStatus S = MCDisassembler::Success;
885 S = MCDisassembler::SoftFail;
887 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
893 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
894 uint64_t Address, const void *Decoder) {
895 DecodeStatus S = MCDisassembler::Success;
899 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
900 return MCDisassembler::Success;
903 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
907 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
908 uint64_t Address, const void *Decoder) {
910 return MCDisassembler::Fail;
911 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
914 static const uint16_t GPRPairDecoderTable[] = {
915 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
916 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
919 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
920 uint64_t Address, const void *Decoder) {
921 DecodeStatus S = MCDisassembler::Success;
924 return MCDisassembler::Fail;
926 if ((RegNo & 1) || RegNo == 0xe)
927 S = MCDisassembler::SoftFail;
929 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
930 Inst.addOperand(MCOperand::createReg(RegisterPair));
934 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
935 uint64_t Address, const void *Decoder) {
936 unsigned Register = 0;
957 return MCDisassembler::Fail;
960 Inst.addOperand(MCOperand::createReg(Register));
961 return MCDisassembler::Success;
964 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
965 uint64_t Address, const void *Decoder) {
966 DecodeStatus S = MCDisassembler::Success;
968 const FeatureBitset &featureBits =
969 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
971 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
972 S = MCDisassembler::SoftFail;
974 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
978 static const uint16_t SPRDecoderTable[] = {
979 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
980 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
981 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
982 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
983 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
984 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
985 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
986 ARM::S28, ARM::S29, ARM::S30, ARM::S31
989 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
990 uint64_t Address, const void *Decoder) {
992 return MCDisassembler::Fail;
994 unsigned Register = SPRDecoderTable[RegNo];
995 Inst.addOperand(MCOperand::createReg(Register));
996 return MCDisassembler::Success;
999 static const uint16_t DPRDecoderTable[] = {
1000 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1001 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1002 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1003 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1004 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1005 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1006 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1007 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1010 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1011 uint64_t Address, const void *Decoder) {
1012 const FeatureBitset &featureBits =
1013 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1015 bool hasD16 = featureBits[ARM::FeatureD16];
1017 if (RegNo > 31 || (hasD16 && RegNo > 15))
1018 return MCDisassembler::Fail;
1020 unsigned Register = DPRDecoderTable[RegNo];
1021 Inst.addOperand(MCOperand::createReg(Register));
1022 return MCDisassembler::Success;
1025 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1026 uint64_t Address, const void *Decoder) {
1028 return MCDisassembler::Fail;
1029 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1033 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1034 uint64_t Address, const void *Decoder) {
1036 return MCDisassembler::Fail;
1037 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1040 static const uint16_t QPRDecoderTable[] = {
1041 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1042 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1043 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1044 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1047 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1048 uint64_t Address, const void *Decoder) {
1049 if (RegNo > 31 || (RegNo & 1) != 0)
1050 return MCDisassembler::Fail;
1053 unsigned Register = QPRDecoderTable[RegNo];
1054 Inst.addOperand(MCOperand::createReg(Register));
1055 return MCDisassembler::Success;
1058 static const uint16_t DPairDecoderTable[] = {
1059 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1060 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1061 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1062 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1063 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1067 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1068 uint64_t Address, const void *Decoder) {
1070 return MCDisassembler::Fail;
1072 unsigned Register = DPairDecoderTable[RegNo];
1073 Inst.addOperand(MCOperand::createReg(Register));
1074 return MCDisassembler::Success;
1077 static const uint16_t DPairSpacedDecoderTable[] = {
1078 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1079 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1080 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1081 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1082 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1083 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1084 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1085 ARM::D28_D30, ARM::D29_D31
1088 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1091 const void *Decoder) {
1093 return MCDisassembler::Fail;
1095 unsigned Register = DPairSpacedDecoderTable[RegNo];
1096 Inst.addOperand(MCOperand::createReg(Register));
1097 return MCDisassembler::Success;
1100 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1101 uint64_t Address, const void *Decoder) {
1102 if (Val == 0xF) return MCDisassembler::Fail;
1103 // AL predicate is not allowed on Thumb1 branches.
1104 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1105 return MCDisassembler::Fail;
1106 Inst.addOperand(MCOperand::createImm(Val));
1107 if (Val == ARMCC::AL) {
1108 Inst.addOperand(MCOperand::createReg(0));
1110 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1111 return MCDisassembler::Success;
1114 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1115 uint64_t Address, const void *Decoder) {
1117 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1119 Inst.addOperand(MCOperand::createReg(0));
1120 return MCDisassembler::Success;
1123 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1124 uint64_t Address, const void *Decoder) {
1125 DecodeStatus S = MCDisassembler::Success;
1127 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1128 unsigned type = fieldFromInstruction(Val, 5, 2);
1129 unsigned imm = fieldFromInstruction(Val, 7, 5);
1131 // Register-immediate
1132 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1133 return MCDisassembler::Fail;
1135 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1138 Shift = ARM_AM::lsl;
1141 Shift = ARM_AM::lsr;
1144 Shift = ARM_AM::asr;
1147 Shift = ARM_AM::ror;
1151 if (Shift == ARM_AM::ror && imm == 0)
1152 Shift = ARM_AM::rrx;
1154 unsigned Op = Shift | (imm << 3);
1155 Inst.addOperand(MCOperand::createImm(Op));
1160 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1161 uint64_t Address, const void *Decoder) {
1162 DecodeStatus S = MCDisassembler::Success;
1164 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1165 unsigned type = fieldFromInstruction(Val, 5, 2);
1166 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1168 // Register-register
1169 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1170 return MCDisassembler::Fail;
1171 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1172 return MCDisassembler::Fail;
1174 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1177 Shift = ARM_AM::lsl;
1180 Shift = ARM_AM::lsr;
1183 Shift = ARM_AM::asr;
1186 Shift = ARM_AM::ror;
1190 Inst.addOperand(MCOperand::createImm(Shift));
1195 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1196 uint64_t Address, const void *Decoder) {
1197 DecodeStatus S = MCDisassembler::Success;
1199 bool NeedDisjointWriteback = false;
1200 unsigned WritebackReg = 0;
1201 switch (Inst.getOpcode()) {
1204 case ARM::LDMIA_UPD:
1205 case ARM::LDMDB_UPD:
1206 case ARM::LDMIB_UPD:
1207 case ARM::LDMDA_UPD:
1208 case ARM::t2LDMIA_UPD:
1209 case ARM::t2LDMDB_UPD:
1210 case ARM::t2STMIA_UPD:
1211 case ARM::t2STMDB_UPD:
1212 NeedDisjointWriteback = true;
1213 WritebackReg = Inst.getOperand(0).getReg();
1217 // Empty register lists are not allowed.
1218 if (Val == 0) return MCDisassembler::Fail;
1219 for (unsigned i = 0; i < 16; ++i) {
1220 if (Val & (1 << i)) {
1221 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1222 return MCDisassembler::Fail;
1223 // Writeback not allowed if Rn is in the target list.
1224 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1225 Check(S, MCDisassembler::SoftFail);
1232 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1233 uint64_t Address, const void *Decoder) {
1234 DecodeStatus S = MCDisassembler::Success;
1236 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1237 unsigned regs = fieldFromInstruction(Val, 0, 8);
1239 // In case of unpredictable encoding, tweak the operands.
1240 if (regs == 0 || (Vd + regs) > 32) {
1241 regs = Vd + regs > 32 ? 32 - Vd : regs;
1242 regs = std::max( 1u, regs);
1243 S = MCDisassembler::SoftFail;
1246 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1247 return MCDisassembler::Fail;
1248 for (unsigned i = 0; i < (regs - 1); ++i) {
1249 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1250 return MCDisassembler::Fail;
1256 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1257 uint64_t Address, const void *Decoder) {
1258 DecodeStatus S = MCDisassembler::Success;
1260 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1261 unsigned regs = fieldFromInstruction(Val, 1, 7);
1263 // In case of unpredictable encoding, tweak the operands.
1264 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1265 regs = Vd + regs > 32 ? 32 - Vd : regs;
1266 regs = std::max( 1u, regs);
1267 regs = std::min(16u, regs);
1268 S = MCDisassembler::SoftFail;
1271 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1272 return MCDisassembler::Fail;
1273 for (unsigned i = 0; i < (regs - 1); ++i) {
1274 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1275 return MCDisassembler::Fail;
1281 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1282 uint64_t Address, const void *Decoder) {
1283 // This operand encodes a mask of contiguous zeros between a specified MSB
1284 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1285 // the mask of all bits LSB-and-lower, and then xor them to create
1286 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1287 // create the final mask.
1288 unsigned msb = fieldFromInstruction(Val, 5, 5);
1289 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1291 DecodeStatus S = MCDisassembler::Success;
1293 Check(S, MCDisassembler::SoftFail);
1294 // The check above will cause the warning for the "potentially undefined
1295 // instruction encoding" but we can't build a bad MCOperand value here
1296 // with a lsb > msb or else printing the MCInst will cause a crash.
1300 uint32_t msb_mask = 0xFFFFFFFF;
1301 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1302 uint32_t lsb_mask = (1U << lsb) - 1;
1304 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1308 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1309 uint64_t Address, const void *Decoder) {
1310 DecodeStatus S = MCDisassembler::Success;
1312 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1313 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1314 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1315 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1316 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1317 unsigned U = fieldFromInstruction(Insn, 23, 1);
1319 switch (Inst.getOpcode()) {
1320 case ARM::LDC_OFFSET:
1323 case ARM::LDC_OPTION:
1324 case ARM::LDCL_OFFSET:
1326 case ARM::LDCL_POST:
1327 case ARM::LDCL_OPTION:
1328 case ARM::STC_OFFSET:
1331 case ARM::STC_OPTION:
1332 case ARM::STCL_OFFSET:
1334 case ARM::STCL_POST:
1335 case ARM::STCL_OPTION:
1336 case ARM::t2LDC_OFFSET:
1337 case ARM::t2LDC_PRE:
1338 case ARM::t2LDC_POST:
1339 case ARM::t2LDC_OPTION:
1340 case ARM::t2LDCL_OFFSET:
1341 case ARM::t2LDCL_PRE:
1342 case ARM::t2LDCL_POST:
1343 case ARM::t2LDCL_OPTION:
1344 case ARM::t2STC_OFFSET:
1345 case ARM::t2STC_PRE:
1346 case ARM::t2STC_POST:
1347 case ARM::t2STC_OPTION:
1348 case ARM::t2STCL_OFFSET:
1349 case ARM::t2STCL_PRE:
1350 case ARM::t2STCL_POST:
1351 case ARM::t2STCL_OPTION:
1352 if (coproc == 0xA || coproc == 0xB)
1353 return MCDisassembler::Fail;
1359 const FeatureBitset &featureBits =
1360 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1361 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1362 return MCDisassembler::Fail;
1364 Inst.addOperand(MCOperand::createImm(coproc));
1365 Inst.addOperand(MCOperand::createImm(CRd));
1366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1367 return MCDisassembler::Fail;
1369 switch (Inst.getOpcode()) {
1370 case ARM::t2LDC2_OFFSET:
1371 case ARM::t2LDC2L_OFFSET:
1372 case ARM::t2LDC2_PRE:
1373 case ARM::t2LDC2L_PRE:
1374 case ARM::t2STC2_OFFSET:
1375 case ARM::t2STC2L_OFFSET:
1376 case ARM::t2STC2_PRE:
1377 case ARM::t2STC2L_PRE:
1378 case ARM::LDC2_OFFSET:
1379 case ARM::LDC2L_OFFSET:
1381 case ARM::LDC2L_PRE:
1382 case ARM::STC2_OFFSET:
1383 case ARM::STC2L_OFFSET:
1385 case ARM::STC2L_PRE:
1386 case ARM::t2LDC_OFFSET:
1387 case ARM::t2LDCL_OFFSET:
1388 case ARM::t2LDC_PRE:
1389 case ARM::t2LDCL_PRE:
1390 case ARM::t2STC_OFFSET:
1391 case ARM::t2STCL_OFFSET:
1392 case ARM::t2STC_PRE:
1393 case ARM::t2STCL_PRE:
1394 case ARM::LDC_OFFSET:
1395 case ARM::LDCL_OFFSET:
1398 case ARM::STC_OFFSET:
1399 case ARM::STCL_OFFSET:
1402 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1403 Inst.addOperand(MCOperand::createImm(imm));
1405 case ARM::t2LDC2_POST:
1406 case ARM::t2LDC2L_POST:
1407 case ARM::t2STC2_POST:
1408 case ARM::t2STC2L_POST:
1409 case ARM::LDC2_POST:
1410 case ARM::LDC2L_POST:
1411 case ARM::STC2_POST:
1412 case ARM::STC2L_POST:
1413 case ARM::t2LDC_POST:
1414 case ARM::t2LDCL_POST:
1415 case ARM::t2STC_POST:
1416 case ARM::t2STCL_POST:
1418 case ARM::LDCL_POST:
1420 case ARM::STCL_POST:
1424 // The 'option' variant doesn't encode 'U' in the immediate since
1425 // the immediate is unsigned [0,255].
1426 Inst.addOperand(MCOperand::createImm(imm));
1430 switch (Inst.getOpcode()) {
1431 case ARM::LDC_OFFSET:
1434 case ARM::LDC_OPTION:
1435 case ARM::LDCL_OFFSET:
1437 case ARM::LDCL_POST:
1438 case ARM::LDCL_OPTION:
1439 case ARM::STC_OFFSET:
1442 case ARM::STC_OPTION:
1443 case ARM::STCL_OFFSET:
1445 case ARM::STCL_POST:
1446 case ARM::STCL_OPTION:
1447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1448 return MCDisassembler::Fail;
1458 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1459 uint64_t Address, const void *Decoder) {
1460 DecodeStatus S = MCDisassembler::Success;
1462 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1463 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1464 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1465 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1466 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1467 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1468 unsigned P = fieldFromInstruction(Insn, 24, 1);
1469 unsigned W = fieldFromInstruction(Insn, 21, 1);
1471 // On stores, the writeback operand precedes Rt.
1472 switch (Inst.getOpcode()) {
1473 case ARM::STR_POST_IMM:
1474 case ARM::STR_POST_REG:
1475 case ARM::STRB_POST_IMM:
1476 case ARM::STRB_POST_REG:
1477 case ARM::STRT_POST_REG:
1478 case ARM::STRT_POST_IMM:
1479 case ARM::STRBT_POST_REG:
1480 case ARM::STRBT_POST_IMM:
1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1482 return MCDisassembler::Fail;
1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1489 return MCDisassembler::Fail;
1491 // On loads, the writeback operand comes after Rt.
1492 switch (Inst.getOpcode()) {
1493 case ARM::LDR_POST_IMM:
1494 case ARM::LDR_POST_REG:
1495 case ARM::LDRB_POST_IMM:
1496 case ARM::LDRB_POST_REG:
1497 case ARM::LDRBT_POST_REG:
1498 case ARM::LDRBT_POST_IMM:
1499 case ARM::LDRT_POST_REG:
1500 case ARM::LDRT_POST_IMM:
1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1502 return MCDisassembler::Fail;
1508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1509 return MCDisassembler::Fail;
1511 ARM_AM::AddrOpc Op = ARM_AM::add;
1512 if (!fieldFromInstruction(Insn, 23, 1))
1515 bool writeback = (P == 0) || (W == 1);
1516 unsigned idx_mode = 0;
1518 idx_mode = ARMII::IndexModePre;
1519 else if (!P && writeback)
1520 idx_mode = ARMII::IndexModePost;
1522 if (writeback && (Rn == 15 || Rn == Rt))
1523 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1526 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1527 return MCDisassembler::Fail;
1528 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1529 switch( fieldFromInstruction(Insn, 5, 2)) {
1543 return MCDisassembler::Fail;
1545 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1546 if (Opc == ARM_AM::ror && amt == 0)
1548 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1550 Inst.addOperand(MCOperand::createImm(imm));
1552 Inst.addOperand(MCOperand::createReg(0));
1553 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1554 Inst.addOperand(MCOperand::createImm(tmp));
1557 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1558 return MCDisassembler::Fail;
1563 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1564 uint64_t Address, const void *Decoder) {
1565 DecodeStatus S = MCDisassembler::Success;
1567 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1568 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1569 unsigned type = fieldFromInstruction(Val, 5, 2);
1570 unsigned imm = fieldFromInstruction(Val, 7, 5);
1571 unsigned U = fieldFromInstruction(Val, 12, 1);
1573 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1589 if (ShOp == ARM_AM::ror && imm == 0)
1592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1593 return MCDisassembler::Fail;
1594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1595 return MCDisassembler::Fail;
1598 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1600 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1601 Inst.addOperand(MCOperand::createImm(shift));
1607 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1608 uint64_t Address, const void *Decoder) {
1609 DecodeStatus S = MCDisassembler::Success;
1611 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1612 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1613 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1614 unsigned type = fieldFromInstruction(Insn, 22, 1);
1615 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1616 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1617 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1618 unsigned W = fieldFromInstruction(Insn, 21, 1);
1619 unsigned P = fieldFromInstruction(Insn, 24, 1);
1620 unsigned Rt2 = Rt + 1;
1622 bool writeback = (W == 1) | (P == 0);
1624 // For {LD,ST}RD, Rt must be even, else undefined.
1625 switch (Inst.getOpcode()) {
1628 case ARM::STRD_POST:
1631 case ARM::LDRD_POST:
1632 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1637 switch (Inst.getOpcode()) {
1640 case ARM::STRD_POST:
1641 if (P == 0 && W == 1)
1642 S = MCDisassembler::SoftFail;
1644 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1645 S = MCDisassembler::SoftFail;
1646 if (type && Rm == 15)
1647 S = MCDisassembler::SoftFail;
1649 S = MCDisassembler::SoftFail;
1650 if (!type && fieldFromInstruction(Insn, 8, 4))
1651 S = MCDisassembler::SoftFail;
1655 case ARM::STRH_POST:
1657 S = MCDisassembler::SoftFail;
1658 if (writeback && (Rn == 15 || Rn == Rt))
1659 S = MCDisassembler::SoftFail;
1660 if (!type && Rm == 15)
1661 S = MCDisassembler::SoftFail;
1665 case ARM::LDRD_POST:
1666 if (type && Rn == 15) {
1668 S = MCDisassembler::SoftFail;
1671 if (P == 0 && W == 1)
1672 S = MCDisassembler::SoftFail;
1673 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1674 S = MCDisassembler::SoftFail;
1675 if (!type && writeback && Rn == 15)
1676 S = MCDisassembler::SoftFail;
1677 if (writeback && (Rn == Rt || Rn == Rt2))
1678 S = MCDisassembler::SoftFail;
1682 case ARM::LDRH_POST:
1683 if (type && Rn == 15) {
1685 S = MCDisassembler::SoftFail;
1689 S = MCDisassembler::SoftFail;
1690 if (!type && Rm == 15)
1691 S = MCDisassembler::SoftFail;
1692 if (!type && writeback && (Rn == 15 || Rn == Rt))
1693 S = MCDisassembler::SoftFail;
1696 case ARM::LDRSH_PRE:
1697 case ARM::LDRSH_POST:
1699 case ARM::LDRSB_PRE:
1700 case ARM::LDRSB_POST:
1701 if (type && Rn == 15) {
1703 S = MCDisassembler::SoftFail;
1706 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1707 S = MCDisassembler::SoftFail;
1708 if (!type && (Rt == 15 || Rm == 15))
1709 S = MCDisassembler::SoftFail;
1710 if (!type && writeback && (Rn == 15 || Rn == Rt))
1711 S = MCDisassembler::SoftFail;
1717 if (writeback) { // Writeback
1719 U |= ARMII::IndexModePre << 9;
1721 U |= ARMII::IndexModePost << 9;
1723 // On stores, the writeback operand precedes Rt.
1724 switch (Inst.getOpcode()) {
1727 case ARM::STRD_POST:
1730 case ARM::STRH_POST:
1731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1732 return MCDisassembler::Fail;
1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1740 return MCDisassembler::Fail;
1741 switch (Inst.getOpcode()) {
1744 case ARM::STRD_POST:
1747 case ARM::LDRD_POST:
1748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1749 return MCDisassembler::Fail;
1756 // On loads, the writeback operand comes after Rt.
1757 switch (Inst.getOpcode()) {
1760 case ARM::LDRD_POST:
1763 case ARM::LDRH_POST:
1765 case ARM::LDRSH_PRE:
1766 case ARM::LDRSH_POST:
1768 case ARM::LDRSB_PRE:
1769 case ARM::LDRSB_POST:
1772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1773 return MCDisassembler::Fail;
1780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1781 return MCDisassembler::Fail;
1784 Inst.addOperand(MCOperand::createReg(0));
1785 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1788 return MCDisassembler::Fail;
1789 Inst.addOperand(MCOperand::createImm(U));
1792 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1793 return MCDisassembler::Fail;
1798 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1799 uint64_t Address, const void *Decoder) {
1800 DecodeStatus S = MCDisassembler::Success;
1802 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1803 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1820 Inst.addOperand(MCOperand::createImm(mode));
1821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1822 return MCDisassembler::Fail;
1827 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1828 uint64_t Address, const void *Decoder) {
1829 DecodeStatus S = MCDisassembler::Success;
1831 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1832 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1833 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1834 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1837 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1839 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1840 return MCDisassembler::Fail;
1841 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1842 return MCDisassembler::Fail;
1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1844 return MCDisassembler::Fail;
1845 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1846 return MCDisassembler::Fail;
1850 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1852 uint64_t Address, const void *Decoder) {
1853 DecodeStatus S = MCDisassembler::Success;
1855 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1856 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1857 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1860 // Ambiguous with RFE and SRS
1861 switch (Inst.getOpcode()) {
1863 Inst.setOpcode(ARM::RFEDA);
1865 case ARM::LDMDA_UPD:
1866 Inst.setOpcode(ARM::RFEDA_UPD);
1869 Inst.setOpcode(ARM::RFEDB);
1871 case ARM::LDMDB_UPD:
1872 Inst.setOpcode(ARM::RFEDB_UPD);
1875 Inst.setOpcode(ARM::RFEIA);
1877 case ARM::LDMIA_UPD:
1878 Inst.setOpcode(ARM::RFEIA_UPD);
1881 Inst.setOpcode(ARM::RFEIB);
1883 case ARM::LDMIB_UPD:
1884 Inst.setOpcode(ARM::RFEIB_UPD);
1887 Inst.setOpcode(ARM::SRSDA);
1889 case ARM::STMDA_UPD:
1890 Inst.setOpcode(ARM::SRSDA_UPD);
1893 Inst.setOpcode(ARM::SRSDB);
1895 case ARM::STMDB_UPD:
1896 Inst.setOpcode(ARM::SRSDB_UPD);
1899 Inst.setOpcode(ARM::SRSIA);
1901 case ARM::STMIA_UPD:
1902 Inst.setOpcode(ARM::SRSIA_UPD);
1905 Inst.setOpcode(ARM::SRSIB);
1907 case ARM::STMIB_UPD:
1908 Inst.setOpcode(ARM::SRSIB_UPD);
1911 return MCDisassembler::Fail;
1914 // For stores (which become SRS's, the only operand is the mode.
1915 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1916 // Check SRS encoding constraints
1917 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1918 fieldFromInstruction(Insn, 20, 1) == 0))
1919 return MCDisassembler::Fail;
1922 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1926 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1930 return MCDisassembler::Fail;
1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1932 return MCDisassembler::Fail; // Tied
1933 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1934 return MCDisassembler::Fail;
1935 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1936 return MCDisassembler::Fail;
1941 // Check for UNPREDICTABLE predicated ESB instruction
1942 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1943 uint64_t Address, const void *Decoder) {
1944 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1945 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1946 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1947 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1949 DecodeStatus S = MCDisassembler::Success;
1951 Inst.addOperand(MCOperand::createImm(imm8));
1953 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1954 return MCDisassembler::Fail;
1956 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1957 // so all predicates should be allowed.
1958 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1959 S = MCDisassembler::SoftFail;
1964 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1965 uint64_t Address, const void *Decoder) {
1966 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1967 unsigned M = fieldFromInstruction(Insn, 17, 1);
1968 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1969 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1971 DecodeStatus S = MCDisassembler::Success;
1973 // This decoder is called from multiple location that do not check
1974 // the full encoding is valid before they do.
1975 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1976 fieldFromInstruction(Insn, 16, 1) != 0 ||
1977 fieldFromInstruction(Insn, 20, 8) != 0x10)
1978 return MCDisassembler::Fail;
1980 // imod == '01' --> UNPREDICTABLE
1981 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1982 // return failure here. The '01' imod value is unprintable, so there's
1983 // nothing useful we could do even if we returned UNPREDICTABLE.
1985 if (imod == 1) return MCDisassembler::Fail;
1988 Inst.setOpcode(ARM::CPS3p);
1989 Inst.addOperand(MCOperand::createImm(imod));
1990 Inst.addOperand(MCOperand::createImm(iflags));
1991 Inst.addOperand(MCOperand::createImm(mode));
1992 } else if (imod && !M) {
1993 Inst.setOpcode(ARM::CPS2p);
1994 Inst.addOperand(MCOperand::createImm(imod));
1995 Inst.addOperand(MCOperand::createImm(iflags));
1996 if (mode) S = MCDisassembler::SoftFail;
1997 } else if (!imod && M) {
1998 Inst.setOpcode(ARM::CPS1p);
1999 Inst.addOperand(MCOperand::createImm(mode));
2000 if (iflags) S = MCDisassembler::SoftFail;
2002 // imod == '00' && M == '0' --> UNPREDICTABLE
2003 Inst.setOpcode(ARM::CPS1p);
2004 Inst.addOperand(MCOperand::createImm(mode));
2005 S = MCDisassembler::SoftFail;
2011 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2012 uint64_t Address, const void *Decoder) {
2013 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2014 unsigned M = fieldFromInstruction(Insn, 8, 1);
2015 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2016 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2018 DecodeStatus S = MCDisassembler::Success;
2020 // imod == '01' --> UNPREDICTABLE
2021 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2022 // return failure here. The '01' imod value is unprintable, so there's
2023 // nothing useful we could do even if we returned UNPREDICTABLE.
2025 if (imod == 1) return MCDisassembler::Fail;
2028 Inst.setOpcode(ARM::t2CPS3p);
2029 Inst.addOperand(MCOperand::createImm(imod));
2030 Inst.addOperand(MCOperand::createImm(iflags));
2031 Inst.addOperand(MCOperand::createImm(mode));
2032 } else if (imod && !M) {
2033 Inst.setOpcode(ARM::t2CPS2p);
2034 Inst.addOperand(MCOperand::createImm(imod));
2035 Inst.addOperand(MCOperand::createImm(iflags));
2036 if (mode) S = MCDisassembler::SoftFail;
2037 } else if (!imod && M) {
2038 Inst.setOpcode(ARM::t2CPS1p);
2039 Inst.addOperand(MCOperand::createImm(mode));
2040 if (iflags) S = MCDisassembler::SoftFail;
2042 // imod == '00' && M == '0' --> this is a HINT instruction
2043 int imm = fieldFromInstruction(Insn, 0, 8);
2044 // HINT are defined only for immediate in [0..4]
2045 if(imm > 4) return MCDisassembler::Fail;
2046 Inst.setOpcode(ARM::t2HINT);
2047 Inst.addOperand(MCOperand::createImm(imm));
2053 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2054 uint64_t Address, const void *Decoder) {
2055 DecodeStatus S = MCDisassembler::Success;
2057 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2060 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2061 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2062 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2063 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2065 if (Inst.getOpcode() == ARM::t2MOVTi16)
2066 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2067 return MCDisassembler::Fail;
2068 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2069 return MCDisassembler::Fail;
2071 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2072 Inst.addOperand(MCOperand::createImm(imm));
2077 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2078 uint64_t Address, const void *Decoder) {
2079 DecodeStatus S = MCDisassembler::Success;
2081 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2082 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2085 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2086 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2088 if (Inst.getOpcode() == ARM::MOVTi16)
2089 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2090 return MCDisassembler::Fail;
2092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2093 return MCDisassembler::Fail;
2095 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2096 Inst.addOperand(MCOperand::createImm(imm));
2098 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2099 return MCDisassembler::Fail;
2104 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2105 uint64_t Address, const void *Decoder) {
2106 DecodeStatus S = MCDisassembler::Success;
2108 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2109 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2110 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2111 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2112 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2115 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2118 return MCDisassembler::Fail;
2119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2120 return MCDisassembler::Fail;
2121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2122 return MCDisassembler::Fail;
2123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2124 return MCDisassembler::Fail;
2126 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2127 return MCDisassembler::Fail;
2132 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2133 uint64_t Address, const void *Decoder) {
2134 DecodeStatus S = MCDisassembler::Success;
2136 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2137 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2138 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2141 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2144 return MCDisassembler::Fail;
2145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2146 return MCDisassembler::Fail;
2147 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2148 return MCDisassembler::Fail;
2153 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2154 uint64_t Address, const void *Decoder) {
2155 DecodeStatus S = MCDisassembler::Success;
2157 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2159 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2160 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2162 if (!FeatureBits[ARM::HasV8_1aOps] ||
2163 !FeatureBits[ARM::HasV8Ops])
2164 return MCDisassembler::Fail;
2166 // Decoder can be called from DecodeTST, which does not check the full
2167 // encoding is valid.
2168 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2169 fieldFromInstruction(Insn, 4,4) != 0)
2170 return MCDisassembler::Fail;
2171 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2172 fieldFromInstruction(Insn, 0,4) != 0)
2173 S = MCDisassembler::SoftFail;
2175 Inst.setOpcode(ARM::SETPAN);
2176 Inst.addOperand(MCOperand::createImm(Imm));
2181 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2182 uint64_t Address, const void *Decoder) {
2183 DecodeStatus S = MCDisassembler::Success;
2185 unsigned add = fieldFromInstruction(Val, 12, 1);
2186 unsigned imm = fieldFromInstruction(Val, 0, 12);
2187 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2190 return MCDisassembler::Fail;
2192 if (!add) imm *= -1;
2193 if (imm == 0 && !add) imm = INT32_MIN;
2194 Inst.addOperand(MCOperand::createImm(imm));
2196 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2201 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2202 uint64_t Address, const void *Decoder) {
2203 DecodeStatus S = MCDisassembler::Success;
2205 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2206 // U == 1 to add imm, 0 to subtract it.
2207 unsigned U = fieldFromInstruction(Val, 8, 1);
2208 unsigned imm = fieldFromInstruction(Val, 0, 8);
2210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2211 return MCDisassembler::Fail;
2214 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2216 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2221 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2222 uint64_t Address, const void *Decoder) {
2223 DecodeStatus S = MCDisassembler::Success;
2225 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2226 // U == 1 to add imm, 0 to subtract it.
2227 unsigned U = fieldFromInstruction(Val, 8, 1);
2228 unsigned imm = fieldFromInstruction(Val, 0, 8);
2230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2231 return MCDisassembler::Fail;
2234 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2236 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2241 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2242 uint64_t Address, const void *Decoder) {
2243 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2247 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2248 uint64_t Address, const void *Decoder) {
2249 DecodeStatus Status = MCDisassembler::Success;
2251 // Note the J1 and J2 values are from the encoded instruction. So here
2252 // change them to I1 and I2 values via as documented:
2253 // I1 = NOT(J1 EOR S);
2254 // I2 = NOT(J2 EOR S);
2255 // and build the imm32 with one trailing zero as documented:
2256 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2257 unsigned S = fieldFromInstruction(Insn, 26, 1);
2258 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2259 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2260 unsigned I1 = !(J1 ^ S);
2261 unsigned I2 = !(J2 ^ S);
2262 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2263 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2264 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2265 int imm32 = SignExtend32<25>(tmp << 1);
2266 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2267 true, 4, Inst, Decoder))
2268 Inst.addOperand(MCOperand::createImm(imm32));
2274 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2275 uint64_t Address, const void *Decoder) {
2276 DecodeStatus S = MCDisassembler::Success;
2278 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2279 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2282 Inst.setOpcode(ARM::BLXi);
2283 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2284 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2285 true, 4, Inst, Decoder))
2286 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2290 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2291 true, 4, Inst, Decoder))
2292 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2294 return MCDisassembler::Fail;
2299 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2300 uint64_t Address, const void *Decoder) {
2301 DecodeStatus S = MCDisassembler::Success;
2303 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2304 unsigned align = fieldFromInstruction(Val, 4, 2);
2306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2307 return MCDisassembler::Fail;
2309 Inst.addOperand(MCOperand::createImm(0));
2311 Inst.addOperand(MCOperand::createImm(4 << align));
2316 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2317 uint64_t Address, const void *Decoder) {
2318 DecodeStatus S = MCDisassembler::Success;
2320 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2321 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2322 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2324 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2325 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2327 // First output register
2328 switch (Inst.getOpcode()) {
2329 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2330 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2331 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2332 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2333 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2334 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2335 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2336 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2337 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2338 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2339 return MCDisassembler::Fail;
2344 case ARM::VLD2b16wb_fixed:
2345 case ARM::VLD2b16wb_register:
2346 case ARM::VLD2b32wb_fixed:
2347 case ARM::VLD2b32wb_register:
2348 case ARM::VLD2b8wb_fixed:
2349 case ARM::VLD2b8wb_register:
2350 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2351 return MCDisassembler::Fail;
2354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2355 return MCDisassembler::Fail;
2358 // Second output register
2359 switch (Inst.getOpcode()) {
2363 case ARM::VLD3d8_UPD:
2364 case ARM::VLD3d16_UPD:
2365 case ARM::VLD3d32_UPD:
2369 case ARM::VLD4d8_UPD:
2370 case ARM::VLD4d16_UPD:
2371 case ARM::VLD4d32_UPD:
2372 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2373 return MCDisassembler::Fail;
2378 case ARM::VLD3q8_UPD:
2379 case ARM::VLD3q16_UPD:
2380 case ARM::VLD3q32_UPD:
2384 case ARM::VLD4q8_UPD:
2385 case ARM::VLD4q16_UPD:
2386 case ARM::VLD4q32_UPD:
2387 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2388 return MCDisassembler::Fail;
2393 // Third output register
2394 switch(Inst.getOpcode()) {
2398 case ARM::VLD3d8_UPD:
2399 case ARM::VLD3d16_UPD:
2400 case ARM::VLD3d32_UPD:
2404 case ARM::VLD4d8_UPD:
2405 case ARM::VLD4d16_UPD:
2406 case ARM::VLD4d32_UPD:
2407 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2408 return MCDisassembler::Fail;
2413 case ARM::VLD3q8_UPD:
2414 case ARM::VLD3q16_UPD:
2415 case ARM::VLD3q32_UPD:
2419 case ARM::VLD4q8_UPD:
2420 case ARM::VLD4q16_UPD:
2421 case ARM::VLD4q32_UPD:
2422 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2423 return MCDisassembler::Fail;
2429 // Fourth output register
2430 switch (Inst.getOpcode()) {
2434 case ARM::VLD4d8_UPD:
2435 case ARM::VLD4d16_UPD:
2436 case ARM::VLD4d32_UPD:
2437 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2438 return MCDisassembler::Fail;
2443 case ARM::VLD4q8_UPD:
2444 case ARM::VLD4q16_UPD:
2445 case ARM::VLD4q32_UPD:
2446 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2447 return MCDisassembler::Fail;
2453 // Writeback operand
2454 switch (Inst.getOpcode()) {
2455 case ARM::VLD1d8wb_fixed:
2456 case ARM::VLD1d16wb_fixed:
2457 case ARM::VLD1d32wb_fixed:
2458 case ARM::VLD1d64wb_fixed:
2459 case ARM::VLD1d8wb_register:
2460 case ARM::VLD1d16wb_register:
2461 case ARM::VLD1d32wb_register:
2462 case ARM::VLD1d64wb_register:
2463 case ARM::VLD1q8wb_fixed:
2464 case ARM::VLD1q16wb_fixed:
2465 case ARM::VLD1q32wb_fixed:
2466 case ARM::VLD1q64wb_fixed:
2467 case ARM::VLD1q8wb_register:
2468 case ARM::VLD1q16wb_register:
2469 case ARM::VLD1q32wb_register:
2470 case ARM::VLD1q64wb_register:
2471 case ARM::VLD1d8Twb_fixed:
2472 case ARM::VLD1d8Twb_register:
2473 case ARM::VLD1d16Twb_fixed:
2474 case ARM::VLD1d16Twb_register:
2475 case ARM::VLD1d32Twb_fixed:
2476 case ARM::VLD1d32Twb_register:
2477 case ARM::VLD1d64Twb_fixed:
2478 case ARM::VLD1d64Twb_register:
2479 case ARM::VLD1d8Qwb_fixed:
2480 case ARM::VLD1d8Qwb_register:
2481 case ARM::VLD1d16Qwb_fixed:
2482 case ARM::VLD1d16Qwb_register:
2483 case ARM::VLD1d32Qwb_fixed:
2484 case ARM::VLD1d32Qwb_register:
2485 case ARM::VLD1d64Qwb_fixed:
2486 case ARM::VLD1d64Qwb_register:
2487 case ARM::VLD2d8wb_fixed:
2488 case ARM::VLD2d16wb_fixed:
2489 case ARM::VLD2d32wb_fixed:
2490 case ARM::VLD2q8wb_fixed:
2491 case ARM::VLD2q16wb_fixed:
2492 case ARM::VLD2q32wb_fixed:
2493 case ARM::VLD2d8wb_register:
2494 case ARM::VLD2d16wb_register:
2495 case ARM::VLD2d32wb_register:
2496 case ARM::VLD2q8wb_register:
2497 case ARM::VLD2q16wb_register:
2498 case ARM::VLD2q32wb_register:
2499 case ARM::VLD2b8wb_fixed:
2500 case ARM::VLD2b16wb_fixed:
2501 case ARM::VLD2b32wb_fixed:
2502 case ARM::VLD2b8wb_register:
2503 case ARM::VLD2b16wb_register:
2504 case ARM::VLD2b32wb_register:
2505 Inst.addOperand(MCOperand::createImm(0));
2507 case ARM::VLD3d8_UPD:
2508 case ARM::VLD3d16_UPD:
2509 case ARM::VLD3d32_UPD:
2510 case ARM::VLD3q8_UPD:
2511 case ARM::VLD3q16_UPD:
2512 case ARM::VLD3q32_UPD:
2513 case ARM::VLD4d8_UPD:
2514 case ARM::VLD4d16_UPD:
2515 case ARM::VLD4d32_UPD:
2516 case ARM::VLD4q8_UPD:
2517 case ARM::VLD4q16_UPD:
2518 case ARM::VLD4q32_UPD:
2519 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2520 return MCDisassembler::Fail;
2526 // AddrMode6 Base (register+alignment)
2527 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2528 return MCDisassembler::Fail;
2530 // AddrMode6 Offset (register)
2531 switch (Inst.getOpcode()) {
2533 // The below have been updated to have explicit am6offset split
2534 // between fixed and register offset. For those instructions not
2535 // yet updated, we need to add an additional reg0 operand for the
2538 // The fixed offset encodes as Rm == 0xd, so we check for that.
2540 Inst.addOperand(MCOperand::createReg(0));
2543 // Fall through to handle the register offset variant.
2545 case ARM::VLD1d8wb_fixed:
2546 case ARM::VLD1d16wb_fixed:
2547 case ARM::VLD1d32wb_fixed:
2548 case ARM::VLD1d64wb_fixed:
2549 case ARM::VLD1d8Twb_fixed:
2550 case ARM::VLD1d16Twb_fixed:
2551 case ARM::VLD1d32Twb_fixed:
2552 case ARM::VLD1d64Twb_fixed:
2553 case ARM::VLD1d8Qwb_fixed:
2554 case ARM::VLD1d16Qwb_fixed:
2555 case ARM::VLD1d32Qwb_fixed:
2556 case ARM::VLD1d64Qwb_fixed:
2557 case ARM::VLD1d8wb_register:
2558 case ARM::VLD1d16wb_register:
2559 case ARM::VLD1d32wb_register:
2560 case ARM::VLD1d64wb_register:
2561 case ARM::VLD1q8wb_fixed:
2562 case ARM::VLD1q16wb_fixed:
2563 case ARM::VLD1q32wb_fixed:
2564 case ARM::VLD1q64wb_fixed:
2565 case ARM::VLD1q8wb_register:
2566 case ARM::VLD1q16wb_register:
2567 case ARM::VLD1q32wb_register:
2568 case ARM::VLD1q64wb_register:
2569 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2570 // variant encodes Rm == 0xf. Anything else is a register offset post-
2571 // increment and we need to add the register operand to the instruction.
2572 if (Rm != 0xD && Rm != 0xF &&
2573 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2574 return MCDisassembler::Fail;
2576 case ARM::VLD2d8wb_fixed:
2577 case ARM::VLD2d16wb_fixed:
2578 case ARM::VLD2d32wb_fixed:
2579 case ARM::VLD2b8wb_fixed:
2580 case ARM::VLD2b16wb_fixed:
2581 case ARM::VLD2b32wb_fixed:
2582 case ARM::VLD2q8wb_fixed:
2583 case ARM::VLD2q16wb_fixed:
2584 case ARM::VLD2q32wb_fixed:
2591 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2592 uint64_t Address, const void *Decoder) {
2593 unsigned type = fieldFromInstruction(Insn, 8, 4);
2594 unsigned align = fieldFromInstruction(Insn, 4, 2);
2595 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2596 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2597 if (type == 10 && align == 3) return MCDisassembler::Fail;
2599 unsigned load = fieldFromInstruction(Insn, 21, 1);
2600 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2601 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2604 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2605 uint64_t Address, const void *Decoder) {
2606 unsigned size = fieldFromInstruction(Insn, 6, 2);
2607 if (size == 3) return MCDisassembler::Fail;
2609 unsigned type = fieldFromInstruction(Insn, 8, 4);
2610 unsigned align = fieldFromInstruction(Insn, 4, 2);
2611 if (type == 8 && align == 3) return MCDisassembler::Fail;
2612 if (type == 9 && align == 3) return MCDisassembler::Fail;
2614 unsigned load = fieldFromInstruction(Insn, 21, 1);
2615 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2616 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2619 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2620 uint64_t Address, const void *Decoder) {
2621 unsigned size = fieldFromInstruction(Insn, 6, 2);
2622 if (size == 3) return MCDisassembler::Fail;
2624 unsigned align = fieldFromInstruction(Insn, 4, 2);
2625 if (align & 2) return MCDisassembler::Fail;
2627 unsigned load = fieldFromInstruction(Insn, 21, 1);
2628 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2629 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2632 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2633 uint64_t Address, const void *Decoder) {
2634 unsigned size = fieldFromInstruction(Insn, 6, 2);
2635 if (size == 3) return MCDisassembler::Fail;
2637 unsigned load = fieldFromInstruction(Insn, 21, 1);
2638 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2639 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2642 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2643 uint64_t Address, const void *Decoder) {
2644 DecodeStatus S = MCDisassembler::Success;
2646 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2647 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2648 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2649 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2650 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2651 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2653 // Writeback Operand
2654 switch (Inst.getOpcode()) {
2655 case ARM::VST1d8wb_fixed:
2656 case ARM::VST1d16wb_fixed:
2657 case ARM::VST1d32wb_fixed:
2658 case ARM::VST1d64wb_fixed:
2659 case ARM::VST1d8wb_register:
2660 case ARM::VST1d16wb_register:
2661 case ARM::VST1d32wb_register:
2662 case ARM::VST1d64wb_register:
2663 case ARM::VST1q8wb_fixed:
2664 case ARM::VST1q16wb_fixed:
2665 case ARM::VST1q32wb_fixed:
2666 case ARM::VST1q64wb_fixed:
2667 case ARM::VST1q8wb_register:
2668 case ARM::VST1q16wb_register:
2669 case ARM::VST1q32wb_register:
2670 case ARM::VST1q64wb_register:
2671 case ARM::VST1d8Twb_fixed:
2672 case ARM::VST1d16Twb_fixed:
2673 case ARM::VST1d32Twb_fixed:
2674 case ARM::VST1d64Twb_fixed:
2675 case ARM::VST1d8Twb_register:
2676 case ARM::VST1d16Twb_register:
2677 case ARM::VST1d32Twb_register:
2678 case ARM::VST1d64Twb_register:
2679 case ARM::VST1d8Qwb_fixed:
2680 case ARM::VST1d16Qwb_fixed:
2681 case ARM::VST1d32Qwb_fixed:
2682 case ARM::VST1d64Qwb_fixed:
2683 case ARM::VST1d8Qwb_register:
2684 case ARM::VST1d16Qwb_register:
2685 case ARM::VST1d32Qwb_register:
2686 case ARM::VST1d64Qwb_register:
2687 case ARM::VST2d8wb_fixed:
2688 case ARM::VST2d16wb_fixed:
2689 case ARM::VST2d32wb_fixed:
2690 case ARM::VST2d8wb_register:
2691 case ARM::VST2d16wb_register:
2692 case ARM::VST2d32wb_register:
2693 case ARM::VST2q8wb_fixed:
2694 case ARM::VST2q16wb_fixed:
2695 case ARM::VST2q32wb_fixed:
2696 case ARM::VST2q8wb_register:
2697 case ARM::VST2q16wb_register:
2698 case ARM::VST2q32wb_register:
2699 case ARM::VST2b8wb_fixed:
2700 case ARM::VST2b16wb_fixed:
2701 case ARM::VST2b32wb_fixed:
2702 case ARM::VST2b8wb_register:
2703 case ARM::VST2b16wb_register:
2704 case ARM::VST2b32wb_register:
2706 return MCDisassembler::Fail;
2707 Inst.addOperand(MCOperand::createImm(0));
2709 case ARM::VST3d8_UPD:
2710 case ARM::VST3d16_UPD:
2711 case ARM::VST3d32_UPD:
2712 case ARM::VST3q8_UPD:
2713 case ARM::VST3q16_UPD:
2714 case ARM::VST3q32_UPD:
2715 case ARM::VST4d8_UPD:
2716 case ARM::VST4d16_UPD:
2717 case ARM::VST4d32_UPD:
2718 case ARM::VST4q8_UPD:
2719 case ARM::VST4q16_UPD:
2720 case ARM::VST4q32_UPD:
2721 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2722 return MCDisassembler::Fail;
2728 // AddrMode6 Base (register+alignment)
2729 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2730 return MCDisassembler::Fail;
2732 // AddrMode6 Offset (register)
2733 switch (Inst.getOpcode()) {
2736 Inst.addOperand(MCOperand::createReg(0));
2737 else if (Rm != 0xF) {
2738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2739 return MCDisassembler::Fail;
2742 case ARM::VST1d8wb_fixed:
2743 case ARM::VST1d16wb_fixed:
2744 case ARM::VST1d32wb_fixed:
2745 case ARM::VST1d64wb_fixed:
2746 case ARM::VST1q8wb_fixed:
2747 case ARM::VST1q16wb_fixed:
2748 case ARM::VST1q32wb_fixed:
2749 case ARM::VST1q64wb_fixed:
2750 case ARM::VST1d8Twb_fixed:
2751 case ARM::VST1d16Twb_fixed:
2752 case ARM::VST1d32Twb_fixed:
2753 case ARM::VST1d64Twb_fixed:
2754 case ARM::VST1d8Qwb_fixed:
2755 case ARM::VST1d16Qwb_fixed:
2756 case ARM::VST1d32Qwb_fixed:
2757 case ARM::VST1d64Qwb_fixed:
2758 case ARM::VST2d8wb_fixed:
2759 case ARM::VST2d16wb_fixed:
2760 case ARM::VST2d32wb_fixed:
2761 case ARM::VST2q8wb_fixed:
2762 case ARM::VST2q16wb_fixed:
2763 case ARM::VST2q32wb_fixed:
2764 case ARM::VST2b8wb_fixed:
2765 case ARM::VST2b16wb_fixed:
2766 case ARM::VST2b32wb_fixed:
2770 // First input register
2771 switch (Inst.getOpcode()) {
2776 case ARM::VST1q16wb_fixed:
2777 case ARM::VST1q16wb_register:
2778 case ARM::VST1q32wb_fixed:
2779 case ARM::VST1q32wb_register:
2780 case ARM::VST1q64wb_fixed:
2781 case ARM::VST1q64wb_register:
2782 case ARM::VST1q8wb_fixed:
2783 case ARM::VST1q8wb_register:
2787 case ARM::VST2d16wb_fixed:
2788 case ARM::VST2d16wb_register:
2789 case ARM::VST2d32wb_fixed:
2790 case ARM::VST2d32wb_register:
2791 case ARM::VST2d8wb_fixed:
2792 case ARM::VST2d8wb_register:
2793 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2794 return MCDisassembler::Fail;
2799 case ARM::VST2b16wb_fixed:
2800 case ARM::VST2b16wb_register:
2801 case ARM::VST2b32wb_fixed:
2802 case ARM::VST2b32wb_register:
2803 case ARM::VST2b8wb_fixed:
2804 case ARM::VST2b8wb_register:
2805 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2806 return MCDisassembler::Fail;
2809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2810 return MCDisassembler::Fail;
2813 // Second input register
2814 switch (Inst.getOpcode()) {
2818 case ARM::VST3d8_UPD:
2819 case ARM::VST3d16_UPD:
2820 case ARM::VST3d32_UPD:
2824 case ARM::VST4d8_UPD:
2825 case ARM::VST4d16_UPD:
2826 case ARM::VST4d32_UPD:
2827 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2828 return MCDisassembler::Fail;
2833 case ARM::VST3q8_UPD:
2834 case ARM::VST3q16_UPD:
2835 case ARM::VST3q32_UPD:
2839 case ARM::VST4q8_UPD:
2840 case ARM::VST4q16_UPD:
2841 case ARM::VST4q32_UPD:
2842 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2843 return MCDisassembler::Fail;
2849 // Third input register
2850 switch (Inst.getOpcode()) {
2854 case ARM::VST3d8_UPD:
2855 case ARM::VST3d16_UPD:
2856 case ARM::VST3d32_UPD:
2860 case ARM::VST4d8_UPD:
2861 case ARM::VST4d16_UPD:
2862 case ARM::VST4d32_UPD:
2863 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2864 return MCDisassembler::Fail;
2869 case ARM::VST3q8_UPD:
2870 case ARM::VST3q16_UPD:
2871 case ARM::VST3q32_UPD:
2875 case ARM::VST4q8_UPD:
2876 case ARM::VST4q16_UPD:
2877 case ARM::VST4q32_UPD:
2878 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2879 return MCDisassembler::Fail;
2885 // Fourth input register
2886 switch (Inst.getOpcode()) {
2890 case ARM::VST4d8_UPD:
2891 case ARM::VST4d16_UPD:
2892 case ARM::VST4d32_UPD:
2893 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2894 return MCDisassembler::Fail;
2899 case ARM::VST4q8_UPD:
2900 case ARM::VST4q16_UPD:
2901 case ARM::VST4q32_UPD:
2902 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2903 return MCDisassembler::Fail;
2912 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2913 uint64_t Address, const void *Decoder) {
2914 DecodeStatus S = MCDisassembler::Success;
2916 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2917 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2918 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2919 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2920 unsigned align = fieldFromInstruction(Insn, 4, 1);
2921 unsigned size = fieldFromInstruction(Insn, 6, 2);
2923 if (size == 0 && align == 1)
2924 return MCDisassembler::Fail;
2925 align *= (1 << size);
2927 switch (Inst.getOpcode()) {
2928 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2929 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2930 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2931 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2932 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2933 return MCDisassembler::Fail;
2936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2937 return MCDisassembler::Fail;
2941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2942 return MCDisassembler::Fail;
2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2946 return MCDisassembler::Fail;
2947 Inst.addOperand(MCOperand::createImm(align));
2949 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2950 // variant encodes Rm == 0xf. Anything else is a register offset post-
2951 // increment and we need to add the register operand to the instruction.
2952 if (Rm != 0xD && Rm != 0xF &&
2953 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2954 return MCDisassembler::Fail;
2959 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2960 uint64_t Address, const void *Decoder) {
2961 DecodeStatus S = MCDisassembler::Success;
2963 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2964 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2965 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2966 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2967 unsigned align = fieldFromInstruction(Insn, 4, 1);
2968 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2971 switch (Inst.getOpcode()) {
2972 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2973 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2974 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2975 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2976 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2977 return MCDisassembler::Fail;
2979 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2980 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2981 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2982 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2983 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2984 return MCDisassembler::Fail;
2987 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2988 return MCDisassembler::Fail;
2993 Inst.addOperand(MCOperand::createImm(0));
2995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2996 return MCDisassembler::Fail;
2997 Inst.addOperand(MCOperand::createImm(align));
2999 if (Rm != 0xD && Rm != 0xF) {
3000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3001 return MCDisassembler::Fail;
3007 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3008 uint64_t Address, const void *Decoder) {
3009 DecodeStatus S = MCDisassembler::Success;
3011 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3012 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3013 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3014 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3015 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3018 return MCDisassembler::Fail;
3019 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3020 return MCDisassembler::Fail;
3021 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3022 return MCDisassembler::Fail;
3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3025 return MCDisassembler::Fail;
3028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3029 return MCDisassembler::Fail;
3030 Inst.addOperand(MCOperand::createImm(0));
3033 Inst.addOperand(MCOperand::createReg(0));
3034 else if (Rm != 0xF) {
3035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3036 return MCDisassembler::Fail;
3042 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3043 uint64_t Address, const void *Decoder) {
3044 DecodeStatus S = MCDisassembler::Success;
3046 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3047 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3048 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3049 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3050 unsigned size = fieldFromInstruction(Insn, 6, 2);
3051 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3052 unsigned align = fieldFromInstruction(Insn, 4, 1);
3056 return MCDisassembler::Fail;
3067 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3068 return MCDisassembler::Fail;
3069 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3070 return MCDisassembler::Fail;
3071 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3072 return MCDisassembler::Fail;
3073 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3074 return MCDisassembler::Fail;
3076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3077 return MCDisassembler::Fail;
3080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3081 return MCDisassembler::Fail;
3082 Inst.addOperand(MCOperand::createImm(align));
3085 Inst.addOperand(MCOperand::createReg(0));
3086 else if (Rm != 0xF) {
3087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3088 return MCDisassembler::Fail;
3095 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3096 uint64_t Address, const void *Decoder) {
3097 DecodeStatus S = MCDisassembler::Success;
3099 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3100 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3101 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3102 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3103 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3104 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3105 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3106 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3109 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3110 return MCDisassembler::Fail;
3112 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3113 return MCDisassembler::Fail;
3116 Inst.addOperand(MCOperand::createImm(imm));
3118 switch (Inst.getOpcode()) {
3119 case ARM::VORRiv4i16:
3120 case ARM::VORRiv2i32:
3121 case ARM::VBICiv4i16:
3122 case ARM::VBICiv2i32:
3123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3124 return MCDisassembler::Fail;
3126 case ARM::VORRiv8i16:
3127 case ARM::VORRiv4i32:
3128 case ARM::VBICiv8i16:
3129 case ARM::VBICiv4i32:
3130 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3131 return MCDisassembler::Fail;
3140 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3141 uint64_t Address, const void *Decoder) {
3142 DecodeStatus S = MCDisassembler::Success;
3144 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3145 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3146 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3147 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3148 unsigned size = fieldFromInstruction(Insn, 18, 2);
3150 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3151 return MCDisassembler::Fail;
3152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3153 return MCDisassembler::Fail;
3154 Inst.addOperand(MCOperand::createImm(8 << size));
3159 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3160 uint64_t Address, const void *Decoder) {
3161 Inst.addOperand(MCOperand::createImm(8 - Val));
3162 return MCDisassembler::Success;
3165 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3166 uint64_t Address, const void *Decoder) {
3167 Inst.addOperand(MCOperand::createImm(16 - Val));
3168 return MCDisassembler::Success;
3171 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3172 uint64_t Address, const void *Decoder) {
3173 Inst.addOperand(MCOperand::createImm(32 - Val));
3174 return MCDisassembler::Success;
3177 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3178 uint64_t Address, const void *Decoder) {
3179 Inst.addOperand(MCOperand::createImm(64 - Val));
3180 return MCDisassembler::Success;
3183 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3184 uint64_t Address, const void *Decoder) {
3185 DecodeStatus S = MCDisassembler::Success;
3187 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3188 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3189 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3190 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3191 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3192 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3193 unsigned op = fieldFromInstruction(Insn, 6, 1);
3195 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3196 return MCDisassembler::Fail;
3198 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3199 return MCDisassembler::Fail; // Writeback
3202 switch (Inst.getOpcode()) {
3205 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3206 return MCDisassembler::Fail;
3209 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3210 return MCDisassembler::Fail;
3213 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3214 return MCDisassembler::Fail;
3219 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3220 uint64_t Address, const void *Decoder) {
3221 DecodeStatus S = MCDisassembler::Success;
3223 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3224 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3226 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3227 return MCDisassembler::Fail;
3229 switch(Inst.getOpcode()) {
3231 return MCDisassembler::Fail;
3233 break; // tADR does not explicitly represent the PC as an operand.
3235 Inst.addOperand(MCOperand::createReg(ARM::SP));
3239 Inst.addOperand(MCOperand::createImm(imm));
3243 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3244 uint64_t Address, const void *Decoder) {
3245 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3246 true, 2, Inst, Decoder))
3247 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3248 return MCDisassembler::Success;
3251 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3252 uint64_t Address, const void *Decoder) {
3253 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3254 true, 4, Inst, Decoder))
3255 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3256 return MCDisassembler::Success;
3259 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3260 uint64_t Address, const void *Decoder) {
3261 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3262 true, 2, Inst, Decoder))
3263 Inst.addOperand(MCOperand::createImm(Val << 1));
3264 return MCDisassembler::Success;
3267 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3268 uint64_t Address, const void *Decoder) {
3269 DecodeStatus S = MCDisassembler::Success;
3271 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3272 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3274 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3275 return MCDisassembler::Fail;
3276 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3277 return MCDisassembler::Fail;
3282 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3283 uint64_t Address, const void *Decoder) {
3284 DecodeStatus S = MCDisassembler::Success;
3286 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3287 unsigned imm = fieldFromInstruction(Val, 3, 5);
3289 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3290 return MCDisassembler::Fail;
3291 Inst.addOperand(MCOperand::createImm(imm));
3296 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3297 uint64_t Address, const void *Decoder) {
3298 unsigned imm = Val << 2;
3300 Inst.addOperand(MCOperand::createImm(imm));
3301 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3303 return MCDisassembler::Success;
3306 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3307 uint64_t Address, const void *Decoder) {
3308 Inst.addOperand(MCOperand::createReg(ARM::SP));
3309 Inst.addOperand(MCOperand::createImm(Val));
3311 return MCDisassembler::Success;
3314 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3315 uint64_t Address, const void *Decoder) {
3316 DecodeStatus S = MCDisassembler::Success;
3318 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3319 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3320 unsigned imm = fieldFromInstruction(Val, 0, 2);
3322 // Thumb stores cannot use PC as dest register.
3323 switch (Inst.getOpcode()) {
3328 return MCDisassembler::Fail;
3333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3334 return MCDisassembler::Fail;
3335 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3336 return MCDisassembler::Fail;
3337 Inst.addOperand(MCOperand::createImm(imm));
3342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3343 uint64_t Address, const void *Decoder) {
3344 DecodeStatus S = MCDisassembler::Success;
3346 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3347 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3349 const FeatureBitset &featureBits =
3350 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3352 bool hasMP = featureBits[ARM::FeatureMP];
3353 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3356 switch (Inst.getOpcode()) {
3358 Inst.setOpcode(ARM::t2LDRBpci);
3361 Inst.setOpcode(ARM::t2LDRHpci);
3364 Inst.setOpcode(ARM::t2LDRSHpci);
3367 Inst.setOpcode(ARM::t2LDRSBpci);
3370 Inst.setOpcode(ARM::t2LDRpci);
3373 Inst.setOpcode(ARM::t2PLDpci);
3376 Inst.setOpcode(ARM::t2PLIpci);
3379 return MCDisassembler::Fail;
3382 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3386 switch (Inst.getOpcode()) {
3388 return MCDisassembler::Fail;
3390 Inst.setOpcode(ARM::t2PLDWs);
3393 Inst.setOpcode(ARM::t2PLIs);
3399 switch (Inst.getOpcode()) {
3404 return MCDisassembler::Fail;
3407 if (!hasV7Ops || !hasMP)
3408 return MCDisassembler::Fail;
3411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3412 return MCDisassembler::Fail;
3415 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3416 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3417 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3418 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3419 return MCDisassembler::Fail;
3424 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3425 uint64_t Address, const void* Decoder) {
3426 DecodeStatus S = MCDisassembler::Success;
3428 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3429 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3430 unsigned U = fieldFromInstruction(Insn, 9, 1);
3431 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3434 unsigned add = fieldFromInstruction(Insn, 9, 1);
3436 const FeatureBitset &featureBits =
3437 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3439 bool hasMP = featureBits[ARM::FeatureMP];
3440 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3443 switch (Inst.getOpcode()) {
3445 Inst.setOpcode(ARM::t2LDRpci);
3448 Inst.setOpcode(ARM::t2LDRBpci);
3450 case ARM::t2LDRSBi8:
3451 Inst.setOpcode(ARM::t2LDRSBpci);
3454 Inst.setOpcode(ARM::t2LDRHpci);
3456 case ARM::t2LDRSHi8:
3457 Inst.setOpcode(ARM::t2LDRSHpci);
3460 Inst.setOpcode(ARM::t2PLDpci);
3463 Inst.setOpcode(ARM::t2PLIpci);
3466 return MCDisassembler::Fail;
3468 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3472 switch (Inst.getOpcode()) {
3473 case ARM::t2LDRSHi8:
3474 return MCDisassembler::Fail;
3477 Inst.setOpcode(ARM::t2PLDWi8);
3479 case ARM::t2LDRSBi8:
3480 Inst.setOpcode(ARM::t2PLIi8);
3487 switch (Inst.getOpcode()) {
3492 return MCDisassembler::Fail;
3495 if (!hasV7Ops || !hasMP)
3496 return MCDisassembler::Fail;
3499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3500 return MCDisassembler::Fail;
3503 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3504 return MCDisassembler::Fail;
3508 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3509 uint64_t Address, const void* Decoder) {
3510 DecodeStatus S = MCDisassembler::Success;
3512 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3513 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3514 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3517 const FeatureBitset &featureBits =
3518 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3520 bool hasMP = featureBits[ARM::FeatureMP];
3521 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3524 switch (Inst.getOpcode()) {
3526 Inst.setOpcode(ARM::t2LDRpci);
3528 case ARM::t2LDRHi12:
3529 Inst.setOpcode(ARM::t2LDRHpci);
3531 case ARM::t2LDRSHi12:
3532 Inst.setOpcode(ARM::t2LDRSHpci);
3534 case ARM::t2LDRBi12:
3535 Inst.setOpcode(ARM::t2LDRBpci);
3537 case ARM::t2LDRSBi12:
3538 Inst.setOpcode(ARM::t2LDRSBpci);
3541 Inst.setOpcode(ARM::t2PLDpci);
3544 Inst.setOpcode(ARM::t2PLIpci);
3547 return MCDisassembler::Fail;
3549 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3553 switch (Inst.getOpcode()) {
3554 case ARM::t2LDRSHi12:
3555 return MCDisassembler::Fail;
3556 case ARM::t2LDRHi12:
3557 Inst.setOpcode(ARM::t2PLDWi12);
3559 case ARM::t2LDRSBi12:
3560 Inst.setOpcode(ARM::t2PLIi12);
3567 switch (Inst.getOpcode()) {
3572 return MCDisassembler::Fail;
3574 case ARM::t2PLDWi12:
3575 if (!hasV7Ops || !hasMP)
3576 return MCDisassembler::Fail;
3579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3580 return MCDisassembler::Fail;
3583 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3584 return MCDisassembler::Fail;
3588 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3589 uint64_t Address, const void* Decoder) {
3590 DecodeStatus S = MCDisassembler::Success;
3592 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3593 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3594 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3598 switch (Inst.getOpcode()) {
3600 Inst.setOpcode(ARM::t2LDRpci);
3603 Inst.setOpcode(ARM::t2LDRBpci);
3606 Inst.setOpcode(ARM::t2LDRHpci);
3609 Inst.setOpcode(ARM::t2LDRSBpci);
3612 Inst.setOpcode(ARM::t2LDRSHpci);
3615 return MCDisassembler::Fail;
3617 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3620 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3621 return MCDisassembler::Fail;
3622 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3623 return MCDisassembler::Fail;
3627 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3628 uint64_t Address, const void* Decoder) {
3629 DecodeStatus S = MCDisassembler::Success;
3631 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3632 unsigned U = fieldFromInstruction(Insn, 23, 1);
3633 int imm = fieldFromInstruction(Insn, 0, 12);
3635 const FeatureBitset &featureBits =
3636 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3638 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3641 switch (Inst.getOpcode()) {
3642 case ARM::t2LDRBpci:
3643 case ARM::t2LDRHpci:
3644 Inst.setOpcode(ARM::t2PLDpci);
3646 case ARM::t2LDRSBpci:
3647 Inst.setOpcode(ARM::t2PLIpci);
3649 case ARM::t2LDRSHpci:
3650 return MCDisassembler::Fail;
3656 switch(Inst.getOpcode()) {
3661 return MCDisassembler::Fail;
3664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3665 return MCDisassembler::Fail;
3669 // Special case for #-0.
3675 Inst.addOperand(MCOperand::createImm(imm));
3680 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3681 uint64_t Address, const void *Decoder) {
3683 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3685 int imm = Val & 0xFF;
3687 if (!(Val & 0x100)) imm *= -1;
3688 Inst.addOperand(MCOperand::createImm(imm * 4));
3691 return MCDisassembler::Success;
3694 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3695 uint64_t Address, const void *Decoder) {
3696 DecodeStatus S = MCDisassembler::Success;
3698 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3699 unsigned imm = fieldFromInstruction(Val, 0, 9);
3701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3702 return MCDisassembler::Fail;
3703 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3704 return MCDisassembler::Fail;
3709 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3710 uint64_t Address, const void *Decoder) {
3711 DecodeStatus S = MCDisassembler::Success;
3713 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3714 unsigned imm = fieldFromInstruction(Val, 0, 8);
3716 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3717 return MCDisassembler::Fail;
3719 Inst.addOperand(MCOperand::createImm(imm));
3724 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3725 uint64_t Address, const void *Decoder) {
3726 int imm = Val & 0xFF;
3729 else if (!(Val & 0x100))
3731 Inst.addOperand(MCOperand::createImm(imm));
3733 return MCDisassembler::Success;
3736 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3737 uint64_t Address, const void *Decoder) {
3738 DecodeStatus S = MCDisassembler::Success;
3740 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3741 unsigned imm = fieldFromInstruction(Val, 0, 9);
3743 // Thumb stores cannot use PC as dest register.
3744 switch (Inst.getOpcode()) {
3752 return MCDisassembler::Fail;
3758 // Some instructions always use an additive offset.
3759 switch (Inst.getOpcode()) {
3774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3775 return MCDisassembler::Fail;
3776 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3777 return MCDisassembler::Fail;
3782 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3783 uint64_t Address, const void *Decoder) {
3784 DecodeStatus S = MCDisassembler::Success;
3786 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3787 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3788 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3789 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3791 unsigned load = fieldFromInstruction(Insn, 20, 1);
3794 switch (Inst.getOpcode()) {
3795 case ARM::t2LDR_PRE:
3796 case ARM::t2LDR_POST:
3797 Inst.setOpcode(ARM::t2LDRpci);
3799 case ARM::t2LDRB_PRE:
3800 case ARM::t2LDRB_POST:
3801 Inst.setOpcode(ARM::t2LDRBpci);
3803 case ARM::t2LDRH_PRE:
3804 case ARM::t2LDRH_POST:
3805 Inst.setOpcode(ARM::t2LDRHpci);
3807 case ARM::t2LDRSB_PRE:
3808 case ARM::t2LDRSB_POST:
3810 Inst.setOpcode(ARM::t2PLIpci);
3812 Inst.setOpcode(ARM::t2LDRSBpci);
3814 case ARM::t2LDRSH_PRE:
3815 case ARM::t2LDRSH_POST:
3816 Inst.setOpcode(ARM::t2LDRSHpci);
3819 return MCDisassembler::Fail;
3821 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3826 return MCDisassembler::Fail;
3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3830 return MCDisassembler::Fail;
3833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3834 return MCDisassembler::Fail;
3837 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3838 return MCDisassembler::Fail;
3843 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3844 uint64_t Address, const void *Decoder) {
3845 DecodeStatus S = MCDisassembler::Success;
3847 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3848 unsigned imm = fieldFromInstruction(Val, 0, 12);
3850 // Thumb stores cannot use PC as dest register.
3851 switch (Inst.getOpcode()) {
3853 case ARM::t2STRBi12:
3854 case ARM::t2STRHi12:
3856 return MCDisassembler::Fail;
3861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3862 return MCDisassembler::Fail;
3863 Inst.addOperand(MCOperand::createImm(imm));
3868 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3869 uint64_t Address, const void *Decoder) {
3870 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3872 Inst.addOperand(MCOperand::createReg(ARM::SP));
3873 Inst.addOperand(MCOperand::createReg(ARM::SP));
3874 Inst.addOperand(MCOperand::createImm(imm));
3876 return MCDisassembler::Success;
3879 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3880 uint64_t Address, const void *Decoder) {
3881 DecodeStatus S = MCDisassembler::Success;
3883 if (Inst.getOpcode() == ARM::tADDrSP) {
3884 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3885 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3888 return MCDisassembler::Fail;
3889 Inst.addOperand(MCOperand::createReg(ARM::SP));
3890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892 } else if (Inst.getOpcode() == ARM::tADDspr) {
3893 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3895 Inst.addOperand(MCOperand::createReg(ARM::SP));
3896 Inst.addOperand(MCOperand::createReg(ARM::SP));
3897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3898 return MCDisassembler::Fail;
3904 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3905 uint64_t Address, const void *Decoder) {
3906 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3907 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3909 Inst.addOperand(MCOperand::createImm(imod));
3910 Inst.addOperand(MCOperand::createImm(flags));
3912 return MCDisassembler::Success;
3915 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3916 uint64_t Address, const void *Decoder) {
3917 DecodeStatus S = MCDisassembler::Success;
3918 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3919 unsigned add = fieldFromInstruction(Insn, 4, 1);
3921 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3922 return MCDisassembler::Fail;
3923 Inst.addOperand(MCOperand::createImm(add));
3928 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3929 uint64_t Address, const void *Decoder) {
3930 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3931 // Note only one trailing zero not two. Also the J1 and J2 values are from
3932 // the encoded instruction. So here change to I1 and I2 values via:
3933 // I1 = NOT(J1 EOR S);
3934 // I2 = NOT(J2 EOR S);
3935 // and build the imm32 with two trailing zeros as documented:
3936 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3937 unsigned S = (Val >> 23) & 1;
3938 unsigned J1 = (Val >> 22) & 1;
3939 unsigned J2 = (Val >> 21) & 1;
3940 unsigned I1 = !(J1 ^ S);
3941 unsigned I2 = !(J2 ^ S);
3942 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3943 int imm32 = SignExtend32<25>(tmp << 1);
3945 if (!tryAddingSymbolicOperand(Address,
3946 (Address & ~2u) + imm32 + 4,
3947 true, 4, Inst, Decoder))
3948 Inst.addOperand(MCOperand::createImm(imm32));
3949 return MCDisassembler::Success;
3952 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3953 uint64_t Address, const void *Decoder) {
3954 if (Val == 0xA || Val == 0xB)
3955 return MCDisassembler::Fail;
3957 const FeatureBitset &featureBits =
3958 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3960 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3961 return MCDisassembler::Fail;
3963 Inst.addOperand(MCOperand::createImm(Val));
3964 return MCDisassembler::Success;
3968 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3969 uint64_t Address, const void *Decoder) {
3970 DecodeStatus S = MCDisassembler::Success;
3972 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3973 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3975 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3976 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3977 return MCDisassembler::Fail;
3978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3979 return MCDisassembler::Fail;
3984 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3985 uint64_t Address, const void *Decoder) {
3986 DecodeStatus S = MCDisassembler::Success;
3988 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3989 if (pred == 0xE || pred == 0xF) {
3990 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3993 return MCDisassembler::Fail;
3995 Inst.setOpcode(ARM::t2DSB);
3998 Inst.setOpcode(ARM::t2DMB);
4001 Inst.setOpcode(ARM::t2ISB);
4005 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4006 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4009 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4010 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4011 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4012 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4013 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4015 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4016 return MCDisassembler::Fail;
4017 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4018 return MCDisassembler::Fail;
4023 // Decode a shifted immediate operand. These basically consist
4024 // of an 8-bit value, and a 4-bit directive that specifies either
4025 // a splat operation or a rotation.
4026 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4027 uint64_t Address, const void *Decoder) {
4028 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4030 unsigned byte = fieldFromInstruction(Val, 8, 2);
4031 unsigned imm = fieldFromInstruction(Val, 0, 8);
4034 Inst.addOperand(MCOperand::createImm(imm));
4037 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4040 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4043 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4048 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4049 unsigned rot = fieldFromInstruction(Val, 7, 5);
4050 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4051 Inst.addOperand(MCOperand::createImm(imm));
4054 return MCDisassembler::Success;
4058 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4059 uint64_t Address, const void *Decoder) {
4060 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4061 true, 2, Inst, Decoder))
4062 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4063 return MCDisassembler::Success;
4066 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4068 const void *Decoder) {
4069 // Val is passed in as S:J1:J2:imm10:imm11
4070 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4071 // the encoded instruction. So here change to I1 and I2 values via:
4072 // I1 = NOT(J1 EOR S);
4073 // I2 = NOT(J2 EOR S);
4074 // and build the imm32 with one trailing zero as documented:
4075 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4076 unsigned S = (Val >> 23) & 1;
4077 unsigned J1 = (Val >> 22) & 1;
4078 unsigned J2 = (Val >> 21) & 1;
4079 unsigned I1 = !(J1 ^ S);
4080 unsigned I2 = !(J2 ^ S);
4081 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4082 int imm32 = SignExtend32<25>(tmp << 1);
4084 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4085 true, 4, Inst, Decoder))
4086 Inst.addOperand(MCOperand::createImm(imm32));
4087 return MCDisassembler::Success;
4090 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4091 uint64_t Address, const void *Decoder) {
4093 return MCDisassembler::Fail;
4095 Inst.addOperand(MCOperand::createImm(Val));
4096 return MCDisassembler::Success;
4099 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4100 uint64_t Address, const void *Decoder) {
4102 return MCDisassembler::Fail;
4104 Inst.addOperand(MCOperand::createImm(Val));
4105 return MCDisassembler::Success;
4108 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4109 uint64_t Address, const void *Decoder) {
4110 DecodeStatus S = MCDisassembler::Success;
4111 const FeatureBitset &FeatureBits =
4112 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4114 if (FeatureBits[ARM::FeatureMClass]) {
4115 unsigned ValLow = Val & 0xff;
4117 // Validate the SYSm value first.
4132 case 18: // basepri_max
4133 case 19: // faultmask
4134 if (!(FeatureBits[ARM::HasV7Ops]))
4135 // Values basepri, basepri_max and faultmask are only valid for v7m.
4136 return MCDisassembler::Fail;
4138 case 0x8a: // msplim_ns
4139 case 0x8b: // psplim_ns
4140 case 0x91: // basepri_ns
4141 case 0x92: // basepri_max_ns
4142 case 0x93: // faultmask_ns
4143 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4144 return MCDisassembler::Fail;
4148 case 0x88: // msp_ns
4149 case 0x89: // psp_ns
4150 case 0x90: // primask_ns
4151 case 0x94: // control_ns
4153 if (!(FeatureBits[ARM::Feature8MSecExt]))
4154 return MCDisassembler::Fail;
4157 return MCDisassembler::Fail;
4160 if (Inst.getOpcode() == ARM::t2MSR_M) {
4161 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4162 if (!(FeatureBits[ARM::HasV7Ops])) {
4163 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4166 S = MCDisassembler::SoftFail;
4169 // The ARMv7-M architecture stores an additional 2-bit mask value in
4170 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4171 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4172 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4173 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4174 // only if the processor includes the DSP extension.
4175 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4176 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4177 S = MCDisassembler::SoftFail;
4183 return MCDisassembler::Fail;
4185 Inst.addOperand(MCOperand::createImm(Val));
4189 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4190 uint64_t Address, const void *Decoder) {
4191 unsigned R = fieldFromInstruction(Val, 5, 1);
4192 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4194 // The table of encodings for these banked registers comes from B9.2.3 of the
4195 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4196 // neater. So by fiat, these values are UNPREDICTABLE:
4198 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4199 SysM == 0x1a || SysM == 0x1b)
4200 return MCDisassembler::SoftFail;
4202 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4203 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4204 return MCDisassembler::SoftFail;
4207 Inst.addOperand(MCOperand::createImm(Val));
4208 return MCDisassembler::Success;
4211 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4212 uint64_t Address, const void *Decoder) {
4213 DecodeStatus S = MCDisassembler::Success;
4215 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4216 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4217 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4220 S = MCDisassembler::SoftFail;
4222 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4223 return MCDisassembler::Fail;
4224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4225 return MCDisassembler::Fail;
4226 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4227 return MCDisassembler::Fail;
4232 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4234 const void *Decoder) {
4235 DecodeStatus S = MCDisassembler::Success;
4237 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4238 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4239 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4240 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4242 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4243 return MCDisassembler::Fail;
4245 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4246 S = MCDisassembler::SoftFail;
4248 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4249 return MCDisassembler::Fail;
4250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4251 return MCDisassembler::Fail;
4252 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4253 return MCDisassembler::Fail;
4258 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4259 uint64_t Address, const void *Decoder) {
4260 DecodeStatus S = MCDisassembler::Success;
4262 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4263 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4264 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4265 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4266 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4267 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4269 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4272 return MCDisassembler::Fail;
4273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4274 return MCDisassembler::Fail;
4275 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4276 return MCDisassembler::Fail;
4277 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4278 return MCDisassembler::Fail;
4283 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4284 uint64_t Address, const void *Decoder) {
4285 DecodeStatus S = MCDisassembler::Success;
4287 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4288 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4289 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4290 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4291 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4292 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4293 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4295 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4296 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4299 return MCDisassembler::Fail;
4300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4301 return MCDisassembler::Fail;
4302 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4303 return MCDisassembler::Fail;
4304 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4305 return MCDisassembler::Fail;
4310 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4311 uint64_t Address, const void *Decoder) {
4312 DecodeStatus S = MCDisassembler::Success;
4314 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4315 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4316 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4317 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4318 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4319 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4321 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4324 return MCDisassembler::Fail;
4325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4326 return MCDisassembler::Fail;
4327 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4328 return MCDisassembler::Fail;
4329 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4330 return MCDisassembler::Fail;
4335 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4336 uint64_t Address, const void *Decoder) {
4337 DecodeStatus S = MCDisassembler::Success;
4339 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4340 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4341 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4342 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4343 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4344 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4346 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4349 return MCDisassembler::Fail;
4350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4351 return MCDisassembler::Fail;
4352 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4353 return MCDisassembler::Fail;
4354 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4355 return MCDisassembler::Fail;
4360 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4361 uint64_t Address, const void *Decoder) {
4362 DecodeStatus S = MCDisassembler::Success;
4364 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4365 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4366 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4367 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4368 unsigned size = fieldFromInstruction(Insn, 10, 2);
4374 return MCDisassembler::Fail;
4376 if (fieldFromInstruction(Insn, 4, 1))
4377 return MCDisassembler::Fail; // UNDEFINED
4378 index = fieldFromInstruction(Insn, 5, 3);
4381 if (fieldFromInstruction(Insn, 5, 1))
4382 return MCDisassembler::Fail; // UNDEFINED
4383 index = fieldFromInstruction(Insn, 6, 2);
4384 if (fieldFromInstruction(Insn, 4, 1))
4388 if (fieldFromInstruction(Insn, 6, 1))
4389 return MCDisassembler::Fail; // UNDEFINED
4390 index = fieldFromInstruction(Insn, 7, 1);
4392 switch (fieldFromInstruction(Insn, 4, 2)) {
4398 return MCDisassembler::Fail;
4403 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4404 return MCDisassembler::Fail;
4405 if (Rm != 0xF) { // Writeback
4406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4407 return MCDisassembler::Fail;
4409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4410 return MCDisassembler::Fail;
4411 Inst.addOperand(MCOperand::createImm(align));
4414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4415 return MCDisassembler::Fail;
4417 Inst.addOperand(MCOperand::createReg(0));
4420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4421 return MCDisassembler::Fail;
4422 Inst.addOperand(MCOperand::createImm(index));
4427 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4428 uint64_t Address, const void *Decoder) {
4429 DecodeStatus S = MCDisassembler::Success;
4431 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4432 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4433 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4434 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4435 unsigned size = fieldFromInstruction(Insn, 10, 2);
4441 return MCDisassembler::Fail;
4443 if (fieldFromInstruction(Insn, 4, 1))
4444 return MCDisassembler::Fail; // UNDEFINED
4445 index = fieldFromInstruction(Insn, 5, 3);
4448 if (fieldFromInstruction(Insn, 5, 1))
4449 return MCDisassembler::Fail; // UNDEFINED
4450 index = fieldFromInstruction(Insn, 6, 2);
4451 if (fieldFromInstruction(Insn, 4, 1))
4455 if (fieldFromInstruction(Insn, 6, 1))
4456 return MCDisassembler::Fail; // UNDEFINED
4457 index = fieldFromInstruction(Insn, 7, 1);
4459 switch (fieldFromInstruction(Insn, 4, 2)) {
4465 return MCDisassembler::Fail;
4470 if (Rm != 0xF) { // Writeback
4471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4472 return MCDisassembler::Fail;
4474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4475 return MCDisassembler::Fail;
4476 Inst.addOperand(MCOperand::createImm(align));
4479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4480 return MCDisassembler::Fail;
4482 Inst.addOperand(MCOperand::createReg(0));
4485 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4486 return MCDisassembler::Fail;
4487 Inst.addOperand(MCOperand::createImm(index));
4492 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4493 uint64_t Address, const void *Decoder) {
4494 DecodeStatus S = MCDisassembler::Success;
4496 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4497 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4498 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4499 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4500 unsigned size = fieldFromInstruction(Insn, 10, 2);
4507 return MCDisassembler::Fail;
4509 index = fieldFromInstruction(Insn, 5, 3);
4510 if (fieldFromInstruction(Insn, 4, 1))
4514 index = fieldFromInstruction(Insn, 6, 2);
4515 if (fieldFromInstruction(Insn, 4, 1))
4517 if (fieldFromInstruction(Insn, 5, 1))
4521 if (fieldFromInstruction(Insn, 5, 1))
4522 return MCDisassembler::Fail; // UNDEFINED
4523 index = fieldFromInstruction(Insn, 7, 1);
4524 if (fieldFromInstruction(Insn, 4, 1) != 0)
4526 if (fieldFromInstruction(Insn, 6, 1))
4531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4532 return MCDisassembler::Fail;
4533 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4534 return MCDisassembler::Fail;
4535 if (Rm != 0xF) { // Writeback
4536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4537 return MCDisassembler::Fail;
4539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4540 return MCDisassembler::Fail;
4541 Inst.addOperand(MCOperand::createImm(align));
4544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4545 return MCDisassembler::Fail;
4547 Inst.addOperand(MCOperand::createReg(0));
4550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4551 return MCDisassembler::Fail;
4552 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4553 return MCDisassembler::Fail;
4554 Inst.addOperand(MCOperand::createImm(index));
4559 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4560 uint64_t Address, const void *Decoder) {
4561 DecodeStatus S = MCDisassembler::Success;
4563 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4564 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4565 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4566 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4567 unsigned size = fieldFromInstruction(Insn, 10, 2);
4574 return MCDisassembler::Fail;
4576 index = fieldFromInstruction(Insn, 5, 3);
4577 if (fieldFromInstruction(Insn, 4, 1))
4581 index = fieldFromInstruction(Insn, 6, 2);
4582 if (fieldFromInstruction(Insn, 4, 1))
4584 if (fieldFromInstruction(Insn, 5, 1))
4588 if (fieldFromInstruction(Insn, 5, 1))
4589 return MCDisassembler::Fail; // UNDEFINED
4590 index = fieldFromInstruction(Insn, 7, 1);
4591 if (fieldFromInstruction(Insn, 4, 1) != 0)
4593 if (fieldFromInstruction(Insn, 6, 1))
4598 if (Rm != 0xF) { // Writeback
4599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4600 return MCDisassembler::Fail;
4602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4603 return MCDisassembler::Fail;
4604 Inst.addOperand(MCOperand::createImm(align));
4607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4608 return MCDisassembler::Fail;
4610 Inst.addOperand(MCOperand::createReg(0));
4613 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4614 return MCDisassembler::Fail;
4615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4616 return MCDisassembler::Fail;
4617 Inst.addOperand(MCOperand::createImm(index));
4622 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4623 uint64_t Address, const void *Decoder) {
4624 DecodeStatus S = MCDisassembler::Success;
4626 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4627 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4628 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4629 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4630 unsigned size = fieldFromInstruction(Insn, 10, 2);
4637 return MCDisassembler::Fail;
4639 if (fieldFromInstruction(Insn, 4, 1))
4640 return MCDisassembler::Fail; // UNDEFINED
4641 index = fieldFromInstruction(Insn, 5, 3);
4644 if (fieldFromInstruction(Insn, 4, 1))
4645 return MCDisassembler::Fail; // UNDEFINED
4646 index = fieldFromInstruction(Insn, 6, 2);
4647 if (fieldFromInstruction(Insn, 5, 1))
4651 if (fieldFromInstruction(Insn, 4, 2))
4652 return MCDisassembler::Fail; // UNDEFINED
4653 index = fieldFromInstruction(Insn, 7, 1);
4654 if (fieldFromInstruction(Insn, 6, 1))
4659 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4660 return MCDisassembler::Fail;
4661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4662 return MCDisassembler::Fail;
4663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4664 return MCDisassembler::Fail;
4666 if (Rm != 0xF) { // Writeback
4667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4668 return MCDisassembler::Fail;
4670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4671 return MCDisassembler::Fail;
4672 Inst.addOperand(MCOperand::createImm(align));
4675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4676 return MCDisassembler::Fail;
4678 Inst.addOperand(MCOperand::createReg(0));
4681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4682 return MCDisassembler::Fail;
4683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4684 return MCDisassembler::Fail;
4685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4686 return MCDisassembler::Fail;
4687 Inst.addOperand(MCOperand::createImm(index));
4692 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4693 uint64_t Address, const void *Decoder) {
4694 DecodeStatus S = MCDisassembler::Success;
4696 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4697 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4698 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4699 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4700 unsigned size = fieldFromInstruction(Insn, 10, 2);
4707 return MCDisassembler::Fail;
4709 if (fieldFromInstruction(Insn, 4, 1))
4710 return MCDisassembler::Fail; // UNDEFINED
4711 index = fieldFromInstruction(Insn, 5, 3);
4714 if (fieldFromInstruction(Insn, 4, 1))
4715 return MCDisassembler::Fail; // UNDEFINED
4716 index = fieldFromInstruction(Insn, 6, 2);
4717 if (fieldFromInstruction(Insn, 5, 1))
4721 if (fieldFromInstruction(Insn, 4, 2))
4722 return MCDisassembler::Fail; // UNDEFINED
4723 index = fieldFromInstruction(Insn, 7, 1);
4724 if (fieldFromInstruction(Insn, 6, 1))
4729 if (Rm != 0xF) { // Writeback
4730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4731 return MCDisassembler::Fail;
4733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4734 return MCDisassembler::Fail;
4735 Inst.addOperand(MCOperand::createImm(align));
4738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4739 return MCDisassembler::Fail;
4741 Inst.addOperand(MCOperand::createReg(0));
4744 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4745 return MCDisassembler::Fail;
4746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4747 return MCDisassembler::Fail;
4748 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4749 return MCDisassembler::Fail;
4750 Inst.addOperand(MCOperand::createImm(index));
4755 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4756 uint64_t Address, const void *Decoder) {
4757 DecodeStatus S = MCDisassembler::Success;
4759 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4760 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4761 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4762 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4763 unsigned size = fieldFromInstruction(Insn, 10, 2);
4770 return MCDisassembler::Fail;
4772 if (fieldFromInstruction(Insn, 4, 1))
4774 index = fieldFromInstruction(Insn, 5, 3);
4777 if (fieldFromInstruction(Insn, 4, 1))
4779 index = fieldFromInstruction(Insn, 6, 2);
4780 if (fieldFromInstruction(Insn, 5, 1))
4784 switch (fieldFromInstruction(Insn, 4, 2)) {
4788 return MCDisassembler::Fail;
4790 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4793 index = fieldFromInstruction(Insn, 7, 1);
4794 if (fieldFromInstruction(Insn, 6, 1))
4799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4800 return MCDisassembler::Fail;
4801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4802 return MCDisassembler::Fail;
4803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4804 return MCDisassembler::Fail;
4805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4806 return MCDisassembler::Fail;
4808 if (Rm != 0xF) { // Writeback
4809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4810 return MCDisassembler::Fail;
4812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4813 return MCDisassembler::Fail;
4814 Inst.addOperand(MCOperand::createImm(align));
4817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4818 return MCDisassembler::Fail;
4820 Inst.addOperand(MCOperand::createReg(0));
4823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4824 return MCDisassembler::Fail;
4825 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4826 return MCDisassembler::Fail;
4827 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4828 return MCDisassembler::Fail;
4829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4830 return MCDisassembler::Fail;
4831 Inst.addOperand(MCOperand::createImm(index));
4836 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4837 uint64_t Address, const void *Decoder) {
4838 DecodeStatus S = MCDisassembler::Success;
4840 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4841 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4842 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4843 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4844 unsigned size = fieldFromInstruction(Insn, 10, 2);
4851 return MCDisassembler::Fail;
4853 if (fieldFromInstruction(Insn, 4, 1))
4855 index = fieldFromInstruction(Insn, 5, 3);
4858 if (fieldFromInstruction(Insn, 4, 1))
4860 index = fieldFromInstruction(Insn, 6, 2);
4861 if (fieldFromInstruction(Insn, 5, 1))
4865 switch (fieldFromInstruction(Insn, 4, 2)) {
4869 return MCDisassembler::Fail;
4871 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4874 index = fieldFromInstruction(Insn, 7, 1);
4875 if (fieldFromInstruction(Insn, 6, 1))
4880 if (Rm != 0xF) { // Writeback
4881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4882 return MCDisassembler::Fail;
4884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4885 return MCDisassembler::Fail;
4886 Inst.addOperand(MCOperand::createImm(align));
4889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4890 return MCDisassembler::Fail;
4892 Inst.addOperand(MCOperand::createReg(0));
4895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4896 return MCDisassembler::Fail;
4897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4898 return MCDisassembler::Fail;
4899 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4900 return MCDisassembler::Fail;
4901 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4902 return MCDisassembler::Fail;
4903 Inst.addOperand(MCOperand::createImm(index));
4908 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4909 uint64_t Address, const void *Decoder) {
4910 DecodeStatus S = MCDisassembler::Success;
4911 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4912 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4913 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4914 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4915 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4917 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4918 S = MCDisassembler::SoftFail;
4920 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4921 return MCDisassembler::Fail;
4922 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4923 return MCDisassembler::Fail;
4924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4925 return MCDisassembler::Fail;
4926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4927 return MCDisassembler::Fail;
4928 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4929 return MCDisassembler::Fail;
4934 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4935 uint64_t Address, const void *Decoder) {
4936 DecodeStatus S = MCDisassembler::Success;
4937 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4938 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4939 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4940 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4941 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4943 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4944 S = MCDisassembler::SoftFail;
4946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4947 return MCDisassembler::Fail;
4948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4949 return MCDisassembler::Fail;
4950 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4951 return MCDisassembler::Fail;
4952 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4953 return MCDisassembler::Fail;
4954 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4955 return MCDisassembler::Fail;
4960 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4961 uint64_t Address, const void *Decoder) {
4962 DecodeStatus S = MCDisassembler::Success;
4963 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4964 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4968 S = MCDisassembler::SoftFail;
4972 return MCDisassembler::Fail;
4974 Inst.addOperand(MCOperand::createImm(pred));
4975 Inst.addOperand(MCOperand::createImm(mask));
4980 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4981 uint64_t Address, const void *Decoder) {
4982 DecodeStatus S = MCDisassembler::Success;
4984 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4985 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4986 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4987 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4988 unsigned W = fieldFromInstruction(Insn, 21, 1);
4989 unsigned U = fieldFromInstruction(Insn, 23, 1);
4990 unsigned P = fieldFromInstruction(Insn, 24, 1);
4991 bool writeback = (W == 1) | (P == 0);
4993 addr |= (U << 8) | (Rn << 9);
4995 if (writeback && (Rn == Rt || Rn == Rt2))
4996 Check(S, MCDisassembler::SoftFail);
4998 Check(S, MCDisassembler::SoftFail);
5001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5002 return MCDisassembler::Fail;
5004 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5005 return MCDisassembler::Fail;
5006 // Writeback operand
5007 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5008 return MCDisassembler::Fail;
5010 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5011 return MCDisassembler::Fail;
5017 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5018 uint64_t Address, const void *Decoder) {
5019 DecodeStatus S = MCDisassembler::Success;
5021 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5022 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5023 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5024 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5025 unsigned W = fieldFromInstruction(Insn, 21, 1);
5026 unsigned U = fieldFromInstruction(Insn, 23, 1);
5027 unsigned P = fieldFromInstruction(Insn, 24, 1);
5028 bool writeback = (W == 1) | (P == 0);
5030 addr |= (U << 8) | (Rn << 9);
5032 if (writeback && (Rn == Rt || Rn == Rt2))
5033 Check(S, MCDisassembler::SoftFail);
5035 // Writeback operand
5036 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5037 return MCDisassembler::Fail;
5039 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5040 return MCDisassembler::Fail;
5042 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5043 return MCDisassembler::Fail;
5045 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5046 return MCDisassembler::Fail;
5051 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5052 uint64_t Address, const void *Decoder) {
5053 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5054 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5055 if (sign1 != sign2) return MCDisassembler::Fail;
5057 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5058 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5059 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5061 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5063 return MCDisassembler::Success;
5066 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5068 const void *Decoder) {
5069 DecodeStatus S = MCDisassembler::Success;
5071 // Shift of "asr #32" is not allowed in Thumb2 mode.
5072 if (Val == 0x20) S = MCDisassembler::Fail;
5073 Inst.addOperand(MCOperand::createImm(Val));
5077 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5078 uint64_t Address, const void *Decoder) {
5079 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5080 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5081 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5082 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5085 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5087 DecodeStatus S = MCDisassembler::Success;
5089 if (Rt == Rn || Rn == Rt2)
5090 S = MCDisassembler::SoftFail;
5092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5093 return MCDisassembler::Fail;
5094 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5095 return MCDisassembler::Fail;
5096 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5097 return MCDisassembler::Fail;
5098 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5099 return MCDisassembler::Fail;
5104 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5105 uint64_t Address, const void *Decoder) {
5106 const FeatureBitset &featureBits =
5107 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5108 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5110 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5111 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5112 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5113 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5114 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5115 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5116 unsigned op = fieldFromInstruction(Insn, 5, 1);
5118 DecodeStatus S = MCDisassembler::Success;
5120 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5121 if (!(imm & 0x38)) {
5123 if (op == 1) return MCDisassembler::Fail;
5124 Inst.setOpcode(ARM::VMOVv2f32);
5129 Inst.setOpcode(ARM::VMOVv1i64);
5131 Inst.setOpcode(ARM::VMOVv8i8);
5136 Inst.setOpcode(ARM::VMVNv2i32);
5138 Inst.setOpcode(ARM::VMOVv2i32);
5143 Inst.setOpcode(ARM::VMVNv2i32);
5145 Inst.setOpcode(ARM::VMOVv2i32);
5149 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5152 if (!(imm & 0x20)) return MCDisassembler::Fail;
5154 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5155 return MCDisassembler::Fail;
5156 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5157 return MCDisassembler::Fail;
5158 Inst.addOperand(MCOperand::createImm(64 - imm));
5163 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5164 uint64_t Address, const void *Decoder) {
5165 const FeatureBitset &featureBits =
5166 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5167 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5169 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5170 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5171 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5172 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5173 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5174 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5175 unsigned op = fieldFromInstruction(Insn, 5, 1);
5177 DecodeStatus S = MCDisassembler::Success;
5179 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5180 if (!(imm & 0x38)) {
5182 if (op == 1) return MCDisassembler::Fail;
5183 Inst.setOpcode(ARM::VMOVv4f32);
5188 Inst.setOpcode(ARM::VMOVv2i64);
5190 Inst.setOpcode(ARM::VMOVv16i8);
5195 Inst.setOpcode(ARM::VMVNv4i32);
5197 Inst.setOpcode(ARM::VMOVv4i32);
5202 Inst.setOpcode(ARM::VMVNv4i32);
5204 Inst.setOpcode(ARM::VMOVv4i32);
5208 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5211 if (!(imm & 0x20)) return MCDisassembler::Fail;
5213 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5214 return MCDisassembler::Fail;
5215 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5216 return MCDisassembler::Fail;
5217 Inst.addOperand(MCOperand::createImm(64 - imm));
5222 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5225 const void *Decoder) {
5226 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5227 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5228 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5229 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5230 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5231 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5232 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5233 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5235 DecodeStatus S = MCDisassembler::Success;
5237 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5239 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5240 return MCDisassembler::Fail;
5241 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5242 return MCDisassembler::Fail;
5243 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5244 return MCDisassembler::Fail;
5245 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5246 return MCDisassembler::Fail;
5247 // The lane index does not have any bits in the encoding, because it can only
5249 Inst.addOperand(MCOperand::createImm(0));
5250 Inst.addOperand(MCOperand::createImm(rotate));
5255 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5256 uint64_t Address, const void *Decoder) {
5257 DecodeStatus S = MCDisassembler::Success;
5259 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5260 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5261 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5262 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5263 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5265 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5266 S = MCDisassembler::SoftFail;
5268 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5269 return MCDisassembler::Fail;
5270 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5271 return MCDisassembler::Fail;
5272 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5273 return MCDisassembler::Fail;
5274 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5275 return MCDisassembler::Fail;
5276 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5277 return MCDisassembler::Fail;
5282 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5283 uint64_t Address, const void *Decoder) {
5284 DecodeStatus S = MCDisassembler::Success;
5286 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5287 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5288 unsigned cop = fieldFromInstruction(Val, 8, 4);
5289 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5290 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5292 if ((cop & ~0x1) == 0xa)
5293 return MCDisassembler::Fail;
5296 S = MCDisassembler::SoftFail;
5298 // We have to check if the instruction is MRRC2
5299 // or MCRR2 when constructing the operands for
5300 // Inst. Reason is because MRRC2 stores to two
5301 // registers so it's tablegen desc has has two
5302 // outputs whereas MCRR doesn't store to any
5303 // registers so all of it's operands are listed
5304 // as inputs, therefore the operand order for
5305 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5306 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5308 if (Inst.getOpcode() == ARM::MRRC2) {
5309 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5310 return MCDisassembler::Fail;
5311 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5312 return MCDisassembler::Fail;
5314 Inst.addOperand(MCOperand::createImm(cop));
5315 Inst.addOperand(MCOperand::createImm(opc1));
5316 if (Inst.getOpcode() == ARM::MCRR2) {
5317 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5318 return MCDisassembler::Fail;
5319 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5320 return MCDisassembler::Fail;
5322 Inst.addOperand(MCOperand::createImm(CRm));
5327 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5329 const void *Decoder) {
5330 const FeatureBitset &featureBits =
5331 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5332 DecodeStatus S = MCDisassembler::Success;
5334 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5336 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5337 if (Rt == 13 || Rt == 15)
5338 S = MCDisassembler::SoftFail;
5339 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5341 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5343 if (featureBits[ARM::ModeThumb]) {
5344 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5345 Inst.addOperand(MCOperand::createReg(0));
5347 unsigned pred = fieldFromInstruction(Val, 28, 4);
5348 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5349 return MCDisassembler::Fail;