1 //===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM addressing mode implementation stuff.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/bit.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/MathExtras.h"
26 /// ARM_AM - ARM Addressing Mode Stuff
42 inline const char *getAddrOpcStr(AddrOpc Op) { return Op == sub ? "-" : ""; }
44 inline const char *getShiftOpcStr(ShiftOpc Op) {
46 default: llvm_unreachable("Unknown shift opc!");
47 case ARM_AM::asr: return "asr";
48 case ARM_AM::lsl: return "lsl";
49 case ARM_AM::lsr: return "lsr";
50 case ARM_AM::ror: return "ror";
51 case ARM_AM::rrx: return "rrx";
55 inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
57 default: llvm_unreachable("Unknown shift opc!");
58 case ARM_AM::asr: return 2;
59 case ARM_AM::lsl: return 0;
60 case ARM_AM::lsr: return 1;
61 case ARM_AM::ror: return 3;
73 inline const char *getAMSubModeStr(AMSubMode Mode) {
75 default: llvm_unreachable("Unknown addressing sub-mode!");
76 case ARM_AM::ia: return "ia";
77 case ARM_AM::ib: return "ib";
78 case ARM_AM::da: return "da";
79 case ARM_AM::db: return "db";
83 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
85 inline unsigned rotr32(unsigned Val, unsigned Amt) {
86 assert(Amt < 32 && "Invalid rotate amount");
87 return (Val >> Amt) | (Val << ((32-Amt)&31));
90 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
92 inline unsigned rotl32(unsigned Val, unsigned Amt) {
93 assert(Amt < 32 && "Invalid rotate amount");
94 return (Val << Amt) | (Val >> ((32-Amt)&31));
97 //===--------------------------------------------------------------------===//
98 // Addressing Mode #1: shift_operand with registers
99 //===--------------------------------------------------------------------===//
101 // This 'addressing mode' is used for arithmetic instructions. It can
102 // represent things like:
104 // reg [asr|lsl|lsr|ror|rrx] reg
105 // reg [asr|lsl|lsr|ror|rrx] imm
107 // This is stored three operands [rega, regb, opc]. The first is the base
108 // reg, the second is the shift amount (or reg0 if not present or imm). The
109 // third operand encodes the shift opcode and the imm if a reg isn't present.
111 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
112 return ShOp | (Imm << 3);
114 inline unsigned getSORegOffset(unsigned Op) { return Op >> 3; }
115 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); }
117 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
118 /// the 8-bit imm value.
119 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; }
120 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
121 /// the rotate amount.
122 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; }
124 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
125 /// computing the rotate amount to use. If this immediate value cannot be
126 /// handled with a single shifter-op, determine a good rotate amount that will
127 /// take a maximal chunk of bits out of the immediate.
128 inline unsigned getSOImmValRotate(unsigned Imm) {
129 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
131 if ((Imm & ~255U) == 0) return 0;
133 // Use CTZ to compute the rotate amount.
134 unsigned TZ = countTrailingZeros(Imm);
136 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
138 unsigned RotAmt = TZ & ~1;
140 // If we can handle this spread, return it.
141 if ((rotr32(Imm, RotAmt) & ~255U) == 0)
142 return (32-RotAmt)&31; // HW rotates right, not left.
144 // For values like 0xF000000F, we should ignore the low 6 bits, then
147 unsigned TZ2 = countTrailingZeros(Imm & ~63U);
148 unsigned RotAmt2 = TZ2 & ~1;
149 if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
150 return (32-RotAmt2)&31; // HW rotates right, not left.
153 // Otherwise, we have no way to cover this span of bits with a single
154 // shifter_op immediate. Return a chunk of bits that will be useful to
156 return (32-RotAmt)&31; // HW rotates right, not left.
159 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
160 /// into an shifter_operand immediate operand, return the 12-bit encoding for
161 /// it. If not, return -1.
162 inline int getSOImmVal(unsigned Arg) {
163 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
165 if ((Arg & ~255U) == 0) return Arg;
167 unsigned RotAmt = getSOImmValRotate(Arg);
169 // If this cannot be handled with a single shifter_op, bail out.
170 if (rotr32(~255U, RotAmt) & Arg)
173 // Encode this correctly.
174 return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
177 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
178 /// or'ing together two SOImmVal's.
179 inline bool isSOImmTwoPartVal(unsigned V) {
180 // If this can be handled with a single shifter_op, bail out.
181 V = rotr32(~255U, getSOImmValRotate(V)) & V;
185 // If this can be handled with two shifter_op's, accept.
186 V = rotr32(~255U, getSOImmValRotate(V)) & V;
190 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
191 /// return the first chunk of it.
192 inline unsigned getSOImmTwoPartFirst(unsigned V) {
193 return rotr32(255U, getSOImmValRotate(V)) & V;
196 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
197 /// return the second chunk of it.
198 inline unsigned getSOImmTwoPartSecond(unsigned V) {
199 // Mask out the first hunk.
200 V = rotr32(~255U, getSOImmValRotate(V)) & V;
203 assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
207 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
208 /// by a left shift. Returns the shift amount to use.
209 inline unsigned getThumbImmValShift(unsigned Imm) {
210 // 8-bit (or less) immediates are trivially immediate operand with a shift
212 if ((Imm & ~255U) == 0) return 0;
214 // Use CTZ to compute the shift amount.
215 return countTrailingZeros(Imm);
218 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
219 /// by left shifting a 8-bit immediate.
220 inline bool isThumbImmShiftedVal(unsigned V) {
221 // If this can be handled with
222 V = (~255U << getThumbImmValShift(V)) & V;
226 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
227 /// by a left shift. Returns the shift amount to use.
228 inline unsigned getThumbImm16ValShift(unsigned Imm) {
229 // 16-bit (or less) immediates are trivially immediate operand with a shift
231 if ((Imm & ~65535U) == 0) return 0;
233 // Use CTZ to compute the shift amount.
234 return countTrailingZeros(Imm);
237 /// isThumbImm16ShiftedVal - Return true if the specified value can be
238 /// obtained by left shifting a 16-bit immediate.
239 inline bool isThumbImm16ShiftedVal(unsigned V) {
240 // If this can be handled with
241 V = (~65535U << getThumbImm16ValShift(V)) & V;
245 /// getThumbImmNonShiftedVal - If V is a value that satisfies
246 /// isThumbImmShiftedVal, return the non-shiftd value.
247 inline unsigned getThumbImmNonShiftedVal(unsigned V) {
248 return V >> getThumbImmValShift(V);
252 /// getT2SOImmValSplat - Return the 12-bit encoded representation
253 /// if the specified value can be obtained by splatting the low 8 bits
254 /// into every other byte or every byte of a 32-bit value. i.e.,
255 /// 00000000 00000000 00000000 abcdefgh control = 0
256 /// 00000000 abcdefgh 00000000 abcdefgh control = 1
257 /// abcdefgh 00000000 abcdefgh 00000000 control = 2
258 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
259 /// Return -1 if none of the above apply.
260 /// See ARM Reference Manual A6.3.2.
261 inline int getT2SOImmValSplatVal(unsigned V) {
264 if ((V & 0xffffff00) == 0)
267 // If the value is zeroes in the first byte, just shift those off
268 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
269 // Any passing value only has 8 bits of payload, splatted across the word
271 // Likewise, any passing values have the payload splatted into the 3rd byte
272 u = Imm | (Imm << 16);
276 return (((Vs == V) ? 1 : 2) << 8) | Imm;
279 if (Vs == (u | (u << 8)))
280 return (3 << 8) | Imm;
285 /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
286 /// specified value is a rotated 8-bit value. Return -1 if no rotation
287 /// encoding is possible.
288 /// See ARM Reference Manual A6.3.2.
289 inline int getT2SOImmValRotateVal(unsigned V) {
290 unsigned RotAmt = countLeadingZeros(V);
294 // If 'Arg' can be handled with a single shifter_op return the value.
295 if ((rotr32(0xff000000U, RotAmt) & V) == V)
296 return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
301 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
302 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
303 /// encoding for it. If not, return -1.
304 /// See ARM Reference Manual A6.3.2.
305 inline int getT2SOImmVal(unsigned Arg) {
306 // If 'Arg' is an 8-bit splat, then get the encoded value.
307 int Splat = getT2SOImmValSplatVal(Arg);
311 // If 'Arg' can be handled with a single shifter_op return the value.
312 int Rot = getT2SOImmValRotateVal(Arg);
319 inline unsigned getT2SOImmValRotate(unsigned V) {
320 if ((V & ~255U) == 0) return 0;
321 // Use CTZ to compute the rotate amount.
322 unsigned RotAmt = countTrailingZeros(V);
323 return (32 - RotAmt) & 31;
326 inline bool isT2SOImmTwoPartVal(unsigned Imm) {
328 // Passing values can be any combination of splat values and shifter
329 // values. If this can be handled with a single shifter or splat, bail
330 // out. Those should be handled directly, not with a two-part val.
331 if (getT2SOImmValSplatVal(V) != -1)
333 V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
337 // If this can be handled as an immediate, accept.
338 if (getT2SOImmVal(V) != -1) return true;
340 // Likewise, try masking out a splat value first.
342 if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
344 else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
346 // If what's left can be handled as an immediate, accept.
347 if (getT2SOImmVal(V) != -1) return true;
349 // Otherwise, do not accept.
353 inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
354 assert (isT2SOImmTwoPartVal(Imm) &&
355 "Immedate cannot be encoded as two part immediate!");
356 // Try a shifter operand as one part
357 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
358 // If the rest is encodable as an immediate, then return it.
359 if (getT2SOImmVal(V) != -1) return V;
361 // Try masking out a splat value first.
362 if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
363 return Imm & 0xff00ff00U;
365 // The other splat is all that's left as an option.
366 assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
367 return Imm & 0x00ff00ffU;
370 inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
371 // Mask out the first hunk
372 Imm ^= getT2SOImmTwoPartFirst(Imm);
373 // Return what's left
374 assert (getT2SOImmVal(Imm) != -1 &&
375 "Unable to encode second part of T2 two part SO immediate");
380 //===--------------------------------------------------------------------===//
381 // Addressing Mode #2
382 //===--------------------------------------------------------------------===//
384 // This is used for most simple load/store instructions.
386 // addrmode2 := reg +/- reg shop imm
387 // addrmode2 := reg +/- imm12
389 // The first operand is always a Reg. The second operand is a reg if in
390 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
391 // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
392 // fourth operand 16-17 encodes the index mode.
394 // If this addressing mode is a frame index (before prolog/epilog insertion
395 // and code rewriting), this operand will have the form: FI#, reg0, <offs>
396 // with no shift amount for the frame offset.
398 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
399 unsigned IdxMode = 0) {
400 assert(Imm12 < (1 << 12) && "Imm too large!");
401 bool isSub = Opc == sub;
402 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
404 inline unsigned getAM2Offset(unsigned AM2Opc) {
405 return AM2Opc & ((1 << 12)-1);
407 inline AddrOpc getAM2Op(unsigned AM2Opc) {
408 return ((AM2Opc >> 12) & 1) ? sub : add;
410 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
411 return (ShiftOpc)((AM2Opc >> 13) & 7);
413 inline unsigned getAM2IdxMode(unsigned AM2Opc) { return (AM2Opc >> 16); }
415 //===--------------------------------------------------------------------===//
416 // Addressing Mode #3
417 //===--------------------------------------------------------------------===//
419 // This is used for sign-extending loads, and load/store-pair instructions.
421 // addrmode3 := reg +/- reg
422 // addrmode3 := reg +/- imm8
424 // The first operand is always a Reg. The second operand is a reg if in
425 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
426 // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
429 /// getAM3Opc - This function encodes the addrmode3 opc field.
430 inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
431 unsigned IdxMode = 0) {
432 bool isSub = Opc == sub;
433 return ((int)isSub << 8) | Offset | (IdxMode << 9);
435 inline unsigned char getAM3Offset(unsigned AM3Opc) { return AM3Opc & 0xFF; }
436 inline AddrOpc getAM3Op(unsigned AM3Opc) {
437 return ((AM3Opc >> 8) & 1) ? sub : add;
439 inline unsigned getAM3IdxMode(unsigned AM3Opc) { return (AM3Opc >> 9); }
441 //===--------------------------------------------------------------------===//
442 // Addressing Mode #4
443 //===--------------------------------------------------------------------===//
445 // This is used for load / store multiple instructions.
447 // addrmode4 := reg, <mode>
449 // The four modes are:
450 // IA - Increment after
451 // IB - Increment before
452 // DA - Decrement after
453 // DB - Decrement before
454 // For VFP instructions, only the IA and DB modes are valid.
456 inline AMSubMode getAM4SubMode(unsigned Mode) {
457 return (AMSubMode)(Mode & 0x7);
460 inline unsigned getAM4ModeImm(AMSubMode SubMode) { return (int)SubMode; }
462 //===--------------------------------------------------------------------===//
463 // Addressing Mode #5
464 //===--------------------------------------------------------------------===//
466 // This is used for coprocessor instructions, such as FP load/stores.
468 // addrmode5 := reg +/- imm8*4
470 // The first operand is always a Reg. The second operand encodes the
471 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
473 /// getAM5Opc - This function encodes the addrmode5 opc field.
474 inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
475 bool isSub = Opc == sub;
476 return ((int)isSub << 8) | Offset;
478 inline unsigned char getAM5Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; }
479 inline AddrOpc getAM5Op(unsigned AM5Opc) {
480 return ((AM5Opc >> 8) & 1) ? sub : add;
483 //===--------------------------------------------------------------------===//
484 // Addressing Mode #5 FP16
485 //===--------------------------------------------------------------------===//
487 // This is used for coprocessor instructions, such as 16-bit FP load/stores.
489 // addrmode5fp16 := reg +/- imm8*2
491 // The first operand is always a Reg. The second operand encodes the
492 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
494 /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
495 inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) {
496 bool isSub = Opc == sub;
497 return ((int)isSub << 8) | Offset;
499 inline unsigned char getAM5FP16Offset(unsigned AM5Opc) {
500 return AM5Opc & 0xFF;
502 inline AddrOpc getAM5FP16Op(unsigned AM5Opc) {
503 return ((AM5Opc >> 8) & 1) ? sub : add;
506 //===--------------------------------------------------------------------===//
507 // Addressing Mode #6
508 //===--------------------------------------------------------------------===//
510 // This is used for NEON load / store instructions.
512 // addrmode6 := reg with optional alignment
514 // This is stored in two operands [regaddr, align]. The first is the
515 // address register. The second operand is the value of the alignment
516 // specifier in bytes or zero if no explicit alignment.
517 // Valid alignments depend on the specific instruction.
519 //===--------------------------------------------------------------------===//
520 // NEON Modified Immediates
521 //===--------------------------------------------------------------------===//
523 // Several NEON instructions (e.g., VMOV) take a "modified immediate"
524 // vector operand, where a small immediate encoded in the instruction
525 // specifies a full NEON vector value. These modified immediates are
526 // represented here as encoded integers. The low 8 bits hold the immediate
527 // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
528 // the "Cmode" field of the instruction. The interfaces below treat the
529 // Op and Cmode values as a single 5-bit value.
531 inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) {
532 return (OpCmode << 8) | Val;
534 inline unsigned getNEONModImmOpCmode(unsigned ModImm) {
535 return (ModImm >> 8) & 0x1f;
537 inline unsigned getNEONModImmVal(unsigned ModImm) { return ModImm & 0xff; }
539 /// decodeNEONModImm - Decode a NEON modified immediate value into the
540 /// element value and the element size in bits. (If the element size is
541 /// smaller than the vector, it is splatted into all the elements.)
542 inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) {
543 unsigned OpCmode = getNEONModImmOpCmode(ModImm);
544 unsigned Imm8 = getNEONModImmVal(ModImm);
547 if (OpCmode == 0xe) {
548 // 8-bit vector elements
551 } else if ((OpCmode & 0xc) == 0x8) {
552 // 16-bit vector elements
553 unsigned ByteNum = (OpCmode & 0x6) >> 1;
554 Val = Imm8 << (8 * ByteNum);
556 } else if ((OpCmode & 0x8) == 0) {
557 // 32-bit vector elements, zero with one byte set
558 unsigned ByteNum = (OpCmode & 0x6) >> 1;
559 Val = Imm8 << (8 * ByteNum);
561 } else if ((OpCmode & 0xe) == 0xc) {
562 // 32-bit vector elements, one byte with low bits set
563 unsigned ByteNum = 1 + (OpCmode & 0x1);
564 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
566 } else if (OpCmode == 0x1e) {
567 // 64-bit vector elements
568 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
569 if ((ModImm >> ByteNum) & 1)
570 Val |= (uint64_t)0xff << (8 * ByteNum);
574 llvm_unreachable("Unsupported NEON immediate");
579 // Generic validation for single-byte immediate (0X00, 00X0, etc).
580 inline bool isNEONBytesplat(unsigned Value, unsigned Size) {
581 assert(Size >= 1 && Size <= 4 && "Invalid size");
583 for (unsigned i = 0; i < Size; ++i) {
584 if (Value & 0xff) count++;
590 /// Checks if Value is a correct immediate for instructions like VBIC/VORR.
591 inline bool isNEONi16splat(unsigned Value) {
594 // i16 value with set bits only in one byte X0 or 0X.
595 return Value == 0 || isNEONBytesplat(Value, 2);
598 // Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
599 inline unsigned encodeNEONi16splat(unsigned Value) {
600 assert(isNEONi16splat(Value) && "Invalid NEON splat value");
602 Value = (Value >> 8) | 0xa00;
608 /// Checks if Value is a correct immediate for instructions like VBIC/VORR.
609 inline bool isNEONi32splat(unsigned Value) {
610 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
611 return Value == 0 || isNEONBytesplat(Value, 4);
614 /// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
615 inline unsigned encodeNEONi32splat(unsigned Value) {
616 assert(isNEONi32splat(Value) && "Invalid NEON splat value");
617 if (Value >= 0x100 && Value <= 0xff00)
618 Value = (Value >> 8) | 0x200;
619 else if (Value > 0xffff && Value <= 0xff0000)
620 Value = (Value >> 16) | 0x400;
621 else if (Value > 0xffffff)
622 Value = (Value >> 24) | 0x600;
626 //===--------------------------------------------------------------------===//
627 // Floating-point Immediates
629 inline float getFPImmFloat(unsigned Imm) {
630 // We expect an 8-bit binary encoding of a floating-point number here.
632 uint8_t Sign = (Imm >> 7) & 0x1;
633 uint8_t Exp = (Imm >> 4) & 0x7;
634 uint8_t Mantissa = Imm & 0xf;
636 // 8-bit FP IEEE Float Encoding
637 // abcd efgh aBbbbbbc defgh000 00000000 00000000
642 I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
643 I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
644 I |= (Exp & 0x3) << 23;
646 return bit_cast<float>(I);
649 /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
650 /// floating-point value. If the value cannot be represented as an 8-bit
651 /// floating-point value, then return -1.
652 inline int getFP16Imm(const APInt &Imm) {
653 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
654 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15
655 int64_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits
657 // We can handle 4 bits of mantissa.
658 // mantissa = (16+UInt(e:f:g:h))/16.
663 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
664 if (Exp < -3 || Exp > 4)
666 Exp = ((Exp+3) & 0x7) ^ 4;
668 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
671 inline int getFP16Imm(const APFloat &FPImm) {
672 return getFP16Imm(FPImm.bitcastToAPInt());
675 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
676 /// floating-point value. If the value cannot be represented as an 8-bit
677 /// floating-point value, then return -1.
678 inline int getFP32Imm(const APInt &Imm) {
679 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
680 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
681 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
683 // We can handle 4 bits of mantissa.
684 // mantissa = (16+UInt(e:f:g:h))/16.
685 if (Mantissa & 0x7ffff)
688 if ((Mantissa & 0xf) != Mantissa)
691 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
692 if (Exp < -3 || Exp > 4)
694 Exp = ((Exp+3) & 0x7) ^ 4;
696 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
699 inline int getFP32Imm(const APFloat &FPImm) {
700 return getFP32Imm(FPImm.bitcastToAPInt());
703 /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
704 /// floating-point value. If the value cannot be represented as an 8-bit
705 /// floating-point value, then return -1.
706 inline int getFP64Imm(const APInt &Imm) {
707 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
708 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
709 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
711 // We can handle 4 bits of mantissa.
712 // mantissa = (16+UInt(e:f:g:h))/16.
713 if (Mantissa & 0xffffffffffffULL)
716 if ((Mantissa & 0xf) != Mantissa)
719 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
720 if (Exp < -3 || Exp > 4)
722 Exp = ((Exp+3) & 0x7) ^ 4;
724 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
727 inline int getFP64Imm(const APFloat &FPImm) {
728 return getFP64Imm(FPImm.bitcastToAPInt());
731 } // end namespace ARM_AM
732 } // end namespace llvm