1 //===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM addressing mode implementation stuff.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/MathExtras.h"
25 /// ARM_AM - ARM Addressing Mode Stuff
41 inline const char *getAddrOpcStr(AddrOpc Op) { return Op == sub ? "-" : ""; }
43 inline const char *getShiftOpcStr(ShiftOpc Op) {
45 default: llvm_unreachable("Unknown shift opc!");
46 case ARM_AM::asr: return "asr";
47 case ARM_AM::lsl: return "lsl";
48 case ARM_AM::lsr: return "lsr";
49 case ARM_AM::ror: return "ror";
50 case ARM_AM::rrx: return "rrx";
54 inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
56 default: llvm_unreachable("Unknown shift opc!");
57 case ARM_AM::asr: return 2;
58 case ARM_AM::lsl: return 0;
59 case ARM_AM::lsr: return 1;
60 case ARM_AM::ror: return 3;
72 inline const char *getAMSubModeStr(AMSubMode Mode) {
74 default: llvm_unreachable("Unknown addressing sub-mode!");
75 case ARM_AM::ia: return "ia";
76 case ARM_AM::ib: return "ib";
77 case ARM_AM::da: return "da";
78 case ARM_AM::db: return "db";
82 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
84 inline unsigned rotr32(unsigned Val, unsigned Amt) {
85 assert(Amt < 32 && "Invalid rotate amount");
86 return (Val >> Amt) | (Val << ((32-Amt)&31));
89 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
91 inline unsigned rotl32(unsigned Val, unsigned Amt) {
92 assert(Amt < 32 && "Invalid rotate amount");
93 return (Val << Amt) | (Val >> ((32-Amt)&31));
96 //===--------------------------------------------------------------------===//
97 // Addressing Mode #1: shift_operand with registers
98 //===--------------------------------------------------------------------===//
100 // This 'addressing mode' is used for arithmetic instructions. It can
101 // represent things like:
103 // reg [asr|lsl|lsr|ror|rrx] reg
104 // reg [asr|lsl|lsr|ror|rrx] imm
106 // This is stored three operands [rega, regb, opc]. The first is the base
107 // reg, the second is the shift amount (or reg0 if not present or imm). The
108 // third operand encodes the shift opcode and the imm if a reg isn't present.
110 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
111 return ShOp | (Imm << 3);
113 inline unsigned getSORegOffset(unsigned Op) { return Op >> 3; }
114 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); }
116 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
117 /// the 8-bit imm value.
118 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; }
119 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
120 /// the rotate amount.
121 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; }
123 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
124 /// computing the rotate amount to use. If this immediate value cannot be
125 /// handled with a single shifter-op, determine a good rotate amount that will
126 /// take a maximal chunk of bits out of the immediate.
127 inline unsigned getSOImmValRotate(unsigned Imm) {
128 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
130 if ((Imm & ~255U) == 0) return 0;
132 // Use CTZ to compute the rotate amount.
133 unsigned TZ = countTrailingZeros(Imm);
135 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
137 unsigned RotAmt = TZ & ~1;
139 // If we can handle this spread, return it.
140 if ((rotr32(Imm, RotAmt) & ~255U) == 0)
141 return (32-RotAmt)&31; // HW rotates right, not left.
143 // For values like 0xF000000F, we should ignore the low 6 bits, then
146 unsigned TZ2 = countTrailingZeros(Imm & ~63U);
147 unsigned RotAmt2 = TZ2 & ~1;
148 if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
149 return (32-RotAmt2)&31; // HW rotates right, not left.
152 // Otherwise, we have no way to cover this span of bits with a single
153 // shifter_op immediate. Return a chunk of bits that will be useful to
155 return (32-RotAmt)&31; // HW rotates right, not left.
158 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
159 /// into an shifter_operand immediate operand, return the 12-bit encoding for
160 /// it. If not, return -1.
161 inline int getSOImmVal(unsigned Arg) {
162 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
164 if ((Arg & ~255U) == 0) return Arg;
166 unsigned RotAmt = getSOImmValRotate(Arg);
168 // If this cannot be handled with a single shifter_op, bail out.
169 if (rotr32(~255U, RotAmt) & Arg)
172 // Encode this correctly.
173 return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
176 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
177 /// or'ing together two SOImmVal's.
178 inline bool isSOImmTwoPartVal(unsigned V) {
179 // If this can be handled with a single shifter_op, bail out.
180 V = rotr32(~255U, getSOImmValRotate(V)) & V;
184 // If this can be handled with two shifter_op's, accept.
185 V = rotr32(~255U, getSOImmValRotate(V)) & V;
189 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
190 /// return the first chunk of it.
191 inline unsigned getSOImmTwoPartFirst(unsigned V) {
192 return rotr32(255U, getSOImmValRotate(V)) & V;
195 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
196 /// return the second chunk of it.
197 inline unsigned getSOImmTwoPartSecond(unsigned V) {
198 // Mask out the first hunk.
199 V = rotr32(~255U, getSOImmValRotate(V)) & V;
202 assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
206 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
207 /// by a left shift. Returns the shift amount to use.
208 inline unsigned getThumbImmValShift(unsigned Imm) {
209 // 8-bit (or less) immediates are trivially immediate operand with a shift
211 if ((Imm & ~255U) == 0) return 0;
213 // Use CTZ to compute the shift amount.
214 return countTrailingZeros(Imm);
217 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
218 /// by left shifting a 8-bit immediate.
219 inline bool isThumbImmShiftedVal(unsigned V) {
220 // If this can be handled with
221 V = (~255U << getThumbImmValShift(V)) & V;
225 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
226 /// by a left shift. Returns the shift amount to use.
227 inline unsigned getThumbImm16ValShift(unsigned Imm) {
228 // 16-bit (or less) immediates are trivially immediate operand with a shift
230 if ((Imm & ~65535U) == 0) return 0;
232 // Use CTZ to compute the shift amount.
233 return countTrailingZeros(Imm);
236 /// isThumbImm16ShiftedVal - Return true if the specified value can be
237 /// obtained by left shifting a 16-bit immediate.
238 inline bool isThumbImm16ShiftedVal(unsigned V) {
239 // If this can be handled with
240 V = (~65535U << getThumbImm16ValShift(V)) & V;
244 /// getThumbImmNonShiftedVal - If V is a value that satisfies
245 /// isThumbImmShiftedVal, return the non-shiftd value.
246 inline unsigned getThumbImmNonShiftedVal(unsigned V) {
247 return V >> getThumbImmValShift(V);
251 /// getT2SOImmValSplat - Return the 12-bit encoded representation
252 /// if the specified value can be obtained by splatting the low 8 bits
253 /// into every other byte or every byte of a 32-bit value. i.e.,
254 /// 00000000 00000000 00000000 abcdefgh control = 0
255 /// 00000000 abcdefgh 00000000 abcdefgh control = 1
256 /// abcdefgh 00000000 abcdefgh 00000000 control = 2
257 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
258 /// Return -1 if none of the above apply.
259 /// See ARM Reference Manual A6.3.2.
260 inline int getT2SOImmValSplatVal(unsigned V) {
263 if ((V & 0xffffff00) == 0)
266 // If the value is zeroes in the first byte, just shift those off
267 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
268 // Any passing value only has 8 bits of payload, splatted across the word
270 // Likewise, any passing values have the payload splatted into the 3rd byte
271 u = Imm | (Imm << 16);
275 return (((Vs == V) ? 1 : 2) << 8) | Imm;
278 if (Vs == (u | (u << 8)))
279 return (3 << 8) | Imm;
284 /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
285 /// specified value is a rotated 8-bit value. Return -1 if no rotation
286 /// encoding is possible.
287 /// See ARM Reference Manual A6.3.2.
288 inline int getT2SOImmValRotateVal(unsigned V) {
289 unsigned RotAmt = countLeadingZeros(V);
293 // If 'Arg' can be handled with a single shifter_op return the value.
294 if ((rotr32(0xff000000U, RotAmt) & V) == V)
295 return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
300 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
301 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
302 /// encoding for it. If not, return -1.
303 /// See ARM Reference Manual A6.3.2.
304 inline int getT2SOImmVal(unsigned Arg) {
305 // If 'Arg' is an 8-bit splat, then get the encoded value.
306 int Splat = getT2SOImmValSplatVal(Arg);
310 // If 'Arg' can be handled with a single shifter_op return the value.
311 int Rot = getT2SOImmValRotateVal(Arg);
318 inline unsigned getT2SOImmValRotate(unsigned V) {
319 if ((V & ~255U) == 0) return 0;
320 // Use CTZ to compute the rotate amount.
321 unsigned RotAmt = countTrailingZeros(V);
322 return (32 - RotAmt) & 31;
325 inline bool isT2SOImmTwoPartVal(unsigned Imm) {
327 // Passing values can be any combination of splat values and shifter
328 // values. If this can be handled with a single shifter or splat, bail
329 // out. Those should be handled directly, not with a two-part val.
330 if (getT2SOImmValSplatVal(V) != -1)
332 V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
336 // If this can be handled as an immediate, accept.
337 if (getT2SOImmVal(V) != -1) return true;
339 // Likewise, try masking out a splat value first.
341 if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
343 else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
345 // If what's left can be handled as an immediate, accept.
346 if (getT2SOImmVal(V) != -1) return true;
348 // Otherwise, do not accept.
352 inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
353 assert (isT2SOImmTwoPartVal(Imm) &&
354 "Immedate cannot be encoded as two part immediate!");
355 // Try a shifter operand as one part
356 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
357 // If the rest is encodable as an immediate, then return it.
358 if (getT2SOImmVal(V) != -1) return V;
360 // Try masking out a splat value first.
361 if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
362 return Imm & 0xff00ff00U;
364 // The other splat is all that's left as an option.
365 assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
366 return Imm & 0x00ff00ffU;
369 inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
370 // Mask out the first hunk
371 Imm ^= getT2SOImmTwoPartFirst(Imm);
372 // Return what's left
373 assert (getT2SOImmVal(Imm) != -1 &&
374 "Unable to encode second part of T2 two part SO immediate");
379 //===--------------------------------------------------------------------===//
380 // Addressing Mode #2
381 //===--------------------------------------------------------------------===//
383 // This is used for most simple load/store instructions.
385 // addrmode2 := reg +/- reg shop imm
386 // addrmode2 := reg +/- imm12
388 // The first operand is always a Reg. The second operand is a reg if in
389 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
390 // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
391 // fourth operand 16-17 encodes the index mode.
393 // If this addressing mode is a frame index (before prolog/epilog insertion
394 // and code rewriting), this operand will have the form: FI#, reg0, <offs>
395 // with no shift amount for the frame offset.
397 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
398 unsigned IdxMode = 0) {
399 assert(Imm12 < (1 << 12) && "Imm too large!");
400 bool isSub = Opc == sub;
401 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
403 inline unsigned getAM2Offset(unsigned AM2Opc) {
404 return AM2Opc & ((1 << 12)-1);
406 inline AddrOpc getAM2Op(unsigned AM2Opc) {
407 return ((AM2Opc >> 12) & 1) ? sub : add;
409 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
410 return (ShiftOpc)((AM2Opc >> 13) & 7);
412 inline unsigned getAM2IdxMode(unsigned AM2Opc) { return (AM2Opc >> 16); }
414 //===--------------------------------------------------------------------===//
415 // Addressing Mode #3
416 //===--------------------------------------------------------------------===//
418 // This is used for sign-extending loads, and load/store-pair instructions.
420 // addrmode3 := reg +/- reg
421 // addrmode3 := reg +/- imm8
423 // The first operand is always a Reg. The second operand is a reg if in
424 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
425 // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
428 /// getAM3Opc - This function encodes the addrmode3 opc field.
429 inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
430 unsigned IdxMode = 0) {
431 bool isSub = Opc == sub;
432 return ((int)isSub << 8) | Offset | (IdxMode << 9);
434 inline unsigned char getAM3Offset(unsigned AM3Opc) { return AM3Opc & 0xFF; }
435 inline AddrOpc getAM3Op(unsigned AM3Opc) {
436 return ((AM3Opc >> 8) & 1) ? sub : add;
438 inline unsigned getAM3IdxMode(unsigned AM3Opc) { return (AM3Opc >> 9); }
440 //===--------------------------------------------------------------------===//
441 // Addressing Mode #4
442 //===--------------------------------------------------------------------===//
444 // This is used for load / store multiple instructions.
446 // addrmode4 := reg, <mode>
448 // The four modes are:
449 // IA - Increment after
450 // IB - Increment before
451 // DA - Decrement after
452 // DB - Decrement before
453 // For VFP instructions, only the IA and DB modes are valid.
455 inline AMSubMode getAM4SubMode(unsigned Mode) {
456 return (AMSubMode)(Mode & 0x7);
459 inline unsigned getAM4ModeImm(AMSubMode SubMode) { return (int)SubMode; }
461 //===--------------------------------------------------------------------===//
462 // Addressing Mode #5
463 //===--------------------------------------------------------------------===//
465 // This is used for coprocessor instructions, such as FP load/stores.
467 // addrmode5 := reg +/- imm8*4
469 // The first operand is always a Reg. The second operand encodes the
470 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
472 /// getAM5Opc - This function encodes the addrmode5 opc field.
473 inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
474 bool isSub = Opc == sub;
475 return ((int)isSub << 8) | Offset;
477 inline unsigned char getAM5Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; }
478 inline AddrOpc getAM5Op(unsigned AM5Opc) {
479 return ((AM5Opc >> 8) & 1) ? sub : add;
482 //===--------------------------------------------------------------------===//
483 // Addressing Mode #5 FP16
484 //===--------------------------------------------------------------------===//
486 // This is used for coprocessor instructions, such as 16-bit FP load/stores.
488 // addrmode5fp16 := reg +/- imm8*2
490 // The first operand is always a Reg. The second operand encodes the
491 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
493 /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
494 inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) {
495 bool isSub = Opc == sub;
496 return ((int)isSub << 8) | Offset;
498 inline unsigned char getAM5FP16Offset(unsigned AM5Opc) {
499 return AM5Opc & 0xFF;
501 inline AddrOpc getAM5FP16Op(unsigned AM5Opc) {
502 return ((AM5Opc >> 8) & 1) ? sub : add;
505 //===--------------------------------------------------------------------===//
506 // Addressing Mode #6
507 //===--------------------------------------------------------------------===//
509 // This is used for NEON load / store instructions.
511 // addrmode6 := reg with optional alignment
513 // This is stored in two operands [regaddr, align]. The first is the
514 // address register. The second operand is the value of the alignment
515 // specifier in bytes or zero if no explicit alignment.
516 // Valid alignments depend on the specific instruction.
518 //===--------------------------------------------------------------------===//
519 // NEON Modified Immediates
520 //===--------------------------------------------------------------------===//
522 // Several NEON instructions (e.g., VMOV) take a "modified immediate"
523 // vector operand, where a small immediate encoded in the instruction
524 // specifies a full NEON vector value. These modified immediates are
525 // represented here as encoded integers. The low 8 bits hold the immediate
526 // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
527 // the "Cmode" field of the instruction. The interfaces below treat the
528 // Op and Cmode values as a single 5-bit value.
530 inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) {
531 return (OpCmode << 8) | Val;
533 inline unsigned getNEONModImmOpCmode(unsigned ModImm) {
534 return (ModImm >> 8) & 0x1f;
536 inline unsigned getNEONModImmVal(unsigned ModImm) { return ModImm & 0xff; }
538 /// decodeNEONModImm - Decode a NEON modified immediate value into the
539 /// element value and the element size in bits. (If the element size is
540 /// smaller than the vector, it is splatted into all the elements.)
541 inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) {
542 unsigned OpCmode = getNEONModImmOpCmode(ModImm);
543 unsigned Imm8 = getNEONModImmVal(ModImm);
546 if (OpCmode == 0xe) {
547 // 8-bit vector elements
550 } else if ((OpCmode & 0xc) == 0x8) {
551 // 16-bit vector elements
552 unsigned ByteNum = (OpCmode & 0x6) >> 1;
553 Val = Imm8 << (8 * ByteNum);
555 } else if ((OpCmode & 0x8) == 0) {
556 // 32-bit vector elements, zero with one byte set
557 unsigned ByteNum = (OpCmode & 0x6) >> 1;
558 Val = Imm8 << (8 * ByteNum);
560 } else if ((OpCmode & 0xe) == 0xc) {
561 // 32-bit vector elements, one byte with low bits set
562 unsigned ByteNum = 1 + (OpCmode & 0x1);
563 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
565 } else if (OpCmode == 0x1e) {
566 // 64-bit vector elements
567 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
568 if ((ModImm >> ByteNum) & 1)
569 Val |= (uint64_t)0xff << (8 * ByteNum);
573 llvm_unreachable("Unsupported NEON immediate");
578 // Generic validation for single-byte immediate (0X00, 00X0, etc).
579 inline bool isNEONBytesplat(unsigned Value, unsigned Size) {
580 assert(Size >= 1 && Size <= 4 && "Invalid size");
582 for (unsigned i = 0; i < Size; ++i) {
583 if (Value & 0xff) count++;
589 /// Checks if Value is a correct immediate for instructions like VBIC/VORR.
590 inline bool isNEONi16splat(unsigned Value) {
593 // i16 value with set bits only in one byte X0 or 0X.
594 return Value == 0 || isNEONBytesplat(Value, 2);
597 // Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
598 inline unsigned encodeNEONi16splat(unsigned Value) {
599 assert(isNEONi16splat(Value) && "Invalid NEON splat value");
601 Value = (Value >> 8) | 0xa00;
607 /// Checks if Value is a correct immediate for instructions like VBIC/VORR.
608 inline bool isNEONi32splat(unsigned Value) {
609 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
610 return Value == 0 || isNEONBytesplat(Value, 4);
613 /// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
614 inline unsigned encodeNEONi32splat(unsigned Value) {
615 assert(isNEONi32splat(Value) && "Invalid NEON splat value");
616 if (Value >= 0x100 && Value <= 0xff00)
617 Value = (Value >> 8) | 0x200;
618 else if (Value > 0xffff && Value <= 0xff0000)
619 Value = (Value >> 16) | 0x400;
620 else if (Value > 0xffffff)
621 Value = (Value >> 24) | 0x600;
625 //===--------------------------------------------------------------------===//
626 // Floating-point Immediates
628 inline float getFPImmFloat(unsigned Imm) {
629 // We expect an 8-bit binary encoding of a floating-point number here.
635 uint8_t Sign = (Imm >> 7) & 0x1;
636 uint8_t Exp = (Imm >> 4) & 0x7;
637 uint8_t Mantissa = Imm & 0xf;
639 // 8-bit FP iEEEE Float Encoding
640 // abcd efgh aBbbbbbc defgh000 00000000 00000000
645 FPUnion.I |= Sign << 31;
646 FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
647 FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
648 FPUnion.I |= (Exp & 0x3) << 23;
649 FPUnion.I |= Mantissa << 19;
653 /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
654 /// floating-point value. If the value cannot be represented as an 8-bit
655 /// floating-point value, then return -1.
656 inline int getFP16Imm(const APInt &Imm) {
657 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
658 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15
659 int64_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits
661 // We can handle 4 bits of mantissa.
662 // mantissa = (16+UInt(e:f:g:h))/16.
667 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
668 if (Exp < -3 || Exp > 4)
670 Exp = ((Exp+3) & 0x7) ^ 4;
672 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
675 inline int getFP16Imm(const APFloat &FPImm) {
676 return getFP16Imm(FPImm.bitcastToAPInt());
679 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
680 /// floating-point value. If the value cannot be represented as an 8-bit
681 /// floating-point value, then return -1.
682 inline int getFP32Imm(const APInt &Imm) {
683 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
684 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
685 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
687 // We can handle 4 bits of mantissa.
688 // mantissa = (16+UInt(e:f:g:h))/16.
689 if (Mantissa & 0x7ffff)
692 if ((Mantissa & 0xf) != Mantissa)
695 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
696 if (Exp < -3 || Exp > 4)
698 Exp = ((Exp+3) & 0x7) ^ 4;
700 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
703 inline int getFP32Imm(const APFloat &FPImm) {
704 return getFP32Imm(FPImm.bitcastToAPInt());
707 /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
708 /// floating-point value. If the value cannot be represented as an 8-bit
709 /// floating-point value, then return -1.
710 inline int getFP64Imm(const APInt &Imm) {
711 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
712 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
713 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
715 // We can handle 4 bits of mantissa.
716 // mantissa = (16+UInt(e:f:g:h))/16.
717 if (Mantissa & 0xffffffffffffULL)
720 if ((Mantissa & 0xf) != Mantissa)
723 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
724 if (Exp < -3 || Exp > 4)
726 Exp = ((Exp+3) & 0x7) ^ 4;
728 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
731 inline int getFP64Imm(const APFloat &FPImm) {
732 return getFP64Imm(FPImm.bitcastToAPInt());
735 } // end namespace ARM_AM
736 } // end namespace llvm