1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
18 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
20 #include "ARMMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "Utils/ARMBaseInfo.h"
38 inline static const char *IFlagsToString(unsigned val) {
40 default: llvm_unreachable("Unknown iflags operand");
47 inline static const char *IModToString(unsigned val) {
49 default: llvm_unreachable("Unknown imod operand");
57 // The Memory Barrier Option constants map directly to the 4-bit encoding of
58 // the option field for memory barrier operations.
78 inline static const char *MemBOptToString(unsigned val, bool HasV8) {
80 default: llvm_unreachable("Unknown memory operation");
83 case LD: return HasV8 ? "ld" : "#0xd";
84 case RESERVED_12: return "#0xc";
85 case ISH: return "ish";
86 case ISHST: return "ishst";
87 case ISHLD: return HasV8 ? "ishld" : "#0x9";
88 case RESERVED_8: return "#0x8";
89 case NSH: return "nsh";
90 case NSHST: return "nshst";
91 case NSHLD: return HasV8 ? "nshld" : "#0x5";
92 case RESERVED_4: return "#0x4";
93 case OSH: return "osh";
94 case OSHST: return "oshst";
95 case OSHLD: return HasV8 ? "oshld" : "#0x1";
96 case RESERVED_0: return "#0x0";
106 inline static const char *TraceSyncBOptToString(unsigned val) {
109 llvm_unreachable("Unknown trace synchronization barrier operation");
110 case CSYNC: return "csync";
113 } // namespace ARM_TSB
135 inline static const char *InstSyncBOptToString(unsigned val) {
138 llvm_unreachable("Unknown memory operation");
139 case RESERVED_0: return "#0x0";
140 case RESERVED_1: return "#0x1";
141 case RESERVED_2: return "#0x2";
142 case RESERVED_3: return "#0x3";
143 case RESERVED_4: return "#0x4";
144 case RESERVED_5: return "#0x5";
145 case RESERVED_6: return "#0x6";
146 case RESERVED_7: return "#0x7";
147 case RESERVED_8: return "#0x8";
148 case RESERVED_9: return "#0x9";
149 case RESERVED_10: return "#0xa";
150 case RESERVED_11: return "#0xb";
151 case RESERVED_12: return "#0xc";
152 case RESERVED_13: return "#0xd";
153 case RESERVED_14: return "#0xe";
154 case SY: return "sy";
157 } // namespace ARM_ISB
159 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
161 static inline bool isARMLowRegister(unsigned Reg) {
164 case R0: case R1: case R2: case R3:
165 case R4: case R5: case R6: case R7:
172 /// ARMII - This namespace holds all of the target specific flags that
173 /// instruction info tracks.
185 /// ARM Addressing Modes
197 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
201 AddrModeT2_pc = 14, // +/- i12 for pc relative data
202 AddrModeT2_i8s4 = 15, // i8 * 4
204 AddrMode5FP16 = 17, // i8 * 2
205 AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
208 inline static const char *AddrModeToString(AddrMode addrmode) {
210 case AddrModeNone: return "AddrModeNone";
211 case AddrMode1: return "AddrMode1";
212 case AddrMode2: return "AddrMode2";
213 case AddrMode3: return "AddrMode3";
214 case AddrMode4: return "AddrMode4";
215 case AddrMode5: return "AddrMode5";
216 case AddrMode5FP16: return "AddrMode5FP16";
217 case AddrMode6: return "AddrMode6";
218 case AddrModeT1_1: return "AddrModeT1_1";
219 case AddrModeT1_2: return "AddrModeT1_2";
220 case AddrModeT1_4: return "AddrModeT1_4";
221 case AddrModeT1_s: return "AddrModeT1_s";
222 case AddrModeT2_i12: return "AddrModeT2_i12";
223 case AddrModeT2_i8: return "AddrModeT2_i8";
224 case AddrModeT2_so: return "AddrModeT2_so";
225 case AddrModeT2_pc: return "AddrModeT2_pc";
226 case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
227 case AddrMode_i12: return "AddrMode_i12";
228 case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
232 /// Target Operand Flag enum.
234 //===------------------------------------------------------------------===//
235 // ARM Specific MachineOperand flags.
239 /// MO_LO16 - On a symbol operand, this represents a relocation containing
240 /// lower 16 bit of the address. Used only via movw instruction.
243 /// MO_HI16 - On a symbol operand, this represents a relocation containing
244 /// higher 16 bit of the address. Used only via movt instruction.
247 /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
248 /// just that part of the flag set.
249 MO_OPTION_MASK = 0x3,
251 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
252 /// reference is actually to the ".refptrp.FOO" symbol. This is used for
253 /// stub symbols on windows.
256 /// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
259 /// MO_SBREL - On a symbol operand, this represents a static base relative
260 /// relocation. Used in movw and movt instructions.
263 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
264 /// to the symbol is for an import stub. This is used for DLL import
265 /// storage class indication on Windows.
268 /// MO_SECREL - On a symbol operand this indicates that the immediate is
269 /// the offset from beginning of section.
271 /// This is the TLS offset for the COFF/Windows TLS mechanism.
274 /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
275 /// represents a symbol which, if indirect, will get special Darwin mangling
276 /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
277 /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
281 // It's undefined behaviour if an enum overflows the range between its
282 // smallest and largest values, but since these are |ed together, it can
283 // happen. Put a sentinel in (values of this enum are stored as "unsigned
285 MO_UNUSED_MAXIMUM = 0xff
289 //===------------------------------------------------------------------===//
290 // Instruction Flags.
292 //===------------------------------------------------------------------===//
293 // This four-bit field describes the addressing mode used.
294 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
296 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
297 // and store ops only. Generic "updating" flag is used for ld/st multiple.
298 // The index mode enums are declared in ARMBaseInfo.h
300 IndexModeMask = 3 << IndexModeShift,
302 //===------------------------------------------------------------------===//
303 // Instruction encoding formats.
306 FormMask = 0x3f << FormShift,
308 // Pseudo instructions
309 Pseudo = 0 << FormShift,
311 // Multiply instructions
312 MulFrm = 1 << FormShift,
314 // Branch instructions
315 BrFrm = 2 << FormShift,
316 BrMiscFrm = 3 << FormShift,
318 // Data Processing instructions
319 DPFrm = 4 << FormShift,
320 DPSoRegFrm = 5 << FormShift,
323 LdFrm = 6 << FormShift,
324 StFrm = 7 << FormShift,
325 LdMiscFrm = 8 << FormShift,
326 StMiscFrm = 9 << FormShift,
327 LdStMulFrm = 10 << FormShift,
329 LdStExFrm = 11 << FormShift,
331 // Miscellaneous arithmetic instructions
332 ArithMiscFrm = 12 << FormShift,
333 SatFrm = 13 << FormShift,
335 // Extend instructions
336 ExtFrm = 14 << FormShift,
339 VFPUnaryFrm = 15 << FormShift,
340 VFPBinaryFrm = 16 << FormShift,
341 VFPConv1Frm = 17 << FormShift,
342 VFPConv2Frm = 18 << FormShift,
343 VFPConv3Frm = 19 << FormShift,
344 VFPConv4Frm = 20 << FormShift,
345 VFPConv5Frm = 21 << FormShift,
346 VFPLdStFrm = 22 << FormShift,
347 VFPLdStMulFrm = 23 << FormShift,
348 VFPMiscFrm = 24 << FormShift,
351 ThumbFrm = 25 << FormShift,
353 // Miscelleaneous format
354 MiscFrm = 26 << FormShift,
357 NGetLnFrm = 27 << FormShift,
358 NSetLnFrm = 28 << FormShift,
359 NDupFrm = 29 << FormShift,
360 NLdStFrm = 30 << FormShift,
361 N1RegModImmFrm= 31 << FormShift,
362 N2RegFrm = 32 << FormShift,
363 NVCVTFrm = 33 << FormShift,
364 NVDupLnFrm = 34 << FormShift,
365 N2RegVShLFrm = 35 << FormShift,
366 N2RegVShRFrm = 36 << FormShift,
367 N3RegFrm = 37 << FormShift,
368 N3RegVShFrm = 38 << FormShift,
369 NVExtFrm = 39 << FormShift,
370 NVMulSLFrm = 40 << FormShift,
371 NVTBLFrm = 41 << FormShift,
372 N3RegCplxFrm = 43 << FormShift,
374 //===------------------------------------------------------------------===//
377 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
378 // it doesn't have a Rn operand.
381 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
382 // a 16-bit Thumb instruction if certain conditions are met.
383 Xform16Bit = 1 << 14,
385 // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
386 // instruction. Used by the parser to determine whether to require the 'S'
387 // suffix on the mnemonic (when not in an IT block) or preclude it (when
389 ThumbArithFlagSetting = 1 << 18,
391 //===------------------------------------------------------------------===//
394 DomainMask = 7 << DomainShift,
395 DomainGeneral = 0 << DomainShift,
396 DomainVFP = 1 << DomainShift,
397 DomainNEON = 2 << DomainShift,
398 DomainNEONA8 = 4 << DomainShift,
400 //===------------------------------------------------------------------===//
401 // Field shifts - such shifts are used to set field while generating
402 // machine instructions.
404 // FIXME: This list will need adjusting/fixing as the MC code emitter
405 // takes shape and the ARMCodeEmitter.cpp bits go away.
430 } // end namespace ARMII
432 } // end namespace llvm;