contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

   1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18 #include <string>
  19
  20 namespace llvm {
  21 class formatted_raw_ostream;
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInstrInfo;
  26 class MCInstPrinter;
  27 class MCObjectWriter;
  28 class MCRegisterInfo;
  29 class MCSubtargetInfo;
  30 class MCStreamer;
  31 class MCTargetOptions;
  32 class MCRelocationInfo;
  33 class MCTargetStreamer;
  34 class StringRef;
  35 class Target;
  36 class Triple;
  37 class raw_ostream;
  38 class raw_pwrite_stream;
  39
  40 Target &getTheARMLETarget();
  41 Target &getTheThumbLETarget();
  42 Target &getTheARMBETarget();
  43 Target &getTheThumbBETarget();
  44
  45 namespace ARM_MC {
  46 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
  47
  48 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
  49 /// do not need to go through TargetRegistry.
  50 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
  51                                           StringRef FS);
  52 }
  53
  54 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
  55 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
  56                                              formatted_raw_ostream &OS,
  57                                              MCInstPrinter *InstPrint,
  58                                              bool isVerboseAsm);
  59 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
  60                                                 const MCSubtargetInfo &STI);
  61
  62 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
  63                                         const MCRegisterInfo &MRI,
  64                                         MCContext &Ctx);
  65
  66 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
  67                                         const MCRegisterInfo &MRI,
  68                                         MCContext &Ctx);
  69
  70 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  71                                   const Triple &TT, StringRef CPU,
  72                                   const MCTargetOptions &Options,
  73                                   bool IsLittleEndian);
  74
  75 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  76                                     const Triple &TT, StringRef CPU,
  77                                     const MCTargetOptions &Options);
  78
  79 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  80                                     const Triple &TT, StringRef CPU,
  81                                     const MCTargetOptions &Options);
  82
  83 MCAsmBackend *createThumbLEAsmBackend(const Target &T,
  84                                       const MCRegisterInfo &MRI,
  85                                       const Triple &TT, StringRef CPU,
  86                                       const MCTargetOptions &Options);
  87
  88 MCAsmBackend *createThumbBEAsmBackend(const Target &T,
  89                                       const MCRegisterInfo &MRI,
  90                                       const Triple &TT, StringRef CPU,
  91                                       const MCTargetOptions &Options);
  92
  93 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
  94 // object file.
  95 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
  96                                      raw_pwrite_stream &OS,
  97                                      MCCodeEmitter *Emitter, bool RelaxAll,
  98                                      bool IncrementalLinkerCompatible);
  99
 100 /// Construct an ELF Mach-O object writer.
 101 MCObjectWriter *createARMELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
 102                                          bool IsLittleEndian);
 103
 104 /// Construct an ARM Mach-O object writer.
 105 MCObjectWriter *createARMMachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
 106                                           uint32_t CPUType,
 107                                           uint32_t CPUSubtype);
 108
 109 /// Construct an ARM PE/COFF object writer.
 110 MCObjectWriter *createARMWinCOFFObjectWriter(raw_pwrite_stream &OS,
 111                                              bool Is64Bit);
 112
 113 /// Construct ARM Mach-O relocation info.
 114 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
 115 } // End llvm namespace
 116
 117 // Defines symbolic names for ARM registers.  This defines a mapping from
 118 // register name to register number.
 119 //
 120 #define GET_REGINFO_ENUM
 121 #include "ARMGenRegisterInfo.inc"
 122
 123 // Defines symbolic names for the ARM instructions.
 124 //
 125 #define GET_INSTRINFO_ENUM
 126 #include "ARMGenInstrInfo.inc"
 127
 128 #define GET_SUBTARGETINFO_ENUM
 129 #include "ARMGenSubtargetInfo.inc"
 130
 131 #endif