1 //===-- ARMMachObjectWriter.cpp - ARM Mach Object Writer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMFixupKinds.h"
12 #include "MCTargetDesc/ARMMCTargetDesc.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/BinaryFormat/MachO.h"
15 #include "llvm/MC/MCAsmLayout.h"
16 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCFixupKindInfo.h"
21 #include "llvm/MC/MCMachObjectWriter.h"
22 #include "llvm/MC/MCSection.h"
23 #include "llvm/MC/MCValue.h"
24 #include "llvm/Support/ErrorHandling.h"
28 class ARMMachObjectWriter : public MCMachObjectTargetWriter {
29 void RecordARMScatteredRelocation(MachObjectWriter *Writer,
30 const MCAssembler &Asm,
31 const MCAsmLayout &Layout,
32 const MCFragment *Fragment,
37 uint64_t &FixedValue);
38 void RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
39 const MCAssembler &Asm,
40 const MCAsmLayout &Layout,
41 const MCFragment *Fragment,
42 const MCFixup &Fixup, MCValue Target,
43 uint64_t &FixedValue);
45 bool requiresExternRelocation(MachObjectWriter *Writer,
46 const MCAssembler &Asm,
47 const MCFragment &Fragment, unsigned RelocType,
48 const MCSymbol &S, uint64_t FixedValue);
51 ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
52 : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
54 void recordRelocation(MachObjectWriter *Writer, MCAssembler &Asm,
55 const MCAsmLayout &Layout, const MCFragment *Fragment,
56 const MCFixup &Fixup, MCValue Target,
57 uint64_t &FixedValue) override;
61 static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
63 RelocType = unsigned(MachO::ARM_RELOC_VANILLA);
71 Log2Size = llvm::Log2_32(1);
74 Log2Size = llvm::Log2_32(2);
77 Log2Size = llvm::Log2_32(4);
80 Log2Size = llvm::Log2_32(8);
83 // These fixups are expected to always be resolvable at assembly time and
84 // have no relocations supported.
85 case ARM::fixup_arm_ldst_pcrel_12:
86 case ARM::fixup_arm_pcrel_10:
87 case ARM::fixup_arm_adr_pcrel_12:
88 case ARM::fixup_arm_thumb_br:
91 // Handle 24-bit branch kinds.
92 case ARM::fixup_arm_condbranch:
93 case ARM::fixup_arm_uncondbranch:
94 case ARM::fixup_arm_uncondbl:
95 case ARM::fixup_arm_condbl:
96 case ARM::fixup_arm_blx:
97 RelocType = unsigned(MachO::ARM_RELOC_BR24);
98 // Report as 'long', even though that is not quite accurate.
99 Log2Size = llvm::Log2_32(4);
102 case ARM::fixup_t2_uncondbranch:
103 case ARM::fixup_arm_thumb_bl:
104 case ARM::fixup_arm_thumb_blx:
105 RelocType = unsigned(MachO::ARM_THUMB_RELOC_BR22);
106 Log2Size = llvm::Log2_32(4);
109 // For movw/movt r_type relocations they always have a pair following them and
110 // the r_length bits are used differently. The encoding of the r_length is as
112 // low bit of r_length:
113 // 0 - :lower16: for movw instructions
114 // 1 - :upper16: for movt instructions
115 // high bit of r_length:
116 // 0 - arm instructions
117 // 1 - thumb instructions
118 case ARM::fixup_arm_movt_hi16:
119 RelocType = unsigned(MachO::ARM_RELOC_HALF);
122 case ARM::fixup_t2_movt_hi16:
123 RelocType = unsigned(MachO::ARM_RELOC_HALF);
127 case ARM::fixup_arm_movw_lo16:
128 RelocType = unsigned(MachO::ARM_RELOC_HALF);
131 case ARM::fixup_t2_movw_lo16:
132 RelocType = unsigned(MachO::ARM_RELOC_HALF);
138 void ARMMachObjectWriter::
139 RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
140 const MCAssembler &Asm,
141 const MCAsmLayout &Layout,
142 const MCFragment *Fragment,
143 const MCFixup &Fixup,
145 uint64_t &FixedValue) {
146 uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
147 unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
148 unsigned Type = MachO::ARM_RELOC_HALF;
151 const MCSymbol *A = &Target.getSymA()->getSymbol();
153 if (!A->getFragment()) {
154 Asm.getContext().reportError(Fixup.getLoc(),
155 "symbol '" + A->getName() +
156 "' can not be undefined in a subtraction expression");
160 uint32_t Value = Writer->getSymbolAddress(*A, Layout);
162 uint64_t SecAddr = Writer->getSectionAddress(A->getFragment()->getParent());
163 FixedValue += SecAddr;
165 if (const MCSymbolRefExpr *B = Target.getSymB()) {
166 const MCSymbol *SB = &B->getSymbol();
168 if (!SB->getFragment()) {
169 Asm.getContext().reportError(Fixup.getLoc(),
170 "symbol '" + B->getSymbol().getName() +
171 "' can not be undefined in a subtraction expression");
175 // Select the appropriate difference relocation type.
176 Type = MachO::ARM_RELOC_HALF_SECTDIFF;
177 Value2 = Writer->getSymbolAddress(B->getSymbol(), Layout);
178 FixedValue -= Writer->getSectionAddress(SB->getFragment()->getParent());
181 // Relocations are written out in reverse order, so the PAIR comes first.
182 // ARM_RELOC_HALF and ARM_RELOC_HALF_SECTDIFF abuse the r_length field:
184 // For these two r_type relocations they always have a pair following them and
185 // the r_length bits are used differently. The encoding of the r_length is as
187 // low bit of r_length:
188 // 0 - :lower16: for movw instructions
189 // 1 - :upper16: for movt instructions
190 // high bit of r_length:
191 // 0 - arm instructions
192 // 1 - thumb instructions
193 // the other half of the relocated expression is in the following pair
194 // relocation entry in the low 16 bits of r_address field.
195 unsigned ThumbBit = 0;
196 unsigned MovtBit = 0;
197 switch ((unsigned)Fixup.getKind()) {
199 case ARM::fixup_arm_movt_hi16:
201 // The thumb bit shouldn't be set in the 'other-half' bit of the
202 // relocation, but it will be set in FixedValue if the base symbol
203 // is a thumb function. Clear it out here.
204 if (Asm.isThumbFunc(A))
205 FixedValue &= 0xfffffffe;
207 case ARM::fixup_t2_movt_hi16:
208 if (Asm.isThumbFunc(A))
209 FixedValue &= 0xfffffffe;
212 case ARM::fixup_t2_movw_lo16:
217 if (Type == MachO::ARM_RELOC_HALF_SECTDIFF) {
218 uint32_t OtherHalf = MovtBit
219 ? (FixedValue & 0xffff) : ((FixedValue & 0xffff0000) >> 16);
221 MachO::any_relocation_info MRE;
222 MRE.r_word0 = ((OtherHalf << 0) |
223 (MachO::ARM_RELOC_PAIR << 24) |
228 MRE.r_word1 = Value2;
229 Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
232 MachO::any_relocation_info MRE;
233 MRE.r_word0 = ((FixupOffset << 0) |
240 Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
243 void ARMMachObjectWriter::RecordARMScatteredRelocation(MachObjectWriter *Writer,
244 const MCAssembler &Asm,
245 const MCAsmLayout &Layout,
246 const MCFragment *Fragment,
247 const MCFixup &Fixup,
251 uint64_t &FixedValue) {
252 uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
253 unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
256 const MCSymbol *A = &Target.getSymA()->getSymbol();
258 if (!A->getFragment()) {
259 Asm.getContext().reportError(Fixup.getLoc(),
260 "symbol '" + A->getName() +
261 "' can not be undefined in a subtraction expression");
265 uint32_t Value = Writer->getSymbolAddress(*A, Layout);
266 uint64_t SecAddr = Writer->getSectionAddress(A->getFragment()->getParent());
267 FixedValue += SecAddr;
270 if (const MCSymbolRefExpr *B = Target.getSymB()) {
271 assert(Type == MachO::ARM_RELOC_VANILLA && "invalid reloc for 2 symbols");
272 const MCSymbol *SB = &B->getSymbol();
274 if (!SB->getFragment()) {
275 Asm.getContext().reportError(Fixup.getLoc(),
276 "symbol '" + B->getSymbol().getName() +
277 "' can not be undefined in a subtraction expression");
281 // Select the appropriate difference relocation type.
282 Type = MachO::ARM_RELOC_SECTDIFF;
283 Value2 = Writer->getSymbolAddress(B->getSymbol(), Layout);
284 FixedValue -= Writer->getSectionAddress(SB->getFragment()->getParent());
287 // Relocations are written out in reverse order, so the PAIR comes first.
288 if (Type == MachO::ARM_RELOC_SECTDIFF ||
289 Type == MachO::ARM_RELOC_LOCAL_SECTDIFF) {
290 MachO::any_relocation_info MRE;
291 MRE.r_word0 = ((0 << 0) |
292 (MachO::ARM_RELOC_PAIR << 24) |
296 MRE.r_word1 = Value2;
297 Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
300 MachO::any_relocation_info MRE;
301 MRE.r_word0 = ((FixupOffset << 0) |
307 Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
310 bool ARMMachObjectWriter::requiresExternRelocation(MachObjectWriter *Writer,
311 const MCAssembler &Asm,
312 const MCFragment &Fragment,
315 uint64_t FixedValue) {
316 // Most cases can be identified purely from the symbol.
317 if (Writer->doesSymbolRequireExternRelocation(S))
319 int64_t Value = (int64_t)FixedValue; // The displacement is signed.
324 case MachO::ARM_RELOC_BR24:
325 // An ARM call might be to a Thumb function, in which case the offset may
326 // not be encodable in the instruction and we must use an external
327 // relocation that explicitly mentions the function. Not a problem if it's
328 // to a temporary "Lwhatever" symbol though, and in fact trying to use an
329 // external relocation there causes more issues.
330 if (!S.isTemporary())
333 // PC pre-adjustment of 8 for these instructions.
335 // ARM BL/BLX has a 25-bit offset.
338 case MachO::ARM_THUMB_RELOC_BR22:
339 // PC pre-adjustment of 4 for these instructions.
341 // Thumb BL/BLX has a 24-bit offset.
344 // BL/BLX also use external relocations when an internal relocation
345 // would result in the target being out of range. This gives the linker
346 // enough information to generate a branch island.
347 Value += Writer->getSectionAddress(&S.getSection());
348 Value -= Writer->getSectionAddress(Fragment.getParent());
349 // If the resultant value would be out of range for an internal relocation,
350 // use an external instead.
351 if (Value > Range || Value < -(Range + 1))
356 void ARMMachObjectWriter::recordRelocation(MachObjectWriter *Writer,
358 const MCAsmLayout &Layout,
359 const MCFragment *Fragment,
360 const MCFixup &Fixup, MCValue Target,
361 uint64_t &FixedValue) {
362 unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
364 unsigned RelocType = MachO::ARM_RELOC_VANILLA;
365 if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size)) {
366 // If we failed to get fixup kind info, it's because there's no legal
367 // relocation type for the fixup kind. This happens when it's a fixup that's
368 // expected to always be resolvable at assembly time and not have any
369 // relocations needed.
370 Asm.getContext().reportError(Fixup.getLoc(),
371 "unsupported relocation on symbol");
375 // If this is a difference or a defined symbol plus an offset, then we need a
376 // scattered relocation entry. Differences always require scattered
378 if (Target.getSymB()) {
379 if (RelocType == MachO::ARM_RELOC_HALF)
380 return RecordARMScatteredHalfRelocation(Writer, Asm, Layout, Fragment,
381 Fixup, Target, FixedValue);
382 return RecordARMScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
383 Target, RelocType, Log2Size,
387 // Get the symbol data, if any.
388 const MCSymbol *A = nullptr;
389 if (Target.getSymA())
390 A = &Target.getSymA()->getSymbol();
392 // FIXME: For other platforms, we need to use scattered relocations for
393 // internal relocations with offsets. If this is an internal relocation with
394 // an offset, it also needs a scattered relocation entry.
396 // Is this right for ARM?
397 uint32_t Offset = Target.getConstant();
398 if (IsPCRel && RelocType == MachO::ARM_RELOC_VANILLA)
399 Offset += 1 << Log2Size;
400 if (Offset && A && !Writer->doesSymbolRequireExternRelocation(*A) &&
401 RelocType != MachO::ARM_RELOC_HALF)
402 return RecordARMScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
403 Target, RelocType, Log2Size,
407 uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
410 const MCSymbol *RelSymbol = nullptr;
412 if (Target.isAbsolute()) { // constant
414 report_fatal_error("FIXME: relocations to absolute targets "
415 "not yet implemented");
417 // Resolve constant variables.
418 if (A->isVariable()) {
420 if (A->getVariableValue()->evaluateAsAbsolute(
421 Res, Layout, Writer->getSectionAddressMap())) {
427 // Check whether we need an external or internal relocation.
428 if (requiresExternRelocation(Writer, Asm, *Fragment, RelocType, *A,
432 // For external relocations, make sure to offset the fixup value to
433 // compensate for the addend of the symbol address, if it was
434 // undefined. This occurs with weak definitions, for example.
435 if (!A->isUndefined())
436 FixedValue -= Layout.getSymbolOffset(*A);
438 // The index is the section ordinal (1-based).
439 const MCSection &Sec = A->getSection();
440 Index = Sec.getOrdinal() + 1;
441 FixedValue += Writer->getSectionAddress(&Sec);
444 FixedValue -= Writer->getSectionAddress(Fragment->getParent());
446 // The type is determined by the fixup kind.
450 // struct relocation_info (8 bytes)
451 MachO::any_relocation_info MRE;
452 MRE.r_word0 = FixupOffset;
454 (Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
456 // Even when it's not a scattered relocation, movw/movt always uses
457 // a PAIR relocation.
458 if (Type == MachO::ARM_RELOC_HALF) {
459 // The entire addend is needed to correctly apply a relocation. One half is
460 // extracted from the instruction itself, the other comes from this
461 // PAIR. I.e. it's correct that we insert the high bits of the addend in the
462 // MOVW case here. relocation entries.
464 switch ((unsigned)Fixup.getKind()) {
466 case ARM::fixup_arm_movw_lo16:
467 case ARM::fixup_t2_movw_lo16:
468 Value = (FixedValue >> 16) & 0xffff;
470 case ARM::fixup_arm_movt_hi16:
471 case ARM::fixup_t2_movt_hi16:
472 Value = FixedValue & 0xffff;
475 MachO::any_relocation_info MREPair;
476 MREPair.r_word0 = Value;
477 MREPair.r_word1 = ((0xffffff << 0) |
479 (MachO::ARM_RELOC_PAIR << 28));
481 Writer->addRelocation(nullptr, Fragment->getParent(), MREPair);
484 Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
487 std::unique_ptr<MCObjectTargetWriter>
488 llvm::createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
489 uint32_t CPUSubtype) {
490 return llvm::make_unique<ARMMachObjectWriter>(Is64Bit, CPUType, CPUSubtype);