1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "MCTargetDesc/ARMBaseInfo.h"
20 #include "Thumb1InstrInfo.h"
21 #include "ThumbRegisterInfo.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/CodeGen/LivePhysRegs.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/DebugLoc.h"
36 #include "llvm/MC/MCDwarf.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetSubtargetInfo.h"
47 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
48 : ARMFrameLowering(sti) {}
50 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
51 const MachineFrameInfo &MFI = MF.getFrameInfo();
52 unsigned CFSize = MFI.getMaxCallFrameSize();
53 // It's not always a good idea to include the call frame as part of the
54 // stack frame. ARM (especially Thumb) has small immediate offset to
55 // address the stack frame. So a large call frame can cause poor codegen
56 // and may even makes it impossible to scavenge a register.
57 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
60 return !MFI.hasVarSizedObjects();
63 static void emitSPUpdate(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator &MBBI,
65 const TargetInstrInfo &TII, const DebugLoc &dl,
66 const ThumbRegisterInfo &MRI, int NumBytes,
67 unsigned MIFlags = MachineInstr::NoFlags) {
68 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
73 MachineBasicBlock::iterator Thumb1FrameLowering::
74 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator I) const {
76 const Thumb1InstrInfo &TII =
77 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
78 const ThumbRegisterInfo *RegInfo =
79 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
80 if (!hasReservedCallFrame(MF)) {
81 // If we have alloca, convert as follows:
82 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
83 // ADJCALLSTACKUP -> add, sp, sp, amount
84 MachineInstr &Old = *I;
85 DebugLoc dl = Old.getDebugLoc();
86 unsigned Amount = TII.getFrameSize(Old);
88 // We need to keep the stack aligned properly. To do this, we round the
89 // amount of space needed for the outgoing arguments up to the next
90 // alignment boundary.
91 Amount = alignTo(Amount, getStackAlignment());
93 // Replace the pseudo instruction with a new instruction...
94 unsigned Opc = Old.getOpcode();
95 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
96 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
98 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
99 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
106 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
107 MachineBasicBlock &MBB) const {
108 MachineBasicBlock::iterator MBBI = MBB.begin();
109 MachineFrameInfo &MFI = MF.getFrameInfo();
110 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
111 MachineModuleInfo &MMI = MF.getMMI();
112 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
113 const ThumbRegisterInfo *RegInfo =
114 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
115 const Thumb1InstrInfo &TII =
116 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
118 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
119 unsigned NumBytes = MFI.getStackSize();
120 assert(NumBytes >= ArgRegsSaveSize &&
121 "ArgRegsSaveSize is included in NumBytes");
122 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
124 // Debug location must be unknown since the first debug location is used
125 // to determine the end of the prologue.
128 unsigned FramePtr = RegInfo->getFrameRegister(MF);
129 unsigned BasePtr = RegInfo->getBaseRegister();
132 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
133 NumBytes = (NumBytes + 3) & ~3;
134 MFI.setStackSize(NumBytes);
136 // Determine the sizes of each callee-save spill areas and record which frame
137 // belongs to which callee-save spill areas.
138 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
139 int FramePtrSpillFI = 0;
141 if (ArgRegsSaveSize) {
142 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
143 MachineInstr::FrameSetup);
144 CFAOffset -= ArgRegsSaveSize;
145 unsigned CFIIndex = MF.addFrameInst(
146 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
147 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
148 .addCFIIndex(CFIIndex)
149 .setMIFlags(MachineInstr::FrameSetup);
152 if (!AFI->hasStackFrame()) {
153 if (NumBytes - ArgRegsSaveSize != 0) {
154 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
155 MachineInstr::FrameSetup);
156 CFAOffset -= NumBytes - ArgRegsSaveSize;
157 unsigned CFIIndex = MF.addFrameInst(
158 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
159 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
160 .addCFIIndex(CFIIndex)
161 .setMIFlags(MachineInstr::FrameSetup);
166 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
167 unsigned Reg = CSI[i].getReg();
168 int FI = CSI[i].getFrameIdx();
174 if (STI.splitFramePushPop(MF)) {
185 FramePtrSpillFI = FI;
193 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
197 // Determine starting offsets of spill areas.
198 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
199 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
200 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
201 bool HasFP = hasFP(MF);
203 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
205 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
206 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
207 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
208 NumBytes = DPRCSOffset;
210 int FramePtrOffsetInBlock = 0;
211 unsigned adjustedGPRCS1Size = GPRCS1Size;
212 if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
213 tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
214 FramePtrOffsetInBlock = NumBytes;
215 adjustedGPRCS1Size += NumBytes;
219 if (adjustedGPRCS1Size) {
220 CFAOffset -= adjustedGPRCS1Size;
221 unsigned CFIIndex = MF.addFrameInst(
222 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
223 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
224 .addCFIIndex(CFIIndex)
225 .setMIFlags(MachineInstr::FrameSetup);
227 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
228 E = CSI.end(); I != E; ++I) {
229 unsigned Reg = I->getReg();
230 int FI = I->getFrameIdx();
237 if (STI.splitFramePushPop(MF))
249 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
250 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
251 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
252 .addCFIIndex(CFIIndex)
253 .setMIFlags(MachineInstr::FrameSetup);
258 // Adjust FP so it point to the stack slot that contains the previous FP.
260 FramePtrOffsetInBlock +=
261 MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
262 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
264 .addImm(FramePtrOffsetInBlock / 4)
265 .setMIFlags(MachineInstr::FrameSetup)
266 .add(predOps(ARMCC::AL));
267 if(FramePtrOffsetInBlock) {
268 CFAOffset += FramePtrOffsetInBlock;
269 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
270 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
271 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
272 .addCFIIndex(CFIIndex)
273 .setMIFlags(MachineInstr::FrameSetup);
276 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
277 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
278 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
279 .addCFIIndex(CFIIndex)
280 .setMIFlags(MachineInstr::FrameSetup);
283 // If offset is > 508 then sp cannot be adjusted in a single instruction,
284 // try restoring from fp instead.
285 AFI->setShouldRestoreSPFromFP(true);
288 // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
289 // and tMOVr instructions. We don't need to add any call frame information
290 // in-between these instructions, because they do not modify the high
293 MachineBasicBlock::iterator OldMBBI = MBBI;
294 // Skip a run of tMOVr instructions
295 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
297 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
300 // We have reached an instruction which is not a push, so the previous
301 // run of tMOVr instructions (which may have been empty) was not part of
302 // the prologue. Reset MBBI back to the last PUSH of the prologue.
308 // Emit call frame information for the callee-saved high registers.
309 for (auto &I : CSI) {
310 unsigned Reg = I.getReg();
311 int FI = I.getFrameIdx();
318 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
319 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
320 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
321 .addCFIIndex(CFIIndex)
322 .setMIFlags(MachineInstr::FrameSetup);
331 // Insert it after all the callee-save spills.
332 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
333 MachineInstr::FrameSetup);
335 CFAOffset -= NumBytes;
336 unsigned CFIIndex = MF.addFrameInst(
337 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
338 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
339 .addCFIIndex(CFIIndex)
340 .setMIFlags(MachineInstr::FrameSetup);
344 if (STI.isTargetELF() && HasFP)
345 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
346 AFI->getFramePtrSpillOffset());
348 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
349 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
350 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
352 // Thumb1 does not currently support dynamic stack realignment. Report a
353 // fatal error rather then silently generate bad code.
354 if (RegInfo->needsStackRealignment(MF))
355 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
357 // If we need a base pointer, set it up here. It's whatever the value
358 // of the stack pointer is at this point. Any variable size objects
359 // will be allocated after this, so we can still use the base pointer
360 // to reference locals.
361 if (RegInfo->hasBasePointer(MF))
362 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
364 .add(predOps(ARMCC::AL));
366 // If the frame has variable sized objects then the epilogue must restore
367 // the sp from fp. We can assume there's an FP here since hasFP already
368 // checks for hasVarSizedObjects.
369 if (MFI.hasVarSizedObjects())
370 AFI->setShouldRestoreSPFromFP(true);
372 // In some cases, virtual registers have been introduced, e.g. by uses of
373 // emitThumbRegPlusImmInReg.
374 MF.getProperties().reset(MachineFunctionProperties::Property::NoVRegs);
377 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
378 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
379 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
381 else if (MI.getOpcode() == ARM::tPOP) {
383 } else if (MI.getOpcode() == ARM::tMOVr) {
384 unsigned Dst = MI.getOperand(0).getReg();
385 unsigned Src = MI.getOperand(1).getReg();
386 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
387 ARM::hGPRRegClass.contains(Dst));
392 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
393 MachineBasicBlock &MBB) const {
394 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
395 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
396 MachineFrameInfo &MFI = MF.getFrameInfo();
397 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
398 const ThumbRegisterInfo *RegInfo =
399 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
400 const Thumb1InstrInfo &TII =
401 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
403 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
404 int NumBytes = (int)MFI.getStackSize();
405 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
406 "ArgRegsSaveSize is included in NumBytes");
407 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
408 unsigned FramePtr = RegInfo->getFrameRegister(MF);
410 if (!AFI->hasStackFrame()) {
411 if (NumBytes - ArgRegsSaveSize != 0)
412 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
414 // Unwind MBBI to point to first LDR / VLDRD.
415 if (MBBI != MBB.begin()) {
418 while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
419 if (!isCSRestore(*MBBI, CSRegs))
423 // Move SP to start of FP callee save spill area.
424 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
425 AFI->getGPRCalleeSavedArea2Size() +
426 AFI->getDPRCalleeSavedAreaSize() +
429 if (AFI->shouldRestoreSPFromFP()) {
430 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
431 // Reset SP based on frame pointer only if the stack frame extends beyond
432 // frame pointer stack slot, the target is ELF and the function has FP, or
433 // the target uses var sized objects.
435 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
436 "No scratch register to restore SP from FP!");
437 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
439 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
441 .add(predOps(ARMCC::AL));
443 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
445 .add(predOps(ARMCC::AL));
447 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
448 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
449 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
450 if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
451 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
452 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
453 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
457 if (needPopSpecialFixUp(MF)) {
458 bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
460 assert(Done && "Emission of the special fixup failed!?");
464 bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
465 if (!needPopSpecialFixUp(*MBB.getParent()))
468 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
469 return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
472 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
473 ARMFunctionInfo *AFI =
474 const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
475 if (AFI->getArgRegsSaveSize())
478 // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
479 for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
480 if (CSI.getReg() == ARM::LR)
486 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
488 MachineFunction &MF = *MBB.getParent();
489 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
490 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
491 const TargetInstrInfo &TII = *STI.getInstrInfo();
492 const ThumbRegisterInfo *RegInfo =
493 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
495 // If MBBI is a return instruction, or is a tPOP followed by a return
496 // instruction in the successor BB, we may be able to directly restore
498 // This is only possible with v5T ops (v4T can't change the Thumb bit via
499 // a POP PC instruction), and only if we do not need to emit any SP update.
500 // Otherwise, we need a temporary register to pop the value
501 // and copy that value into LR.
502 auto MBBI = MBB.getFirstTerminator();
503 bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
504 if (CanRestoreDirectly) {
505 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
506 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
507 MBBI->getOpcode() == ARM::tPOP_RET);
509 auto MBBI_prev = MBBI;
511 assert(MBBI_prev->getOpcode() == ARM::tPOP);
512 assert(MBB.succ_size() == 1);
513 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
514 MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
516 CanRestoreDirectly = false;
520 if (CanRestoreDirectly) {
521 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
523 MachineInstrBuilder MIB =
524 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
525 .add(predOps(ARMCC::AL));
526 // Copy implicit ops and popped registers, if any.
527 for (auto MO: MBBI->operands())
528 if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
530 MIB.addReg(ARM::PC, RegState::Define);
531 // Erase the old instruction (tBX_RET or tPOP).
536 // Look for a temporary register to use.
537 // First, compute the liveness information.
538 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
539 LivePhysRegs UsedRegs(TRI);
540 UsedRegs.addLiveOuts(MBB);
541 // The semantic of pristines changed recently and now,
542 // the callee-saved registers that are touched in the function
543 // are not part of the pristines set anymore.
544 // Add those callee-saved now.
545 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
546 for (unsigned i = 0; CSRegs[i]; ++i)
547 UsedRegs.addReg(CSRegs[i]);
549 DebugLoc dl = DebugLoc();
550 if (MBBI != MBB.end()) {
551 dl = MBBI->getDebugLoc();
552 auto InstUpToMBBI = MBB.end();
553 while (InstUpToMBBI != MBBI)
554 // The pre-decrement is on purpose here.
555 // We want to have the liveness right before MBBI.
556 UsedRegs.stepBackward(*--InstUpToMBBI);
559 // Look for a register that can be directly use in the POP.
561 // And some temporary register, just in case.
562 unsigned TemporaryReg = 0;
563 BitVector PopFriendly =
564 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
565 assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
566 // Rebuild the GPRs from the high registers because they are removed
567 // form the GPR reg class for thumb1.
568 BitVector GPRsNoLRSP =
569 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
570 GPRsNoLRSP |= PopFriendly;
571 GPRsNoLRSP.reset(ARM::LR);
572 GPRsNoLRSP.reset(ARM::SP);
573 GPRsNoLRSP.reset(ARM::PC);
574 for (unsigned Register : GPRsNoLRSP.set_bits()) {
575 if (!UsedRegs.contains(Register)) {
576 // Remember the first pop-friendly register and exit.
577 if (PopFriendly.test(Register)) {
582 // Otherwise, remember that the register will be available to
583 // save a pop-friendly register.
584 TemporaryReg = Register;
588 if (!DoIt && !PopReg && !TemporaryReg)
591 assert((PopReg || TemporaryReg) && "Cannot get LR");
594 assert(!PopReg && "Unnecessary MOV is about to be inserted");
595 PopReg = PopFriendly.find_first();
596 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
597 .addReg(TemporaryReg, RegState::Define)
598 .addReg(PopReg, RegState::Kill)
599 .add(predOps(ARMCC::AL));
602 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
603 // We couldn't use the direct restoration above, so
604 // perform the opposite conversion: tPOP_RET to tPOP.
605 MachineInstrBuilder MIB =
606 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
607 .add(predOps(ARMCC::AL));
609 for (auto MO: MBBI->operands())
610 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
611 MO.getReg() != ARM::PC) {
613 if (!MO.isImplicit())
616 // Is there anything left to pop?
618 MBB.erase(MIB.getInstr());
619 // Erase the old instruction.
621 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
622 .add(predOps(ARMCC::AL));
625 assert(PopReg && "Do not know how to get LR");
626 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
627 .add(predOps(ARMCC::AL))
628 .addReg(PopReg, RegState::Define);
630 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
632 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
633 .addReg(ARM::LR, RegState::Define)
634 .addReg(PopReg, RegState::Kill)
635 .add(predOps(ARMCC::AL));
638 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
639 .addReg(PopReg, RegState::Define)
640 .addReg(TemporaryReg, RegState::Kill)
641 .add(predOps(ARMCC::AL));
646 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
647 // or OrderEnd if no further registers are in that set. This does not advance
648 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
649 template <unsigned SetSize>
650 static const unsigned *
651 findNextOrderedReg(const unsigned *CurrentReg,
652 SmallSet<unsigned, SetSize> &EnabledRegs,
653 const unsigned *OrderEnd) {
654 while (CurrentReg != OrderEnd && !EnabledRegs.count(*CurrentReg))
659 bool Thumb1FrameLowering::
660 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
661 MachineBasicBlock::iterator MI,
662 const std::vector<CalleeSavedInfo> &CSI,
663 const TargetRegisterInfo *TRI) const {
668 const TargetInstrInfo &TII = *STI.getInstrInfo();
669 MachineFunction &MF = *MBB.getParent();
670 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
671 MF.getSubtarget().getRegisterInfo());
673 SmallSet<unsigned, 9> LoRegsToSave; // r0-r7, lr
674 SmallSet<unsigned, 4> HiRegsToSave; // r8-r11
675 SmallSet<unsigned, 9> CopyRegs; // Registers which can be used after pushing
676 // LoRegs for saving HiRegs.
678 for (unsigned i = CSI.size(); i != 0; --i) {
679 unsigned Reg = CSI[i-1].getReg();
681 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
682 LoRegsToSave.insert(Reg);
683 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
684 HiRegsToSave.insert(Reg);
686 llvm_unreachable("callee-saved register of unexpected class");
689 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
690 !MF.getRegInfo().isLiveIn(Reg) &&
691 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
692 CopyRegs.insert(Reg);
695 // Unused argument registers can be used for the high register saving.
696 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
697 if (!MF.getRegInfo().isLiveIn(ArgReg))
698 CopyRegs.insert(ArgReg);
700 // Push the low registers and lr
701 const MachineRegisterInfo &MRI = MF.getRegInfo();
702 if (!LoRegsToSave.empty()) {
703 MachineInstrBuilder MIB =
704 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
705 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
706 if (LoRegsToSave.count(Reg)) {
707 bool isKill = !MRI.isLiveIn(Reg);
708 if (isKill && !MRI.isReserved(Reg))
711 MIB.addReg(Reg, getKillRegState(isKill));
714 MIB.setMIFlags(MachineInstr::FrameSetup);
717 // Push the high registers. There are no store instructions that can access
718 // these registers directly, so we have to move them to low registers, and
719 // push them. This might take multiple pushes, as it is possible for there to
720 // be fewer low registers available than high registers which need saving.
722 // These are in reverse order so that in the case where we need to use
723 // multiple PUSH instructions, the order of the registers on the stack still
724 // matches the unwind info. They need to be swicthed back to ascending order
725 // before adding to the PUSH instruction.
726 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
727 ARM::R5, ARM::R4, ARM::R3,
728 ARM::R2, ARM::R1, ARM::R0};
729 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
731 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
732 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
734 // Find the first register to save.
735 const unsigned *HiRegToSave = findNextOrderedReg(
736 std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
738 while (HiRegToSave != AllHighRegsEnd) {
739 // Find the first low register to use.
740 const unsigned *CopyReg =
741 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
743 // Create the PUSH, but don't insert it yet (the MOVs need to come first).
744 MachineInstrBuilder PushMIB =
745 BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
747 SmallVector<unsigned, 4> RegsToPush;
748 while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
749 if (HiRegsToSave.count(*HiRegToSave)) {
750 bool isKill = !MRI.isLiveIn(*HiRegToSave);
751 if (isKill && !MRI.isReserved(*HiRegToSave))
752 MBB.addLiveIn(*HiRegToSave);
754 // Emit a MOV from the high reg to the low reg.
755 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
756 .addReg(*CopyReg, RegState::Define)
757 .addReg(*HiRegToSave, getKillRegState(isKill))
758 .add(predOps(ARMCC::AL));
760 // Record the register that must be added to the PUSH.
761 RegsToPush.push_back(*CopyReg);
763 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
765 findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
769 // Add the low registers to the PUSH, in ascending order.
770 for (unsigned Reg : llvm::reverse(RegsToPush))
771 PushMIB.addReg(Reg, RegState::Kill);
773 // Insert the PUSH instruction after the MOVs.
774 MBB.insert(MI, PushMIB);
780 bool Thumb1FrameLowering::
781 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
782 MachineBasicBlock::iterator MI,
783 const std::vector<CalleeSavedInfo> &CSI,
784 const TargetRegisterInfo *TRI) const {
788 MachineFunction &MF = *MBB.getParent();
789 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
790 const TargetInstrInfo &TII = *STI.getInstrInfo();
791 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
792 MF.getSubtarget().getRegisterInfo());
794 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
795 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
797 SmallSet<unsigned, 9> LoRegsToRestore;
798 SmallSet<unsigned, 4> HiRegsToRestore;
799 // Low registers (r0-r7) which can be used to restore the high registers.
800 SmallSet<unsigned, 9> CopyRegs;
802 for (CalleeSavedInfo I : CSI) {
803 unsigned Reg = I.getReg();
805 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
806 LoRegsToRestore.insert(Reg);
807 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
808 HiRegsToRestore.insert(Reg);
810 llvm_unreachable("callee-saved register of unexpected class");
813 // If this is a low register not used as the frame pointer, we may want to
814 // use it for restoring the high registers.
815 if ((ARM::tGPRRegClass.contains(Reg)) &&
816 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
817 CopyRegs.insert(Reg);
820 // If this is a return block, we may be able to use some unused return value
821 // registers for restoring the high regs.
822 auto Terminator = MBB.getFirstTerminator();
823 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
824 CopyRegs.insert(ARM::R0);
825 CopyRegs.insert(ARM::R1);
826 CopyRegs.insert(ARM::R2);
827 CopyRegs.insert(ARM::R3);
828 for (auto Op : Terminator->implicit_operands()) {
830 CopyRegs.erase(Op.getReg());
834 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
835 ARM::R4, ARM::R5, ARM::R6, ARM::R7};
836 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
838 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
839 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
841 // Find the first register to restore.
842 auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
843 HiRegsToRestore, AllHighRegsEnd);
845 while (HiRegToRestore != AllHighRegsEnd) {
846 assert(!CopyRegs.empty());
847 // Find the first low register to use.
849 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
851 // Create the POP instruction.
852 MachineInstrBuilder PopMIB =
853 BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
855 while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
856 // Add the low register to the POP.
857 PopMIB.addReg(*CopyReg, RegState::Define);
859 // Create the MOV from low to high register.
860 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
861 .addReg(*HiRegToRestore, RegState::Define)
862 .addReg(*CopyReg, RegState::Kill)
863 .add(predOps(ARMCC::AL));
865 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
867 findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
871 MachineInstrBuilder MIB =
872 BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
874 bool NeedsPop = false;
875 for (unsigned i = CSI.size(); i != 0; --i) {
876 unsigned Reg = CSI[i-1].getReg();
878 // High registers (excluding lr) have already been dealt with
879 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
882 if (Reg == ARM::LR) {
883 if (MBB.succ_empty()) {
884 // Special epilogue for vararg functions. See emitEpilogue
887 // ARMv4T requires BX, see emitEpilogue
888 if (!STI.hasV5TOps())
890 // Tailcall optimization failed; change TCRETURN to a tBL
891 if (MI->getOpcode() == ARM::TCRETURNdi ||
892 MI->getOpcode() == ARM::TCRETURNri) {
893 unsigned Opcode = MI->getOpcode() == ARM::TCRETURNdi
894 ? ARM::tBL : ARM::tBLXr;
895 MachineInstrBuilder BL = BuildMI(MF, DL, TII.get(Opcode));
896 BL.add(predOps(ARMCC::AL));
897 BL.add(MI->getOperand(0));
898 MBB.insert(MI, &*BL);
901 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
903 MIB.copyImplicitOps(*MI);
906 // LR may only be popped into PC, as part of return sequence.
907 // If this isn't the return sequence, we'll need emitPopSpecialFixUp
908 // to restore LR the hard way.
911 MIB.addReg(Reg, getDefRegState(true));
915 // It's illegal to emit pop instruction without operands.
917 MBB.insert(MI, &*MIB);
919 MF.DeleteMachineInstr(MIB);