1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/LivePhysRegs.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
26 : ARMFrameLowering(sti) {}
28 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
29 const MachineFrameInfo &MFI = MF.getFrameInfo();
30 unsigned CFSize = MFI.getMaxCallFrameSize();
31 // It's not always a good idea to include the call frame as part of the
32 // stack frame. ARM (especially Thumb) has small immediate offset to
33 // address the stack frame. So a large call frame can cause poor codegen
34 // and may even makes it impossible to scavenge a register.
35 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
38 return !MFI.hasVarSizedObjects();
41 static void emitSPUpdate(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator &MBBI,
43 const TargetInstrInfo &TII, const DebugLoc &dl,
44 const ThumbRegisterInfo &MRI, int NumBytes,
45 unsigned MIFlags = MachineInstr::NoFlags) {
46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
51 MachineBasicBlock::iterator Thumb1FrameLowering::
52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator I) const {
54 const Thumb1InstrInfo &TII =
55 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
56 const ThumbRegisterInfo *RegInfo =
57 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
58 if (!hasReservedCallFrame(MF)) {
59 // If we have alloca, convert as follows:
60 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
61 // ADJCALLSTACKUP -> add, sp, sp, amount
62 MachineInstr &Old = *I;
63 DebugLoc dl = Old.getDebugLoc();
64 unsigned Amount = Old.getOperand(0).getImm();
66 // We need to keep the stack aligned properly. To do this, we round the
67 // amount of space needed for the outgoing arguments up to the next
68 // alignment boundary.
69 unsigned Align = getStackAlignment();
70 Amount = (Amount+Align-1)/Align*Align;
72 // Replace the pseudo instruction with a new instruction...
73 unsigned Opc = Old.getOpcode();
74 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
77 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
85 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
86 MachineBasicBlock &MBB) const {
87 MachineBasicBlock::iterator MBBI = MBB.begin();
88 MachineFrameInfo &MFI = MF.getFrameInfo();
89 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
90 MachineModuleInfo &MMI = MF.getMMI();
91 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
92 const ThumbRegisterInfo *RegInfo =
93 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
94 const Thumb1InstrInfo &TII =
95 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
97 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
98 unsigned NumBytes = MFI.getStackSize();
99 assert(NumBytes >= ArgRegsSaveSize &&
100 "ArgRegsSaveSize is included in NumBytes");
101 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
103 // Debug location must be unknown since the first debug location is used
104 // to determine the end of the prologue.
107 unsigned FramePtr = RegInfo->getFrameRegister(MF);
108 unsigned BasePtr = RegInfo->getBaseRegister();
111 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
112 NumBytes = (NumBytes + 3) & ~3;
113 MFI.setStackSize(NumBytes);
115 // Determine the sizes of each callee-save spill areas and record which frame
116 // belongs to which callee-save spill areas.
117 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
118 int FramePtrSpillFI = 0;
120 if (ArgRegsSaveSize) {
121 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
122 MachineInstr::FrameSetup);
123 CFAOffset -= ArgRegsSaveSize;
124 unsigned CFIIndex = MF.addFrameInst(
125 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
126 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
127 .addCFIIndex(CFIIndex)
128 .setMIFlags(MachineInstr::FrameSetup);
131 if (!AFI->hasStackFrame()) {
132 if (NumBytes - ArgRegsSaveSize != 0) {
133 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
134 MachineInstr::FrameSetup);
135 CFAOffset -= NumBytes - ArgRegsSaveSize;
136 unsigned CFIIndex = MF.addFrameInst(
137 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
138 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
139 .addCFIIndex(CFIIndex)
140 .setMIFlags(MachineInstr::FrameSetup);
145 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
146 unsigned Reg = CSI[i].getReg();
147 int FI = CSI[i].getFrameIdx();
153 if (STI.splitFramePushPop(MF)) {
164 FramePtrSpillFI = FI;
172 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
176 // Determine starting offsets of spill areas.
177 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
178 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
179 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
180 bool HasFP = hasFP(MF);
182 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
184 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
185 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
186 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
187 NumBytes = DPRCSOffset;
189 int FramePtrOffsetInBlock = 0;
190 unsigned adjustedGPRCS1Size = GPRCS1Size;
191 if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
192 tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
193 FramePtrOffsetInBlock = NumBytes;
194 adjustedGPRCS1Size += NumBytes;
198 if (adjustedGPRCS1Size) {
199 CFAOffset -= adjustedGPRCS1Size;
200 unsigned CFIIndex = MF.addFrameInst(
201 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
202 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
203 .addCFIIndex(CFIIndex)
204 .setMIFlags(MachineInstr::FrameSetup);
206 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
207 E = CSI.end(); I != E; ++I) {
208 unsigned Reg = I->getReg();
209 int FI = I->getFrameIdx();
216 if (STI.splitFramePushPop(MF))
228 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
229 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
230 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
231 .addCFIIndex(CFIIndex)
232 .setMIFlags(MachineInstr::FrameSetup);
237 // Adjust FP so it point to the stack slot that contains the previous FP.
239 FramePtrOffsetInBlock +=
240 MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
241 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
242 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
243 .setMIFlags(MachineInstr::FrameSetup));
244 if(FramePtrOffsetInBlock) {
245 CFAOffset += FramePtrOffsetInBlock;
246 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
247 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
248 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
249 .addCFIIndex(CFIIndex)
250 .setMIFlags(MachineInstr::FrameSetup);
253 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
254 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
255 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
256 .addCFIIndex(CFIIndex)
257 .setMIFlags(MachineInstr::FrameSetup);
260 // If offset is > 508 then sp cannot be adjusted in a single instruction,
261 // try restoring from fp instead.
262 AFI->setShouldRestoreSPFromFP(true);
265 // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
266 // and tMOVr instructions. We don't need to add any call frame information
267 // in-between these instructions, because they do not modify the high
270 MachineBasicBlock::iterator OldMBBI = MBBI;
271 // Skip a run of tMOVr instructions
272 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
274 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
277 // We have reached an instruction which is not a push, so the previous
278 // run of tMOVr instructions (which may have been empty) was not part of
279 // the prologue. Reset MBBI back to the last PUSH of the prologue.
285 // Emit call frame information for the callee-saved high registers.
286 for (auto &I : CSI) {
287 unsigned Reg = I.getReg();
288 int FI = I.getFrameIdx();
295 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
296 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
297 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
298 .addCFIIndex(CFIIndex)
299 .setMIFlags(MachineInstr::FrameSetup);
308 // Insert it after all the callee-save spills.
309 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
310 MachineInstr::FrameSetup);
312 CFAOffset -= NumBytes;
313 unsigned CFIIndex = MF.addFrameInst(
314 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
315 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
316 .addCFIIndex(CFIIndex)
317 .setMIFlags(MachineInstr::FrameSetup);
321 if (STI.isTargetELF() && HasFP)
322 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
323 AFI->getFramePtrSpillOffset());
325 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
326 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
327 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
329 // Thumb1 does not currently support dynamic stack realignment. Report a
330 // fatal error rather then silently generate bad code.
331 if (RegInfo->needsStackRealignment(MF))
332 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
334 // If we need a base pointer, set it up here. It's whatever the value
335 // of the stack pointer is at this point. Any variable size objects
336 // will be allocated after this, so we can still use the base pointer
337 // to reference locals.
338 if (RegInfo->hasBasePointer(MF))
339 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
342 // If the frame has variable sized objects then the epilogue must restore
343 // the sp from fp. We can assume there's an FP here since hasFP already
344 // checks for hasVarSizedObjects.
345 if (MFI.hasVarSizedObjects())
346 AFI->setShouldRestoreSPFromFP(true);
349 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
350 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
351 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
353 else if (MI.getOpcode() == ARM::tPOP) {
355 } else if (MI.getOpcode() == ARM::tMOVr) {
356 unsigned Dst = MI.getOperand(0).getReg();
357 unsigned Src = MI.getOperand(1).getReg();
358 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
359 ARM::hGPRRegClass.contains(Dst));
364 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
365 MachineBasicBlock &MBB) const {
366 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
367 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
368 MachineFrameInfo &MFI = MF.getFrameInfo();
369 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
370 const ThumbRegisterInfo *RegInfo =
371 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
372 const Thumb1InstrInfo &TII =
373 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
375 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
376 int NumBytes = (int)MFI.getStackSize();
377 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
378 "ArgRegsSaveSize is included in NumBytes");
379 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
380 unsigned FramePtr = RegInfo->getFrameRegister(MF);
382 if (!AFI->hasStackFrame()) {
383 if (NumBytes - ArgRegsSaveSize != 0)
384 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
386 // Unwind MBBI to point to first LDR / VLDRD.
387 if (MBBI != MBB.begin()) {
390 while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
391 if (!isCSRestore(*MBBI, CSRegs))
395 // Move SP to start of FP callee save spill area.
396 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
397 AFI->getGPRCalleeSavedArea2Size() +
398 AFI->getDPRCalleeSavedAreaSize() +
401 if (AFI->shouldRestoreSPFromFP()) {
402 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
403 // Reset SP based on frame pointer only if the stack frame extends beyond
404 // frame pointer stack slot, the target is ELF and the function has FP, or
405 // the target uses var sized objects.
407 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
408 "No scratch register to restore SP from FP!");
409 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
411 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
415 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
419 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
420 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
421 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
422 if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
423 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
424 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
425 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
429 if (needPopSpecialFixUp(MF)) {
430 bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
432 assert(Done && "Emission of the special fixup failed!?");
436 bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
437 if (!needPopSpecialFixUp(*MBB.getParent()))
440 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
441 return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
444 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
445 ARMFunctionInfo *AFI =
446 const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
447 if (AFI->getArgRegsSaveSize())
450 // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
451 for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
452 if (CSI.getReg() == ARM::LR)
458 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
460 MachineFunction &MF = *MBB.getParent();
461 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
462 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
463 const TargetInstrInfo &TII = *STI.getInstrInfo();
464 const ThumbRegisterInfo *RegInfo =
465 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
467 // If MBBI is a return instruction, or is a tPOP followed by a return
468 // instruction in the successor BB, we may be able to directly restore
470 // This is only possible with v5T ops (v4T can't change the Thumb bit via
471 // a POP PC instruction), and only if we do not need to emit any SP update.
472 // Otherwise, we need a temporary register to pop the value
473 // and copy that value into LR.
474 auto MBBI = MBB.getFirstTerminator();
475 bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
476 if (CanRestoreDirectly) {
477 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
478 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
479 MBBI->getOpcode() == ARM::tPOP_RET);
481 auto MBBI_prev = MBBI;
483 assert(MBBI_prev->getOpcode() == ARM::tPOP);
484 assert(MBB.succ_size() == 1);
485 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
486 MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
488 CanRestoreDirectly = false;
492 if (CanRestoreDirectly) {
493 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
495 MachineInstrBuilder MIB =
497 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)));
498 // Copy implicit ops and popped registers, if any.
499 for (auto MO: MBBI->operands())
500 if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
502 MIB.addReg(ARM::PC, RegState::Define);
503 // Erase the old instruction (tBX_RET or tPOP).
508 // Look for a temporary register to use.
509 // First, compute the liveness information.
510 LivePhysRegs UsedRegs(STI.getRegisterInfo());
511 UsedRegs.addLiveOuts(MBB);
512 // The semantic of pristines changed recently and now,
513 // the callee-saved registers that are touched in the function
514 // are not part of the pristines set anymore.
515 // Add those callee-saved now.
516 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
517 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
518 for (unsigned i = 0; CSRegs[i]; ++i)
519 UsedRegs.addReg(CSRegs[i]);
521 DebugLoc dl = DebugLoc();
522 if (MBBI != MBB.end()) {
523 dl = MBBI->getDebugLoc();
524 auto InstUpToMBBI = MBB.end();
525 while (InstUpToMBBI != MBBI)
526 // The pre-decrement is on purpose here.
527 // We want to have the liveness right before MBBI.
528 UsedRegs.stepBackward(*--InstUpToMBBI);
531 // Look for a register that can be directly use in the POP.
533 // And some temporary register, just in case.
534 unsigned TemporaryReg = 0;
535 BitVector PopFriendly =
536 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID));
537 assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
538 // Rebuild the GPRs from the high registers because they are removed
539 // form the GPR reg class for thumb1.
540 BitVector GPRsNoLRSP =
541 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID));
542 GPRsNoLRSP |= PopFriendly;
543 GPRsNoLRSP.reset(ARM::LR);
544 GPRsNoLRSP.reset(ARM::SP);
545 GPRsNoLRSP.reset(ARM::PC);
546 for (int Register = GPRsNoLRSP.find_first(); Register != -1;
547 Register = GPRsNoLRSP.find_next(Register)) {
548 if (!UsedRegs.contains(Register)) {
549 // Remember the first pop-friendly register and exit.
550 if (PopFriendly.test(Register)) {
555 // Otherwise, remember that the register will be available to
556 // save a pop-friendly register.
557 TemporaryReg = Register;
561 if (!DoIt && !PopReg && !TemporaryReg)
564 assert((PopReg || TemporaryReg) && "Cannot get LR");
567 assert(!PopReg && "Unnecessary MOV is about to be inserted");
568 PopReg = PopFriendly.find_first();
569 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
570 .addReg(TemporaryReg, RegState::Define)
571 .addReg(PopReg, RegState::Kill));
574 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
575 // We couldn't use the direct restoration above, so
576 // perform the opposite conversion: tPOP_RET to tPOP.
577 MachineInstrBuilder MIB =
579 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP)));
581 for (auto MO: MBBI->operands())
582 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
583 MO.getReg() != ARM::PC) {
585 if (!MO.isImplicit())
588 // Is there anything left to pop?
590 MBB.erase(MIB.getInstr());
591 // Erase the old instruction.
593 MBBI = AddDefaultPred(BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET)));
596 assert(PopReg && "Do not know how to get LR");
597 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
598 .addReg(PopReg, RegState::Define);
600 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
602 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
603 .addReg(ARM::LR, RegState::Define)
604 .addReg(PopReg, RegState::Kill));
607 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
608 .addReg(PopReg, RegState::Define)
609 .addReg(TemporaryReg, RegState::Kill));
614 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
615 // or OrderEnd if no further registers are in that set. This does not advance
616 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
617 template <unsigned SetSize>
618 static const unsigned *
619 findNextOrderedReg(const unsigned *CurrentReg,
620 SmallSet<unsigned, SetSize> &EnabledRegs,
621 const unsigned *OrderEnd) {
622 while (CurrentReg != OrderEnd && !EnabledRegs.count(*CurrentReg))
627 bool Thumb1FrameLowering::
628 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
629 MachineBasicBlock::iterator MI,
630 const std::vector<CalleeSavedInfo> &CSI,
631 const TargetRegisterInfo *TRI) const {
636 const TargetInstrInfo &TII = *STI.getInstrInfo();
637 MachineFunction &MF = *MBB.getParent();
638 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
639 MF.getSubtarget().getRegisterInfo());
641 SmallSet<unsigned, 9> LoRegsToSave; // r0-r7, lr
642 SmallSet<unsigned, 4> HiRegsToSave; // r8-r11
643 SmallSet<unsigned, 9> CopyRegs; // Registers which can be used after pushing
644 // LoRegs for saving HiRegs.
646 for (unsigned i = CSI.size(); i != 0; --i) {
647 unsigned Reg = CSI[i-1].getReg();
649 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
650 LoRegsToSave.insert(Reg);
651 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
652 HiRegsToSave.insert(Reg);
654 llvm_unreachable("callee-saved register of unexpected class");
657 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
658 !MF.getRegInfo().isLiveIn(Reg) &&
659 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
660 CopyRegs.insert(Reg);
663 // Unused argument registers can be used for the high register saving.
664 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
665 if (!MF.getRegInfo().isLiveIn(ArgReg))
666 CopyRegs.insert(ArgReg);
668 // Push the low registers and lr
669 if (!LoRegsToSave.empty()) {
670 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
672 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
673 if (LoRegsToSave.count(Reg)) {
674 bool isKill = !MF.getRegInfo().isLiveIn(Reg);
678 MIB.addReg(Reg, getKillRegState(isKill));
681 MIB.setMIFlags(MachineInstr::FrameSetup);
684 // Push the high registers. There are no store instructions that can access
685 // these registers directly, so we have to move them to low registers, and
686 // push them. This might take multiple pushes, as it is possible for there to
687 // be fewer low registers available than high registers which need saving.
689 // These are in reverse order so that in the case where we need to use
690 // multiple PUSH instructions, the order of the registers on the stack still
691 // matches the unwind info. They need to be swicthed back to ascending order
692 // before adding to the PUSH instruction.
693 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
694 ARM::R5, ARM::R4, ARM::R3,
695 ARM::R2, ARM::R1, ARM::R0};
696 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
698 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
699 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
701 // Find the first register to save.
702 const unsigned *HiRegToSave = findNextOrderedReg(
703 std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
705 while (HiRegToSave != AllHighRegsEnd) {
706 // Find the first low register to use.
707 const unsigned *CopyReg =
708 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
710 // Create the PUSH, but don't insert it yet (the MOVs need to come first).
711 MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH));
712 AddDefaultPred(PushMIB);
714 SmallVector<unsigned, 4> RegsToPush;
715 while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
716 if (HiRegsToSave.count(*HiRegToSave)) {
717 bool isKill = !MF.getRegInfo().isLiveIn(*HiRegToSave);
719 MBB.addLiveIn(*HiRegToSave);
721 // Emit a MOV from the high reg to the low reg.
722 MachineInstrBuilder MIB =
723 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr));
724 MIB.addReg(*CopyReg, RegState::Define);
725 MIB.addReg(*HiRegToSave, getKillRegState(isKill));
728 // Record the register that must be added to the PUSH.
729 RegsToPush.push_back(*CopyReg);
731 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
733 findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
737 // Add the low registers to the PUSH, in ascending order.
738 for (unsigned Reg : reverse(RegsToPush))
739 PushMIB.addReg(Reg, RegState::Kill);
741 // Insert the PUSH instruction after the MOVs.
742 MBB.insert(MI, PushMIB);
748 bool Thumb1FrameLowering::
749 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
750 MachineBasicBlock::iterator MI,
751 const std::vector<CalleeSavedInfo> &CSI,
752 const TargetRegisterInfo *TRI) const {
756 MachineFunction &MF = *MBB.getParent();
757 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
758 const TargetInstrInfo &TII = *STI.getInstrInfo();
759 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
760 MF.getSubtarget().getRegisterInfo());
762 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
763 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
765 SmallSet<unsigned, 9> LoRegsToRestore;
766 SmallSet<unsigned, 4> HiRegsToRestore;
767 // Low registers (r0-r7) which can be used to restore the high registers.
768 SmallSet<unsigned, 9> CopyRegs;
770 for (CalleeSavedInfo I : CSI) {
771 unsigned Reg = I.getReg();
773 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
774 LoRegsToRestore.insert(Reg);
775 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
776 HiRegsToRestore.insert(Reg);
778 llvm_unreachable("callee-saved register of unexpected class");
781 // If this is a low register not used as the frame pointer, we may want to
782 // use it for restoring the high registers.
783 if ((ARM::tGPRRegClass.contains(Reg)) &&
784 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
785 CopyRegs.insert(Reg);
788 // If this is a return block, we may be able to use some unused return value
789 // registers for restoring the high regs.
790 auto Terminator = MBB.getFirstTerminator();
791 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
792 CopyRegs.insert(ARM::R0);
793 CopyRegs.insert(ARM::R1);
794 CopyRegs.insert(ARM::R2);
795 CopyRegs.insert(ARM::R3);
796 for (auto Op : Terminator->implicit_operands()) {
798 CopyRegs.erase(Op.getReg());
802 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
803 ARM::R4, ARM::R5, ARM::R6, ARM::R7};
804 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
806 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
807 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
809 // Find the first register to restore.
810 auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
811 HiRegsToRestore, AllHighRegsEnd);
813 while (HiRegToRestore != AllHighRegsEnd) {
814 assert(!CopyRegs.empty());
815 // Find the first low register to use.
817 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
819 // Create the POP instruction.
820 MachineInstrBuilder PopMIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPOP));
821 AddDefaultPred(PopMIB);
823 while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
824 // Add the low register to the POP.
825 PopMIB.addReg(*CopyReg, RegState::Define);
827 // Create the MOV from low to high register.
828 MachineInstrBuilder MIB =
829 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr));
830 MIB.addReg(*HiRegToRestore, RegState::Define);
831 MIB.addReg(*CopyReg, RegState::Kill);
834 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
836 findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
843 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
846 bool NeedsPop = false;
847 for (unsigned i = CSI.size(); i != 0; --i) {
848 unsigned Reg = CSI[i-1].getReg();
850 // High registers (excluding lr) have already been dealt with
851 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
854 if (Reg == ARM::LR) {
855 if (MBB.succ_empty()) {
856 // Special epilogue for vararg functions. See emitEpilogue
859 // ARMv4T requires BX, see emitEpilogue
860 if (!STI.hasV5TOps())
863 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
865 MIB.copyImplicitOps(*MI);
868 // LR may only be popped into PC, as part of return sequence.
869 // If this isn't the return sequence, we'll need emitPopSpecialFixUp
870 // to restore LR the hard way.
873 MIB.addReg(Reg, getDefRegState(true));
877 // It's illegal to emit pop instruction without operands.
879 MBB.insert(MI, &*MIB);
881 MF.DeleteMachineInstr(MIB);