1 //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "ThumbRegisterInfo.h"
21 #include "Utils/ARMBaseInfo.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/CodeGen/LivePhysRegs.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/TargetInstrInfo.h"
35 #include "llvm/CodeGen/TargetOpcodes.h"
36 #include "llvm/CodeGen/TargetSubtargetInfo.h"
37 #include "llvm/IR/DebugLoc.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCDwarf.h"
40 #include "llvm/MC/MCRegisterInfo.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/MathExtras.h"
51 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
52 : ARMFrameLowering(sti) {}
54 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
55 const MachineFrameInfo &MFI = MF.getFrameInfo();
56 unsigned CFSize = MFI.getMaxCallFrameSize();
57 // It's not always a good idea to include the call frame as part of the
58 // stack frame. ARM (especially Thumb) has small immediate offset to
59 // address the stack frame. So a large call frame can cause poor codegen
60 // and may even makes it impossible to scavenge a register.
61 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
64 return !MFI.hasVarSizedObjects();
67 static void emitSPUpdate(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator &MBBI,
69 const TargetInstrInfo &TII, const DebugLoc &dl,
70 const ThumbRegisterInfo &MRI, int NumBytes,
71 unsigned MIFlags = MachineInstr::NoFlags) {
72 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
76 MachineBasicBlock::iterator Thumb1FrameLowering::
77 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator I) const {
79 const Thumb1InstrInfo &TII =
80 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
81 const ThumbRegisterInfo *RegInfo =
82 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
83 if (!hasReservedCallFrame(MF)) {
84 // If we have alloca, convert as follows:
85 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
86 // ADJCALLSTACKUP -> add, sp, sp, amount
87 MachineInstr &Old = *I;
88 DebugLoc dl = Old.getDebugLoc();
89 unsigned Amount = TII.getFrameSize(Old);
91 // We need to keep the stack aligned properly. To do this, we round the
92 // amount of space needed for the outgoing arguments up to the next
93 // alignment boundary.
94 Amount = alignTo(Amount, getStackAlignment());
96 // Replace the pseudo instruction with a new instruction...
97 unsigned Opc = Old.getOpcode();
98 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
99 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
101 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
102 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
109 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
110 MachineBasicBlock &MBB) const {
111 MachineBasicBlock::iterator MBBI = MBB.begin();
112 MachineFrameInfo &MFI = MF.getFrameInfo();
113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
114 MachineModuleInfo &MMI = MF.getMMI();
115 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
116 const ThumbRegisterInfo *RegInfo =
117 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
118 const Thumb1InstrInfo &TII =
119 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
121 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
122 unsigned NumBytes = MFI.getStackSize();
123 assert(NumBytes >= ArgRegsSaveSize &&
124 "ArgRegsSaveSize is included in NumBytes");
125 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
127 // Debug location must be unknown since the first debug location is used
128 // to determine the end of the prologue.
131 unsigned FramePtr = RegInfo->getFrameRegister(MF);
132 unsigned BasePtr = RegInfo->getBaseRegister();
135 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
136 NumBytes = (NumBytes + 3) & ~3;
137 MFI.setStackSize(NumBytes);
139 // Determine the sizes of each callee-save spill areas and record which frame
140 // belongs to which callee-save spill areas.
141 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
142 int FramePtrSpillFI = 0;
144 if (ArgRegsSaveSize) {
145 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
146 MachineInstr::FrameSetup);
147 CFAOffset -= ArgRegsSaveSize;
148 unsigned CFIIndex = MF.addFrameInst(
149 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
150 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
151 .addCFIIndex(CFIIndex)
152 .setMIFlags(MachineInstr::FrameSetup);
155 if (!AFI->hasStackFrame()) {
156 if (NumBytes - ArgRegsSaveSize != 0) {
157 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
158 MachineInstr::FrameSetup);
159 CFAOffset -= NumBytes - ArgRegsSaveSize;
160 unsigned CFIIndex = MF.addFrameInst(
161 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
162 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
163 .addCFIIndex(CFIIndex)
164 .setMIFlags(MachineInstr::FrameSetup);
169 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
170 unsigned Reg = CSI[i].getReg();
171 int FI = CSI[i].getFrameIdx();
177 if (STI.splitFramePushPop(MF)) {
188 FramePtrSpillFI = FI;
196 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
200 // Determine starting offsets of spill areas.
201 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
202 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
203 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
204 bool HasFP = hasFP(MF);
206 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
208 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
209 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
210 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
211 NumBytes = DPRCSOffset;
213 int FramePtrOffsetInBlock = 0;
214 unsigned adjustedGPRCS1Size = GPRCS1Size;
215 if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
216 tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
217 FramePtrOffsetInBlock = NumBytes;
218 adjustedGPRCS1Size += NumBytes;
222 if (adjustedGPRCS1Size) {
223 CFAOffset -= adjustedGPRCS1Size;
224 unsigned CFIIndex = MF.addFrameInst(
225 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
226 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
227 .addCFIIndex(CFIIndex)
228 .setMIFlags(MachineInstr::FrameSetup);
230 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
231 E = CSI.end(); I != E; ++I) {
232 unsigned Reg = I->getReg();
233 int FI = I->getFrameIdx();
240 if (STI.splitFramePushPop(MF))
252 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
253 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
254 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255 .addCFIIndex(CFIIndex)
256 .setMIFlags(MachineInstr::FrameSetup);
261 // Adjust FP so it point to the stack slot that contains the previous FP.
263 FramePtrOffsetInBlock +=
264 MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
265 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
267 .addImm(FramePtrOffsetInBlock / 4)
268 .setMIFlags(MachineInstr::FrameSetup)
269 .add(predOps(ARMCC::AL));
270 if(FramePtrOffsetInBlock) {
271 CFAOffset += FramePtrOffsetInBlock;
272 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
273 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
274 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
275 .addCFIIndex(CFIIndex)
276 .setMIFlags(MachineInstr::FrameSetup);
279 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
280 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
281 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
282 .addCFIIndex(CFIIndex)
283 .setMIFlags(MachineInstr::FrameSetup);
286 // If offset is > 508 then sp cannot be adjusted in a single instruction,
287 // try restoring from fp instead.
288 AFI->setShouldRestoreSPFromFP(true);
291 // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
292 // and tMOVr instructions. We don't need to add any call frame information
293 // in-between these instructions, because they do not modify the high
296 MachineBasicBlock::iterator OldMBBI = MBBI;
297 // Skip a run of tMOVr instructions
298 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
300 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
303 // We have reached an instruction which is not a push, so the previous
304 // run of tMOVr instructions (which may have been empty) was not part of
305 // the prologue. Reset MBBI back to the last PUSH of the prologue.
311 // Emit call frame information for the callee-saved high registers.
312 for (auto &I : CSI) {
313 unsigned Reg = I.getReg();
314 int FI = I.getFrameIdx();
321 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
322 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
323 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
324 .addCFIIndex(CFIIndex)
325 .setMIFlags(MachineInstr::FrameSetup);
334 // Insert it after all the callee-save spills.
335 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
336 MachineInstr::FrameSetup);
338 CFAOffset -= NumBytes;
339 unsigned CFIIndex = MF.addFrameInst(
340 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
341 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
342 .addCFIIndex(CFIIndex)
343 .setMIFlags(MachineInstr::FrameSetup);
347 if (STI.isTargetELF() && HasFP)
348 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
349 AFI->getFramePtrSpillOffset());
351 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
352 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
353 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
355 if (RegInfo->needsStackRealignment(MF)) {
356 const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
357 // Emit the following sequence, using R4 as a temporary, since we cannot use
358 // SP as a source or destination register for the shifts:
360 // lsrs r4, r4, #NrBitsToZero
361 // lsls r4, r4, #NrBitsToZero
363 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
364 .addReg(ARM::SP, RegState::Kill)
365 .add(predOps(ARMCC::AL));
367 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
369 .addReg(ARM::R4, RegState::Kill)
370 .addImm(NrBitsToZero)
371 .add(predOps(ARMCC::AL));
373 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
375 .addReg(ARM::R4, RegState::Kill)
376 .addImm(NrBitsToZero)
377 .add(predOps(ARMCC::AL));
379 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
380 .addReg(ARM::R4, RegState::Kill)
381 .add(predOps(ARMCC::AL));
383 AFI->setShouldRestoreSPFromFP(true);
386 // If we need a base pointer, set it up here. It's whatever the value
387 // of the stack pointer is at this point. Any variable size objects
388 // will be allocated after this, so we can still use the base pointer
389 // to reference locals.
390 if (RegInfo->hasBasePointer(MF))
391 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
393 .add(predOps(ARMCC::AL));
395 // If the frame has variable sized objects then the epilogue must restore
396 // the sp from fp. We can assume there's an FP here since hasFP already
397 // checks for hasVarSizedObjects.
398 if (MFI.hasVarSizedObjects())
399 AFI->setShouldRestoreSPFromFP(true);
401 // In some cases, virtual registers have been introduced, e.g. by uses of
402 // emitThumbRegPlusImmInReg.
403 MF.getProperties().reset(MachineFunctionProperties::Property::NoVRegs);
406 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
407 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
408 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
410 else if (MI.getOpcode() == ARM::tPOP) {
412 } else if (MI.getOpcode() == ARM::tMOVr) {
413 unsigned Dst = MI.getOperand(0).getReg();
414 unsigned Src = MI.getOperand(1).getReg();
415 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
416 ARM::hGPRRegClass.contains(Dst));
421 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
422 MachineBasicBlock &MBB) const {
423 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
424 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
425 MachineFrameInfo &MFI = MF.getFrameInfo();
426 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
427 const ThumbRegisterInfo *RegInfo =
428 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
429 const Thumb1InstrInfo &TII =
430 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
432 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
433 int NumBytes = (int)MFI.getStackSize();
434 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
435 "ArgRegsSaveSize is included in NumBytes");
436 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
437 unsigned FramePtr = RegInfo->getFrameRegister(MF);
439 if (!AFI->hasStackFrame()) {
440 if (NumBytes - ArgRegsSaveSize != 0)
441 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
443 // Unwind MBBI to point to first LDR / VLDRD.
444 if (MBBI != MBB.begin()) {
447 while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
448 if (!isCSRestore(*MBBI, CSRegs))
452 // Move SP to start of FP callee save spill area.
453 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
454 AFI->getGPRCalleeSavedArea2Size() +
455 AFI->getDPRCalleeSavedAreaSize() +
458 if (AFI->shouldRestoreSPFromFP()) {
459 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
460 // Reset SP based on frame pointer only if the stack frame extends beyond
461 // frame pointer stack slot, the target is ELF and the function has FP, or
462 // the target uses var sized objects.
464 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
465 "No scratch register to restore SP from FP!");
466 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
468 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
470 .add(predOps(ARMCC::AL));
472 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
474 .add(predOps(ARMCC::AL));
476 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
477 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
478 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
479 if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
480 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
481 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
482 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
486 if (needPopSpecialFixUp(MF)) {
487 bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
489 assert(Done && "Emission of the special fixup failed!?");
493 bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
494 if (!needPopSpecialFixUp(*MBB.getParent()))
497 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
498 return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
501 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
502 ARMFunctionInfo *AFI =
503 const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
504 if (AFI->getArgRegsSaveSize())
507 // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
508 for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
509 if (CSI.getReg() == ARM::LR)
515 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
516 const BitVector &PopFriendly,
517 const LivePhysRegs &UsedRegs, unsigned &PopReg,
520 for (auto Reg : GPRsNoLRSP.set_bits()) {
521 if (!UsedRegs.contains(Reg)) {
522 // Remember the first pop-friendly register and exit.
523 if (PopFriendly.test(Reg)) {
528 // Otherwise, remember that the register will be available to
529 // save a pop-friendly register.
535 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
537 MachineFunction &MF = *MBB.getParent();
538 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
539 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
540 const TargetInstrInfo &TII = *STI.getInstrInfo();
541 const ThumbRegisterInfo *RegInfo =
542 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
544 // If MBBI is a return instruction, or is a tPOP followed by a return
545 // instruction in the successor BB, we may be able to directly restore
547 // This is only possible with v5T ops (v4T can't change the Thumb bit via
548 // a POP PC instruction), and only if we do not need to emit any SP update.
549 // Otherwise, we need a temporary register to pop the value
550 // and copy that value into LR.
551 auto MBBI = MBB.getFirstTerminator();
552 bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
553 if (CanRestoreDirectly) {
554 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
555 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
556 MBBI->getOpcode() == ARM::tPOP_RET);
558 auto MBBI_prev = MBBI;
560 assert(MBBI_prev->getOpcode() == ARM::tPOP);
561 assert(MBB.succ_size() == 1);
562 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
563 MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
565 CanRestoreDirectly = false;
569 if (CanRestoreDirectly) {
570 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
572 MachineInstrBuilder MIB =
573 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
574 .add(predOps(ARMCC::AL));
575 // Copy implicit ops and popped registers, if any.
576 for (auto MO: MBBI->operands())
577 if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
579 MIB.addReg(ARM::PC, RegState::Define);
580 // Erase the old instruction (tBX_RET or tPOP).
585 // Look for a temporary register to use.
586 // First, compute the liveness information.
587 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
588 LivePhysRegs UsedRegs(TRI);
589 UsedRegs.addLiveOuts(MBB);
590 // The semantic of pristines changed recently and now,
591 // the callee-saved registers that are touched in the function
592 // are not part of the pristines set anymore.
593 // Add those callee-saved now.
594 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
595 for (unsigned i = 0; CSRegs[i]; ++i)
596 UsedRegs.addReg(CSRegs[i]);
598 DebugLoc dl = DebugLoc();
599 if (MBBI != MBB.end()) {
600 dl = MBBI->getDebugLoc();
601 auto InstUpToMBBI = MBB.end();
602 while (InstUpToMBBI != MBBI)
603 // The pre-decrement is on purpose here.
604 // We want to have the liveness right before MBBI.
605 UsedRegs.stepBackward(*--InstUpToMBBI);
608 // Look for a register that can be directly use in the POP.
610 // And some temporary register, just in case.
611 unsigned TemporaryReg = 0;
612 BitVector PopFriendly =
613 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
614 assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
615 // Rebuild the GPRs from the high registers because they are removed
616 // form the GPR reg class for thumb1.
617 BitVector GPRsNoLRSP =
618 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
619 GPRsNoLRSP |= PopFriendly;
620 GPRsNoLRSP.reset(ARM::LR);
621 GPRsNoLRSP.reset(ARM::SP);
622 GPRsNoLRSP.reset(ARM::PC);
623 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
625 // If we couldn't find a pop-friendly register, restore LR before popping the
626 // other callee-saved registers, so we can use one of them as a temporary.
627 bool UseLDRSP = false;
628 if (!PopReg && MBBI != MBB.begin()) {
629 auto PrevMBBI = MBBI;
631 if (PrevMBBI->getOpcode() == ARM::tPOP) {
633 UsedRegs.stepBackward(*MBBI);
634 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
639 if (!DoIt && !PopReg && !TemporaryReg)
642 assert((PopReg || TemporaryReg) && "Cannot get LR");
645 assert(PopReg && "Do not know how to get LR");
646 // Load the LR via LDR tmp, [SP, #off]
647 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
648 .addReg(PopReg, RegState::Define)
650 .addImm(MBBI->getNumExplicitOperands() - 2)
651 .add(predOps(ARMCC::AL));
652 // Move from the temporary register to the LR.
653 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
654 .addReg(ARM::LR, RegState::Define)
655 .addReg(PopReg, RegState::Kill)
656 .add(predOps(ARMCC::AL));
657 // Advance past the pop instruction.
660 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize + 4);
665 assert(!PopReg && "Unnecessary MOV is about to be inserted");
666 PopReg = PopFriendly.find_first();
667 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
668 .addReg(TemporaryReg, RegState::Define)
669 .addReg(PopReg, RegState::Kill)
670 .add(predOps(ARMCC::AL));
673 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
674 // We couldn't use the direct restoration above, so
675 // perform the opposite conversion: tPOP_RET to tPOP.
676 MachineInstrBuilder MIB =
677 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
678 .add(predOps(ARMCC::AL));
680 for (auto MO: MBBI->operands())
681 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
682 MO.getReg() != ARM::PC) {
684 if (!MO.isImplicit())
687 // Is there anything left to pop?
689 MBB.erase(MIB.getInstr());
690 // Erase the old instruction.
692 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
693 .add(predOps(ARMCC::AL));
696 assert(PopReg && "Do not know how to get LR");
697 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
698 .add(predOps(ARMCC::AL))
699 .addReg(PopReg, RegState::Define);
701 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
703 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
704 .addReg(ARM::LR, RegState::Define)
705 .addReg(PopReg, RegState::Kill)
706 .add(predOps(ARMCC::AL));
709 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
710 .addReg(PopReg, RegState::Define)
711 .addReg(TemporaryReg, RegState::Kill)
712 .add(predOps(ARMCC::AL));
717 using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
719 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
720 // or OrderEnd if no further registers are in that set. This does not advance
721 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
722 static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
723 const ARMRegSet &EnabledRegs,
724 const unsigned *OrderEnd) {
725 while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
730 bool Thumb1FrameLowering::
731 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
732 MachineBasicBlock::iterator MI,
733 const std::vector<CalleeSavedInfo> &CSI,
734 const TargetRegisterInfo *TRI) const {
739 const TargetInstrInfo &TII = *STI.getInstrInfo();
740 MachineFunction &MF = *MBB.getParent();
741 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
742 MF.getSubtarget().getRegisterInfo());
744 ARMRegSet LoRegsToSave; // r0-r7, lr
745 ARMRegSet HiRegsToSave; // r8-r11
746 ARMRegSet CopyRegs; // Registers which can be used after pushing
747 // LoRegs for saving HiRegs.
749 for (unsigned i = CSI.size(); i != 0; --i) {
750 unsigned Reg = CSI[i-1].getReg();
752 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
753 LoRegsToSave[Reg] = true;
754 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
755 HiRegsToSave[Reg] = true;
757 llvm_unreachable("callee-saved register of unexpected class");
760 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
761 !MF.getRegInfo().isLiveIn(Reg) &&
762 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
763 CopyRegs[Reg] = true;
766 // Unused argument registers can be used for the high register saving.
767 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
768 if (!MF.getRegInfo().isLiveIn(ArgReg))
769 CopyRegs[ArgReg] = true;
771 // Push the low registers and lr
772 const MachineRegisterInfo &MRI = MF.getRegInfo();
773 if (!LoRegsToSave.none()) {
774 MachineInstrBuilder MIB =
775 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
776 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
777 if (LoRegsToSave[Reg]) {
778 bool isKill = !MRI.isLiveIn(Reg);
779 if (isKill && !MRI.isReserved(Reg))
782 MIB.addReg(Reg, getKillRegState(isKill));
785 MIB.setMIFlags(MachineInstr::FrameSetup);
788 // Push the high registers. There are no store instructions that can access
789 // these registers directly, so we have to move them to low registers, and
790 // push them. This might take multiple pushes, as it is possible for there to
791 // be fewer low registers available than high registers which need saving.
793 // These are in reverse order so that in the case where we need to use
794 // multiple PUSH instructions, the order of the registers on the stack still
795 // matches the unwind info. They need to be swicthed back to ascending order
796 // before adding to the PUSH instruction.
797 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
798 ARM::R5, ARM::R4, ARM::R3,
799 ARM::R2, ARM::R1, ARM::R0};
800 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
802 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
803 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
805 // Find the first register to save.
806 const unsigned *HiRegToSave = findNextOrderedReg(
807 std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
809 while (HiRegToSave != AllHighRegsEnd) {
810 // Find the first low register to use.
811 const unsigned *CopyReg =
812 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
814 // Create the PUSH, but don't insert it yet (the MOVs need to come first).
815 MachineInstrBuilder PushMIB =
816 BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
818 SmallVector<unsigned, 4> RegsToPush;
819 while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
820 if (HiRegsToSave[*HiRegToSave]) {
821 bool isKill = !MRI.isLiveIn(*HiRegToSave);
822 if (isKill && !MRI.isReserved(*HiRegToSave))
823 MBB.addLiveIn(*HiRegToSave);
825 // Emit a MOV from the high reg to the low reg.
826 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
827 .addReg(*CopyReg, RegState::Define)
828 .addReg(*HiRegToSave, getKillRegState(isKill))
829 .add(predOps(ARMCC::AL));
831 // Record the register that must be added to the PUSH.
832 RegsToPush.push_back(*CopyReg);
834 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
836 findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
840 // Add the low registers to the PUSH, in ascending order.
841 for (unsigned Reg : llvm::reverse(RegsToPush))
842 PushMIB.addReg(Reg, RegState::Kill);
844 // Insert the PUSH instruction after the MOVs.
845 MBB.insert(MI, PushMIB);
851 bool Thumb1FrameLowering::
852 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
853 MachineBasicBlock::iterator MI,
854 std::vector<CalleeSavedInfo> &CSI,
855 const TargetRegisterInfo *TRI) const {
859 MachineFunction &MF = *MBB.getParent();
860 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
861 const TargetInstrInfo &TII = *STI.getInstrInfo();
862 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
863 MF.getSubtarget().getRegisterInfo());
865 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
866 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
868 ARMRegSet LoRegsToRestore;
869 ARMRegSet HiRegsToRestore;
870 // Low registers (r0-r7) which can be used to restore the high registers.
873 for (CalleeSavedInfo I : CSI) {
874 unsigned Reg = I.getReg();
876 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
877 LoRegsToRestore[Reg] = true;
878 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
879 HiRegsToRestore[Reg] = true;
881 llvm_unreachable("callee-saved register of unexpected class");
884 // If this is a low register not used as the frame pointer, we may want to
885 // use it for restoring the high registers.
886 if ((ARM::tGPRRegClass.contains(Reg)) &&
887 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
888 CopyRegs[Reg] = true;
891 // If this is a return block, we may be able to use some unused return value
892 // registers for restoring the high regs.
893 auto Terminator = MBB.getFirstTerminator();
894 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
895 CopyRegs[ARM::R0] = true;
896 CopyRegs[ARM::R1] = true;
897 CopyRegs[ARM::R2] = true;
898 CopyRegs[ARM::R3] = true;
899 for (auto Op : Terminator->implicit_operands()) {
901 CopyRegs[Op.getReg()] = false;
905 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
906 ARM::R4, ARM::R5, ARM::R6, ARM::R7};
907 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
909 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
910 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
912 // Find the first register to restore.
913 auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
914 HiRegsToRestore, AllHighRegsEnd);
916 while (HiRegToRestore != AllHighRegsEnd) {
917 assert(!CopyRegs.none());
918 // Find the first low register to use.
920 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
922 // Create the POP instruction.
923 MachineInstrBuilder PopMIB =
924 BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
926 while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
927 // Add the low register to the POP.
928 PopMIB.addReg(*CopyReg, RegState::Define);
930 // Create the MOV from low to high register.
931 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
932 .addReg(*HiRegToRestore, RegState::Define)
933 .addReg(*CopyReg, RegState::Kill)
934 .add(predOps(ARMCC::AL));
936 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
938 findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
942 MachineInstrBuilder MIB =
943 BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
945 bool NeedsPop = false;
946 for (unsigned i = CSI.size(); i != 0; --i) {
947 CalleeSavedInfo &Info = CSI[i-1];
948 unsigned Reg = Info.getReg();
950 // High registers (excluding lr) have already been dealt with
951 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
954 if (Reg == ARM::LR) {
955 Info.setRestored(false);
956 if (!MBB.succ_empty() ||
957 MI->getOpcode() == ARM::TCRETURNdi ||
958 MI->getOpcode() == ARM::TCRETURNri)
959 // LR may only be popped into PC, as part of return sequence.
960 // If this isn't the return sequence, we'll need emitPopSpecialFixUp
961 // to restore LR the hard way.
962 // FIXME: if we don't pass any stack arguments it would be actually
963 // advantageous *and* correct to do the conversion to an ordinary call
966 // Special epilogue for vararg functions. See emitEpilogue
969 // ARMv4T requires BX, see emitEpilogue
970 if (!STI.hasV5TOps())
975 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
977 MIB.copyImplicitOps(*MI);
980 MIB.addReg(Reg, getDefRegState(true));
984 // It's illegal to emit pop instruction without operands.
986 MBB.insert(MI, &*MIB);
988 MF.DeleteMachineInstr(MIB);