1 //===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions. This pass should be run after register allocation but before
12 // the post-regalloc scheduling pass.
14 //===----------------------------------------------------------------------===//
17 #include "AVRInstrInfo.h"
18 #include "AVRTargetMachine.h"
19 #include "MCTargetDesc/AVRMCTargetDesc.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/CodeGen/TargetRegisterInfo.h"
29 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
33 /// Expands "placeholder" instructions marked as pseudo into
34 /// actual AVR instructions.
35 class AVRExpandPseudo : public MachineFunctionPass {
39 AVRExpandPseudo() : MachineFunctionPass(ID) {
40 initializeAVRExpandPseudoPass(*PassRegistry::getPassRegistry());
43 bool runOnMachineFunction(MachineFunction &MF) override;
45 StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
48 typedef MachineBasicBlock Block;
49 typedef Block::iterator BlockIt;
51 const AVRRegisterInfo *TRI;
52 const TargetInstrInfo *TII;
54 /// The register to be used for temporary storage.
55 const unsigned SCRATCH_REGISTER = AVR::R0;
56 /// The IO address of the status register.
57 const unsigned SREG_ADDR = 0x3f;
59 bool expandMBB(Block &MBB);
60 bool expandMI(Block &MBB, BlockIt MBBI);
61 template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
63 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
64 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
67 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
69 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
72 MachineRegisterInfo &getRegInfo(Block &MBB) { return MBB.getParent()->getRegInfo(); }
74 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
75 bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
76 bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
77 bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
79 template<typename Func>
80 bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
82 template<typename Func>
83 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
85 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
87 bool expandAtomicArithmeticOp(unsigned MemOpcode,
92 /// Scavenges a free GPR8 register for use.
93 unsigned scavengeGPR8(MachineInstr &MI);
96 char AVRExpandPseudo::ID = 0;
98 bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
99 bool Modified = false;
101 BlockIt MBBI = MBB.begin(), E = MBB.end();
103 BlockIt NMBBI = std::next(MBBI);
104 Modified |= expandMI(MBB, MBBI);
111 bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
112 bool Modified = false;
114 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
115 TRI = STI.getRegisterInfo();
116 TII = STI.getInstrInfo();
118 // We need to track liveness in order to use register scavenging.
119 MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
121 for (Block &MBB : MF) {
122 bool ContinueExpanding = true;
123 unsigned ExpandCount = 0;
125 // Continue expanding the block until all pseudos are expanded.
127 assert(ExpandCount < 10 && "pseudo expand limit reached");
129 bool BlockModified = expandMBB(MBB);
130 Modified |= BlockModified;
133 ContinueExpanding = BlockModified;
134 } while (ContinueExpanding);
140 bool AVRExpandPseudo::
141 expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {
142 MachineInstr &MI = *MBBI;
143 unsigned SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
144 unsigned DstReg = MI.getOperand(0).getReg();
145 unsigned SrcReg = MI.getOperand(2).getReg();
146 bool DstIsDead = MI.getOperand(0).isDead();
147 bool DstIsKill = MI.getOperand(1).isKill();
148 bool SrcIsKill = MI.getOperand(2).isKill();
149 bool ImpIsDead = MI.getOperand(3).isDead();
150 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
151 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
153 buildMI(MBB, MBBI, OpLo)
154 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
155 .addReg(DstLoReg, getKillRegState(DstIsKill))
156 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
158 auto MIBHI = buildMI(MBB, MBBI, OpHi)
159 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
160 .addReg(DstHiReg, getKillRegState(DstIsKill))
161 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
164 MIBHI->getOperand(3).setIsDead();
166 // SREG is always implicitly killed
167 MIBHI->getOperand(4).setIsKill();
169 MI.eraseFromParent();
173 bool AVRExpandPseudo::
174 expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
175 MachineInstr &MI = *MBBI;
176 unsigned SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
177 unsigned DstReg = MI.getOperand(0).getReg();
178 unsigned SrcReg = MI.getOperand(2).getReg();
179 bool DstIsDead = MI.getOperand(0).isDead();
180 bool DstIsKill = MI.getOperand(1).isKill();
181 bool SrcIsKill = MI.getOperand(2).isKill();
182 bool ImpIsDead = MI.getOperand(3).isDead();
183 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
184 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
186 auto MIBLO = buildMI(MBB, MBBI, Op)
187 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
188 .addReg(DstLoReg, getKillRegState(DstIsKill))
189 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
191 // SREG is always implicitly dead
192 MIBLO->getOperand(3).setIsDead();
194 auto MIBHI = buildMI(MBB, MBBI, Op)
195 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
196 .addReg(DstHiReg, getKillRegState(DstIsKill))
197 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
200 MIBHI->getOperand(3).setIsDead();
202 MI.eraseFromParent();
206 bool AVRExpandPseudo::
207 isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
209 // ANDI Rd, 0xff is redundant.
210 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
213 // ORI Rd, 0x0 is redundant.
214 if (Op == AVR::ORIRdK && ImmVal == 0x0)
220 bool AVRExpandPseudo::
221 expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
222 MachineInstr &MI = *MBBI;
223 unsigned DstLoReg, DstHiReg;
224 unsigned DstReg = MI.getOperand(0).getReg();
225 bool DstIsDead = MI.getOperand(0).isDead();
226 bool SrcIsKill = MI.getOperand(1).isKill();
227 bool ImpIsDead = MI.getOperand(3).isDead();
228 unsigned Imm = MI.getOperand(2).getImm();
229 unsigned Lo8 = Imm & 0xff;
230 unsigned Hi8 = (Imm >> 8) & 0xff;
231 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
233 if (!isLogicImmOpRedundant(Op, Lo8)) {
234 auto MIBLO = buildMI(MBB, MBBI, Op)
235 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
236 .addReg(DstLoReg, getKillRegState(SrcIsKill))
239 // SREG is always implicitly dead
240 MIBLO->getOperand(3).setIsDead();
243 if (!isLogicImmOpRedundant(Op, Hi8)) {
244 auto MIBHI = buildMI(MBB, MBBI, Op)
245 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
246 .addReg(DstHiReg, getKillRegState(SrcIsKill))
250 MIBHI->getOperand(3).setIsDead();
253 MI.eraseFromParent();
258 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
259 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
263 bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
264 return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
268 bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
269 return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
273 bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
274 MachineInstr &MI = *MBBI;
275 unsigned DstLoReg, DstHiReg;
276 unsigned DstReg = MI.getOperand(0).getReg();
277 bool DstIsDead = MI.getOperand(0).isDead();
278 bool SrcIsKill = MI.getOperand(1).isKill();
279 bool ImpIsDead = MI.getOperand(3).isDead();
280 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
282 auto MIBLO = buildMI(MBB, MBBI, AVR::SUBIRdK)
283 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
284 .addReg(DstLoReg, getKillRegState(SrcIsKill));
286 auto MIBHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
287 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
288 .addReg(DstHiReg, getKillRegState(SrcIsKill));
290 switch (MI.getOperand(2).getType()) {
291 case MachineOperand::MO_GlobalAddress: {
292 const GlobalValue *GV = MI.getOperand(2).getGlobal();
293 int64_t Offs = MI.getOperand(2).getOffset();
294 unsigned TF = MI.getOperand(2).getTargetFlags();
295 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
296 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
299 case MachineOperand::MO_Immediate: {
300 unsigned Imm = MI.getOperand(2).getImm();
301 MIBLO.addImm(Imm & 0xff);
302 MIBHI.addImm((Imm >> 8) & 0xff);
306 llvm_unreachable("Unknown operand type!");
310 MIBHI->getOperand(3).setIsDead();
312 // SREG is always implicitly killed
313 MIBHI->getOperand(4).setIsKill();
315 MI.eraseFromParent();
320 bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
321 return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
325 bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
326 MachineInstr &MI = *MBBI;
327 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
328 unsigned DstReg = MI.getOperand(0).getReg();
329 bool DstIsDead = MI.getOperand(0).isDead();
330 bool SrcIsKill = MI.getOperand(1).isKill();
331 bool ImpIsDead = MI.getOperand(3).isDead();
332 unsigned Imm = MI.getOperand(2).getImm();
333 unsigned Lo8 = Imm & 0xff;
334 unsigned Hi8 = (Imm >> 8) & 0xff;
337 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
339 auto MIBLO = buildMI(MBB, MBBI, OpLo)
340 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
341 .addReg(DstLoReg, getKillRegState(SrcIsKill))
344 // SREG is always implicitly killed
345 MIBLO->getOperand(4).setIsKill();
347 auto MIBHI = buildMI(MBB, MBBI, OpHi)
348 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
349 .addReg(DstHiReg, getKillRegState(SrcIsKill))
353 MIBHI->getOperand(3).setIsDead();
355 // SREG is always implicitly killed
356 MIBHI->getOperand(4).setIsKill();
358 MI.eraseFromParent();
363 bool AVRExpandPseudo::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
364 return expandLogic(AVR::ANDRdRr, MBB, MBBI);
368 bool AVRExpandPseudo::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
369 return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
373 bool AVRExpandPseudo::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
374 return expandLogic(AVR::ORRdRr, MBB, MBBI);
378 bool AVRExpandPseudo::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
379 return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
383 bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
384 return expandLogic(AVR::EORRdRr, MBB, MBBI);
388 bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
389 MachineInstr &MI = *MBBI;
390 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
391 unsigned DstReg = MI.getOperand(0).getReg();
392 bool DstIsDead = MI.getOperand(0).isDead();
393 bool DstIsKill = MI.getOperand(1).isKill();
394 bool ImpIsDead = MI.getOperand(2).isDead();
397 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
399 auto MIBLO = buildMI(MBB, MBBI, OpLo)
400 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
401 .addReg(DstLoReg, getKillRegState(DstIsKill));
403 // SREG is always implicitly dead
404 MIBLO->getOperand(2).setIsDead();
406 auto MIBHI = buildMI(MBB, MBBI, OpHi)
407 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
408 .addReg(DstHiReg, getKillRegState(DstIsKill));
411 MIBHI->getOperand(2).setIsDead();
413 MI.eraseFromParent();
418 bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
419 MachineInstr &MI = *MBBI;
420 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
421 unsigned DstReg = MI.getOperand(0).getReg();
422 unsigned SrcReg = MI.getOperand(1).getReg();
423 bool DstIsKill = MI.getOperand(0).isKill();
424 bool SrcIsKill = MI.getOperand(1).isKill();
425 bool ImpIsDead = MI.getOperand(2).isDead();
428 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
429 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
432 buildMI(MBB, MBBI, OpLo)
433 .addReg(DstLoReg, getKillRegState(DstIsKill))
434 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
436 auto MIBHI = buildMI(MBB, MBBI, OpHi)
437 .addReg(DstHiReg, getKillRegState(DstIsKill))
438 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
441 MIBHI->getOperand(2).setIsDead();
443 // SREG is always implicitly killed
444 MIBHI->getOperand(3).setIsKill();
446 MI.eraseFromParent();
451 bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
452 MachineInstr &MI = *MBBI;
453 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
454 unsigned DstReg = MI.getOperand(0).getReg();
455 unsigned SrcReg = MI.getOperand(1).getReg();
456 bool DstIsKill = MI.getOperand(0).isKill();
457 bool SrcIsKill = MI.getOperand(1).isKill();
458 bool ImpIsDead = MI.getOperand(2).isDead();
461 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
462 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
464 auto MIBLO = buildMI(MBB, MBBI, OpLo)
465 .addReg(DstLoReg, getKillRegState(DstIsKill))
466 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
468 // SREG is always implicitly killed
469 MIBLO->getOperand(3).setIsKill();
471 auto MIBHI = buildMI(MBB, MBBI, OpHi)
472 .addReg(DstHiReg, getKillRegState(DstIsKill))
473 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
476 MIBHI->getOperand(2).setIsDead();
478 // SREG is always implicitly killed
479 MIBHI->getOperand(3).setIsKill();
481 MI.eraseFromParent();
486 bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
487 MachineInstr &MI = *MBBI;
488 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
489 unsigned DstReg = MI.getOperand(0).getReg();
490 bool DstIsDead = MI.getOperand(0).isDead();
493 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
495 auto MIBLO = buildMI(MBB, MBBI, OpLo)
496 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
498 auto MIBHI = buildMI(MBB, MBBI, OpHi)
499 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
501 switch (MI.getOperand(1).getType()) {
502 case MachineOperand::MO_GlobalAddress: {
503 const GlobalValue *GV = MI.getOperand(1).getGlobal();
504 int64_t Offs = MI.getOperand(1).getOffset();
505 unsigned TF = MI.getOperand(1).getTargetFlags();
507 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
508 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
511 case MachineOperand::MO_BlockAddress: {
512 const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
513 unsigned TF = MI.getOperand(1).getTargetFlags();
515 MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
516 MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
519 case MachineOperand::MO_Immediate: {
520 unsigned Imm = MI.getOperand(1).getImm();
522 MIBLO.addImm(Imm & 0xff);
523 MIBHI.addImm((Imm >> 8) & 0xff);
527 llvm_unreachable("Unknown operand type!");
530 MI.eraseFromParent();
535 bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
536 MachineInstr &MI = *MBBI;
537 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
538 unsigned DstReg = MI.getOperand(0).getReg();
539 bool DstIsDead = MI.getOperand(0).isDead();
542 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
544 auto MIBLO = buildMI(MBB, MBBI, OpLo)
545 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
547 auto MIBHI = buildMI(MBB, MBBI, OpHi)
548 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
550 switch (MI.getOperand(1).getType()) {
551 case MachineOperand::MO_GlobalAddress: {
552 const GlobalValue *GV = MI.getOperand(1).getGlobal();
553 int64_t Offs = MI.getOperand(1).getOffset();
554 unsigned TF = MI.getOperand(1).getTargetFlags();
556 MIBLO.addGlobalAddress(GV, Offs, TF);
557 MIBHI.addGlobalAddress(GV, Offs + 1, TF);
560 case MachineOperand::MO_Immediate: {
561 unsigned Imm = MI.getOperand(1).getImm();
564 MIBHI.addImm(Imm + 1);
568 llvm_unreachable("Unknown operand type!");
571 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
572 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
574 MI.eraseFromParent();
579 bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
580 MachineInstr &MI = *MBBI;
581 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
582 unsigned DstReg = MI.getOperand(0).getReg();
583 unsigned TmpReg = 0; // 0 for no temporary register
584 unsigned SrcReg = MI.getOperand(1).getReg();
585 bool SrcIsKill = MI.getOperand(1).isKill();
586 OpLo = AVR::LDRdPtrPi;
588 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
590 // Use a temporary register if src and dst registers are the same.
591 if (DstReg == SrcReg)
592 TmpReg = scavengeGPR8(MI);
594 unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
595 unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
598 auto MIBLO = buildMI(MBB, MBBI, OpLo)
599 .addReg(CurDstLoReg, RegState::Define)
600 .addReg(SrcReg, RegState::Define)
603 // Push low byte onto stack if necessary.
605 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
608 auto MIBHI = buildMI(MBB, MBBI, OpHi)
609 .addReg(CurDstHiReg, RegState::Define)
610 .addReg(SrcReg, getKillRegState(SrcIsKill));
613 // Move the high byte into the final destination.
614 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
616 // Move the low byte from the scratch space into the final destination.
617 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
620 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
621 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
623 MI.eraseFromParent();
628 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
629 MachineInstr &MI = *MBBI;
630 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
631 unsigned DstReg = MI.getOperand(0).getReg();
632 unsigned SrcReg = MI.getOperand(1).getReg();
633 bool DstIsDead = MI.getOperand(0).isDead();
634 bool SrcIsDead = MI.getOperand(1).isKill();
635 OpLo = AVR::LDRdPtrPi;
636 OpHi = AVR::LDRdPtrPi;
637 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
639 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
641 auto MIBLO = buildMI(MBB, MBBI, OpLo)
642 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
643 .addReg(SrcReg, RegState::Define)
644 .addReg(SrcReg, RegState::Kill);
646 auto MIBHI = buildMI(MBB, MBBI, OpHi)
647 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
648 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
649 .addReg(SrcReg, RegState::Kill);
651 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
652 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
654 MI.eraseFromParent();
659 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
660 MachineInstr &MI = *MBBI;
661 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
662 unsigned DstReg = MI.getOperand(0).getReg();
663 unsigned SrcReg = MI.getOperand(1).getReg();
664 bool DstIsDead = MI.getOperand(0).isDead();
665 bool SrcIsDead = MI.getOperand(1).isKill();
666 OpLo = AVR::LDRdPtrPd;
667 OpHi = AVR::LDRdPtrPd;
668 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
670 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
672 auto MIBHI = buildMI(MBB, MBBI, OpHi)
673 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
674 .addReg(SrcReg, RegState::Define)
675 .addReg(SrcReg, RegState::Kill);
677 auto MIBLO = buildMI(MBB, MBBI, OpLo)
678 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
679 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
680 .addReg(SrcReg, RegState::Kill);
682 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
683 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
685 MI.eraseFromParent();
690 bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
691 MachineInstr &MI = *MBBI;
692 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
693 unsigned DstReg = MI.getOperand(0).getReg();
694 unsigned TmpReg = 0; // 0 for no temporary register
695 unsigned SrcReg = MI.getOperand(1).getReg();
696 unsigned Imm = MI.getOperand(2).getImm();
697 bool SrcIsKill = MI.getOperand(1).isKill();
698 OpLo = AVR::LDDRdPtrQ;
699 OpHi = AVR::LDDRdPtrQ;
700 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
702 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
703 // allowed for the instruction, 62 is the limit here.
704 assert(Imm <= 62 && "Offset is out of range");
706 // Use a temporary register if src and dst registers are the same.
707 if (DstReg == SrcReg)
708 TmpReg = scavengeGPR8(MI);
710 unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
711 unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
714 auto MIBLO = buildMI(MBB, MBBI, OpLo)
715 .addReg(CurDstLoReg, RegState::Define)
719 // Push low byte onto stack if necessary.
721 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
724 auto MIBHI = buildMI(MBB, MBBI, OpHi)
725 .addReg(CurDstHiReg, RegState::Define)
726 .addReg(SrcReg, getKillRegState(SrcIsKill))
730 // Move the high byte into the final destination.
731 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
733 // Move the low byte from the scratch space into the final destination.
734 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
737 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
738 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
740 MI.eraseFromParent();
745 bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
746 MachineInstr &MI = *MBBI;
747 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
748 unsigned DstReg = MI.getOperand(0).getReg();
749 unsigned TmpReg = 0; // 0 for no temporary register
750 unsigned SrcReg = MI.getOperand(1).getReg();
751 bool SrcIsKill = MI.getOperand(1).isKill();
752 OpLo = AVR::LPMRdZPi;
754 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
756 // Use a temporary register if src and dst registers are the same.
757 if (DstReg == SrcReg)
758 TmpReg = scavengeGPR8(MI);
760 unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
761 unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
764 auto MIBLO = buildMI(MBB, MBBI, OpLo)
765 .addReg(CurDstLoReg, RegState::Define)
768 // Push low byte onto stack if necessary.
770 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
773 auto MIBHI = buildMI(MBB, MBBI, OpHi)
774 .addReg(CurDstHiReg, RegState::Define)
775 .addReg(SrcReg, getKillRegState(SrcIsKill));
778 // Move the high byte into the final destination.
779 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
781 // Move the low byte from the scratch space into the final destination.
782 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
785 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
786 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
788 MI.eraseFromParent();
793 bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
794 llvm_unreachable("wide LPMPi is unimplemented");
797 template<typename Func>
798 bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
799 // Remove the pseudo instruction.
800 MachineInstr &MI = *MBBI;
803 buildMI(MBB, MBBI, AVR::INRdA)
804 .addReg(SCRATCH_REGISTER, RegState::Define)
807 // Disable exceptions.
808 buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
812 // Restore the status reg.
813 buildMI(MBB, MBBI, AVR::OUTARr)
815 .addReg(SCRATCH_REGISTER);
817 MI.eraseFromParent();
821 template<typename Func>
822 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
826 return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
827 auto Op1 = MI.getOperand(0);
828 auto Op2 = MI.getOperand(1);
830 MachineInstr &NewInst =
831 *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
836 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
839 return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
842 bool AVRExpandPseudo::expandAtomicArithmeticOp(unsigned Width,
843 unsigned ArithOpcode,
846 return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
847 auto Op1 = MI.getOperand(0);
848 auto Op2 = MI.getOperand(1);
850 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
851 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
854 buildMI(MBB, MBBI, LoadOpcode).add(Op1).add(Op2);
856 // Create the arithmetic op
857 buildMI(MBB, MBBI, ArithOpcode).add(Op1).add(Op1).add(Op2);
860 buildMI(MBB, MBBI, StoreOpcode).add(Op2).add(Op1);
864 unsigned AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {
865 MachineBasicBlock &MBB = *MI.getParent();
868 RS.enterBasicBlock(MBB);
871 BitVector Candidates =
872 TRI->getAllocatableSet
873 (*MBB.getParent(), &AVR::GPR8RegClass);
875 // Exclude all the registers being used by the instruction.
876 for (MachineOperand &MO : MI.operands()) {
877 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
878 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
879 Candidates.reset(MO.getReg());
882 BitVector Available = RS.getRegsAvailable(&AVR::GPR8RegClass);
883 Available &= Candidates;
885 signed Reg = Available.find_first();
886 assert(Reg != -1 && "ran out of registers");
891 bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
892 return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
896 bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
897 return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
901 bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
902 return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
906 bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
907 return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
911 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd8>(Block &MBB, BlockIt MBBI) {
912 return expandAtomicArithmeticOp(8, AVR::ADDRdRr, MBB, MBBI);
916 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd16>(Block &MBB, BlockIt MBBI) {
917 return expandAtomicArithmeticOp(16, AVR::ADDWRdRr, MBB, MBBI);
921 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub8>(Block &MBB, BlockIt MBBI) {
922 return expandAtomicArithmeticOp(8, AVR::SUBRdRr, MBB, MBBI);
926 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub16>(Block &MBB, BlockIt MBBI) {
927 return expandAtomicArithmeticOp(16, AVR::SUBWRdRr, MBB, MBBI);
931 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd8>(Block &MBB, BlockIt MBBI) {
932 return expandAtomicArithmeticOp(8, AVR::ANDRdRr, MBB, MBBI);
936 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd16>(Block &MBB, BlockIt MBBI) {
937 return expandAtomicArithmeticOp(16, AVR::ANDWRdRr, MBB, MBBI);
941 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr8>(Block &MBB, BlockIt MBBI) {
942 return expandAtomicArithmeticOp(8, AVR::ORRdRr, MBB, MBBI);
946 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr16>(Block &MBB, BlockIt MBBI) {
947 return expandAtomicArithmeticOp(16, AVR::ORWRdRr, MBB, MBBI);
951 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor8>(Block &MBB, BlockIt MBBI) {
952 return expandAtomicArithmeticOp(8, AVR::EORRdRr, MBB, MBBI);
956 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor16>(Block &MBB, BlockIt MBBI) {
957 return expandAtomicArithmeticOp(16, AVR::EORWRdRr, MBB, MBBI);
961 bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
962 // On AVR, there is only one core and so atomic fences do nothing.
963 MBBI->eraseFromParent();
968 bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
969 MachineInstr &MI = *MBBI;
970 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;
971 unsigned SrcReg = MI.getOperand(1).getReg();
972 bool SrcIsKill = MI.getOperand(1).isKill();
975 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
977 // Write the high byte first in case this address belongs to a special
978 // I/O address with a special temporary register.
979 auto MIBHI = buildMI(MBB, MBBI, OpHi);
980 auto MIBLO = buildMI(MBB, MBBI, OpLo);
982 switch (MI.getOperand(0).getType()) {
983 case MachineOperand::MO_GlobalAddress: {
984 const GlobalValue *GV = MI.getOperand(0).getGlobal();
985 int64_t Offs = MI.getOperand(0).getOffset();
986 unsigned TF = MI.getOperand(0).getTargetFlags();
988 MIBLO.addGlobalAddress(GV, Offs, TF);
989 MIBHI.addGlobalAddress(GV, Offs + 1, TF);
992 case MachineOperand::MO_Immediate: {
993 unsigned Imm = MI.getOperand(0).getImm();
996 MIBHI.addImm(Imm + 1);
1000 llvm_unreachable("Unknown operand type!");
1003 MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
1004 MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
1006 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1007 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1009 MI.eraseFromParent();
1014 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
1015 MachineInstr &MI = *MBBI;
1016 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;
1017 unsigned DstReg = MI.getOperand(0).getReg();
1018 unsigned SrcReg = MI.getOperand(1).getReg();
1019 bool SrcIsKill = MI.getOperand(1).isKill();
1020 OpLo = AVR::STPtrRr;
1021 OpHi = AVR::STDPtrQRr;
1022 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1024 //:TODO: need to reverse this order like inw and stsw?
1025 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1027 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1029 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1032 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1034 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1035 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1037 MI.eraseFromParent();
1042 bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1043 MachineInstr &MI = *MBBI;
1044 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;
1045 unsigned DstReg = MI.getOperand(0).getReg();
1046 unsigned SrcReg = MI.getOperand(2).getReg();
1047 unsigned Imm = MI.getOperand(3).getImm();
1048 bool DstIsDead = MI.getOperand(0).isDead();
1049 bool SrcIsKill = MI.getOperand(2).isKill();
1050 OpLo = AVR::STPtrPiRr;
1051 OpHi = AVR::STPtrPiRr;
1052 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1054 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1056 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1057 .addReg(DstReg, RegState::Define)
1058 .addReg(DstReg, RegState::Kill)
1059 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1062 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1063 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1064 .addReg(DstReg, RegState::Kill)
1065 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1068 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1069 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1071 MI.eraseFromParent();
1076 bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1077 MachineInstr &MI = *MBBI;
1078 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;
1079 unsigned DstReg = MI.getOperand(0).getReg();
1080 unsigned SrcReg = MI.getOperand(2).getReg();
1081 unsigned Imm = MI.getOperand(3).getImm();
1082 bool DstIsDead = MI.getOperand(0).isDead();
1083 bool SrcIsKill = MI.getOperand(2).isKill();
1084 OpLo = AVR::STPtrPdRr;
1085 OpHi = AVR::STPtrPdRr;
1086 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1088 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1090 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1091 .addReg(DstReg, RegState::Define)
1092 .addReg(DstReg, RegState::Kill)
1093 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1096 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1097 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1098 .addReg(DstReg, RegState::Kill)
1099 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1102 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1103 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1105 MI.eraseFromParent();
1110 bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1111 MachineInstr &MI = *MBBI;
1112 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;
1113 unsigned DstReg = MI.getOperand(0).getReg();
1114 unsigned SrcReg = MI.getOperand(2).getReg();
1115 unsigned Imm = MI.getOperand(1).getImm();
1116 bool DstIsKill = MI.getOperand(0).isKill();
1117 bool SrcIsKill = MI.getOperand(2).isKill();
1118 OpLo = AVR::STDPtrQRr;
1119 OpHi = AVR::STDPtrQRr;
1120 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1122 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1123 // allowed for the instruction, 62 is the limit here.
1124 assert(Imm <= 62 && "Offset is out of range");
1126 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1129 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1131 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1132 .addReg(DstReg, getKillRegState(DstIsKill))
1134 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1136 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1137 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1139 MI.eraseFromParent();
1144 bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1145 MachineInstr &MI = *MBBI;
1146 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
1147 unsigned Imm = MI.getOperand(1).getImm();
1148 unsigned DstReg = MI.getOperand(0).getReg();
1149 bool DstIsDead = MI.getOperand(0).isDead();
1152 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1154 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1155 // allowed for the instruction, 62 is the limit here.
1156 assert(Imm <= 62 && "Address is out of range");
1158 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1159 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1162 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1163 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1166 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1167 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1169 MI.eraseFromParent();
1174 bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1175 MachineInstr &MI = *MBBI;
1176 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;
1177 unsigned Imm = MI.getOperand(0).getImm();
1178 unsigned SrcReg = MI.getOperand(1).getReg();
1179 bool SrcIsKill = MI.getOperand(1).isKill();
1182 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1184 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1185 // allowed for the instruction, 62 is the limit here.
1186 assert(Imm <= 62 && "Address is out of range");
1188 // 16 bit I/O writes need the high byte first
1189 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1191 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1193 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1195 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1197 MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1198 MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1200 MI.eraseFromParent();
1205 bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1206 MachineInstr &MI = *MBBI;
1207 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;
1208 unsigned SrcReg = MI.getOperand(0).getReg();
1209 bool SrcIsKill = MI.getOperand(0).isKill();
1210 unsigned Flags = MI.getFlags();
1213 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1216 buildMI(MBB, MBBI, OpLo)
1217 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1221 buildMI(MBB, MBBI, OpHi)
1222 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1225 MI.eraseFromParent();
1230 bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1231 MachineInstr &MI = *MBBI;
1232 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
1233 unsigned DstReg = MI.getOperand(0).getReg();
1234 unsigned Flags = MI.getFlags();
1237 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1239 buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1240 buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1242 MI.eraseFromParent();
1247 bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1248 MachineInstr &MI = *MBBI;
1249 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
1250 unsigned DstReg = MI.getOperand(0).getReg();
1251 bool DstIsDead = MI.getOperand(0).isDead();
1252 bool DstIsKill = MI.getOperand(1).isKill();
1253 bool ImpIsDead = MI.getOperand(2).isDead();
1256 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1259 buildMI(MBB, MBBI, OpLo)
1260 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1261 .addReg(DstLoReg, getKillRegState(DstIsKill));
1263 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1264 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1265 .addReg(DstHiReg, getKillRegState(DstIsKill));
1268 MIBHI->getOperand(2).setIsDead();
1270 // SREG is always implicitly killed
1271 MIBHI->getOperand(3).setIsKill();
1273 MI.eraseFromParent();
1278 bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1279 MachineInstr &MI = *MBBI;
1280 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
1281 unsigned DstReg = MI.getOperand(0).getReg();
1282 bool DstIsDead = MI.getOperand(0).isDead();
1283 bool DstIsKill = MI.getOperand(1).isKill();
1284 bool ImpIsDead = MI.getOperand(2).isDead();
1287 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1290 buildMI(MBB, MBBI, OpHi)
1291 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1292 .addReg(DstHiReg, getKillRegState(DstIsKill));
1294 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1295 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1296 .addReg(DstLoReg, getKillRegState(DstIsKill));
1299 MIBLO->getOperand(2).setIsDead();
1301 // SREG is always implicitly killed
1302 MIBLO->getOperand(3).setIsKill();
1304 MI.eraseFromParent();
1309 bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
1310 llvm_unreachable("RORW unimplemented");
1315 bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
1316 llvm_unreachable("ROLW unimplemented");
1321 bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
1322 MachineInstr &MI = *MBBI;
1323 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
1324 unsigned DstReg = MI.getOperand(0).getReg();
1325 bool DstIsDead = MI.getOperand(0).isDead();
1326 bool DstIsKill = MI.getOperand(1).isKill();
1327 bool ImpIsDead = MI.getOperand(2).isDead();
1330 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1333 buildMI(MBB, MBBI, OpHi)
1334 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1335 .addReg(DstHiReg, getKillRegState(DstIsKill));
1337 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1338 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1339 .addReg(DstLoReg, getKillRegState(DstIsKill));
1342 MIBLO->getOperand(2).setIsDead();
1344 // SREG is always implicitly killed
1345 MIBLO->getOperand(3).setIsKill();
1347 MI.eraseFromParent();
1351 template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
1352 MachineInstr &MI = *MBBI;
1353 unsigned DstLoReg, DstHiReg;
1354 // sext R17:R16, R17
1358 // sext R17:R16, R13
1363 // sext R17:R16, R16
1367 unsigned DstReg = MI.getOperand(0).getReg();
1368 unsigned SrcReg = MI.getOperand(1).getReg();
1369 bool DstIsDead = MI.getOperand(0).isDead();
1370 bool SrcIsKill = MI.getOperand(1).isKill();
1371 bool ImpIsDead = MI.getOperand(2).isDead();
1372 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1374 if (SrcReg != DstLoReg) {
1375 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
1376 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1379 if (SrcReg == DstHiReg) {
1380 MOV->getOperand(1).setIsKill();
1384 if (SrcReg != DstHiReg) {
1385 buildMI(MBB, MBBI, AVR::MOVRdRr)
1386 .addReg(DstHiReg, RegState::Define)
1387 .addReg(SrcReg, getKillRegState(SrcIsKill));
1390 buildMI(MBB, MBBI, AVR::LSLRd)
1391 .addReg(DstHiReg, RegState::Define)
1392 .addReg(DstHiReg, RegState::Kill);
1394 auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
1395 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1396 .addReg(DstHiReg, RegState::Kill)
1397 .addReg(DstHiReg, RegState::Kill);
1400 SBC->getOperand(3).setIsDead();
1402 // SREG is always implicitly killed
1403 SBC->getOperand(4).setIsKill();
1405 MI.eraseFromParent();
1409 template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
1410 MachineInstr &MI = *MBBI;
1411 unsigned DstLoReg, DstHiReg;
1412 // zext R25:R24, R20
1415 // zext R25:R24, R24
1417 // zext R25:R24, R25
1420 unsigned DstReg = MI.getOperand(0).getReg();
1421 unsigned SrcReg = MI.getOperand(1).getReg();
1422 bool DstIsDead = MI.getOperand(0).isDead();
1423 bool SrcIsKill = MI.getOperand(1).isKill();
1424 bool ImpIsDead = MI.getOperand(2).isDead();
1425 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1427 if (SrcReg != DstLoReg) {
1428 buildMI(MBB, MBBI, AVR::MOVRdRr)
1429 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1430 .addReg(SrcReg, getKillRegState(SrcIsKill));
1433 auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
1434 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1435 .addReg(DstHiReg, RegState::Kill)
1436 .addReg(DstHiReg, RegState::Kill);
1439 EOR->getOperand(3).setIsDead();
1441 MI.eraseFromParent();
1446 bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
1447 MachineInstr &MI = *MBBI;
1448 unsigned OpLo, OpHi, DstLoReg, DstHiReg;
1449 unsigned DstReg = MI.getOperand(0).getReg();
1450 bool DstIsDead = MI.getOperand(0).isDead();
1451 unsigned Flags = MI.getFlags();
1454 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1457 buildMI(MBB, MBBI, OpLo)
1458 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1463 buildMI(MBB, MBBI, OpHi)
1464 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1468 MI.eraseFromParent();
1473 bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
1474 MachineInstr &MI = *MBBI;
1475 unsigned SrcLoReg, SrcHiReg;
1476 unsigned SrcReg = MI.getOperand(1).getReg();
1477 bool SrcIsKill = MI.getOperand(1).isKill();
1478 unsigned Flags = MI.getFlags();
1479 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1481 buildMI(MBB, MBBI, AVR::INRdA)
1482 .addReg(AVR::R0, RegState::Define)
1486 buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
1488 buildMI(MBB, MBBI, AVR::OUTARr)
1490 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1493 buildMI(MBB, MBBI, AVR::OUTARr)
1495 .addReg(AVR::R0, RegState::Kill)
1498 buildMI(MBB, MBBI, AVR::OUTARr)
1500 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1503 MI.eraseFromParent();
1507 bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
1508 MachineInstr &MI = *MBBI;
1509 int Opcode = MBBI->getOpcode();
1511 #define EXPAND(Op) \
1513 return expand<Op>(MBB, MI)
1516 EXPAND(AVR::ADDWRdRr);
1517 EXPAND(AVR::ADCWRdRr);
1518 EXPAND(AVR::SUBWRdRr);
1519 EXPAND(AVR::SUBIWRdK);
1520 EXPAND(AVR::SBCWRdRr);
1521 EXPAND(AVR::SBCIWRdK);
1522 EXPAND(AVR::ANDWRdRr);
1523 EXPAND(AVR::ANDIWRdK);
1524 EXPAND(AVR::ORWRdRr);
1525 EXPAND(AVR::ORIWRdK);
1526 EXPAND(AVR::EORWRdRr);
1527 EXPAND(AVR::COMWRd);
1528 EXPAND(AVR::CPWRdRr);
1529 EXPAND(AVR::CPCWRdRr);
1530 EXPAND(AVR::LDIWRdK);
1531 EXPAND(AVR::LDSWRdK);
1532 EXPAND(AVR::LDWRdPtr);
1533 EXPAND(AVR::LDWRdPtrPi);
1534 EXPAND(AVR::LDWRdPtrPd);
1535 case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
1536 EXPAND(AVR::LDDWRdPtrQ);
1537 EXPAND(AVR::LPMWRdZ);
1538 EXPAND(AVR::LPMWRdZPi);
1539 EXPAND(AVR::AtomicLoad8);
1540 EXPAND(AVR::AtomicLoad16);
1541 EXPAND(AVR::AtomicStore8);
1542 EXPAND(AVR::AtomicStore16);
1543 EXPAND(AVR::AtomicLoadAdd8);
1544 EXPAND(AVR::AtomicLoadAdd16);
1545 EXPAND(AVR::AtomicLoadSub8);
1546 EXPAND(AVR::AtomicLoadSub16);
1547 EXPAND(AVR::AtomicLoadAnd8);
1548 EXPAND(AVR::AtomicLoadAnd16);
1549 EXPAND(AVR::AtomicLoadOr8);
1550 EXPAND(AVR::AtomicLoadOr16);
1551 EXPAND(AVR::AtomicLoadXor8);
1552 EXPAND(AVR::AtomicLoadXor16);
1553 EXPAND(AVR::AtomicFence);
1554 EXPAND(AVR::STSWKRr);
1555 EXPAND(AVR::STWPtrRr);
1556 EXPAND(AVR::STWPtrPiRr);
1557 EXPAND(AVR::STWPtrPdRr);
1558 EXPAND(AVR::STDWPtrQRr);
1559 EXPAND(AVR::INWRdA);
1560 EXPAND(AVR::OUTWARr);
1561 EXPAND(AVR::PUSHWRr);
1562 EXPAND(AVR::POPWRd);
1563 EXPAND(AVR::LSLWRd);
1564 EXPAND(AVR::LSRWRd);
1565 EXPAND(AVR::RORWRd);
1566 EXPAND(AVR::ROLWRd);
1567 EXPAND(AVR::ASRWRd);
1570 EXPAND(AVR::SPREAD);
1571 EXPAND(AVR::SPWRITE);
1577 } // end of anonymous namespace
1579 INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo",
1580 AVR_EXPAND_PSEUDO_NAME, false, false)
1583 FunctionPass *createAVRExpandPseudoPass() { return new AVRExpandPseudo(); }
1585 } // end of namespace llvm