1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "AVRISelLowering.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/ErrorHandling.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRTargetMachine.h"
30 #include "MCTargetDesc/AVRMCTargetDesc.h"
34 AVRTargetLowering::AVRTargetLowering(AVRTargetMachine &tm)
35 : TargetLowering(tm) {
36 // Set up the register classes.
37 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
38 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
40 // Compute derived properties from the register classes.
41 computeRegisterProperties(tm.getSubtargetImpl()->getRegisterInfo());
43 setBooleanContents(ZeroOrOneBooleanContent);
44 setBooleanVectorContents(ZeroOrOneBooleanContent);
45 setSchedulingPreference(Sched::RegPressure);
46 setStackPointerRegisterToSaveRestore(AVR::SP);
47 setSupportsUnalignedAtomics(true);
49 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
50 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
52 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
53 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
54 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
55 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
57 for (MVT VT : MVT::integer_valuetypes()) {
58 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
59 setLoadExtAction(N, VT, MVT::i1, Promote);
60 setLoadExtAction(N, VT, MVT::i8, Expand);
64 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
66 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
67 // revert into a sub since we don't have an add with immediate instruction.
68 setOperationAction(ISD::ADD, MVT::i32, Custom);
69 setOperationAction(ISD::ADD, MVT::i64, Custom);
71 // our shift instructions are only able to shift 1 bit at a time, so handle
72 // this in a custom way.
73 setOperationAction(ISD::SRA, MVT::i8, Custom);
74 setOperationAction(ISD::SHL, MVT::i8, Custom);
75 setOperationAction(ISD::SRL, MVT::i8, Custom);
76 setOperationAction(ISD::SRA, MVT::i16, Custom);
77 setOperationAction(ISD::SHL, MVT::i16, Custom);
78 setOperationAction(ISD::SRL, MVT::i16, Custom);
79 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
80 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
81 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
83 setOperationAction(ISD::ROTL, MVT::i8, Custom);
84 setOperationAction(ISD::ROTL, MVT::i16, Custom);
85 setOperationAction(ISD::ROTR, MVT::i8, Custom);
86 setOperationAction(ISD::ROTR, MVT::i16, Custom);
88 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
90 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
91 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
92 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
94 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
95 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
96 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
97 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
98 setOperationAction(ISD::SETCC, MVT::i8, Custom);
99 setOperationAction(ISD::SETCC, MVT::i16, Custom);
100 setOperationAction(ISD::SETCC, MVT::i32, Custom);
101 setOperationAction(ISD::SETCC, MVT::i64, Custom);
102 setOperationAction(ISD::SELECT, MVT::i8, Expand);
103 setOperationAction(ISD::SELECT, MVT::i16, Expand);
105 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
107 // Add support for postincrement and predecrement load/stores.
108 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
109 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
110 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal);
111 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal);
112 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
113 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
114 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal);
115 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal);
117 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
119 setOperationAction(ISD::VASTART, MVT::Other, Custom);
120 setOperationAction(ISD::VAEND, MVT::Other, Expand);
121 setOperationAction(ISD::VAARG, MVT::Other, Expand);
122 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
124 // Atomic operations which must be lowered to rtlib calls
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand);
127 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand);
128 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand);
129 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand);
130 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand);
131 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
132 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand);
135 // Division/remainder
136 setOperationAction(ISD::UDIV, MVT::i8, Expand);
137 setOperationAction(ISD::UDIV, MVT::i16, Expand);
138 setOperationAction(ISD::UREM, MVT::i8, Expand);
139 setOperationAction(ISD::UREM, MVT::i16, Expand);
140 setOperationAction(ISD::SDIV, MVT::i8, Expand);
141 setOperationAction(ISD::SDIV, MVT::i16, Expand);
142 setOperationAction(ISD::SREM, MVT::i8, Expand);
143 setOperationAction(ISD::SREM, MVT::i16, Expand);
145 // Make division and modulus custom
146 for (MVT VT : MVT::integer_valuetypes()) {
147 setOperationAction(ISD::UDIVREM, VT, Custom);
148 setOperationAction(ISD::SDIVREM, VT, Custom);
151 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
152 setOperationAction(ISD::MUL, MVT::i8, Expand);
153 setOperationAction(ISD::MUL, MVT::i16, Expand);
155 // Expand 16 bit multiplications.
156 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
159 for (MVT VT : MVT::integer_valuetypes()) {
160 setOperationAction(ISD::MULHS, VT, Expand);
161 setOperationAction(ISD::MULHU, VT, Expand);
164 for (MVT VT : MVT::integer_valuetypes()) {
165 setOperationAction(ISD::CTPOP, VT, Expand);
166 setOperationAction(ISD::CTLZ, VT, Expand);
167 setOperationAction(ISD::CTTZ, VT, Expand);
170 for (MVT VT : MVT::integer_valuetypes()) {
171 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
172 // TODO: The generated code is pretty poor. Investigate using the
173 // same "shift and subtract with carry" trick that we do for
174 // extending 8-bit to 16-bit. This may require infrastructure
175 // improvements in how we treat 16-bit "registers" to be feasible.
178 // Division rtlib functions (not supported)
179 setLibcallName(RTLIB::SDIV_I8, nullptr);
180 setLibcallName(RTLIB::SDIV_I16, nullptr);
181 setLibcallName(RTLIB::SDIV_I32, nullptr);
182 setLibcallName(RTLIB::SDIV_I64, nullptr);
183 setLibcallName(RTLIB::SDIV_I128, nullptr);
184 setLibcallName(RTLIB::UDIV_I8, nullptr);
185 setLibcallName(RTLIB::UDIV_I16, nullptr);
186 setLibcallName(RTLIB::UDIV_I32, nullptr);
187 setLibcallName(RTLIB::UDIV_I64, nullptr);
188 setLibcallName(RTLIB::UDIV_I128, nullptr);
190 // Modulus rtlib functions (not supported)
191 setLibcallName(RTLIB::SREM_I8, nullptr);
192 setLibcallName(RTLIB::SREM_I16, nullptr);
193 setLibcallName(RTLIB::SREM_I32, nullptr);
194 setLibcallName(RTLIB::SREM_I64, nullptr);
195 setLibcallName(RTLIB::SREM_I128, nullptr);
196 setLibcallName(RTLIB::UREM_I8, nullptr);
197 setLibcallName(RTLIB::UREM_I16, nullptr);
198 setLibcallName(RTLIB::UREM_I32, nullptr);
199 setLibcallName(RTLIB::UREM_I64, nullptr);
200 setLibcallName(RTLIB::UREM_I128, nullptr);
202 // Division and modulus rtlib functions
203 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
204 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
205 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
206 setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4");
207 setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4");
208 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
209 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
210 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
211 setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4");
212 setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4");
214 // Several of the runtime library functions use a special calling conv
215 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN);
216 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
217 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN);
218 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
220 // Trigonometric rtlib functions
221 setLibcallName(RTLIB::SIN_F32, "sin");
222 setLibcallName(RTLIB::COS_F32, "cos");
224 setMinFunctionAlignment(1);
225 setMinimumJumpTableEntries(INT_MAX);
228 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
257 EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
259 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
263 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
264 //:TODO: this function has to be completely rewritten to produce optimal
265 // code, for now it's producing very long but correct code.
267 const SDNode *N = Op.getNode();
268 EVT VT = Op.getValueType();
271 // Expand non-constant shifts to loops.
272 if (!isa<ConstantSDNode>(N->getOperand(1))) {
273 switch (Op.getOpcode()) {
275 llvm_unreachable("Invalid shift opcode!");
277 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
280 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
283 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
286 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
289 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
294 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
295 SDValue Victim = N->getOperand(0);
297 switch (Op.getOpcode()) {
314 llvm_unreachable("Invalid shift opcode");
317 while (ShiftAmount--) {
318 Victim = DAG.getNode(Opc8, dl, VT, Victim);
324 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
325 unsigned Opcode = Op->getOpcode();
326 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
327 "Invalid opcode for Div/Rem lowering");
328 bool IsSigned = (Opcode == ISD::SDIVREM);
329 EVT VT = Op->getValueType(0);
330 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
333 switch (VT.getSimpleVT().SimpleTy) {
335 llvm_unreachable("Unexpected request for libcall!");
337 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
340 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
343 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
346 LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
350 SDValue InChain = DAG.getEntryNode();
352 TargetLowering::ArgListTy Args;
353 TargetLowering::ArgListEntry Entry;
354 for (SDValue const &Value : Op->op_values()) {
356 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
357 Entry.IsSExt = IsSigned;
358 Entry.IsZExt = !IsSigned;
359 Args.push_back(Entry);
362 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
363 getPointerTy(DAG.getDataLayout()));
365 Type *RetTy = (Type *)StructType::get(Ty, Ty);
368 TargetLowering::CallLoweringInfo CLI(DAG);
371 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
373 .setSExtResult(IsSigned)
374 .setZExtResult(!IsSigned);
376 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
377 return CallInfo.first;
380 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
381 SelectionDAG &DAG) const {
382 auto DL = DAG.getDataLayout();
384 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
385 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
387 // Create the TargetGlobalAddress node, folding in the constant offset.
389 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
390 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
393 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
394 SelectionDAG &DAG) const {
395 auto DL = DAG.getDataLayout();
396 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
398 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
400 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
403 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
404 static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
407 llvm_unreachable("Unknown condition code!");
409 return AVRCC::COND_EQ;
411 return AVRCC::COND_NE;
413 return AVRCC::COND_GE;
415 return AVRCC::COND_LT;
417 return AVRCC::COND_SH;
419 return AVRCC::COND_LO;
423 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
424 /// the given operands.
425 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
426 SDValue &AVRcc, SelectionDAG &DAG,
429 EVT VT = LHS.getValueType();
430 bool UseTest = false;
436 // Swap operands and reverse the branching condition.
442 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
443 switch (C->getSExtValue()) {
445 // When doing lhs > -1 use a tst instruction on the top part of lhs
446 // and use brpl instead of using a chain of cp/cpc.
448 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
452 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
453 // __zero_reg__ in lhs.
455 LHS = DAG.getConstant(0, DL, VT);
460 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
461 // us to fold the constant into the cmp instruction.
462 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
469 // Swap operands and reverse the branching condition.
475 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
476 switch (C->getSExtValue()) {
478 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
479 // __zero_reg__ in lhs.
481 LHS = DAG.getConstant(0, DL, VT);
486 // When doing lhs < 0 use a tst instruction on the top part of lhs
487 // and use brmi instead of using a chain of cp/cpc.
489 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
497 // Swap operands and reverse the branching condition.
503 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
504 // fold the constant into the cmp instruction.
505 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
506 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
510 // Swap operands and reverse the branching condition.
517 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
518 // using the default and/or/xor expansion code which is much longer.
519 if (VT == MVT::i32) {
520 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
521 DAG.getIntPtrConstant(0, DL));
522 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
523 DAG.getIntPtrConstant(1, DL));
524 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
525 DAG.getIntPtrConstant(0, DL));
526 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
527 DAG.getIntPtrConstant(1, DL));
530 // When using tst we only care about the highest part.
531 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
532 DAG.getIntPtrConstant(1, DL));
533 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
535 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
536 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
538 } else if (VT == MVT::i64) {
539 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
540 DAG.getIntPtrConstant(0, DL));
541 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
542 DAG.getIntPtrConstant(1, DL));
544 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
545 DAG.getIntPtrConstant(0, DL));
546 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
547 DAG.getIntPtrConstant(1, DL));
548 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
549 DAG.getIntPtrConstant(0, DL));
550 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
551 DAG.getIntPtrConstant(1, DL));
553 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
554 DAG.getIntPtrConstant(0, DL));
555 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
556 DAG.getIntPtrConstant(1, DL));
558 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
559 DAG.getIntPtrConstant(0, DL));
560 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
561 DAG.getIntPtrConstant(1, DL));
562 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
563 DAG.getIntPtrConstant(0, DL));
564 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
565 DAG.getIntPtrConstant(1, DL));
568 // When using tst we only care about the highest part.
569 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
570 DAG.getIntPtrConstant(1, DL));
571 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
573 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
574 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
575 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
576 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
578 } else if (VT == MVT::i8 || VT == MVT::i16) {
580 // When using tst we only care about the highest part.
581 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
584 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
585 LHS, DAG.getIntPtrConstant(1, DL)));
587 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
590 llvm_unreachable("Invalid comparison size");
593 // When using a test instruction AVRcc is already set.
595 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
601 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
602 SDValue Chain = Op.getOperand(0);
603 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
604 SDValue LHS = Op.getOperand(2);
605 SDValue RHS = Op.getOperand(3);
606 SDValue Dest = Op.getOperand(4);
610 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
612 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
616 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
617 SDValue LHS = Op.getOperand(0);
618 SDValue RHS = Op.getOperand(1);
619 SDValue TrueV = Op.getOperand(2);
620 SDValue FalseV = Op.getOperand(3);
621 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
625 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
627 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
628 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
630 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
633 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
634 SDValue LHS = Op.getOperand(0);
635 SDValue RHS = Op.getOperand(1);
636 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
640 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
642 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
643 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
644 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
645 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
647 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
650 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
651 const MachineFunction &MF = DAG.getMachineFunction();
652 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
653 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
654 auto DL = DAG.getDataLayout();
657 // Vastart just stores the address of the VarArgsFrameIndex slot into the
658 // memory location argument.
659 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
661 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
662 MachinePointerInfo(SV), 0);
665 SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
666 switch (Op.getOpcode()) {
668 llvm_unreachable("Don't know how to custom lower this!");
674 return LowerShifts(Op, DAG);
675 case ISD::GlobalAddress:
676 return LowerGlobalAddress(Op, DAG);
677 case ISD::BlockAddress:
678 return LowerBlockAddress(Op, DAG);
680 return LowerBR_CC(Op, DAG);
682 return LowerSELECT_CC(Op, DAG);
684 return LowerSETCC(Op, DAG);
686 return LowerVASTART(Op, DAG);
689 return LowerDivRem(Op, DAG);
695 /// Replace a node with an illegal result type
696 /// with a new node built out of custom code.
697 void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
698 SmallVectorImpl<SDValue> &Results,
699 SelectionDAG &DAG) const {
702 switch (N->getOpcode()) {
704 // Convert add (x, imm) into sub (x, -imm).
705 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
706 SDValue Sub = DAG.getNode(
707 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
708 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
709 Results.push_back(Sub);
714 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
716 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
717 Results.push_back(Res.getValue(I));
724 /// Return true if the addressing mode represented
725 /// by AM is legal for this target, for a load/store of the specified type.
726 bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
727 const AddrMode &AM, Type *Ty,
728 unsigned AS, Instruction *I) const {
729 int64_t Offs = AM.BaseOffs;
731 // Allow absolute addresses.
732 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
736 // Flash memory instructions only allow zero offsets.
737 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
741 // Allow reg+<6bit> offset.
744 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
751 /// Returns true by value, base pointer and
752 /// offset pointer and addressing mode by reference if the node's address
753 /// can be legally represented as pre-indexed load / store address.
754 bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
756 ISD::MemIndexedMode &AM,
757 SelectionDAG &DAG) const {
762 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
763 VT = LD->getMemoryVT();
764 Op = LD->getBasePtr().getNode();
765 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
767 if (AVR::isProgramMemoryAccess(LD)) {
770 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
771 VT = ST->getMemoryVT();
772 Op = ST->getBasePtr().getNode();
773 if (AVR::isProgramMemoryAccess(ST)) {
780 if (VT != MVT::i8 && VT != MVT::i16) {
784 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
788 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
789 int RHSC = RHS->getSExtValue();
790 if (Op->getOpcode() == ISD::SUB)
793 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
797 Base = Op->getOperand(0);
798 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
807 /// Returns true by value, base pointer and
808 /// offset pointer and addressing mode by reference if this node can be
809 /// combined with a load / store to form a post-indexed load / store.
810 bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
813 ISD::MemIndexedMode &AM,
814 SelectionDAG &DAG) const {
818 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
819 VT = LD->getMemoryVT();
820 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
822 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
823 VT = ST->getMemoryVT();
824 if (AVR::isProgramMemoryAccess(ST)) {
831 if (VT != MVT::i8 && VT != MVT::i16) {
835 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
839 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
840 int RHSC = RHS->getSExtValue();
841 if (Op->getOpcode() == ISD::SUB)
843 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
847 Base = Op->getOperand(0);
848 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
857 bool AVRTargetLowering::isOffsetFoldingLegal(
858 const GlobalAddressSDNode *GA) const {
862 //===----------------------------------------------------------------------===//
863 // Formal Arguments Calling Convention Implementation
864 //===----------------------------------------------------------------------===//
866 #include "AVRGenCallingConv.inc"
868 /// For each argument in a function store the number of pieces it is composed
870 static void parseFunctionArgs(const Function *F, const DataLayout *TD,
871 SmallVectorImpl<unsigned> &Out) {
872 for (Argument const &Arg : F->args()) {
873 unsigned Bytes = (TD->getTypeSizeInBits(Arg.getType()) + 7) / 8;
874 Out.push_back((Bytes + 1) / 2);
878 /// For external symbols there is no function prototype information so we
879 /// have to rely directly on argument sizes.
880 static void parseExternFuncCallArgs(const SmallVectorImpl<ISD::OutputArg> &In,
881 SmallVectorImpl<unsigned> &Out) {
882 for (unsigned i = 0, e = In.size(); i != e;) {
885 while ((i != e) && (In[i].PartOffset == Offset)) {
886 Offset += In[i].VT.getStoreSize();
894 static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI) {
895 SDValue Callee = CLI.Callee;
897 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
898 return G->getSymbol();
901 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
902 return G->getGlobal()->getName();
905 llvm_unreachable("don't know how to get the name for this callee");
908 /// Analyze incoming and outgoing function arguments. We need custom C++ code
909 /// to handle special constraints in the ABI like reversing the order of the
910 /// pieces of splitted arguments. In addition, all pieces of a certain argument
911 /// have to be passed either using registers or the stack but never mixing both.
912 static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI,
913 const Function *F, const DataLayout *TD,
914 const SmallVectorImpl<ISD::OutputArg> *Outs,
915 const SmallVectorImpl<ISD::InputArg> *Ins,
916 CallingConv::ID CallConv,
917 SmallVectorImpl<CCValAssign> &ArgLocs,
918 CCState &CCInfo, bool IsCall, bool IsVarArg) {
919 static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
920 AVR::R18, AVR::R16, AVR::R14,
921 AVR::R12, AVR::R10, AVR::R8};
922 static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
923 AVR::R19R18, AVR::R17R16, AVR::R15R14,
924 AVR::R13R12, AVR::R11R10, AVR::R9R8};
926 // Variadic functions do not need all the analisys below.
928 CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
930 CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
935 // Fill in the Args array which will contain original argument sizes.
936 SmallVector<unsigned, 8> Args;
938 parseExternFuncCallArgs(*Outs, Args);
940 assert(F != nullptr && "function should not be null");
941 parseFunctionArgs(F, TD, Args);
944 unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
945 // Variadic functions always use the stack.
946 bool UsesStack = false;
947 for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
948 unsigned Size = Args[i];
950 // If we have a zero-sized argument, don't attempt to lower it.
951 // AVR-GCC does not support zero-sized arguments and so we need not
952 // worry about ABI compatibility.
953 if (Size == 0) continue;
955 MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
957 // If we have plenty of regs to pass the whole argument do it.
958 if (!UsesStack && (Size <= RegsLeft)) {
959 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
961 for (unsigned j = 0; j != Size; ++j) {
962 unsigned Reg = CCInfo.AllocateReg(
963 ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
965 CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
969 // Reverse the order of the pieces to agree with the "big endian" format
970 // required in the calling convention ABI.
971 std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
973 // Pass the rest of arguments using the stack.
975 for (unsigned j = 0; j != Size; ++j) {
976 unsigned Offset = CCInfo.AllocateStack(
977 TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
978 TD->getABITypeAlignment(
979 EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
980 CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
988 static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI,
989 const Function *F, const DataLayout *TD,
990 const SmallVectorImpl<ISD::OutputArg> *Outs,
991 const SmallVectorImpl<ISD::InputArg> *Ins,
992 CallingConv::ID CallConv,
993 SmallVectorImpl<CCValAssign> &ArgLocs,
994 CCState &CCInfo, bool IsCall, bool IsVarArg) {
995 StringRef FuncName = getFunctionName(CLI);
997 if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
998 CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
1000 analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
1001 CallConv, ArgLocs, CCInfo,
1006 static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
1007 const Function *F, const DataLayout *TD,
1008 const SmallVectorImpl<ISD::OutputArg> *Outs,
1009 const SmallVectorImpl<ISD::InputArg> *Ins,
1010 CallingConv::ID CallConv,
1011 SmallVectorImpl<CCValAssign> &ArgLocs,
1012 CCState &CCInfo, bool IsCall, bool IsVarArg) {
1014 case CallingConv::AVR_BUILTIN: {
1015 analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
1016 CallConv, ArgLocs, CCInfo,
1021 analyzeStandardArguments(CLI, F, TD, Outs, Ins,
1022 CallConv, ArgLocs, CCInfo,
1029 SDValue AVRTargetLowering::LowerFormalArguments(
1030 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1031 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1032 SmallVectorImpl<SDValue> &InVals) const {
1033 MachineFunction &MF = DAG.getMachineFunction();
1034 MachineFrameInfo &MFI = MF.getFrameInfo();
1035 auto DL = DAG.getDataLayout();
1037 // Assign locations to all of the incoming arguments.
1038 SmallVector<CCValAssign, 16> ArgLocs;
1039 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1042 analyzeArguments(nullptr, &MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
1046 for (CCValAssign &VA : ArgLocs) {
1048 // Arguments stored on registers.
1049 if (VA.isRegLoc()) {
1050 EVT RegVT = VA.getLocVT();
1051 const TargetRegisterClass *RC;
1052 if (RegVT == MVT::i8) {
1053 RC = &AVR::GPR8RegClass;
1054 } else if (RegVT == MVT::i16) {
1055 RC = &AVR::DREGSRegClass;
1057 llvm_unreachable("Unknown argument type!");
1060 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1061 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1063 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1064 // following code will handle zexts or sexts generated by other
1065 // front ends. Otherwise:
1066 // If this is an 8 bit value, it is really passed promoted
1067 // to 16 bits. Insert an assert[sz]ext to capture this, then
1068 // truncate to the right size.
1069 switch (VA.getLocInfo()) {
1071 llvm_unreachable("Unknown loc info!");
1072 case CCValAssign::Full:
1074 case CCValAssign::BCvt:
1075 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1077 case CCValAssign::SExt:
1078 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1079 DAG.getValueType(VA.getValVT()));
1080 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1082 case CCValAssign::ZExt:
1083 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1084 DAG.getValueType(VA.getValVT()));
1085 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1089 InVals.push_back(ArgValue);
1092 assert(VA.isMemLoc());
1094 EVT LocVT = VA.getLocVT();
1096 // Create the frame index object for this incoming parameter.
1097 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1098 VA.getLocMemOffset(), true);
1100 // Create the SelectionDAG nodes corresponding to a load
1101 // from this parameter.
1102 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1103 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1104 MachinePointerInfo::getFixedStack(MF, FI),
1109 // If the function takes variable number of arguments, make a frame index for
1110 // the start of the first vararg value... for expansion of llvm.va_start.
1112 unsigned StackSize = CCInfo.getNextStackOffset();
1113 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1115 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1121 //===----------------------------------------------------------------------===//
1122 // Call Calling Convention Implementation
1123 //===----------------------------------------------------------------------===//
1125 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1126 SmallVectorImpl<SDValue> &InVals) const {
1127 SelectionDAG &DAG = CLI.DAG;
1129 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1130 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1131 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1132 SDValue Chain = CLI.Chain;
1133 SDValue Callee = CLI.Callee;
1134 bool &isTailCall = CLI.IsTailCall;
1135 CallingConv::ID CallConv = CLI.CallConv;
1136 bool isVarArg = CLI.IsVarArg;
1138 MachineFunction &MF = DAG.getMachineFunction();
1140 // AVR does not yet support tail call optimization.
1143 // Analyze operands of the call, assigning locations to each operand.
1144 SmallVector<CCValAssign, 16> ArgLocs;
1145 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1148 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1149 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1150 // node so that legalize doesn't hack it.
1151 const Function *F = nullptr;
1152 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1153 const GlobalValue *GV = G->getGlobal();
1155 F = cast<Function>(GV);
1157 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1158 } else if (const ExternalSymbolSDNode *ES =
1159 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1160 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1161 getPointerTy(DAG.getDataLayout()));
1164 analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1167 // Get a count of how many bytes are to be pushed on the stack.
1168 unsigned NumBytes = CCInfo.getNextStackOffset();
1170 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1172 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1174 // First, walk the register assignments, inserting copies.
1176 bool HasStackArgs = false;
1177 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1178 CCValAssign &VA = ArgLocs[AI];
1179 EVT RegVT = VA.getLocVT();
1180 SDValue Arg = OutVals[AI];
1182 // Promote the value if needed. With Clang this should not happen.
1183 switch (VA.getLocInfo()) {
1185 llvm_unreachable("Unknown loc info!");
1186 case CCValAssign::Full:
1188 case CCValAssign::SExt:
1189 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1191 case CCValAssign::ZExt:
1192 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1194 case CCValAssign::AExt:
1195 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1197 case CCValAssign::BCvt:
1198 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1202 // Stop when we encounter a stack argument, we need to process them
1203 // in reverse order in the loop below.
1204 if (VA.isMemLoc()) {
1205 HasStackArgs = true;
1209 // Arguments that can be passed on registers must be kept in the RegsToPass
1211 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1214 // Second, stack arguments have to walked in reverse order by inserting
1215 // chained stores, this ensures their order is not changed by the scheduler
1216 // and that the push instruction sequence generated is correct, otherwise they
1217 // can be freely intermixed.
1219 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1220 unsigned Loc = AI - 1;
1221 CCValAssign &VA = ArgLocs[Loc];
1222 SDValue Arg = OutVals[Loc];
1224 assert(VA.isMemLoc());
1226 // SP points to one stack slot further so add one to adjust it.
1227 SDValue PtrOff = DAG.getNode(
1228 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1229 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1230 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1233 DAG.getStore(Chain, DL, Arg, PtrOff,
1234 MachinePointerInfo::getStack(MF, VA.getLocMemOffset()),
1239 // Build a sequence of copy-to-reg nodes chained together with token chain and
1240 // flag operands which copy the outgoing args into registers. The InFlag in
1241 // necessary since all emited instructions must be stuck together.
1243 for (auto Reg : RegsToPass) {
1244 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1245 InFlag = Chain.getValue(1);
1248 // Returns a chain & a flag for retval copy to use.
1249 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1250 SmallVector<SDValue, 8> Ops;
1251 Ops.push_back(Chain);
1252 Ops.push_back(Callee);
1254 // Add argument registers to the end of the list so that they are known live
1256 for (auto Reg : RegsToPass) {
1257 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1260 // Add a register mask operand representing the call-preserved registers.
1261 const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1262 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
1263 const uint32_t *Mask =
1264 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1265 assert(Mask && "Missing call preserved mask for calling convention");
1266 Ops.push_back(DAG.getRegisterMask(Mask));
1268 if (InFlag.getNode()) {
1269 Ops.push_back(InFlag);
1272 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1273 InFlag = Chain.getValue(1);
1275 // Create the CALLSEQ_END node.
1276 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1277 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1280 InFlag = Chain.getValue(1);
1283 // Handle result values, copying them out of physregs into vregs that we
1285 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1289 /// Lower the result values of a call into the
1290 /// appropriate copies out of appropriate physical registers.
1292 SDValue AVRTargetLowering::LowerCallResult(
1293 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1294 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1295 SmallVectorImpl<SDValue> &InVals) const {
1297 // Assign locations to each value returned by this call.
1298 SmallVector<CCValAssign, 16> RVLocs;
1299 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1302 // Handle runtime calling convs.
1303 auto CCFunction = CCAssignFnForReturn(CallConv);
1304 CCInfo.AnalyzeCallResult(Ins, CCFunction);
1306 if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1307 // Reverse splitted return values to get the "big endian" format required
1308 // to agree with the calling convention ABI.
1309 std::reverse(RVLocs.begin(), RVLocs.end());
1312 // Copy all of the result registers out of their specified physreg.
1313 for (CCValAssign const &RVLoc : RVLocs) {
1314 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1317 InFlag = Chain.getValue(2);
1318 InVals.push_back(Chain.getValue(0));
1324 //===----------------------------------------------------------------------===//
1325 // Return Value Calling Convention Implementation
1326 //===----------------------------------------------------------------------===//
1328 CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
1330 case CallingConv::AVR_BUILTIN:
1331 return RetCC_AVR_BUILTIN;
1338 AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1339 MachineFunction &MF, bool isVarArg,
1340 const SmallVectorImpl<ISD::OutputArg> &Outs,
1341 LLVMContext &Context) const
1343 SmallVector<CCValAssign, 16> RVLocs;
1344 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1346 auto CCFunction = CCAssignFnForReturn(CallConv);
1347 return CCInfo.CheckReturn(Outs, CCFunction);
1351 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1353 const SmallVectorImpl<ISD::OutputArg> &Outs,
1354 const SmallVectorImpl<SDValue> &OutVals,
1355 const SDLoc &dl, SelectionDAG &DAG) const {
1356 // CCValAssign - represent the assignment of the return value to locations.
1357 SmallVector<CCValAssign, 16> RVLocs;
1359 // CCState - Info about the registers and stack slot.
1360 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1363 // Analyze return values.
1364 auto CCFunction = CCAssignFnForReturn(CallConv);
1365 CCInfo.AnalyzeReturn(Outs, CCFunction);
1367 // If this is the first return lowered for this function, add the regs to
1368 // the liveout set for the function.
1369 MachineFunction &MF = DAG.getMachineFunction();
1370 unsigned e = RVLocs.size();
1372 // Reverse splitted return values to get the "big endian" format required
1373 // to agree with the calling convention ABI.
1375 std::reverse(RVLocs.begin(), RVLocs.end());
1379 SmallVector<SDValue, 4> RetOps(1, Chain);
1380 // Copy the result values into the output registers.
1381 for (unsigned i = 0; i != e; ++i) {
1382 CCValAssign &VA = RVLocs[i];
1383 assert(VA.isRegLoc() && "Can only return in registers!");
1385 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1387 // Guarantee that all emitted copies are stuck together with flags.
1388 Flag = Chain.getValue(1);
1389 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1392 // Don't emit the ret/reti instruction when the naked attribute is present in
1393 // the function being compiled.
1394 if (MF.getFunction().getAttributes().hasAttribute(
1395 AttributeList::FunctionIndex, Attribute::Naked)) {
1400 (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL)
1404 RetOps[0] = Chain; // Update chain.
1406 if (Flag.getNode()) {
1407 RetOps.push_back(Flag);
1410 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1413 //===----------------------------------------------------------------------===//
1415 //===----------------------------------------------------------------------===//
1417 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1418 MachineBasicBlock *BB) const {
1420 const TargetRegisterClass *RC;
1421 MachineFunction *F = BB->getParent();
1422 MachineRegisterInfo &RI = F->getRegInfo();
1423 const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1424 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
1425 DebugLoc dl = MI.getDebugLoc();
1427 switch (MI.getOpcode()) {
1429 llvm_unreachable("Invalid shift opcode!");
1432 RC = &AVR::GPR8RegClass;
1436 RC = &AVR::DREGSRegClass;
1440 RC = &AVR::GPR8RegClass;
1444 RC = &AVR::DREGSRegClass;
1448 RC = &AVR::GPR8RegClass;
1452 RC = &AVR::DREGSRegClass;
1456 RC = &AVR::GPR8RegClass;
1460 RC = &AVR::DREGSRegClass;
1464 RC = &AVR::GPR8RegClass;
1468 RC = &AVR::DREGSRegClass;
1472 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1474 MachineFunction::iterator I;
1475 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1476 if (I != F->end()) ++I;
1478 // Create loop block.
1479 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1480 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1482 F->insert(I, LoopBB);
1483 F->insert(I, RemBB);
1485 // Update machine-CFG edges by transferring all successors of the current
1486 // block to the block containing instructions after shift.
1487 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1489 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1491 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1492 BB->addSuccessor(LoopBB);
1493 BB->addSuccessor(RemBB);
1494 LoopBB->addSuccessor(RemBB);
1495 LoopBB->addSuccessor(LoopBB);
1497 unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1498 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1499 unsigned ShiftReg = RI.createVirtualRegister(RC);
1500 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1501 unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1502 unsigned SrcReg = MI.getOperand(1).getReg();
1503 unsigned DstReg = MI.getOperand(0).getReg();
1508 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1509 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1512 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1513 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1514 // ShiftReg2 = shift ShiftReg
1515 // ShiftAmt2 = ShiftAmt - 1;
1516 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1521 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1522 .addReg(ShiftAmtSrcReg)
1524 .addReg(ShiftAmtReg2)
1526 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1527 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1528 .addReg(ShiftAmtReg)
1530 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1533 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1534 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1540 MI.eraseFromParent(); // The pseudo instruction is gone now.
1544 static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
1545 if (I->getOpcode() == AVR::COPY) {
1546 unsigned SrcReg = I->getOperand(1).getReg();
1547 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1553 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1554 // after the result has been evacuated. This is probably not the best way to do
1555 // it, but it works for now.
1556 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1557 MachineBasicBlock *BB) const {
1558 const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1559 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
1560 MachineBasicBlock::iterator I(MI);
1561 ++I; // in any case insert *after* the mul instruction
1562 if (isCopyMulResult(I))
1564 if (isCopyMulResult(I))
1566 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1573 AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1574 MachineBasicBlock *MBB) const {
1575 int Opc = MI.getOpcode();
1577 // Pseudo shift instructions with a non constant shift amount are expanded
1590 return insertShift(MI, MBB);
1593 return insertMul(MI, MBB);
1596 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1597 "Unexpected instr type to insert");
1599 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1603 DebugLoc dl = MI.getDebugLoc();
1605 // To "insert" a SELECT instruction, we insert the diamond
1606 // control-flow pattern. The incoming instruction knows the
1607 // destination vreg to set, the condition code register to branch
1608 // on, the true/false values to select between, and a branch opcode
1611 MachineFunction *MF = MBB->getParent();
1612 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1613 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1614 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1616 MachineFunction::iterator I;
1617 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1618 if (I != MF->end()) ++I;
1619 MF->insert(I, trueMBB);
1620 MF->insert(I, falseMBB);
1622 // Transfer remaining instructions and all successors of the current
1623 // block to the block which will contain the Phi node for the
1625 trueMBB->splice(trueMBB->begin(), MBB,
1626 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1627 trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1629 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1630 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1631 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1632 MBB->addSuccessor(falseMBB);
1633 MBB->addSuccessor(trueMBB);
1635 // Unconditionally flow back to the true block
1636 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1637 falseMBB->addSuccessor(trueMBB);
1639 // Set up the Phi node to determine where we came from
1640 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1641 .addReg(MI.getOperand(1).getReg())
1643 .addReg(MI.getOperand(2).getReg())
1646 MI.eraseFromParent(); // The pseudo instruction is gone now.
1650 //===----------------------------------------------------------------------===//
1651 // Inline Asm Support
1652 //===----------------------------------------------------------------------===//
1654 AVRTargetLowering::ConstraintType
1655 AVRTargetLowering::getConstraintType(StringRef Constraint) const {
1656 if (Constraint.size() == 1) {
1657 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1658 switch (Constraint[0]) {
1659 case 'a': // Simple upper registers
1660 case 'b': // Base pointer registers pairs
1661 case 'd': // Upper register
1662 case 'l': // Lower registers
1663 case 'e': // Pointer register pairs
1664 case 'q': // Stack pointer register
1665 case 'r': // Any register
1666 case 'w': // Special upper register pairs
1667 return C_RegisterClass;
1668 case 't': // Temporary register
1669 case 'x': case 'X': // Pointer register pair X
1670 case 'y': case 'Y': // Pointer register pair Y
1671 case 'z': case 'Z': // Pointer register pair Z
1673 case 'Q': // A memory address based on Y or Z pointer with displacement.
1675 case 'G': // Floating point constant
1676 case 'I': // 6-bit positive integer constant
1677 case 'J': // 6-bit negative integer constant
1678 case 'K': // Integer constant (Range: 2)
1679 case 'L': // Integer constant (Range: 0)
1680 case 'M': // 8-bit integer constant
1681 case 'N': // Integer constant (Range: -1)
1682 case 'O': // Integer constant (Range: 8, 16, 24)
1683 case 'P': // Integer constant (Range: 1)
1684 case 'R': // Integer constant (Range: -6 to 5)x
1691 return TargetLowering::getConstraintType(Constraint);
1695 AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
1696 // Not sure if this is actually the right thing to do, but we got to do
1697 // *something* [agnat]
1698 switch (ConstraintCode[0]) {
1700 return InlineAsm::Constraint_Q;
1702 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1705 AVRTargetLowering::ConstraintWeight
1706 AVRTargetLowering::getSingleConstraintMatchWeight(
1707 AsmOperandInfo &info, const char *constraint) const {
1708 ConstraintWeight weight = CW_Invalid;
1709 Value *CallOperandVal = info.CallOperandVal;
1711 // If we don't have a value, we can't do a match,
1712 // but allow it at the lowest weight.
1713 // (this behaviour has been copied from the ARM backend)
1714 if (!CallOperandVal) {
1718 // Look at the constraint type.
1719 switch (*constraint) {
1721 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1726 weight = CW_Register;
1737 weight = CW_SpecificReg;
1740 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1742 weight = CW_Constant;
1747 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1748 if (isUInt<6>(C->getZExtValue())) {
1749 weight = CW_Constant;
1754 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1755 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1756 weight = CW_Constant;
1761 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1762 if (C->getZExtValue() == 2) {
1763 weight = CW_Constant;
1768 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1769 if (C->getZExtValue() == 0) {
1770 weight = CW_Constant;
1775 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1776 if (isUInt<8>(C->getZExtValue())) {
1777 weight = CW_Constant;
1782 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1783 if (C->getSExtValue() == -1) {
1784 weight = CW_Constant;
1789 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1790 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1791 (C->getZExtValue() == 24)) {
1792 weight = CW_Constant;
1797 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1798 if (C->getZExtValue() == 1) {
1799 weight = CW_Constant;
1804 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1805 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1806 weight = CW_Constant;
1818 std::pair<unsigned, const TargetRegisterClass *>
1819 AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1820 StringRef Constraint,
1822 auto STI = static_cast<const AVRTargetMachine &>(this->getTargetMachine())
1823 .getSubtargetImpl();
1825 // We only support i8 and i16.
1827 //:FIXME: remove this assert for now since it gets sometimes executed
1828 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1830 if (Constraint.size() == 1) {
1831 switch (Constraint[0]) {
1832 case 'a': // Simple upper registers r16..r23.
1833 return std::make_pair(0U, &AVR::LD8loRegClass);
1834 case 'b': // Base pointer registers: y, z.
1835 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1836 case 'd': // Upper registers r16..r31.
1837 return std::make_pair(0U, &AVR::LD8RegClass);
1838 case 'l': // Lower registers r0..r15.
1839 return std::make_pair(0U, &AVR::GPR8loRegClass);
1840 case 'e': // Pointer register pairs: x, y, z.
1841 return std::make_pair(0U, &AVR::PTRREGSRegClass);
1842 case 'q': // Stack pointer register: SPH:SPL.
1843 return std::make_pair(0U, &AVR::GPRSPRegClass);
1844 case 'r': // Any register: r0..r31.
1846 return std::make_pair(0U, &AVR::GPR8RegClass);
1848 assert(VT == MVT::i16 && "inline asm constraint too large");
1849 return std::make_pair(0U, &AVR::DREGSRegClass);
1850 case 't': // Temporary register: r0.
1851 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1852 case 'w': // Special upper register pairs: r24, r26, r28, r30.
1853 return std::make_pair(0U, &AVR::IWREGSRegClass);
1854 case 'x': // Pointer register pair X: r27:r26.
1856 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1857 case 'y': // Pointer register pair Y: r29:r28.
1859 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1860 case 'z': // Pointer register pair Z: r31:r30.
1862 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1868 return TargetLowering::getRegForInlineAsmConstraint(STI->getRegisterInfo(),
1872 void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
1873 std::string &Constraint,
1874 std::vector<SDValue> &Ops,
1875 SelectionDAG &DAG) const {
1876 SDValue Result(0, 0);
1878 EVT Ty = Op.getValueType();
1880 // Currently only support length 1 constraints.
1881 if (Constraint.length() != 1) {
1885 char ConstraintLetter = Constraint[0];
1886 switch (ConstraintLetter) {
1889 // Deal with integers first:
1899 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1904 int64_t CVal64 = C->getSExtValue();
1905 uint64_t CUVal64 = C->getZExtValue();
1906 switch (ConstraintLetter) {
1908 if (!isUInt<6>(CUVal64))
1910 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1913 if (CVal64 < -63 || CVal64 > 0)
1915 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1920 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1925 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1928 if (!isUInt<8>(CUVal64))
1930 // i8 type may be printed as a negative number,
1931 // e.g. 254 would be printed as -2,
1932 // so we force it to i16 at least.
1933 if (Ty.getSimpleVT() == MVT::i8) {
1936 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1941 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1943 case 'O': // 8, 16, 24
1944 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1946 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1951 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1954 if (CVal64 < -6 || CVal64 > 5)
1956 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1963 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
1964 if (!FC || !FC->isZero())
1966 // Soften float to i8 0
1967 Result = DAG.getTargetConstant(0, DL, MVT::i8);
1971 if (Result.getNode()) {
1972 Ops.push_back(Result);
1976 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1979 unsigned AVRTargetLowering::getRegisterByName(const char *RegName,
1981 SelectionDAG &DAG) const {
1984 if (VT == MVT::i8) {
1985 Reg = StringSwitch<unsigned>(RegName)
1986 .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
1987 .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
1988 .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
1989 .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
1990 .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
1991 .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
1992 .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
1993 .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
1994 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
1995 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
1996 .Case("r30", AVR::R30).Case("r31", AVR::R31)
1997 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2000 Reg = StringSwitch<unsigned>(RegName)
2001 .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2002 .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2003 .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2004 .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2005 .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2006 .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2007 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2008 .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2009 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2016 report_fatal_error("Invalid register name global variable");
2019 } // end of namespace llvm