1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_AVR_ISEL_LOWERING_H
16 #define LLVM_AVR_ISEL_LOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/Target/TargetLowering.h"
25 /// AVR Specific DAG Nodes
27 /// Start the numbering where the builtin ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// Return from subroutine.
33 /// Represents an abstract call instruction,
34 /// which includes a bunch of information.
36 /// A wrapper node for TargetConstantPool,
37 /// TargetExternalSymbol, and TargetGlobalAddress.
39 LSL, ///< Logical shift left.
40 LSR, ///< Logical shift right.
41 ASR, ///< Arithmetic shift right.
42 ROR, ///< Bit rotate right.
43 ROL, ///< Bit rotate left.
44 LSLLOOP, ///< A loop of single logical shift left instructions.
45 LSRLOOP, ///< A loop of single logical shift right instructions.
46 ROLLOOP, ///< A loop of single left bit rotate instructions.
47 RORLOOP, ///< A loop of single right bit rotate instructions.
48 ASRLOOP, ///< A loop of single arithmetic shift right instructions.
49 /// AVR conditional branches. Operand 0 is the chain operand, operand 1
50 /// is the block to branch if condition is true, operand 2 is the
51 /// condition code, and operand 3 is the flag operand produced by a CMP
52 /// or TEST instruction.
54 /// Compare instruction.
56 /// Compare with carry instruction.
58 /// Test for zero or minus instruction.
60 /// Operand 0 and operand 1 are selection variable, operand 2
61 /// is condition code and operand 3 is flag operand.
65 } // end of namespace AVRISD
67 class AVRTargetMachine;
69 /// Performs target lowering for the AVR.
70 class AVRTargetLowering : public TargetLowering {
72 explicit AVRTargetLowering(AVRTargetMachine &TM);
75 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
78 const char *getTargetNodeName(unsigned Opcode) const override;
80 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
82 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
83 SelectionDAG &DAG) const override;
85 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
86 unsigned AS) const override;
88 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
89 ISD::MemIndexedMode &AM,
90 SelectionDAG &DAG) const override;
92 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
93 SDValue &Offset, ISD::MemIndexedMode &AM,
94 SelectionDAG &DAG) const override;
96 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
98 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
99 EVT VT) const override;
102 EmitInstrWithCustomInserter(MachineInstr &MI,
103 MachineBasicBlock *MBB) const override;
105 ConstraintType getConstraintType(StringRef Constraint) const override;
108 getSingleConstraintMatchWeight(AsmOperandInfo &info,
109 const char *constraint) const override;
111 std::pair<unsigned, const TargetRegisterClass *>
112 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
113 StringRef Constraint, MVT VT) const override;
115 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
117 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
118 std::vector<SDValue> &Ops,
119 SelectionDAG &DAG) const override;
121 unsigned getRegisterByName(const char* RegName, EVT VT,
122 SelectionDAG &DAG) const override;
125 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
126 SelectionDAG &DAG, SDLoc dl) const;
127 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
137 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
139 bool CanLowerReturn(CallingConv::ID CallConv,
140 MachineFunction &MF, bool isVarArg,
141 const SmallVectorImpl<ISD::OutputArg> &Outs,
142 LLVMContext &Context) const override;
144 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
145 const SmallVectorImpl<ISD::OutputArg> &Outs,
146 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
147 SelectionDAG &DAG) const override;
148 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
150 const SmallVectorImpl<ISD::InputArg> &Ins,
151 const SDLoc &dl, SelectionDAG &DAG,
152 SmallVectorImpl<SDValue> &InVals) const override;
153 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
154 SmallVectorImpl<SDValue> &InVals) const override;
155 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
156 CallingConv::ID CallConv, bool isVarArg,
157 const SmallVectorImpl<ISD::InputArg> &Ins,
158 const SDLoc &dl, SelectionDAG &DAG,
159 SmallVectorImpl<SDValue> &InVals) const;
162 MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
163 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
166 } // end namespace llvm
168 #endif // LLVM_AVR_ISEL_LOWERING_H