1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_AVR_ISEL_LOWERING_H
16 #define LLVM_AVR_ISEL_LOWERING_H
18 #include "llvm/Target/TargetLowering.h"
24 /// AVR Specific DAG Nodes
26 /// Start the numbering where the builtin ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 /// Return from subroutine.
32 /// Represents an abstract call instruction,
33 /// which includes a bunch of information.
35 /// A wrapper node for TargetConstantPool,
36 /// TargetExternalSymbol, and TargetGlobalAddress.
38 LSL, ///< Logical shift left.
39 LSR, ///< Logical shift right.
40 ASR, ///< Arithmetic shift right.
41 ROR, ///< Bit rotate right.
42 ROL, ///< Bit rotate left.
43 LSLLOOP, ///< A loop of single logical shift left instructions.
44 LSRLOOP, ///< A loop of single logical shift right instructions.
45 ASRLOOP, ///< A loop of single arithmetic shift right instructions.
46 /// AVR conditional branches. Operand 0 is the chain operand, operand 1
47 /// is the block to branch if condition is true, operand 2 is the
48 /// condition code, and operand 3 is the flag operand produced by a CMP
49 /// or TEST instruction.
51 /// Compare instruction.
53 /// Compare with carry instruction.
55 /// Test for zero or minus instruction.
57 /// Operand 0 and operand 1 are selection variable, operand 2
58 /// is condition code and operand 3 is flag operand.
62 } // end of namespace AVRISD
64 class AVRTargetMachine;
66 /// Performs target lowering for the AVR.
67 class AVRTargetLowering : public TargetLowering {
69 explicit AVRTargetLowering(AVRTargetMachine &TM);
72 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
75 const char *getTargetNodeName(unsigned Opcode) const override;
77 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
79 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
80 SelectionDAG &DAG) const override;
82 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
83 unsigned AS) const override;
85 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
86 ISD::MemIndexedMode &AM,
87 SelectionDAG &DAG) const override;
89 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
90 SDValue &Offset, ISD::MemIndexedMode &AM,
91 SelectionDAG &DAG) const override;
93 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
96 EmitInstrWithCustomInserter(MachineInstr &MI,
97 MachineBasicBlock *MBB) const override;
99 ConstraintType getConstraintType(StringRef Constraint) const override;
102 getSingleConstraintMatchWeight(AsmOperandInfo &info,
103 const char *constraint) const override;
105 std::pair<unsigned, const TargetRegisterClass *>
106 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
107 StringRef Constraint, MVT VT) const override;
109 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
111 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
112 std::vector<SDValue> &Ops,
113 SelectionDAG &DAG) const override;
116 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
117 SelectionDAG &DAG, SDLoc dl) const;
118 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
129 const SmallVectorImpl<ISD::OutputArg> &Outs,
130 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
131 SelectionDAG &DAG) const override;
132 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
134 const SmallVectorImpl<ISD::InputArg> &Ins,
135 const SDLoc &dl, SelectionDAG &DAG,
136 SmallVectorImpl<SDValue> &InVals) const override;
137 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
138 SmallVectorImpl<SDValue> &InVals) const override;
139 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
140 CallingConv::ID CallConv, bool isVarArg,
141 const SmallVectorImpl<ISD::InputArg> &Ins,
142 const SDLoc &dl, SelectionDAG &DAG,
143 SmallVectorImpl<SDValue> &InVals) const;
146 MachineBasicBlock *insertShift(MachineInstr *MI, MachineBasicBlock *BB) const;
147 MachineBasicBlock *insertMul(MachineInstr *MI, MachineBasicBlock *BB) const;
150 } // end namespace llvm
152 #endif // LLVM_AVR_ISEL_LOWERING_H