1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AVR implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "AVRInstrInfo.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
29 #include "AVRMachineFunctionInfo.h"
30 #include "AVRRegisterInfo.h"
31 #include "AVRTargetMachine.h"
32 #include "MCTargetDesc/AVRMCTargetDesc.h"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "AVRGenInstrInfo.inc"
39 AVRInstrInfo::AVRInstrInfo()
40 : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
42 void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MI,
44 const DebugLoc &DL, unsigned DestReg,
45 unsigned SrcReg, bool KillSrc) const {
46 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
47 const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
50 // Not all AVR devices support the 16-bit `MOVW` instruction.
51 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
53 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
54 .addReg(SrcReg, getKillRegState(KillSrc));
56 unsigned DestLo, DestHi, SrcLo, SrcHi;
58 TRI.splitReg(DestReg, DestLo, DestHi);
59 TRI.splitReg(SrcReg, SrcLo, SrcHi);
61 // Copy each individual register with the `MOV` instruction.
62 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
63 .addReg(SrcLo, getKillRegState(KillSrc));
64 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
65 .addReg(SrcHi, getKillRegState(KillSrc));
68 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
70 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
72 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
75 llvm_unreachable("Impossible reg-to-reg copy");
78 BuildMI(MBB, MI, DL, get(Opc), DestReg)
79 .addReg(SrcReg, getKillRegState(KillSrc));
83 unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
84 int &FrameIndex) const {
85 switch (MI.getOpcode()) {
87 case AVR::LDDWRdYQ: { //:FIXME: remove this once PR13375 gets fixed
88 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
89 MI.getOperand(2).getImm() == 0) {
90 FrameIndex = MI.getOperand(1).getIndex();
91 return MI.getOperand(0).getReg();
102 unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
103 int &FrameIndex) const {
104 switch (MI.getOpcode()) {
106 case AVR::STDWPtrQRr: {
107 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
108 MI.getOperand(1).getImm() == 0) {
109 FrameIndex = MI.getOperand(0).getIndex();
110 return MI.getOperand(2).getReg();
121 void AVRInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator MI,
123 unsigned SrcReg, bool isKill,
125 const TargetRegisterClass *RC,
126 const TargetRegisterInfo *TRI) const {
127 MachineFunction &MF = *MBB.getParent();
128 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
130 AFI->setHasSpills(true);
133 if (MI != MBB.end()) {
134 DL = MI->getDebugLoc();
137 const MachineFrameInfo &MFI = MF.getFrameInfo();
139 MachineMemOperand *MMO = MF.getMachineMemOperand(
140 MachinePointerInfo::getFixedStack(MF, FrameIndex),
141 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
142 MFI.getObjectAlignment(FrameIndex));
145 if (RC->hasType(MVT::i8)) {
146 Opcode = AVR::STDPtrQRr;
147 } else if (RC->hasType(MVT::i16)) {
148 Opcode = AVR::STDWPtrQRr;
150 llvm_unreachable("Cannot store this register into a stack slot!");
153 BuildMI(MBB, MI, DL, get(Opcode))
154 .addFrameIndex(FrameIndex)
156 .addReg(SrcReg, getKillRegState(isKill))
160 void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MI,
162 unsigned DestReg, int FrameIndex,
163 const TargetRegisterClass *RC,
164 const TargetRegisterInfo *TRI) const {
166 if (MI != MBB.end()) {
167 DL = MI->getDebugLoc();
170 MachineFunction &MF = *MBB.getParent();
171 const MachineFrameInfo &MFI = MF.getFrameInfo();
173 MachineMemOperand *MMO = MF.getMachineMemOperand(
174 MachinePointerInfo::getFixedStack(MF, FrameIndex),
175 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
176 MFI.getObjectAlignment(FrameIndex));
179 if (RC->hasType(MVT::i8)) {
180 Opcode = AVR::LDDRdPtrQ;
181 } else if (RC->hasType(MVT::i16)) {
182 // Opcode = AVR::LDDWRdPtrQ;
183 //:FIXME: remove this once PR13375 gets fixed
184 Opcode = AVR::LDDWRdYQ;
186 llvm_unreachable("Cannot load this register from a stack slot!");
189 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
190 .addFrameIndex(FrameIndex)
195 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
198 llvm_unreachable("Unknown condition code!");
200 return get(AVR::BREQk);
202 return get(AVR::BRNEk);
204 return get(AVR::BRGEk);
206 return get(AVR::BRLTk);
208 return get(AVR::BRSHk);
210 return get(AVR::BRLOk);
212 return get(AVR::BRMIk);
214 return get(AVR::BRPLk);
218 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
221 return AVRCC::COND_INVALID;
223 return AVRCC::COND_EQ;
225 return AVRCC::COND_NE;
227 return AVRCC::COND_SH;
229 return AVRCC::COND_LO;
231 return AVRCC::COND_MI;
233 return AVRCC::COND_PL;
235 return AVRCC::COND_GE;
237 return AVRCC::COND_LT;
241 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
244 llvm_unreachable("Invalid condition!");
246 return AVRCC::COND_NE;
248 return AVRCC::COND_EQ;
250 return AVRCC::COND_LO;
252 return AVRCC::COND_SH;
254 return AVRCC::COND_LT;
256 return AVRCC::COND_GE;
258 return AVRCC::COND_PL;
260 return AVRCC::COND_MI;
264 bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
265 MachineBasicBlock *&TBB,
266 MachineBasicBlock *&FBB,
267 SmallVectorImpl<MachineOperand> &Cond,
268 bool AllowModify) const {
269 // Start from the bottom of the block and work up, examining the
270 // terminator instructions.
271 MachineBasicBlock::iterator I = MBB.end();
272 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
274 while (I != MBB.begin()) {
276 if (I->isDebugValue()) {
280 // Working from the bottom, when we see a non-terminator
281 // instruction, we're done.
282 if (!isUnpredicatedTerminator(*I)) {
286 // A terminator that isn't a branch can't easily be handled
288 if (!I->getDesc().isBranch()) {
292 // Handle unconditional branches.
293 //:TODO: add here jmp
294 if (I->getOpcode() == AVR::RJMPk) {
298 TBB = I->getOperand(0).getMBB();
302 // If the block has any instructions after a JMP, delete them.
303 while (std::next(I) != MBB.end()) {
304 std::next(I)->eraseFromParent();
310 // Delete the JMP if it's equivalent to a fall-through.
311 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
313 I->eraseFromParent();
315 UnCondBrIter = MBB.end();
319 // TBB is used to indicate the unconditinal destination.
320 TBB = I->getOperand(0).getMBB();
324 // Handle conditional branches.
325 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
326 if (BranchCode == AVRCC::COND_INVALID) {
327 return true; // Can't handle indirect branch.
330 // Working from the bottom, handle the first conditional branch.
332 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
333 if (AllowModify && UnCondBrIter != MBB.end() &&
334 MBB.isLayoutSuccessor(TargetBB)) {
335 // If we can modify the code and it ends in something like:
343 // Then we can change this to:
350 // Which is a bit more efficient.
351 // We conditionally jump to the fall-through block.
352 BranchCode = getOppositeCondition(BranchCode);
353 unsigned JNCC = getBrCond(BranchCode).getOpcode();
354 MachineBasicBlock::iterator OldInst = I;
356 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
357 .addMBB(UnCondBrIter->getOperand(0).getMBB());
358 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
361 OldInst->eraseFromParent();
362 UnCondBrIter->eraseFromParent();
364 // Restart the analysis.
365 UnCondBrIter = MBB.end();
371 TBB = I->getOperand(0).getMBB();
372 Cond.push_back(MachineOperand::CreateImm(BranchCode));
376 // Handle subsequent conditional branches. Only handle the case where all
377 // conditional branches branch to the same destination.
378 assert(Cond.size() == 1);
381 // Only handle the case where all conditional branches branch to
382 // the same destination.
383 if (TBB != I->getOperand(0).getMBB()) {
387 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
388 // If the conditions are the same, we can leave them alone.
389 if (OldBranchCode == BranchCode) {
399 unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
400 MachineBasicBlock *TBB,
401 MachineBasicBlock *FBB,
402 ArrayRef<MachineOperand> Cond,
404 int *BytesAdded) const {
405 assert(!BytesAdded && "code size not handled");
407 // Shouldn't be a fall through.
408 assert(TBB && "insertBranch must not be told to insert a fallthrough");
409 assert((Cond.size() == 1 || Cond.size() == 0) &&
410 "AVR branch conditions have one component!");
413 assert(!FBB && "Unconditional branch with multiple successors!");
414 BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
418 // Conditional branch.
420 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
421 BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
425 // Two-way Conditional branch. Insert the second branch.
426 BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
433 unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
434 int *BytesRemoved) const {
435 assert(!BytesRemoved && "code size not handled");
437 MachineBasicBlock::iterator I = MBB.end();
440 while (I != MBB.begin()) {
442 if (I->isDebugValue()) {
445 //:TODO: add here the missing jmp instructions once they are implemented
446 // like jmp, {e}ijmp, and other cond branches, ...
447 if (I->getOpcode() != AVR::RJMPk &&
448 getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
452 // Remove the branch.
453 I->eraseFromParent();
461 bool AVRInstrInfo::reverseBranchCondition(
462 SmallVectorImpl<MachineOperand> &Cond) const {
463 assert(Cond.size() == 1 && "Invalid AVR branch condition!");
465 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm());
466 Cond[0].setImm(getOppositeCondition(CC));
471 unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
472 unsigned Opcode = MI.getOpcode();
475 // A regular instruction
477 const MCInstrDesc &Desc = get(Opcode);
478 return Desc.getSize();
480 case TargetOpcode::EH_LABEL:
481 case TargetOpcode::IMPLICIT_DEF:
482 case TargetOpcode::KILL:
483 case TargetOpcode::DBG_VALUE:
485 case TargetOpcode::INLINEASM: {
486 const MachineFunction &MF = *MI.getParent()->getParent();
487 const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
488 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
489 const TargetInstrInfo &TII = *STI.getInstrInfo();
491 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
497 } // end of namespace llvm