1 //===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AVR implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_AVR_INSTR_INFO_H
15 #define LLVM_AVR_INSTR_INFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "AVRRegisterInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "AVRGenInstrInfo.inc"
23 #undef GET_INSTRINFO_HEADER
29 /// AVR specific condition codes.
30 /// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
31 /// They must be kept in synch.
34 COND_NE, //!< Not equal
35 COND_GE, //!< Greater than or equal
36 COND_LT, //!< Less than
37 COND_SH, //!< Unsigned same or higher
38 COND_LO, //!< Unsigned lower
44 } // end of namespace AVRCC
48 /// Specifies a target operand flag.
52 /// On a symbol operand, this represents the lo part.
55 /// On a symbol operand, this represents the hi part.
58 /// On a symbol operand, this represents it has to be negated.
62 } // end of namespace AVRII
64 /// Utilities related to the AVR instruction set.
65 class AVRInstrInfo : public AVRGenInstrInfo {
67 explicit AVRInstrInfo();
69 const AVRRegisterInfo &getRegisterInfo() const { return RI; }
70 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
71 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
72 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
73 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
75 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
76 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
77 bool KillSrc) const override;
78 void storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI, unsigned SrcReg,
80 bool isKill, int FrameIndex,
81 const TargetRegisterClass *RC,
82 const TargetRegisterInfo *TRI) const override;
83 void loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI, unsigned DestReg,
85 int FrameIndex, const TargetRegisterClass *RC,
86 const TargetRegisterInfo *TRI) const override;
87 unsigned isLoadFromStackSlot(const MachineInstr &MI,
88 int &FrameIndex) const override;
89 unsigned isStoreToStackSlot(const MachineInstr &MI,
90 int &FrameIndex) const override;
93 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
94 MachineBasicBlock *&FBB,
95 SmallVectorImpl<MachineOperand> &Cond,
96 bool AllowModify = false) const override;
97 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
98 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
100 int *BytesAdded = nullptr) const override;
101 unsigned removeBranch(MachineBasicBlock &MBB,
102 int *BytesRemoved = nullptr) const override;
104 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
107 const AVRRegisterInfo RI;
110 } // end namespace llvm
112 #endif // LLVM_AVR_INSTR_INFO_H