1 //===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AVR instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "AVRInstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
20 def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
21 def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
22 def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
23 def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
24 def SDT_AVRBrcond : SDTypeProfile<0, 2,
25 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
26 def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
27 def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
28 def SDT_AVRSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
29 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
31 //===----------------------------------------------------------------------===//
32 // AVR Specific Node Definitions
33 //===----------------------------------------------------------------------===//
35 def AVRretflag : SDNode<"AVRISD::RET_FLAG", SDTNone,
36 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
37 def AVRretiflag : SDNode<"AVRISD::RETI_FLAG", SDTNone,
38 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
40 def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart,
41 [SDNPHasChain, SDNPOutGlue]>;
42 def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd,
43 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
45 def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall,
46 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
48 def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>;
50 def AVRbrcond : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond,
51 [SDNPHasChain, SDNPInGlue]>;
52 def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;
53 def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;
54 def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;
55 def AVRselectcc: SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
58 def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
59 def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
60 def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
61 def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
62 def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
64 // Pseudo shift nodes for non-constant shift amounts.
65 def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
66 def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>;
67 def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;
69 //===----------------------------------------------------------------------===//
70 // AVR Operands, Complex Patterns and Transformations Definitions.
71 //===----------------------------------------------------------------------===//
73 def imm8_neg_XFORM : SDNodeXForm<imm,
75 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8);
78 def imm16_neg_XFORM : SDNodeXForm<imm,
80 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);
83 def imm0_63_neg : PatLeaf<(imm),
85 int64_t val = -N->getSExtValue();
86 return val >= 0 && val < 64;
89 def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;
91 def ioaddr_XFORM : SDNodeXForm<imm,
93 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()) - 0x20, SDLoc(N), MVT::i8);
96 def iobitpos8_XFORM : SDNodeXForm<imm,
98 return CurDAG->getTargetConstant(Log2_32(uint8_t(N->getZExtValue())),
102 def iobitposn8_XFORM : SDNodeXForm<imm,
104 return CurDAG->getTargetConstant(Log2_32(uint8_t(~N->getZExtValue())),
108 def ioaddr8 : PatLeaf<(imm),
110 uint64_t val = N->getZExtValue();
111 return val >= 0x20 && val < 0x60;
114 def lowioaddr8 : PatLeaf<(imm),
116 uint64_t val = N->getZExtValue();
117 return val >= 0x20 && val < 0x40;
120 def ioaddr16 : PatLeaf<(imm),
122 uint64_t val = N->getZExtValue();
123 return val >= 0x20 && val < 0x5f;
126 def iobitpos8 : PatLeaf<(imm),
128 return isPowerOf2_32(uint8_t(N->getZExtValue()));
129 }], iobitpos8_XFORM>;
131 def iobitposn8 : PatLeaf<(imm),
133 return isPowerOf2_32(uint8_t(~N->getZExtValue()));
134 }], iobitposn8_XFORM>;
136 def MemriAsmOperand : AsmOperandClass {
138 let ParserMethod = "parseMemriOperand";
141 /// Address operand for `reg+imm` used by STD and LDD.
142 def memri : Operand<iPTR>
144 let MIOperandInfo = (ops PTRDISPREGS, i16imm);
146 let PrintMethod = "printMemri";
147 let EncoderMethod = "encodeMemri";
149 let ParserMatchClass = MemriAsmOperand;
152 // Address operand for `SP+imm` used by STD{W}SPQRr
153 def memspi : Operand<iPTR>
155 let MIOperandInfo = (ops GPRSP, i16imm);
158 def imm_com8 : Operand<i8>
160 let EncoderMethod = "encodeComplement";
162 let MIOperandInfo = (ops i8imm);
165 def relbrtarget_7 : Operand<OtherVT>
167 let PrintMethod = "printPCRelImm";
168 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
171 def brtarget_13 : Operand<OtherVT>
173 let PrintMethod = "printPCRelImm";
174 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
177 // The target of a 22 or 16-bit call/jmp instruction.
178 def call_target : Operand<iPTR>
180 let EncoderMethod = "encodeCallTarget";
183 // A 16-bit address (which can lead to an R_AVR_16 relocation).
184 def imm16 : Operand<i16>
186 let EncoderMethod = "encodeImm<AVR::fixup_16>";
189 /// A 6-bit immediate used in the ADIW/SBIW instructions.
190 def imm_arith6 : Operand<i16>
192 let EncoderMethod = "encodeImm<AVR::fixup_6_adiw>";
195 /// An 8-bit immediate inside an instruction with the same format
196 /// as the `LDI` instruction (the `FRdK` format).
197 def imm_ldi8 : Operand<i8>
199 let EncoderMethod = "encodeImm<AVR::fixup_ldi>";
202 /// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).
203 def imm_port5 : Operand<i8>
205 let EncoderMethod = "encodeImm<AVR::fixup_port5>";
208 /// A 6-bit port number used in the `IN` instruction and friends (the
210 def imm_port6 : Operand<i8>
212 let EncoderMethod = "encodeImm<AVR::fixup_port6>";
215 // Addressing mode pattern reg+imm6
216 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>;
218 // AsmOperand class for a pointer register.
219 // Used with the LD/ST family of instructions.
220 // See FSTLD in AVRInstrFormats.td
221 def PtrRegAsmOperand : AsmOperandClass
226 // A special operand type for the LD/ST instructions.
227 // It converts the pointer register number into a two-bit field used in the
229 def LDSTPtrReg : Operand<i16>
231 let MIOperandInfo = (ops PTRREGS);
232 let EncoderMethod = "encodeLDSTPtrReg";
234 let ParserMatchClass = PtrRegAsmOperand;
237 // A special operand type for the LDD/STD instructions.
238 // It behaves identically to the LD/ST version, except restricts
239 // the pointer registers to Y and Z.
240 def LDDSTDPtrReg : Operand<i16>
242 let MIOperandInfo = (ops PTRDISPREGS);
243 let EncoderMethod = "encodeLDSTPtrReg";
245 let ParserMatchClass = PtrRegAsmOperand;
248 //===----------------------------------------------------------------------===//
249 // AVR predicates for subtarget features
250 //===----------------------------------------------------------------------===//
252 def HasSRAM : Predicate<"Subtarget->hasSRAM()">,
253 AssemblerPredicate<"FeatureSRAM">;
255 def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">,
256 AssemblerPredicate<"FeatureJMPCALL">;
258 def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">,
259 AssemblerPredicate<"FeatureIJMPCALL">;
261 def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">,
262 AssemblerPredicate<"FeatureEIJMPCALL">;
264 def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">,
265 AssemblerPredicate<"FeatureADDSUBIW">;
267 def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">,
268 AssemblerPredicate<"FeatureSmallStack">;
270 def HasMOVW : Predicate<"Subtarget->hasMOVW()">,
271 AssemblerPredicate<"FeatureMOVW">;
273 def HasLPM : Predicate<"Subtarget->hasLPM()">,
274 AssemblerPredicate<"FeatureLPM">;
276 def HasLPMX : Predicate<"Subtarget->hasLPMX()">,
277 AssemblerPredicate<"FeatureLPMX">;
279 def HasELPM : Predicate<"Subtarget->hasELPM()">,
280 AssemblerPredicate<"FeatureELPM">;
282 def HasELPMX : Predicate<"Subtarget->hasELPMX()">,
283 AssemblerPredicate<"FeatureELPMX">;
285 def HasSPM : Predicate<"Subtarget->hasSPM()">,
286 AssemblerPredicate<"FeatureSPM">;
288 def HasSPMX : Predicate<"Subtarget->hasSPMX()">,
289 AssemblerPredicate<"FeatureSPMX">;
291 def HasDES : Predicate<"Subtarget->hasDES()">,
292 AssemblerPredicate<"FeatureDES">;
294 def SupportsRMW : Predicate<"Subtarget->supportsRMW()">,
295 AssemblerPredicate<"FeatureRMW">;
297 def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,
298 AssemblerPredicate<"FeatureMultiplication">;
300 def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
301 AssemblerPredicate<"FeatureBREAK">;
303 def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,
304 AssemblerPredicate<"FeatureTinyEncoding">;
307 // AVR specific condition code. These correspond to AVR_*_COND in
308 // AVRInstrInfo.td. They must be kept in synch.
309 def AVR_COND_EQ : PatLeaf<(i8 0)>;
310 def AVR_COND_NE : PatLeaf<(i8 1)>;
311 def AVR_COND_GE : PatLeaf<(i8 2)>;
312 def AVR_COND_LT : PatLeaf<(i8 3)>;
313 def AVR_COND_SH : PatLeaf<(i8 4)>;
314 def AVR_COND_LO : PatLeaf<(i8 5)>;
315 def AVR_COND_MI : PatLeaf<(i8 6)>;
316 def AVR_COND_PL : PatLeaf<(i8 7)>;
319 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
321 // AVR Instruction list
322 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
325 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
326 // a stack adjustment and the codegen must know that they may modify the stack
327 // pointer before prolog-epilog rewriting occurs.
328 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
329 // sub / add which can clobber SREG.
330 let Defs = [SP, SREG],
333 def ADJCALLSTACKDOWN : Pseudo<(outs),
336 [(AVRcallseq_start timm:$amt)]>;
338 // R31R30 is used to update SP, since it is a scratch reg and this instruction
339 // is placed after the function call then R31R30 should be always free.
340 //let Defs = [R31R30],
342 //:TODO: if we enable this, the pseudo is killed because it looks dead
343 def ADJCALLSTACKUP : Pseudo<(outs),
344 (ins i16imm:$amt1, i16imm:$amt2),
346 [(AVRcallseq_end timm:$amt1, timm:$amt2)]>;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
352 let isCommutable = 1,
353 Constraints = "$src = $rd",
357 // Adds two 8-bit registers.
358 def ADDRdRr : FRdRr<0b0000,
361 (ins GPR8:$src, GPR8:$rr),
363 [(set i8:$rd, (add i8:$src, i8:$rr)),
366 // ADDW Rd+1:Rd, Rr+1:Rr
367 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
372 def ADDWRdRr : Pseudo<(outs DREGS:$rd),
373 (ins DREGS:$src, DREGS:$rr),
375 [(set i16:$rd, (add i16:$src, i16:$rr)),
379 // Adds two 8-bit registers with carry.
381 def ADCRdRr : FRdRr<0b0001,
384 (ins GPR8:$src, GPR8:$rr),
386 [(set i8:$rd, (adde i8:$src, i8:$rr)),
389 // ADCW Rd+1:Rd, Rr+1:Rr
390 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
397 def ADCWRdRr : Pseudo<(outs DREGS:$rd),
398 (ins DREGS:$src, DREGS:$rr),
400 [(set i16:$rd, (adde i16:$src, i16:$rr)),
404 // Adds an immediate 6-bit value K to Rd, placing the result in Rd.
405 def ADIWRdK : FWRdK<0b0,
407 (ins IWREGS:$src, imm_arith6:$k),
409 [(set i16:$rd, (add i16:$src, uimm6:$k)),
411 Requires<[HasADDSUBIW]>;
414 //===----------------------------------------------------------------------===//
416 //===----------------------------------------------------------------------===//
417 let Constraints = "$src = $rd",
421 // Subtracts the 8-bit value of Rr from Rd and places the value in Rd.
422 def SUBRdRr : FRdRr<0b0001,
425 (ins GPR8:$src, GPR8:$rr),
427 [(set i8:$rd, (sub i8:$src, i8:$rr)),
430 // SUBW Rd+1:Rd, Rr+1:Rr
431 // Subtracts two 16-bit values and places the result into Rd.
436 def SUBWRdRr : Pseudo<(outs DREGS:$rd),
437 (ins DREGS:$src, DREGS:$rr),
439 [(set i16:$rd, (sub i16:$src, i16:$rr)),
442 def SUBIRdK : FRdK<0b0101,
444 (ins LD8:$src, imm_ldi8:$k),
446 [(set i8:$rd, (sub i8:$src, imm:$k)),
449 // SUBIW Rd+1:Rd, K+1:K
454 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
455 (ins DLDREGS:$src, i16imm:$rr),
457 [(set i16:$rd, (sub i16:$src, imm:$rr)),
460 def SBIWRdK : FWRdK<0b1,
462 (ins IWREGS:$src, imm_arith6:$k),
464 [(set i16:$rd, (sub i16:$src, uimm6:$k)),
466 Requires<[HasADDSUBIW]>;
468 // Subtract with carry operations which must read the carry flag in SREG.
471 def SBCRdRr : FRdRr<0b0000,
474 (ins GPR8:$src, GPR8:$rr),
476 [(set i8:$rd, (sube i8:$src, i8:$rr)),
479 // SBCW Rd+1:Rd, Rr+1:Rr
484 def SBCWRdRr : Pseudo<(outs DREGS:$rd),
485 (ins DREGS:$src, DREGS:$rr),
487 [(set i16:$rd, (sube i16:$src, i16:$rr)),
490 def SBCIRdK : FRdK<0b0100,
492 (ins LD8:$src, imm_ldi8:$k),
494 [(set i8:$rd, (sube i8:$src, imm:$k)),
497 // SBCIW Rd+1:Rd, K+1:K
500 def SBCIWRdK : Pseudo<(outs DLDREGS:$rd),
501 (ins DLDREGS:$src, i16imm:$rr),
503 [(set i16:$rd, (sube i16:$src, imm:$rr)),
508 //===----------------------------------------------------------------------===//
509 // Increment and Decrement
510 //===----------------------------------------------------------------------===//
511 let Constraints = "$src = $rd",
514 def INCRd : FRd<0b1001,
519 [(set i8:$rd, (add i8:$src, 1)), (implicit SREG)]>;
521 def DECRd : FRd<0b1001,
526 [(set i8:$rd, (add i8:$src, -1)), (implicit SREG)]>;
529 //===----------------------------------------------------------------------===//
531 //===----------------------------------------------------------------------===//
533 let isCommutable = 1,
534 Defs = [R1, R0, SREG] in
537 // Multiplies Rd by Rr and places the result into R1:R0.
538 let usesCustomInserter = 1 in {
539 def MULRdRr : FRdRr<0b1001, 0b11,
541 (ins GPR8:$lhs, GPR8:$rhs),
543 [/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>,
544 Requires<[SupportsMultiplication]>;
546 def MULSRdRr : FMUL2RdRr<0,
548 (ins GPR8:$lhs, GPR8:$rhs),
551 Requires<[SupportsMultiplication]>;
554 def MULSURdRr : FMUL2RdRr<1,
556 (ins GPR8:$lhs, GPR8:$rhs),
559 Requires<[SupportsMultiplication]>;
561 def FMUL : FFMULRdRr<0b01,
563 (ins GPR8:$lhs, GPR8:$rhs),
566 Requires<[SupportsMultiplication]>;
568 def FMULS : FFMULRdRr<0b10,
570 (ins GPR8:$lhs, GPR8:$rhs),
573 Requires<[SupportsMultiplication]>;
575 def FMULSU : FFMULRdRr<0b11,
577 (ins GPR8:$lhs, GPR8:$rhs),
578 "fmulsu\t$lhs, $rhs",
580 Requires<[SupportsMultiplication]>;
583 let Defs = [R15, R14, R13, R12, R11, R10, R9,
584 R8, R7, R6, R5, R4, R3, R2, R1, R0] in
585 def DESK : FDES<(outs),
591 //===----------------------------------------------------------------------===//
593 //===----------------------------------------------------------------------===//
594 let Constraints = "$src = $rd",
597 // Register-Register logic instructions (which have the
598 // property of commutativity).
599 let isCommutable = 1 in
601 def ANDRdRr : FRdRr<0b0010,
604 (ins GPR8:$src, GPR8:$rr),
606 [(set i8:$rd, (and i8:$src, i8:$rr)),
609 // ANDW Rd+1:Rd, Rr+1:Rr
614 def ANDWRdRr : Pseudo<(outs DREGS:$rd),
615 (ins DREGS:$src, DREGS:$rr),
617 [(set i16:$rd, (and i16:$src, i16:$rr)),
620 def ORRdRr : FRdRr<0b0010,
623 (ins GPR8:$src, GPR8:$rr),
625 [(set i8:$rd, (or i8:$src, i8:$rr)),
628 // ORW Rd+1:Rd, Rr+1:Rr
633 def ORWRdRr : Pseudo<(outs DREGS:$rd),
634 (ins DREGS:$src, DREGS:$rr),
636 [(set i16:$rd, (or i16:$src, i16:$rr)),
639 def EORRdRr : FRdRr<0b0010,
642 (ins GPR8:$src, GPR8:$rr),
644 [(set i8:$rd, (xor i8:$src, i8:$rr)),
647 // EORW Rd+1:Rd, Rr+1:Rr
652 def EORWRdRr : Pseudo<(outs DREGS:$rd),
653 (ins DREGS:$src, DREGS:$rr),
655 [(set i16:$rd, (xor i16:$src, i16:$rr)),
659 def ANDIRdK : FRdK<0b0111,
661 (ins LD8:$src, imm_ldi8:$k),
663 [(set i8:$rd, (and i8:$src, imm:$k)),
666 // ANDI Rd+1:Rd, K+1:K
671 def ANDIWRdK : Pseudo<(outs DLDREGS:$rd),
672 (ins DLDREGS:$src, i16imm:$k),
674 [(set i16:$rd, (and i16:$src, imm:$k)),
677 def ORIRdK : FRdK<0b0110,
679 (ins LD8:$src, imm_ldi8:$k),
681 [(set i8:$rd, (or i8:$src, imm:$k)),
684 // ORIW Rd+1:Rd, K+1,K
689 def ORIWRdK : Pseudo<(outs DLDREGS:$rd),
690 (ins DLDREGS:$src, i16imm:$rr),
692 [(set i16:$rd, (or i16:$src, imm:$rr)),
696 //===----------------------------------------------------------------------===//
697 // One's/Two's Compliment
698 //===----------------------------------------------------------------------===//
699 let Constraints = "$src = $rd",
702 def COMRd : FRd<0b1001,
707 [(set i8:$rd, (not i8:$src)), (implicit SREG)]>;
714 def COMWRd : Pseudo<(outs DREGS:$rd),
717 [(set i16:$rd, (not i16:$src)), (implicit SREG)]>;
719 //:TODO: optimize NEG for wider types
720 def NEGRd : FRd<0b1001,
725 [(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>;
729 // Test for zero of minus.
730 // This operation is identical to a `Rd AND Rd`.
731 //def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd), 1>;
734 def TSTRd : FTST<0b0010,
741 //===----------------------------------------------------------------------===//
743 //===----------------------------------------------------------------------===//
750 (ins brtarget_13:$target),
754 let isIndirectBranch = 1,
756 def IJMP : F16<0b1001010000001001,
761 Requires<[HasIJMPCALL]>;
763 let isIndirectBranch = 1,
765 def EIJMP : F16<0b1001010000011001,
770 Requires<[HasEIJMPCALL]>;
772 def JMPk : F32BRk<0b110,
774 (ins call_target:$k),
777 Requires<[HasJMPCALL]>;
780 //===----------------------------------------------------------------------===//
782 //===----------------------------------------------------------------------===//
785 // SP is marked as a use to prevent stack-pointer assignments that appear
786 // immediately before calls from potentially appearing dead.
790 (ins brtarget_13:$target),
794 // SP is marked as a use to prevent stack-pointer assignments that appear
795 // immediately before calls from potentially appearing dead.
796 let Uses = [SP, R31R30] in
797 def ICALL : F16<0b1001010100001001,
802 Requires<[HasIJMPCALL]>;
804 // SP is marked as a use to prevent stack-pointer assignments that appear
805 // immediately before calls from potentially appearing dead.
806 let Uses = [SP, R31R30] in
807 def EICALL : F16<0b1001010100011001,
812 Requires<[HasEIJMPCALL]>;
814 // SP is marked as a use to prevent stack-pointer assignments that appear
815 // immediately before calls from potentially appearing dead.
817 //:TODO: the imm field can be either 16 or 22 bits in devices with more
818 // than 64k of ROM, fix it once we support the largest devices.
820 def CALLk : F32BRk<0b111,
822 (ins call_target:$k),
825 Requires<[HasJMPCALL]>;
828 //===----------------------------------------------------------------------===//
829 // Return instructions.
830 //===----------------------------------------------------------------------===//
831 let isTerminator = 1,
835 def RET : F16<0b1001010100001000,
841 def RETI : F16<0b1001010100011000,
848 //===----------------------------------------------------------------------===//
849 // Compare operations.
850 //===----------------------------------------------------------------------===//
854 // Compare Rd and Rr, skipping the next instruction if they are equal.
858 def CPSE : FRdRr<0b0001,
861 (ins GPR8:$rd, GPR8:$rr),
865 def CPRdRr : FRdRr<0b0001,
868 (ins GPR8:$rd, GPR8:$rr),
870 [(AVRcmp i8:$rd, i8:$rr), (implicit SREG)]>;
872 // CPW Rd+1:Rd, Rr+1:Rr
877 def CPWRdRr : Pseudo<(outs),
878 (ins DREGS:$src, DREGS:$src2),
880 [(AVRcmp i16:$src, i16:$src2), (implicit SREG)]>;
883 def CPCRdRr : FRdRr<0b0000,
886 (ins GPR8:$rd, GPR8:$rr),
888 [(AVRcmpc i8:$rd, i8:$rr), (implicit SREG)]>;
890 // CPCW Rd+1:Rd. Rr+1:Rr
896 def CPCWRdRr : Pseudo<(outs),
897 (ins DREGS:$src, DREGS:$src2),
899 [(AVRcmpc i16:$src, i16:$src2), (implicit SREG)]>;
902 // Compares a register with an 8 bit immediate.
904 def CPIRdK : FRdK<0b0011,
906 (ins GPR8:$rd, imm_ldi8:$k),
908 [(AVRcmp i8:$rd, imm:$k), (implicit SREG)]>;
911 //===----------------------------------------------------------------------===//
912 // Register conditional skipping/branching operations.
913 //===----------------------------------------------------------------------===//
917 // Conditional skipping on GPR register bits, and
918 // conditional skipping on IO register bits.
921 def SBRCRrB : FRdB<0b10,
923 (ins GPR8:$rr, i8imm:$b),
927 def SBRSRrB : FRdB<0b11,
929 (ins GPR8:$rr, i8imm:$b),
933 def SBICAb : FIOBIT<0b01,
935 (ins imm_port5:$a, i8imm:$b),
939 def SBISAb : FIOBIT<0b11,
941 (ins imm_port5:$a, i8imm:$b),
946 // Relative branches on status flag bits.
950 // Branch if `s` flag in status register is set.
953 (ins i8imm:$s, relbrtarget_7:$k),
958 // Branch if `s` flag in status register is clear.
961 (ins i8imm:$s, relbrtarget_7:$k),
969 // Branch if carry flag is set
970 def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7:$k)>;
973 // Branch if carry flag is clear
974 def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7:$k)>;
977 // Branch if half carry flag is set
978 def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7:$k)>;
981 // Branch if half carry flag is clear
982 def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7:$k)>;
985 // Branch if the T flag is set
986 def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7:$k)>;
989 // Branch if the T flag is clear
990 def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7:$k)>;
993 // Branch if the overflow flag is set
994 def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7:$k)>;
997 // Branch if the overflow flag is clear
998 def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7:$k)>;
1001 // Branch if the global interrupt flag is enabled
1002 def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7:$k)>;
1005 // Branch if the global interrupt flag is disabled
1006 def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7:$k)>;
1008 //===----------------------------------------------------------------------===//
1009 // PC-relative conditional branches
1010 //===----------------------------------------------------------------------===//
1011 // Based on status register. We cannot simplify these into instruction aliases
1012 // because we also need to be able to specify a pattern to match for ISel.
1017 def BREQk : FBRsk<0,
1020 (ins relbrtarget_7:$target),
1022 [(AVRbrcond bb:$target, AVR_COND_EQ)]>;
1024 def BRNEk : FBRsk<1,
1027 (ins relbrtarget_7:$target),
1029 [(AVRbrcond bb:$target, AVR_COND_NE)]>;
1032 def BRSHk : FBRsk<1,
1035 (ins relbrtarget_7:$target),
1037 [(AVRbrcond bb:$target, AVR_COND_SH)]>;
1039 def BRLOk : FBRsk<0,
1042 (ins relbrtarget_7:$target),
1044 [(AVRbrcond bb:$target, AVR_COND_LO)]>;
1046 def BRMIk : FBRsk<0,
1049 (ins relbrtarget_7:$target),
1051 [(AVRbrcond bb:$target, AVR_COND_MI)]>;
1053 def BRPLk : FBRsk<1,
1056 (ins relbrtarget_7:$target),
1058 [(AVRbrcond bb:$target, AVR_COND_PL)]>;
1060 def BRGEk : FBRsk<1,
1063 (ins relbrtarget_7:$target),
1065 [(AVRbrcond bb:$target, AVR_COND_GE)]>;
1067 def BRLTk : FBRsk<0,
1070 (ins relbrtarget_7:$target),
1072 [(AVRbrcond bb:$target, AVR_COND_LT)]>;
1075 //===----------------------------------------------------------------------===//
1076 // Data transfer instructions
1077 //===----------------------------------------------------------------------===//
1078 // 8 and 16-bit register move instructions.
1079 let hasSideEffects = 0 in
1081 def MOVRdRr : FRdRr<0b0010,
1088 def MOVWRdRr : FMOVWRdRr<(outs DREGS:$dst),
1092 Requires<[HasMOVW]>;
1095 // Load immediate values into registers.
1096 let isReMaterializable = 1 in
1098 def LDIRdK : FRdK<0b1110,
1102 [(set i8:$rd, imm:$k)]>;
1104 // LDIW Rd+1:Rd, K+1:K
1109 def LDIWRdK : Pseudo<(outs DLDREGS:$dst),
1112 [(set i16:$dst, imm:$src)]>;
1115 // Load from data space into register.
1116 let canFoldAsLoad = 1,
1117 isReMaterializable = 1 in
1119 def LDSRdK : F32DM<0b0,
1123 [(set i8:$rd, (load imm:$k))]>,
1124 Requires<[HasSRAM]>;
1126 // LDSW Rd+1:Rd, K+1:K
1130 // lds Rd+1 (K+1:K) + 1
1131 def LDSWRdK : Pseudo<(outs DREGS:$dst),
1134 [(set i16:$dst, (load imm:$src))]>,
1135 Requires<[HasSRAM]>;
1139 let canFoldAsLoad = 1,
1140 isReMaterializable = 1 in
1142 def LDRdPtr : FSTLD<0,
1145 (ins LDSTPtrReg:$ptrreg),
1146 "ld\t$reg, $ptrreg",
1147 [(set GPR8:$reg, (load i16:$ptrreg))]>,
1148 Requires<[HasSRAM]>;
1155 let Constraints = "@earlyclobber $reg" in
1156 def LDWRdPtr : Pseudo<(outs DREGS:$reg),
1157 (ins PTRDISPREGS:$ptrreg),
1158 "ldw\t$reg, $ptrreg",
1159 [(set i16:$reg, (load i16:$ptrreg))]>,
1160 Requires<[HasSRAM]>;
1163 // Indirect loads (with postincrement or predecrement).
1166 Constraints = "$ptrreg = $base_wb,@earlyclobber $reg,@earlyclobber $base_wb" in
1168 def LDRdPtrPi : FSTLD<0,
1170 (outs GPR8:$reg, PTRREGS:$base_wb),
1171 (ins LDSTPtrReg:$ptrreg),
1172 "ld\t$reg, $ptrreg+",
1174 Requires<[HasSRAM]>;
1180 def LDWRdPtrPi : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),
1181 (ins PTRREGS:$ptrreg),
1182 "ldw\t$reg, $ptrreg+",
1184 Requires<[HasSRAM]>;
1186 def LDRdPtrPd : FSTLD<0,
1188 (outs GPR8:$reg, PTRREGS:$base_wb),
1189 (ins LDSTPtrReg:$ptrreg),
1190 "ld\t$reg, -$ptrreg",
1192 Requires<[HasSRAM]>;
1199 def LDWRdPtrPd : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),
1200 (ins PTRREGS:$ptrreg),
1201 "ldw\t$reg, -$ptrreg",
1203 Requires<[HasSRAM]>;
1206 // Load indirect with displacement operations.
1207 let canFoldAsLoad = 1,
1208 isReMaterializable = 1 in
1210 let Constraints = "@earlyclobber $reg" in
1211 def LDDRdPtrQ : FSTDLDD<0,
1214 "ldd\t$reg, $memri",
1215 [(set i8:$reg, (load addr:$memri))]>,
1216 Requires<[HasSRAM]>;
1218 // LDDW Rd+1:Rd, P+q
1223 let Constraints = "@earlyclobber $dst" in
1224 def LDDWRdPtrQ : Pseudo<(outs DREGS:$dst),
1226 "lddw\t$dst, $memri",
1227 [(set i16:$dst, (load addr:$memri))]>,
1228 Requires<[HasSRAM]>;
1232 Constraints = "@earlyclobber $dst" in
1233 def LDDWRdYQ : Pseudo<(outs DREGS:$dst),
1235 "lddw\t$dst, $memri",
1237 Requires<[HasSRAM]>;
1240 class AtomicLoad<PatFrag Op, RegisterClass DRC> :
1241 Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr), "atomic_op",
1242 [(set DRC:$rd, (Op i16:$rr))]>;
1244 class AtomicStore<PatFrag Op, RegisterClass DRC> :
1245 Pseudo<(outs), (ins PTRDISPREGS:$rd, DRC:$rr), "atomic_op",
1246 [(Op i16:$rd, DRC:$rr)]>;
1248 class AtomicLoadOp<PatFrag Op, RegisterClass DRC> :
1249 Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr, DRC:$operand),
1251 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
1253 def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8>;
1254 def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS>;
1256 def AtomicStore8 : AtomicStore<atomic_store_8, GPR8>;
1257 def AtomicStore16 : AtomicStore<atomic_store_16, DREGS>;
1259 def AtomicLoadAdd8 : AtomicLoadOp<atomic_load_add_8, GPR8>;
1260 def AtomicLoadAdd16 : AtomicLoadOp<atomic_load_add_16, DREGS>;
1261 def AtomicLoadSub8 : AtomicLoadOp<atomic_load_sub_8, GPR8>;
1262 def AtomicLoadSub16 : AtomicLoadOp<atomic_load_sub_16, DREGS>;
1263 def AtomicLoadAnd8 : AtomicLoadOp<atomic_load_and_8, GPR8>;
1264 def AtomicLoadAnd16 : AtomicLoadOp<atomic_load_and_16, DREGS>;
1265 def AtomicLoadOr8 : AtomicLoadOp<atomic_load_or_8, GPR8>;
1266 def AtomicLoadOr16 : AtomicLoadOp<atomic_load_or_16, DREGS>;
1267 def AtomicLoadXor8 : AtomicLoadOp<atomic_load_xor_8, GPR8>;
1268 def AtomicLoadXor16 : AtomicLoadOp<atomic_load_xor_16, DREGS>;
1269 def AtomicFence : Pseudo<(outs), (ins), "atomic_fence",
1270 [(atomic_fence imm, imm)]>;
1272 // Indirect store from register to data space.
1273 def STSKRr : F32DM<0b1,
1275 (ins imm16:$k, GPR8:$rd),
1277 [(store i8:$rd, imm:$k)]>,
1278 Requires<[HasSRAM]>;
1280 // STSW K+1:K, Rr+1:Rr
1283 // sts Rr+1, (K+1:K) + 1
1285 def STSWKRr : Pseudo<(outs),
1286 (ins i16imm:$dst, DREGS:$src),
1288 [(store i16:$src, imm:$dst)]>,
1289 Requires<[HasSRAM]>;
1293 // Stores the value of Rr into the location addressed by pointer P.
1294 def STPtrRr : FSTLD<1,
1297 (ins LDSTPtrReg:$ptrreg, GPR8:$reg),
1298 "st\t$ptrreg, $reg",
1299 [(store GPR8:$reg, i16:$ptrreg)]>,
1300 Requires<[HasSRAM]>;
1303 // Stores the value of Rr into the location addressed by pointer P.
1308 def STWPtrRr : Pseudo<(outs),
1309 (ins PTRDISPREGS:$ptrreg, DREGS:$reg),
1310 "stw\t$ptrreg, $reg",
1311 [(store i16:$reg, i16:$ptrreg)]>,
1312 Requires<[HasSRAM]>;
1314 // Indirect stores (with postincrement or predecrement).
1315 let Constraints = "$ptrreg = $base_wb,@earlyclobber $base_wb" in
1319 // Stores the value of Rr into the location addressed by pointer P.
1320 // Post increments P.
1321 def STPtrPiRr : FSTLD<1,
1323 (outs LDSTPtrReg:$base_wb),
1324 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs),
1325 "st\t$ptrreg+, $reg",
1327 (post_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>,
1328 Requires<[HasSRAM]>;
1331 // Stores the value of Rr into the location addressed by pointer P.
1332 // Post increments P.
1337 def STWPtrPiRr : Pseudo<(outs PTRREGS:$base_wb),
1338 (ins PTRREGS:$ptrreg, DREGS:$trh, i8imm:$offs),
1339 "stw\t$ptrreg+, $trh",
1340 [(set PTRREGS:$base_wb,
1341 (post_store DREGS:$trh, PTRREGS:$ptrreg, imm:$offs))]>,
1342 Requires<[HasSRAM]>;
1345 // Stores the value of Rr into the location addressed by pointer P.
1346 // Pre decrements P.
1347 def STPtrPdRr : FSTLD<1,
1349 (outs LDSTPtrReg:$base_wb),
1350 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs),
1351 "st\t-$ptrreg, $reg",
1353 (pre_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>,
1354 Requires<[HasSRAM]>;
1357 // Stores the value of Rr into the location addressed by pointer P.
1358 // Pre decrements P.
1363 def STWPtrPdRr : Pseudo<(outs PTRREGS:$base_wb),
1364 (ins PTRREGS:$ptrreg, DREGS:$reg, i8imm:$offs),
1365 "stw\t-$ptrreg, $reg",
1366 [(set PTRREGS:$base_wb,
1367 (pre_store i16:$reg, i16:$ptrreg, imm:$offs))]>,
1368 Requires<[HasSRAM]>;
1371 // Store indirect with displacement operations.
1373 // Stores the value of Rr into the location addressed by pointer P with a
1374 // displacement of q. Does not modify P.
1375 def STDPtrQRr : FSTDLDD<1,
1377 (ins memri:$memri, GPR8:$reg),
1378 "std\t$memri, $reg",
1379 [(store i8:$reg, addr:$memri)]>,
1380 Requires<[HasSRAM]>;
1382 // STDW P+q, Rr+1:Rr
1383 // Stores the value of Rr into the location addressed by pointer P with a
1384 // displacement of q. Does not modify P.
1389 def STDWPtrQRr : Pseudo<(outs),
1390 (ins memri:$memri, DREGS:$src),
1391 "stdw\t$memri, $src",
1392 [(store i16:$src, addr:$memri)]>,
1393 Requires<[HasSRAM]>;
1396 // Load program memory operations.
1397 let canFoldAsLoad = 1,
1398 isReMaterializable = 1,
1399 hasSideEffects = 0 in
1403 def LPM : F16<0b1001010111001000,
1410 def LPMRdZ : FLPMX<0,
1416 Requires<[HasLPMX]>;
1418 def LPMWRdZ : Pseudo<(outs DREGS:$dst),
1422 Requires<[HasLPMX]>;
1424 // Load program memory, while postincrementing the Z register.
1428 def LPMRdZPi : FLPMX<0,
1434 Requires<[HasLPMX]>;
1436 def LPMWRdZPi : Pseudo<(outs DREGS:$dst),
1440 Requires<[HasLPMX]>;
1444 // Extended load program memory operations.
1446 hasSideEffects = 0 in
1450 def ELPM : F16<0b1001010111011000,
1455 Requires<[HasELPM]>;
1457 def ELPMRdZ : FLPMX<1,
1463 Requires<[HasELPMX]>;
1465 let Defs = [R31R30] in
1466 def ELPMRdZPi : FLPMX<1,
1472 Requires<[HasELPMX]>;
1475 // Store program memory operations.
1476 let Uses = [R1, R0] in
1478 let Uses = [R31R30, R1, R0] in
1479 def SPM : F16<0b1001010111101000,
1486 let Defs = [R31R30] in
1487 def SPMZPi : F16<0b1001010111111000,
1492 Requires<[HasSPMX]>;
1495 // Read data from IO location operations.
1496 let canFoldAsLoad = 1,
1497 isReMaterializable = 1 in
1499 def INRdA : FIORdA<(outs GPR8:$dst),
1500 (ins imm_port6:$src),
1502 [(set i8:$dst, (load ioaddr8:$src))]>;
1504 def INWRdA : Pseudo<(outs DREGS:$dst),
1505 (ins imm_port6:$src),
1507 [(set i16:$dst, (load ioaddr16:$src))]>;
1510 // Write data to IO location operations.
1511 def OUTARr : FIOARr<(outs),
1512 (ins imm_port6:$dst, GPR8:$src),
1514 [(store i8:$src, ioaddr8:$dst)]>;
1516 def OUTWARr : Pseudo<(outs),
1517 (ins imm_port6:$dst, DREGS:$src),
1519 [(store i16:$src, ioaddr16:$dst)]>;
1521 // Stack push/pop operations.
1524 hasSideEffects = 0 in
1526 // Stack push operations.
1529 def PUSHRr : FRd<0b1001,
1535 Requires<[HasSRAM]>;
1537 def PUSHWRr : Pseudo<(outs),
1541 Requires<[HasSRAM]>;
1544 // Stack pop operations.
1547 def POPRd : FRd<0b1001,
1553 Requires<[HasSRAM]>;
1555 def POPWRd : Pseudo<(outs DREGS:$reg),
1559 Requires<[HasSRAM]>;
1563 // Read-Write-Modify (RMW) instructions.
1564 def XCHZRd : FZRd<0b100,
1569 Requires<[SupportsRMW]>;
1571 def LASZRd : FZRd<0b101,
1576 Requires<[SupportsRMW]>;
1578 def LACZRd : FZRd<0b110,
1583 Requires<[SupportsRMW]>;
1585 def LATZRd : FZRd<0b111,
1590 Requires<[SupportsRMW]>;
1592 //===----------------------------------------------------------------------===//
1593 // Bit and bit-test instructions
1594 //===----------------------------------------------------------------------===//
1596 // Bit shift/rotate operations.
1597 let Constraints = "$src = $rd",
1600 def LSLRd : FRdRr<0b0000,
1605 [(set i8:$rd, (AVRlsl i8:$src)), (implicit SREG)]>;
1607 def LSLWRd : Pseudo<(outs DREGS:$rd),
1610 [(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>;
1612 def LSRRd : FRd<0b1001,
1617 [(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>;
1619 def LSRWRd : Pseudo<(outs DREGS:$rd),
1622 [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>;
1624 def ASRRd : FRd<0b1001,
1629 [(set i8:$rd, (AVRasr i8:$src)), (implicit SREG)]>;
1631 def ASRWRd : Pseudo<(outs DREGS:$rd),
1634 [(set i16:$rd, (AVRasr i16:$src)), (implicit SREG)]>;
1636 // Bit rotate operations.
1637 let Uses = [SREG] in
1639 def ROLRd : FRdRr<0b0001,
1644 [(set i8:$rd, (AVRrol i8:$src)), (implicit SREG)]>;
1646 def ROLWRd : Pseudo<(outs DREGS:$rd),
1649 [(set i16:$rd, (AVRrol i16:$src)), (implicit SREG)]>;
1651 def RORRd : FRd<0b1001,
1656 [(set i8:$rd, (AVRror i8:$src)), (implicit SREG)]>;
1658 def RORWRd : Pseudo<(outs DREGS:$rd),
1661 [(set i16:$rd, (AVRror i16:$src)), (implicit SREG)]>;
1666 // Swaps the high and low nibbles in a register.
1667 let Constraints = "$src = $rd" in
1668 def SWAPRd : FRd<0b1001,
1673 [(set i8:$rd, (bswap i8:$src))]>;
1675 // IO register bit set/clear operations.
1676 //:TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi
1677 // instead of in+ori+out which requires one more instr.
1678 def SBIAb : FIOBIT<0b10,
1680 (ins imm_port5:$addr, i8imm:$bit),
1682 [(store (or (i8 (load lowioaddr8:$addr)), iobitpos8:$bit),
1683 lowioaddr8:$addr)]>;
1685 def CBIAb : FIOBIT<0b00,
1687 (ins imm_port5:$addr, i8imm:$bit),
1689 [(store (and (i8 (load lowioaddr8:$addr)), iobitposn8:$bit),
1690 lowioaddr8:$addr)]>;
1692 // Status register bit load/store operations.
1693 let Defs = [SREG] in
1694 def BST : FRdB<0b01,
1696 (ins GPR8:$rd, i8imm:$b),
1700 let Uses = [SREG] in
1701 def BLD : FRdB<0b00,
1703 (ins GPR8:$rd, i8imm:$b),
1707 // Set/clear bit in register operations.
1708 let Constraints = "$src = $rd",
1712 // Alias for ORI Rd, K
1713 def SBRRdK : FRdK<0b0110,
1715 (ins LD8:$src, imm_ldi8:$k),
1717 [(set i8:$rd, (or i8:$src, imm:$k)),
1721 // Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K.
1722 // FIXME: This uses the 'complement' encoder. We need it to also use the
1723 // imm_ldi8 encoder. This will cause no fixups to be created on this instruction.
1724 def CBRRdK : FRdK<0b0111,
1726 (ins LD8:$src, imm_com8:$k),
1732 // Alias for EOR Rd, Rd
1734 // Clears all bits in a register.
1735 def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>;
1738 // Alias for LDI Rd, 0xff
1740 // Sets all bits in a register.
1741 def : InstAlias<"ser\t$rd", (LDIRdK LD8:$rd, 0xff), 0>;
1743 let Defs = [SREG] in
1750 let Defs = [SREG] in
1757 // Set/clear aliases for the carry (C) status flag (bit 0).
1758 def : InstAlias<"sec", (BSETs 0)>;
1759 def : InstAlias<"clc", (BCLRs 0)>;
1761 // Set/clear aliases for the zero (Z) status flag (bit 1).
1762 def : InstAlias<"sez", (BSETs 1)>;
1763 def : InstAlias<"clz", (BCLRs 1)>;
1765 // Set/clear aliases for the negative (N) status flag (bit 2).
1766 def : InstAlias<"sen", (BSETs 2)>;
1767 def : InstAlias<"cln", (BCLRs 2)>;
1769 // Set/clear aliases for the overflow (V) status flag (bit 3).
1770 def : InstAlias<"sev", (BSETs 3)>;
1771 def : InstAlias<"clv", (BCLRs 3)>;
1773 // Set/clear aliases for the signed (S) status flag (bit 4).
1774 def : InstAlias<"ses", (BSETs 4)>;
1775 def : InstAlias<"cls", (BCLRs 4)>;
1777 // Set/clear aliases for the half-carry (H) status flag (bit 5).
1778 def : InstAlias<"seh", (BSETs 5)>;
1779 def : InstAlias<"clh", (BCLRs 5)>;
1781 // Set/clear aliases for the T status flag (bit 6).
1782 def : InstAlias<"set", (BSETs 6)>;
1783 def : InstAlias<"clt", (BCLRs 6)>;
1785 // Set/clear aliases for the interrupt (I) status flag (bit 7).
1786 def : InstAlias<"sei", (BSETs 7)>;
1787 def : InstAlias<"cli", (BCLRs 7)>;
1789 //===----------------------------------------------------------------------===//
1790 // Special/Control instructions
1791 //===----------------------------------------------------------------------===//
1794 // Breakpoint instruction
1796 // <|1001|0101|1001|1000>
1797 def BREAK : F16<0b1001010110011000,
1802 Requires<[HasBREAK]>;
1805 // No-operation instruction
1807 // <|0000|0000|0000|0000>
1808 def NOP : F16<0b0000000000000000,
1815 // Sleep instruction
1817 // <|1001|0101|1000|1000>
1818 def SLEEP : F16<0b1001010110001000,
1827 // <|1001|0101|1010|1000>
1828 def WDR : F16<0b1001010110101000,
1834 //===----------------------------------------------------------------------===//
1835 // Pseudo instructions for later expansion
1836 //===----------------------------------------------------------------------===//
1838 //:TODO: Optimize this for wider types AND optimize the following code
1839 // compile int foo(char a, char b, char c, char d) {return d+b;}
1840 // looks like a missed sext_inreg opportunity.
1841 def SEXT : ExtensionPseudo<
1845 [(set i16:$dst, (sext i8:$src)), (implicit SREG)]
1848 def ZEXT : ExtensionPseudo<
1852 [(set i16:$dst, (zext i8:$src)), (implicit SREG)]
1855 // This pseudo gets expanded into a movw+adiw thus it clobbers SREG.
1857 hasSideEffects = 0 in
1858 def FRMIDX : Pseudo<(outs DLDREGS:$dst),
1859 (ins DLDREGS:$src, i16imm:$src2),
1860 "frmidx\t$dst, $src, $src2",
1863 // This pseudo is either converted to a regular store or a push which clobbers
1865 def STDSPQRr : StorePseudo<
1867 (ins memspi:$dst, GPR8:$src),
1868 "stdstk\t$dst, $src",
1869 [(store i8:$src, addr:$dst)]
1872 // This pseudo is either converted to a regular store or a push which clobbers
1874 def STDWSPQRr : StorePseudo<
1876 (ins memspi:$dst, DREGS:$src),
1877 "stdwstk\t$dst, $src",
1878 [(store i16:$src, addr:$dst)]
1881 // SP read/write pseudos.
1882 let hasSideEffects = 0 in
1885 def SPREAD : Pseudo<
1888 "spread\t$dst, $src",
1893 def SPWRITE : Pseudo<
1896 "spwrite\t$dst, $src",
1900 def Select8 : SelectPseudo<
1902 (ins GPR8:$src, GPR8:$src2, i8imm:$cc),
1904 [(set i8:$dst, (AVRselectcc i8:$src, i8:$src2, imm:$cc))]
1907 def Select16 : SelectPseudo<
1909 (ins DREGS:$src, DREGS:$src2, i8imm:$cc),
1910 "# Select16 PSEUDO",
1911 [(set i16:$dst, (AVRselectcc i16:$src, i16:$src2, imm:$cc))]
1914 def Lsl8 : ShiftPseudo<
1916 (ins GPR8:$src, GPR8:$cnt),
1918 [(set i8:$dst, (AVRlslLoop i8:$src, i8:$cnt))]
1921 def Lsl16 : ShiftPseudo<
1923 (ins DREGS:$src, GPR8:$cnt),
1925 [(set i16:$dst, (AVRlslLoop i16:$src, i8:$cnt))]
1928 def Lsr8 : ShiftPseudo<
1930 (ins GPR8:$src, GPR8:$cnt),
1932 [(set i8:$dst, (AVRlsrLoop i8:$src, i8:$cnt))]
1936 def Lsr16 : ShiftPseudo<
1938 (ins DREGS:$src, GPR8:$cnt),
1940 [(set i16:$dst, (AVRlsrLoop i16:$src, i8:$cnt))]
1943 def Asr8 : ShiftPseudo<
1945 (ins GPR8:$src, GPR8:$cnt),
1947 [(set i8:$dst, (AVRasrLoop i8:$src, i8:$cnt))]
1950 def Asr16 : ShiftPseudo<
1952 (ins DREGS:$src, GPR8:$cnt),
1954 [(set i16:$dst, (AVRasrLoop i16:$src, i8:$cnt))]
1958 //===----------------------------------------------------------------------===//
1959 // Non-Instruction Patterns
1960 //===----------------------------------------------------------------------===//
1962 //:TODO: look in x86InstrCompiler.td for odd encoding trick related to
1963 // add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor)
1965 // the add instruction always writes the carry flag
1966 def : Pat<(addc i8:$src, i8:$src2),
1967 (ADDRdRr i8:$src, i8:$src2)>;
1968 def : Pat<(addc DREGS:$src, DREGS:$src2),
1969 (ADDWRdRr DREGS:$src, DREGS:$src2)>;
1971 // all sub instruction variants always writes the carry flag
1972 def : Pat<(subc i8:$src, i8:$src2),
1973 (SUBRdRr i8:$src, i8:$src2)>;
1974 def : Pat<(subc i16:$src, i16:$src2),
1975 (SUBWRdRr i16:$src, i16:$src2)>;
1976 def : Pat<(subc i8:$src, imm:$src2),
1977 (SUBIRdK i8:$src, imm:$src2)>;
1978 def : Pat<(subc i16:$src, imm:$src2),
1979 (SUBIWRdK i16:$src, imm:$src2)>;
1981 // These patterns convert add (x, -imm) to sub (x, imm) since we dont have
1982 // any add with imm instructions. Also take care of the adiw/sbiw instructions.
1983 def : Pat<(add i16:$src1, imm0_63_neg:$src2),
1984 (SBIWRdK i16:$src1, (imm0_63_neg:$src2))>;
1985 def : Pat<(add i16:$src1, imm:$src2),
1986 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
1987 def : Pat<(addc i16:$src1, imm:$src2),
1988 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
1989 def : Pat<(adde i16:$src1, imm:$src2),
1990 (SBCIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
1992 def : Pat<(add i8:$src1, imm:$src2),
1993 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
1994 def : Pat<(addc i8:$src1, imm:$src2),
1995 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
1996 def : Pat<(adde i8:$src1, imm:$src2),
1997 (SBCIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
2000 def : Pat<(AVRcall (i16 tglobaladdr:$dst)),
2001 (CALLk tglobaladdr:$dst)>;
2002 def : Pat<(AVRcall (i16 texternalsym:$dst)),
2003 (CALLk texternalsym:$dst)>;
2006 def : Pat<(i16 (anyext i8:$src)),
2007 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), i8:$src, sub_lo)>;
2010 def : Pat<(i8 (trunc i16:$src)),
2011 (EXTRACT_SUBREG i16:$src, sub_lo)>;
2014 def : Pat<(sext_inreg i16:$src, i8),
2015 (SEXT (i8 (EXTRACT_SUBREG i16:$src, sub_lo)))>;
2018 def : Pat<(i16 (AVRWrapper tglobaladdr:$dst)),
2019 (LDIWRdK tglobaladdr:$dst)>;
2020 def : Pat<(add i16:$src, (AVRWrapper tglobaladdr:$src2)),
2021 (SUBIWRdK i16:$src, tglobaladdr:$src2)>;
2022 def : Pat<(i8 (load (AVRWrapper tglobaladdr:$dst))),
2023 (LDSRdK tglobaladdr:$dst)>;
2024 def : Pat<(i16 (load (AVRWrapper tglobaladdr:$dst))),
2025 (LDSWRdK tglobaladdr:$dst)>;
2026 def : Pat<(store i8:$src, (i16 (AVRWrapper tglobaladdr:$dst))),
2027 (STSKRr tglobaladdr:$dst, i8:$src)>;
2028 def : Pat<(store i16:$src, (i16 (AVRWrapper tglobaladdr:$dst))),
2029 (STSWKRr tglobaladdr:$dst, i16:$src)>;
2032 def : Pat<(i16 (AVRWrapper tblockaddress:$dst)),
2033 (LDIWRdK tblockaddress:$dst)>;
2035 // hi-reg truncation : trunc(int16 >> 8)
2036 //:FIXME: i think it's better to emit an extract subreg node in the DAG than
2037 // all this mess once we get optimal shift code
2038 // lol... I think so, too. [@agnat]
2039 def : Pat<(i8 (trunc (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr
2040 (AVRlsr DREGS:$src)))))))))),
2041 (EXTRACT_SUBREG DREGS:$src, sub_hi)>;
2043 // :FIXME: DAGCombiner produces an shl node after legalization from these seq:
2044 // BR_JT -> (mul x, 2) -> (shl x, 1)
2045 def : Pat<(shl i16:$src1, (i8 1)),
2046 (LSLWRd i16:$src1)>;